The hardware address is an intrinsic property of the hardware, while
the link-layer address can be changed at runtime.  This separation is
exposed via APIs such as PXE and EFI, but is currently elided by gPXE.

Expose the hardware and link-layer addresses as separate properties
within a net device.  Drivers should now fill in hw_addr, which will
be used to initialise ll_addr at the time of calling
register_netdev().

Signed-off-by: Michael Brown <mcb30@etherboot.org>

Add FILE_LICENCE declarations to almost all files that make up the
various standard builds of gPXE.

Modified-by: Michael Brown <mcb30@etherboot.org>
Signed-off-by: Michael Brown <mcb30@etherboot.org>

Driver was storing the result of pci_bar_start() and pci_bar_size() in
an int, rather than an unsigned long.

(Bug was introduced in the vendor's tree in commit eac85cd "Port
etherfabric driver to net_device api".)

Remove various 32-bit assumptions scattered throughout the codebase.
The code is still not necessarily 64-bit clean, but will at least
compile.

Also clean up minor errors in the use of debug macros.

Some devices (e.g. the Atmel AT24C11) have no concept of a device
address; they respond to every device address and use this value as
the word address.  Some other devices use part of the device address
field to extend the word address field.

Generalise the i2c bit-bashing support to handle this by defining the
device address length and word address length as properties of an i2c
device.  The word address is assumed to overflow into the device
address field if the address used exceeds the width of the word
address field.

Also add a bus reset mechanism.  i2c chips don't usually have a reset
line, so rebooting the host will not clear any bizarre state that the
chip may be in.  We reset the bus by clocking SCL until we see SDA
high, at which point we know we can generate a start condition and
have it seen by all devices.  We then generate a stop condition to
leave the bus in a known state prior to use.

Finally, add some extra debugging messages to i2c_bit.c.

Signed-off-by: Alexey Zaytsev <alexey.zaytsev@gmail.com>

anywhere other than offset 0 within the EEPROM, so we have to put our
settings at 0x100 instead.

device.

Separated the mechanisms of non-volatile storage access and non-volatile
stored options.

that don't provide the full flexibility of a bit-bashing interface.

Temporarily hacked rtl8139.c to use the new interface.

period before updating to the new driver API (which can cope with
having TX packets in progress).

(This actually matters once you try using TCP, because you *will*
receive full-sized frames.)

Generic PCI code now handles 64-bit BARs correctly when setting
"membase"; drivers should need to call pci_bar_start() only if they want
to use BARs other than the first memory or I/O BAR.

Split rarely-used PCI functions out into pciextra.c.

Core PCI code is now 662 bytes (down from 1308 bytes in Etherboot 5.4).
284 bytes of this saving comes from the pci/pciextra split.

Cosmetic changes to lots of drivers (e.g. vendor_id->vendor in order to
match the names used in Linux).

I want to get to the point where any header in include/ reflects a
standard user-level header (e.g. a POSIX header), while everything that's
specific to gPXE lives in include/gpxe/.  Headers that reflect a Linux
header (e.g. if_ether.h) should also be in include/gpxe/, with the same
name as the Linux header and, preferably, the same names used for the
definitions.