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@@ -104,6 +104,10 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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104
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104
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#define PCI_PM_CTRL_PME_ENABLE 0x0100 /**< PME pin enable */
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105
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#define PCI_PM_CTRL_PME_STATUS 0x8000 /**< PME pin status */
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106
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106
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+/** PCI Express */
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108
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+#define PCI_EXP_DEVCTL 0x08
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109
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+#define PCI_EXP_DEVCTL_FLR 0x8000 /**< Function level reset */
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+
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107
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111
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/** Uncorrectable error status */
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108
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112
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#define PCI_ERR_UNCOR_STATUS 0x04
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109
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113
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@@ -128,6 +132,9 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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128
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132
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( ( ( (base) & 0xff ) << 16 ) | ( ( (sub) & 0xff ) << 8 ) | \
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133
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( ( (progif) & 0xff) << 0 ) )
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130
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134
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135
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+/** PCI Express function level reset delay (in ms) */
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+#define PCI_EXP_FLR_DELAY_MS 100
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137
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+
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131
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138
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/** A PCI device ID list entry */
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132
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139
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struct pci_device_id {
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133
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140
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/** Name */
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