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i82365.h 17KB

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  1. /*
  2. * i82365.h 1.15 1999/10/25 20:03:34
  3. *
  4. * The contents of this file may be used under the
  5. * terms of the GNU General Public License version 2 (the "GPL").
  6. *
  7. * Software distributed under the License is distributed on an "AS IS"
  8. * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
  9. * the License for the specific language governing rights and
  10. * limitations under the License.
  11. *
  12. * The initial developer of the original code is David A. Hinds
  13. * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
  14. * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
  15. */
  16. FILE_LICENCE ( GPL2_ONLY );
  17. #ifndef _LINUX_I82365_H
  18. #define _LINUX_I82365_H
  19. /* register definitions for the Intel 82365SL PCMCIA controller */
  20. /* Offsets for PCIC registers */
  21. #define I365_IDENT 0x00 /* Identification and revision */
  22. #define I365_STATUS 0x01 /* Interface status */
  23. #define I365_POWER 0x02 /* Power and RESETDRV control */
  24. #define I365_INTCTL 0x03 /* Interrupt and general control */
  25. #define I365_CSC 0x04 /* Card status change */
  26. #define I365_CSCINT 0x05 /* Card status change interrupt control */
  27. #define I365_ADDRWIN 0x06 /* Address window enable */
  28. #define I365_IOCTL 0x07 /* I/O control */
  29. #define I365_GENCTL 0x16 /* Card detect and general control */
  30. #define I365_GBLCTL 0x1E /* Global control register */
  31. /* Offsets for I/O and memory window registers */
  32. #define I365_IO(map) (0x08+((map)<<2))
  33. #define I365_MEM(map) (0x10+((map)<<3))
  34. #define I365_W_START 0
  35. #define I365_W_STOP 2
  36. #define I365_W_OFF 4
  37. /* Flags for I365_STATUS */
  38. #define I365_CS_BVD1 0x01
  39. #define I365_CS_STSCHG 0x01
  40. #define I365_CS_BVD2 0x02
  41. #define I365_CS_SPKR 0x02
  42. #define I365_CS_DETECT 0x0C
  43. #define I365_CS_WRPROT 0x10
  44. #define I365_CS_READY 0x20 /* Inverted */
  45. #define I365_CS_POWERON 0x40
  46. #define I365_CS_GPI 0x80
  47. /* Flags for I365_POWER */
  48. #define I365_PWR_OFF 0x00 /* Turn off the socket */
  49. #define I365_PWR_OUT 0x80 /* Output enable */
  50. #define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */
  51. #define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */
  52. #define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */
  53. /* There are different layouts for B-step and DF-step chips: the B
  54. step has independent Vpp1/Vpp2 control, and the DF step has only
  55. Vpp1 control, plus 3V control */
  56. #define I365_VCC_5V 0x10 /* Vcc = 5.0v */
  57. #define I365_VCC_3V 0x18 /* Vcc = 3.3v */
  58. #define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */
  59. #define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */
  60. #define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */
  61. #define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */
  62. #define I365_VPP1_5V 0x01 /* Vpp2 = 5.0v */
  63. #define I365_VPP1_12V 0x02 /* Vpp2 = 12.0v */
  64. /* Flags for I365_INTCTL */
  65. #define I365_RING_ENA 0x80
  66. #define I365_PC_RESET 0x40
  67. #define I365_PC_IOCARD 0x20
  68. #define I365_INTR_ENA 0x10
  69. #define I365_IRQ_MASK 0x0F
  70. /* Flags for I365_CSC and I365_CSCINT*/
  71. #define I365_CSC_BVD1 0x01
  72. #define I365_CSC_STSCHG 0x01
  73. #define I365_CSC_BVD2 0x02
  74. #define I365_CSC_READY 0x04
  75. #define I365_CSC_DETECT 0x08
  76. #define I365_CSC_ANY 0x0F
  77. #define I365_CSC_GPI 0x10
  78. /* Flags for I365_ADDRWIN */
  79. #define I365_ENA_IO(map) (0x40 << (map))
  80. #define I365_ENA_MEM(map) (0x01 << (map))
  81. /* Flags for I365_IOCTL */
  82. #define I365_IOCTL_MASK(map) (0x0F << (map<<2))
  83. #define I365_IOCTL_WAIT(map) (0x08 << (map<<2))
  84. #define I365_IOCTL_0WS(map) (0x04 << (map<<2))
  85. #define I365_IOCTL_IOCS16(map) (0x02 << (map<<2))
  86. #define I365_IOCTL_16BIT(map) (0x01 << (map<<2))
  87. /* Flags for I365_GENCTL */
  88. #define I365_CTL_16DELAY 0x01
  89. #define I365_CTL_RESET 0x02
  90. #define I365_CTL_GPI_ENA 0x04
  91. #define I365_CTL_GPI_CTL 0x08
  92. #define I365_CTL_RESUME 0x10
  93. #define I365_CTL_SW_IRQ 0x20
  94. /* Flags for I365_GBLCTL */
  95. #define I365_GBL_PWRDOWN 0x01
  96. #define I365_GBL_CSC_LEV 0x02
  97. #define I365_GBL_WRBACK 0x04
  98. #define I365_GBL_IRQ_0_LEV 0x08
  99. #define I365_GBL_IRQ_1_LEV 0x10
  100. /* Flags for memory window registers */
  101. #define I365_MEM_16BIT 0x8000 /* In memory start high byte */
  102. #define I365_MEM_0WS 0x4000
  103. #define I365_MEM_WS1 0x8000 /* In memory stop high byte */
  104. #define I365_MEM_WS0 0x4000
  105. #define I365_MEM_WRPROT 0x8000 /* In offset high byte */
  106. #define I365_MEM_REG 0x4000
  107. #define I365_REG(slot, reg) (((slot) << 6) + reg)
  108. #endif /* _LINUX_I82365_H */
  109. //*****************************************************************************
  110. //*****************************************************************************
  111. //*****************************************************************************
  112. //*****************************************************************************
  113. //*****************************************************************************
  114. // Beginning vg468.h (for VADEM chipset)
  115. #ifndef _LINUX_VG468_H
  116. #define _LINUX_VG468_H
  117. /* Special bit in I365_IDENT used for Vadem chip detection */
  118. #define I365_IDENT_VADEM 0x08
  119. /* Special definitions in I365_POWER */
  120. #define VG468_VPP2_MASK 0x0c
  121. #define VG468_VPP2_5V 0x04
  122. #define VG468_VPP2_12V 0x08
  123. /* Unique Vadem registers */
  124. #define VG469_VSENSE 0x1f /* Card voltage sense */
  125. #define VG469_VSELECT 0x2f /* Card voltage select */
  126. #define VG468_CTL 0x38 /* Control register */
  127. #define VG468_TIMER 0x39 /* Timer control */
  128. #define VG468_MISC 0x3a /* Miscellaneous */
  129. #define VG468_GPIO_CFG 0x3b /* GPIO configuration */
  130. #define VG469_EXT_MODE 0x3c /* Extended mode register */
  131. #define VG468_SELECT 0x3d /* Programmable chip select */
  132. #define VG468_SELECT_CFG 0x3e /* Chip select configuration */
  133. #define VG468_ATA 0x3f /* ATA control */
  134. /* Flags for VG469_VSENSE */
  135. #define VG469_VSENSE_A_VS1 0x01
  136. #define VG469_VSENSE_A_VS2 0x02
  137. #define VG469_VSENSE_B_VS1 0x04
  138. #define VG469_VSENSE_B_VS2 0x08
  139. /* Flags for VG469_VSELECT */
  140. #define VG469_VSEL_VCC 0x03
  141. #define VG469_VSEL_5V 0x00
  142. #define VG469_VSEL_3V 0x03
  143. #define VG469_VSEL_MAX 0x0c
  144. #define VG469_VSEL_EXT_STAT 0x10
  145. #define VG469_VSEL_EXT_BUS 0x20
  146. #define VG469_VSEL_MIXED 0x40
  147. #define VG469_VSEL_ISA 0x80
  148. /* Flags for VG468_CTL */
  149. #define VG468_CTL_SLOW 0x01 /* 600ns memory timing */
  150. #define VG468_CTL_ASYNC 0x02 /* Asynchronous bus clocking */
  151. #define VG468_CTL_TSSI 0x08 /* Tri-state some outputs */
  152. #define VG468_CTL_DELAY 0x10 /* Card detect debounce */
  153. #define VG468_CTL_INPACK 0x20 /* Obey INPACK signal? */
  154. #define VG468_CTL_POLARITY 0x40 /* VCCEN polarity */
  155. #define VG468_CTL_COMPAT 0x80 /* Compatibility stuff */
  156. #define VG469_CTL_WS_COMPAT 0x04 /* Wait state compatibility */
  157. #define VG469_CTL_STRETCH 0x10 /* LED stretch */
  158. /* Flags for VG468_TIMER */
  159. #define VG468_TIMER_ZEROPWR 0x10 /* Zero power control */
  160. #define VG468_TIMER_SIGEN 0x20 /* Power up */
  161. #define VG468_TIMER_STATUS 0x40 /* Activity timer status */
  162. #define VG468_TIMER_RES 0x80 /* Timer resolution */
  163. #define VG468_TIMER_MASK 0x0f /* Activity timer timeout */
  164. /* Flags for VG468_MISC */
  165. #define VG468_MISC_GPIO 0x04 /* General-purpose IO */
  166. #define VG468_MISC_DMAWSB 0x08 /* DMA wait state control */
  167. #define VG469_MISC_LEDENA 0x10 /* LED enable */
  168. #define VG468_MISC_VADEMREV 0x40 /* Vadem revision control */
  169. #define VG468_MISC_UNLOCK 0x80 /* Unique register lock */
  170. /* Flags for VG469_EXT_MODE_A */
  171. #define VG469_MODE_VPPST 0x03 /* Vpp steering control */
  172. #define VG469_MODE_INT_SENSE 0x04 /* Internal voltage sense */
  173. #define VG469_MODE_CABLE 0x08
  174. #define VG469_MODE_COMPAT 0x10 /* i82365sl B or DF step */
  175. #define VG469_MODE_TEST 0x20
  176. #define VG469_MODE_RIO 0x40 /* Steer RIO to INTR? */
  177. /* Flags for VG469_EXT_MODE_B */
  178. #define VG469_MODE_B_3V 0x01 /* 3.3v for socket B */
  179. #endif /* _LINUX_VG468_H */
  180. //*****************************************************************************
  181. //*****************************************************************************
  182. //*****************************************************************************
  183. //*****************************************************************************
  184. //*****************************************************************************
  185. // Beginning ricoh.h (RICOH chipsets)
  186. #ifndef _LINUX_RICOH_H
  187. #define _LINUX_RICOH_H
  188. #define RF5C_MODE_CTL 0x1f /* Mode control */
  189. #define RF5C_PWR_CTL 0x2f /* Mixed voltage control */
  190. #define RF5C_CHIP_ID 0x3a /* Chip identification */
  191. #define RF5C_MODE_CTL_3 0x3b /* Mode control 3 */
  192. /* I/O window address offset */
  193. #define RF5C_IO_OFF(w) (0x36+((w)<<1))
  194. /* Flags for RF5C_MODE_CTL */
  195. #define RF5C_MODE_ATA 0x01 /* ATA mode */
  196. #define RF5C_MODE_LED_ENA 0x02 /* IRQ 12 is LED */
  197. #define RF5C_MODE_CA21 0x04
  198. #define RF5C_MODE_CA22 0x08
  199. #define RF5C_MODE_CA23 0x10
  200. #define RF5C_MODE_CA24 0x20
  201. #define RF5C_MODE_CA25 0x40
  202. #define RF5C_MODE_3STATE_BIT7 0x80
  203. /* Flags for RF5C_PWR_CTL */
  204. #define RF5C_PWR_VCC_3V 0x01
  205. #define RF5C_PWR_IREQ_HIGH 0x02
  206. #define RF5C_PWR_INPACK_ENA 0x04
  207. #define RF5C_PWR_5V_DET 0x08
  208. #define RF5C_PWR_TC_SEL 0x10 /* Terminal Count: irq 11 or 15 */
  209. #define RF5C_PWR_DREQ_LOW 0x20
  210. #define RF5C_PWR_DREQ_OFF 0x00 /* DREQ steering control */
  211. #define RF5C_PWR_DREQ_INPACK 0x40
  212. #define RF5C_PWR_DREQ_SPKR 0x80
  213. #define RF5C_PWR_DREQ_IOIS16 0xc0
  214. /* Values for RF5C_CHIP_ID */
  215. #define RF5C_CHIP_RF5C296 0x32
  216. #define RF5C_CHIP_RF5C396 0xb2
  217. /* Flags for RF5C_MODE_CTL_3 */
  218. #define RF5C_MCTL3_DISABLE 0x01 /* Disable PCMCIA interface */
  219. #define RF5C_MCTL3_DMA_ENA 0x02
  220. /* Register definitions for Ricoh PCI-to-CardBus bridges */
  221. /* Extra bits in CB_BRIDGE_CONTROL */
  222. #define RL5C46X_BCR_3E0_ENA 0x0800
  223. #define RL5C46X_BCR_3E2_ENA 0x1000
  224. /* Bridge Configuration Register */
  225. #define RL5C4XX_CONFIG 0x80 /* 16 bit */
  226. #define RL5C4XX_CONFIG_IO_1_MODE 0x0200
  227. #define RL5C4XX_CONFIG_IO_0_MODE 0x0100
  228. #define RL5C4XX_CONFIG_PREFETCH 0x0001
  229. /* Misc Control Register */
  230. #define RL5C4XX_MISC 0x0082 /* 16 bit */
  231. #define RL5C4XX_MISC_HW_SUSPEND_ENA 0x0002
  232. #define RL5C4XX_MISC_VCCEN_POL 0x0100
  233. #define RL5C4XX_MISC_VPPEN_POL 0x0200
  234. #define RL5C46X_MISC_SUSPEND 0x0001
  235. #define RL5C46X_MISC_PWR_SAVE_2 0x0004
  236. #define RL5C46X_MISC_IFACE_BUSY 0x0008
  237. #define RL5C46X_MISC_B_LOCK 0x0010
  238. #define RL5C46X_MISC_A_LOCK 0x0020
  239. #define RL5C46X_MISC_PCI_LOCK 0x0040
  240. #define RL5C47X_MISC_IFACE_BUSY 0x0004
  241. #define RL5C47X_MISC_PCI_INT_MASK 0x0018
  242. #define RL5C47X_MISC_PCI_INT_DIS 0x0020
  243. #define RL5C47X_MISC_SUBSYS_WR 0x0040
  244. #define RL5C47X_MISC_SRIRQ_ENA 0x0080
  245. #define RL5C47X_MISC_5V_DISABLE 0x0400
  246. #define RL5C47X_MISC_LED_POL 0x0800
  247. /* 16-bit Interface Control Register */
  248. #define RL5C4XX_16BIT_CTL 0x0084 /* 16 bit */
  249. #define RL5C4XX_16CTL_IO_TIMING 0x0100
  250. #define RL5C4XX_16CTL_MEM_TIMING 0x0200
  251. #define RL5C46X_16CTL_LEVEL_1 0x0010
  252. #define RL5C46X_16CTL_LEVEL_2 0x0020
  253. /* 16-bit IO and memory timing registers */
  254. #define RL5C4XX_16BIT_IO_0 0x0088 /* 16 bit */
  255. #define RL5C4XX_16BIT_MEM_0 0x0088 /* 16 bit */
  256. #define RL5C4XX_SETUP_MASK 0x0007
  257. #define RL5C4XX_SETUP_SHIFT 0
  258. #define RL5C4XX_CMD_MASK 0x01f0
  259. #define RL5C4XX_CMD_SHIFT 4
  260. #define RL5C4XX_HOLD_MASK 0x1c00
  261. #define RL5C4XX_HOLD_SHIFT 10
  262. #define RL5C4XX_MISC_CONTROL 0x2F /* 8 bit */
  263. #define RL5C4XX_ZV_ENABLE 0x08
  264. #endif /* _LINUX_RICOH_H */
  265. //*****************************************************************************
  266. //*****************************************************************************
  267. //*****************************************************************************
  268. //*****************************************************************************
  269. //*****************************************************************************
  270. // Beginning cirrus.h (CIRRUS chipsets)
  271. #ifndef _LINUX_CIRRUS_H
  272. #define _LINUX_CIRRUS_H
  273. #ifndef PCI_VENDOR_ID_CIRRUS
  274. #define PCI_VENDOR_ID_CIRRUS 0x1013
  275. #endif
  276. #ifndef PCI_DEVICE_ID_CIRRUS_6729
  277. #define PCI_DEVICE_ID_CIRRUS_6729 0x1100
  278. #endif
  279. #ifndef PCI_DEVICE_ID_CIRRUS_6832
  280. #define PCI_DEVICE_ID_CIRRUS_6832 0x1110
  281. #endif
  282. #define PD67_MISC_CTL_1 0x16 /* Misc control 1 */
  283. #define PD67_FIFO_CTL 0x17 /* FIFO control */
  284. #define PD67_MISC_CTL_2 0x1E /* Misc control 2 */
  285. #define PD67_CHIP_INFO 0x1f /* Chip information */
  286. #define PD67_ATA_CTL 0x026 /* 6730: ATA control */
  287. #define PD67_EXT_INDEX 0x2e /* Extension index */
  288. #define PD67_EXT_DATA 0x2f /* Extension data */
  289. /* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
  290. #define PD67_DATA_MASK0 0x01 /* Data mask 0 */
  291. #define PD67_DATA_MASK1 0x02 /* Data mask 1 */
  292. #define PD67_DMA_CTL 0x03 /* DMA control */
  293. /* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
  294. #define PD67_EXT_CTL_1 0x03 /* Extension control 1 */
  295. #define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */
  296. #define PD67_EXTERN_DATA 0x0a
  297. #define PD67_MISC_CTL_3 0x25
  298. #define PD67_SMB_PWR_CTL 0x26
  299. /* I/O window address offset */
  300. #define PD67_IO_OFF(w) (0x36+((w)<<1))
  301. /* Timing register sets */
  302. #define PD67_TIME_SETUP(n) (0x3a + 3*(n))
  303. #define PD67_TIME_CMD(n) (0x3b + 3*(n))
  304. #define PD67_TIME_RECOV(n) (0x3c + 3*(n))
  305. /* Flags for PD67_MISC_CTL_1 */
  306. #define PD67_MC1_5V_DET 0x01 /* 5v detect */
  307. #define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */
  308. #define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */
  309. #define PD67_MC1_PULSE_MGMT 0x04
  310. #define PD67_MC1_PULSE_IRQ 0x08
  311. #define PD67_MC1_SPKR_ENA 0x10
  312. #define PD67_MC1_INPACK_ENA 0x80
  313. /* Flags for PD67_FIFO_CTL */
  314. #define PD67_FIFO_EMPTY 0x80
  315. /* Flags for PD67_MISC_CTL_2 */
  316. #define PD67_MC2_FREQ_BYPASS 0x01
  317. #define PD67_MC2_DYNAMIC_MODE 0x02
  318. #define PD67_MC2_SUSPEND 0x04
  319. #define PD67_MC2_5V_CORE 0x08
  320. #define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */
  321. #define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */
  322. #define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */
  323. #define PD67_MC2_DMA_MODE 0x40
  324. #define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */
  325. /* Flags for PD67_CHIP_INFO */
  326. #define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */
  327. #define PD67_INFO_CHIP_ID 0xc0
  328. #define PD67_INFO_REV 0x1c
  329. /* Fields in PD67_TIME_* registers */
  330. #define PD67_TIME_SCALE 0xc0
  331. #define PD67_TIME_SCALE_1 0x00
  332. #define PD67_TIME_SCALE_16 0x40
  333. #define PD67_TIME_SCALE_256 0x80
  334. #define PD67_TIME_SCALE_4096 0xc0
  335. #define PD67_TIME_MULT 0x3f
  336. /* Fields in PD67_DMA_CTL */
  337. #define PD67_DMA_MODE 0xc0
  338. #define PD67_DMA_OFF 0x00
  339. #define PD67_DMA_DREQ_INPACK 0x40
  340. #define PD67_DMA_DREQ_WP 0x80
  341. #define PD67_DMA_DREQ_BVD2 0xc0
  342. #define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */
  343. /* Fields in PD67_EXT_CTL_1 */
  344. #define PD67_EC1_VCC_PWR_LOCK 0x01
  345. #define PD67_EC1_AUTO_PWR_CLEAR 0x02
  346. #define PD67_EC1_LED_ENA 0x04
  347. #define PD67_EC1_INV_CARD_IRQ 0x08
  348. #define PD67_EC1_INV_MGMT_IRQ 0x10
  349. #define PD67_EC1_PULLUP_CTL 0x20
  350. /* Fields in PD67_MISC_CTL_3 */
  351. #define PD67_MC3_IRQ_MASK 0x03
  352. #define PD67_MC3_IRQ_PCPCI 0x00
  353. #define PD67_MC3_IRQ_EXTERN 0x01
  354. #define PD67_MC3_IRQ_PCIWAY 0x02
  355. #define PD67_MC3_IRQ_PCI 0x03
  356. #define PD67_MC3_PWR_MASK 0x0c
  357. #define PD67_MC3_PWR_SERIAL 0x00
  358. #define PD67_MC3_PWR_TI2202 0x08
  359. #define PD67_MC3_PWR_SMB 0x0c
  360. /* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
  361. /* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
  362. #define PD68_EXT_CTL_2 0x0b
  363. #define PD68_PCI_SPACE 0x22
  364. #define PD68_PCCARD_SPACE 0x23
  365. #define PD68_WINDOW_TYPE 0x24
  366. #define PD68_EXT_CSC 0x2e
  367. #define PD68_MISC_CTL_4 0x2f
  368. #define PD68_MISC_CTL_5 0x30
  369. #define PD68_MISC_CTL_6 0x31
  370. /* Extra flags in PD67_MISC_CTL_3 */
  371. #define PD68_MC3_HW_SUSP 0x10
  372. #define PD68_MC3_MM_EXPAND 0x40
  373. #define PD68_MC3_MM_ARM 0x80
  374. /* Bridge Control Register */
  375. #define PD6832_BCR_MGMT_IRQ_ENA 0x0800
  376. /* Socket Number Register */
  377. #define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */
  378. #endif /* _LINUX_CIRRUS_H */