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  1. #ifndef _VMXNET3_H
  2. #define _VMXNET3_H
  3. /*
  4. * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of the
  9. * License, or any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  19. * 02110-1301, USA.
  20. *
  21. * You can also choose to distribute this program under the terms of
  22. * the Unmodified Binary Distribution Licence (as given in the file
  23. * COPYING.UBDL), provided that you have satisfied its requirements.
  24. */
  25. FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
  26. /**
  27. * @file
  28. *
  29. * VMware vmxnet3 virtual NIC driver
  30. *
  31. */
  32. #include <ipxe/pci.h>
  33. /** Maximum number of TX queues */
  34. #define VMXNET3_MAX_TX_QUEUES 8
  35. /** Maximum number of RX queues */
  36. #define VMXNET3_MAX_RX_QUEUES 16
  37. /** Maximum number of interrupts */
  38. #define VMXNET3_MAX_INTRS 25
  39. /** Maximum packet size */
  40. #define VMXNET3_MAX_PACKET_LEN 0x4000
  41. /** "PT" PCI BAR address */
  42. #define VMXNET3_PT_BAR PCI_BASE_ADDRESS_0
  43. /** "PT" PCI BAR size */
  44. #define VMXNET3_PT_LEN 0x1000
  45. /** Interrupt Mask Register */
  46. #define VMXNET3_PT_IMR 0x0
  47. /** Transmit producer index */
  48. #define VMXNET3_PT_TXPROD 0x600
  49. /** Rx producer index for ring 1 */
  50. #define VMXNET3_PT_RXPROD 0x800
  51. /** Rx producer index for ring 2 */
  52. #define VMXNET3_PT_RXPROD2 0xa00
  53. /** "VD" PCI BAR address */
  54. #define VMXNET3_VD_BAR PCI_BASE_ADDRESS_1
  55. /** "VD" PCI BAR size */
  56. #define VMXNET3_VD_LEN 0x1000
  57. /** vmxnet3 Revision Report Selection */
  58. #define VMXNET3_VD_VRRS 0x0
  59. /** UPT Version Report Selection */
  60. #define VMXNET3_VD_UVRS 0x8
  61. /** Driver Shared Address Low */
  62. #define VMXNET3_VD_DSAL 0x10
  63. /** Driver Shared Address High */
  64. #define VMXNET3_VD_DSAH 0x18
  65. /** Command */
  66. #define VMXNET3_VD_CMD 0x20
  67. /** MAC Address Low */
  68. #define VMXNET3_VD_MACL 0x28
  69. /** MAC Address High */
  70. #define VMXNET3_VD_MACH 0x30
  71. /** Interrupt Cause Register */
  72. #define VMXNET3_VD_ICR 0x38
  73. /** Event Cause Register */
  74. #define VMXNET3_VD_ECR 0x40
  75. /** Commands */
  76. enum vmxnet3_command {
  77. VMXNET3_CMD_FIRST_SET = 0xcafe0000,
  78. VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
  79. VMXNET3_CMD_QUIESCE_DEV,
  80. VMXNET3_CMD_RESET_DEV,
  81. VMXNET3_CMD_UPDATE_RX_MODE,
  82. VMXNET3_CMD_UPDATE_MAC_FILTERS,
  83. VMXNET3_CMD_UPDATE_VLAN_FILTERS,
  84. VMXNET3_CMD_UPDATE_RSSIDT,
  85. VMXNET3_CMD_UPDATE_IML,
  86. VMXNET3_CMD_UPDATE_PMCFG,
  87. VMXNET3_CMD_UPDATE_FEATURE,
  88. VMXNET3_CMD_LOAD_PLUGIN,
  89. VMXNET3_CMD_FIRST_GET = 0xf00d0000,
  90. VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
  91. VMXNET3_CMD_GET_STATS,
  92. VMXNET3_CMD_GET_LINK,
  93. VMXNET3_CMD_GET_PERM_MAC_LO,
  94. VMXNET3_CMD_GET_PERM_MAC_HI,
  95. VMXNET3_CMD_GET_DID_LO,
  96. VMXNET3_CMD_GET_DID_HI,
  97. VMXNET3_CMD_GET_DEV_EXTRA_INFO,
  98. VMXNET3_CMD_GET_CONF_INTR
  99. };
  100. /** Events */
  101. enum vmxnet3_event {
  102. VMXNET3_ECR_RQERR = 0x00000001,
  103. VMXNET3_ECR_TQERR = 0x00000002,
  104. VMXNET3_ECR_LINK = 0x00000004,
  105. VMXNET3_ECR_DIC = 0x00000008,
  106. VMXNET3_ECR_DEBUG = 0x00000010,
  107. };
  108. /** Miscellaneous configuration descriptor */
  109. struct vmxnet3_misc_config {
  110. /** Driver version */
  111. uint32_t version;
  112. /** Guest information */
  113. uint32_t guest_info;
  114. /** Version supported */
  115. uint32_t version_support;
  116. /** UPT version supported */
  117. uint32_t upt_version_support;
  118. /** UPT features supported */
  119. uint64_t upt_features;
  120. /** Driver-private data address */
  121. uint64_t driver_data_address;
  122. /** Queue descriptors data address */
  123. uint64_t queue_desc_address;
  124. /** Driver-private data length */
  125. uint32_t driver_data_len;
  126. /** Queue descriptors data length */
  127. uint32_t queue_desc_len;
  128. /** Maximum transmission unit */
  129. uint32_t mtu;
  130. /** Maximum number of RX scatter-gather */
  131. uint16_t max_num_rx_sg;
  132. /** Number of TX queues */
  133. uint8_t num_tx_queues;
  134. /** Number of RX queues */
  135. uint8_t num_rx_queues;
  136. /** Reserved */
  137. uint32_t reserved0[4];
  138. } __attribute__ (( packed ));
  139. /** Driver version magic */
  140. #define VMXNET3_VERSION_MAGIC 0x69505845
  141. /** Interrupt configuration */
  142. struct vmxnet3_interrupt_config {
  143. uint8_t mask_mode;
  144. uint8_t num_intrs;
  145. uint8_t event_intr_index;
  146. uint8_t moderation_level[VMXNET3_MAX_INTRS];
  147. uint32_t control;
  148. uint32_t reserved0[2];
  149. } __attribute__ (( packed ));
  150. /** Interrupt control - disable all interrupts */
  151. #define VMXNET3_IC_DISABLE_ALL 0x1
  152. /** Receive filter configuration */
  153. struct vmxnet3_rx_filter_config {
  154. /** Receive filter mode */
  155. uint32_t mode;
  156. /** Multicast filter table length */
  157. uint16_t multicast_len;
  158. /** Reserved */
  159. uint16_t reserved0;
  160. /** Multicast filter table address */
  161. uint64_t multicast_address;
  162. /** VLAN filter table (one bit per possible VLAN) */
  163. uint8_t vlan_filter[512];
  164. } __attribute__ (( packed ));
  165. /** Receive filter mode */
  166. enum vmxnet3_rx_filter_mode {
  167. VMXNET3_RXM_UCAST = 0x01, /**< Unicast only */
  168. VMXNET3_RXM_MCAST = 0x02, /**< Multicast passing the filters */
  169. VMXNET3_RXM_BCAST = 0x04, /**< Broadcast only */
  170. VMXNET3_RXM_ALL_MULTI = 0x08, /**< All multicast */
  171. VMXNET3_RXM_PROMISC = 0x10, /**< Promiscuous */
  172. };
  173. /** Variable-length configuration descriptor */
  174. struct vmxnet3_variable_config {
  175. uint32_t version;
  176. uint32_t length;
  177. uint64_t address;
  178. } __attribute__ (( packed ));
  179. /** Driver shared area */
  180. struct vmxnet3_shared {
  181. /** Magic signature */
  182. uint32_t magic;
  183. /** Reserved */
  184. uint32_t reserved0;
  185. /** Miscellaneous configuration */
  186. struct vmxnet3_misc_config misc;
  187. /** Interrupt configuration */
  188. struct vmxnet3_interrupt_config interrupt;
  189. /** Receive filter configuration */
  190. struct vmxnet3_rx_filter_config rx_filter;
  191. /** RSS configuration */
  192. struct vmxnet3_variable_config rss;
  193. /** Pattern-matching configuration */
  194. struct vmxnet3_variable_config pattern;
  195. /** Plugin configuration */
  196. struct vmxnet3_variable_config plugin;
  197. /** Event notifications */
  198. uint32_t ecr;
  199. /** Reserved */
  200. uint32_t reserved1[5];
  201. } __attribute__ (( packed ));
  202. /** Alignment of driver shared area */
  203. #define VMXNET3_SHARED_ALIGN 8
  204. /** Driver shared area magic */
  205. #define VMXNET3_SHARED_MAGIC 0xbabefee1
  206. /** Transmit descriptor */
  207. struct vmxnet3_tx_desc {
  208. /** Address */
  209. uint64_t address;
  210. /** Flags */
  211. uint32_t flags[2];
  212. } __attribute__ (( packed ));
  213. /** Transmit generation flag */
  214. #define VMXNET3_TXF_GEN 0x00004000UL
  215. /** Transmit end-of-packet flag */
  216. #define VMXNET3_TXF_EOP 0x000001000UL
  217. /** Transmit completion request flag */
  218. #define VMXNET3_TXF_CQ 0x000002000UL
  219. /** Transmit completion descriptor */
  220. struct vmxnet3_tx_comp {
  221. /** Index of the end-of-packet descriptor */
  222. uint32_t index;
  223. /** Reserved */
  224. uint32_t reserved0[2];
  225. /** Flags */
  226. uint32_t flags;
  227. } __attribute__ (( packed ));
  228. /** Transmit completion generation flag */
  229. #define VMXNET3_TXCF_GEN 0x80000000UL
  230. /** Transmit queue control */
  231. struct vmxnet3_tx_queue_control {
  232. uint32_t num_deferred;
  233. uint32_t threshold;
  234. uint64_t reserved0;
  235. } __attribute__ (( packed ));
  236. /** Transmit queue configuration */
  237. struct vmxnet3_tx_queue_config {
  238. /** Descriptor ring address */
  239. uint64_t desc_address;
  240. /** Data ring address */
  241. uint64_t immediate_address;
  242. /** Completion ring address */
  243. uint64_t comp_address;
  244. /** Driver-private data address */
  245. uint64_t driver_data_address;
  246. /** Reserved */
  247. uint64_t reserved0;
  248. /** Number of descriptors */
  249. uint32_t num_desc;
  250. /** Number of data descriptors */
  251. uint32_t num_immediate;
  252. /** Number of completion descriptors */
  253. uint32_t num_comp;
  254. /** Driver-private data length */
  255. uint32_t driver_data_len;
  256. /** Interrupt index */
  257. uint8_t intr_index;
  258. /** Reserved */
  259. uint8_t reserved[7];
  260. } __attribute__ (( packed ));
  261. /** Transmit queue statistics */
  262. struct vmxnet3_tx_stats {
  263. /** Reserved */
  264. uint64_t reserved[10];
  265. } __attribute__ (( packed ));
  266. /** Receive descriptor */
  267. struct vmxnet3_rx_desc {
  268. /** Address */
  269. uint64_t address;
  270. /** Flags */
  271. uint32_t flags;
  272. /** Reserved */
  273. uint32_t reserved0;
  274. } __attribute__ (( packed ));
  275. /** Receive generation flag */
  276. #define VMXNET3_RXF_GEN 0x80000000UL
  277. /** Receive completion descriptor */
  278. struct vmxnet3_rx_comp {
  279. /** Descriptor index */
  280. uint32_t index;
  281. /** RSS hash value */
  282. uint32_t rss;
  283. /** Length */
  284. uint32_t len;
  285. /** Flags */
  286. uint32_t flags;
  287. } __attribute__ (( packed ));
  288. /** Receive completion generation flag */
  289. #define VMXNET3_RXCF_GEN 0x80000000UL
  290. /** Receive queue control */
  291. struct vmxnet3_rx_queue_control {
  292. uint8_t update_prod;
  293. uint8_t reserved0[7];
  294. uint64_t reserved1;
  295. } __attribute__ (( packed ));
  296. /** Receive queue configuration */
  297. struct vmxnet3_rx_queue_config {
  298. /** Descriptor ring addresses */
  299. uint64_t desc_address[2];
  300. /** Completion ring address */
  301. uint64_t comp_address;
  302. /** Driver-private data address */
  303. uint64_t driver_data_address;
  304. /** Reserved */
  305. uint64_t reserved0;
  306. /** Number of descriptors */
  307. uint32_t num_desc[2];
  308. /** Number of completion descriptors */
  309. uint32_t num_comp;
  310. /** Driver-private data length */
  311. uint32_t driver_data_len;
  312. /** Interrupt index */
  313. uint8_t intr_index;
  314. /** Reserved */
  315. uint8_t reserved[7];
  316. } __attribute__ (( packed ));
  317. /** Receive queue statistics */
  318. struct vmxnet3_rx_stats {
  319. /** Reserved */
  320. uint64_t reserved[10];
  321. } __attribute__ (( packed ));
  322. /** Queue status */
  323. struct vmxnet3_queue_status {
  324. uint8_t stopped;
  325. uint8_t reserved0[3];
  326. uint32_t error;
  327. } __attribute__ (( packed ));
  328. /** Transmit queue descriptor */
  329. struct vmxnet3_tx_queue {
  330. struct vmxnet3_tx_queue_control ctrl;
  331. struct vmxnet3_tx_queue_config cfg;
  332. struct vmxnet3_queue_status status;
  333. struct vmxnet3_tx_stats state;
  334. uint8_t reserved[88];
  335. } __attribute__ (( packed ));
  336. /** Receive queue descriptor */
  337. struct vmxnet3_rx_queue {
  338. struct vmxnet3_rx_queue_control ctrl;
  339. struct vmxnet3_rx_queue_config cfg;
  340. struct vmxnet3_queue_status status;
  341. struct vmxnet3_rx_stats stats;
  342. uint8_t reserved[88];
  343. } __attribute__ (( packed ));
  344. /**
  345. * Queue descriptor set
  346. *
  347. * We use only a single TX and RX queue
  348. */
  349. struct vmxnet3_queues {
  350. /** Transmit queue descriptor(s) */
  351. struct vmxnet3_tx_queue tx;
  352. /** Receive queue descriptor(s) */
  353. struct vmxnet3_rx_queue rx;
  354. } __attribute__ (( packed ));
  355. /** Alignment of queue descriptor set */
  356. #define VMXNET3_QUEUES_ALIGN 128
  357. /** Alignment of rings */
  358. #define VMXNET3_RING_ALIGN 512
  359. /** Number of TX descriptors */
  360. #define VMXNET3_NUM_TX_DESC 32
  361. /** Number of TX completion descriptors */
  362. #define VMXNET3_NUM_TX_COMP 32
  363. /** Number of RX descriptors */
  364. #define VMXNET3_NUM_RX_DESC 32
  365. /** Number of RX completion descriptors */
  366. #define VMXNET3_NUM_RX_COMP 32
  367. /**
  368. * DMA areas
  369. *
  370. * These are arranged in order of decreasing alignment, to allow for a
  371. * single allocation
  372. */
  373. struct vmxnet3_dma {
  374. /** TX descriptor ring */
  375. struct vmxnet3_tx_desc tx_desc[VMXNET3_NUM_TX_DESC];
  376. /** TX completion ring */
  377. struct vmxnet3_tx_comp tx_comp[VMXNET3_NUM_TX_COMP];
  378. /** RX descriptor ring */
  379. struct vmxnet3_rx_desc rx_desc[VMXNET3_NUM_RX_DESC];
  380. /** RX completion ring */
  381. struct vmxnet3_rx_comp rx_comp[VMXNET3_NUM_RX_COMP];
  382. /** Queue descriptors */
  383. struct vmxnet3_queues queues;
  384. /** Shared area */
  385. struct vmxnet3_shared shared;
  386. } __attribute__ (( packed ));
  387. /** DMA area alignment */
  388. #define VMXNET3_DMA_ALIGN 512
  389. /** Producer and consumer counters */
  390. struct vmxnet3_counters {
  391. /** Transmit producer counter */
  392. unsigned int tx_prod;
  393. /** Transmit completion consumer counter */
  394. unsigned int tx_cons;
  395. /** Receive producer counter */
  396. unsigned int rx_prod;
  397. /** Receive fill level */
  398. unsigned int rx_fill;
  399. /** Receive consumer counter */
  400. unsigned int rx_cons;
  401. };
  402. /** A vmxnet3 NIC */
  403. struct vmxnet3_nic {
  404. /** "PT" register base address */
  405. void *pt;
  406. /** "VD" register base address */
  407. void *vd;
  408. /** DMA area */
  409. struct vmxnet3_dma *dma;
  410. /** Producer and consumer counters */
  411. struct vmxnet3_counters count;
  412. /** Transmit I/O buffers */
  413. struct io_buffer *tx_iobuf[VMXNET3_NUM_TX_DESC];
  414. /** Receive I/O buffers */
  415. struct io_buffer *rx_iobuf[VMXNET3_NUM_RX_DESC];
  416. };
  417. /** vmxnet3 version that we support */
  418. #define VMXNET3_VERSION_SELECT 1
  419. /** UPT version that we support */
  420. #define VMXNET3_UPT_VERSION_SELECT 1
  421. /** MTU size */
  422. #define VMXNET3_MTU ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* FCS */ )
  423. /** Transmit ring maximum fill level */
  424. #define VMXNET3_TX_FILL ( VMXNET3_NUM_TX_DESC - 1 )
  425. /** Receive ring maximum fill level */
  426. #define VMXNET3_RX_FILL 8
  427. /** Received packet alignment padding */
  428. #define NET_IP_ALIGN 2
  429. #endif /* _VMXNET3_H */