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  1. /*
  2. * Definitions for the new Marvell Yukon / SysKonnect driver.
  3. */
  4. #ifndef _SKGE_H
  5. #define _SKGE_H
  6. FILE_LICENCE ( GPL2_ONLY );
  7. /* PCI config registers */
  8. #define PCI_DEV_REG1 0x40
  9. #define PCI_PHY_COMA 0x8000000
  10. #define PCI_VIO 0x2000000
  11. #define PCI_DEV_REG2 0x44
  12. #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
  13. #define PCI_REV_DESC 1<<2 /* Reverse Descriptor bytes */
  14. #define DRV_NAME "skge"
  15. #define DRV_VERSION "1.13"
  16. #define PFX DRV_NAME " "
  17. #define NUM_TX_DESC 8
  18. #define NUM_RX_DESC 8
  19. /* mdeck used a 16 byte alignment, but datasheet says 8 bytes is sufficient */
  20. #define SKGE_RING_ALIGN 8
  21. #define RX_BUF_SIZE 1536
  22. #define PHY_RETRIES 1000
  23. #define TX_RING_SIZE ( NUM_TX_DESC * sizeof ( struct skge_rx_desc ) )
  24. #define RX_RING_SIZE ( NUM_RX_DESC * sizeof ( struct skge_tx_desc ) )
  25. #define RING_SIZE ( TX_RING_SIZE + RX_RING_SIZE )
  26. #define SKGE_REG_SIZE 0x4000
  27. #define SKGE_EEPROM_MAGIC 0x9933aabb
  28. /* Added for iPXE ------------------ */
  29. /* from ethtool.h */
  30. #define AUTONEG_DISABLE 0x00
  31. #define AUTONEG_ENABLE 0x01
  32. #define DUPLEX_HALF 0x00
  33. #define DUPLEX_FULL 0x01
  34. #define SPEED_10 10
  35. #define SPEED_100 100
  36. #define SPEED_1000 1000
  37. #define ADVERTISED_10baseT_Half (1 << 0)
  38. #define ADVERTISED_10baseT_Full (1 << 1)
  39. #define ADVERTISED_100baseT_Half (1 << 2)
  40. #define ADVERTISED_100baseT_Full (1 << 3)
  41. #define ADVERTISED_1000baseT_Half (1 << 4)
  42. #define ADVERTISED_1000baseT_Full (1 << 5)
  43. #define SUPPORTED_10baseT_Half (1 << 0)
  44. #define SUPPORTED_10baseT_Full (1 << 1)
  45. #define SUPPORTED_100baseT_Half (1 << 2)
  46. #define SUPPORTED_100baseT_Full (1 << 3)
  47. #define SUPPORTED_1000baseT_Half (1 << 4)
  48. #define SUPPORTED_1000baseT_Full (1 << 5)
  49. #define SUPPORTED_Autoneg (1 << 6)
  50. #define SUPPORTED_TP (1 << 7)
  51. #define SUPPORTED_FIBRE (1 << 10)
  52. /* ----------------------------------- */
  53. #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
  54. PCI_STATUS_SIG_SYSTEM_ERROR | \
  55. PCI_STATUS_REC_MASTER_ABORT | \
  56. PCI_STATUS_REC_TARGET_ABORT | \
  57. PCI_STATUS_PARITY)
  58. enum csr_regs {
  59. B0_RAP = 0x0000,
  60. B0_CTST = 0x0004,
  61. B0_LED = 0x0006,
  62. B0_POWER_CTRL = 0x0007,
  63. B0_ISRC = 0x0008,
  64. B0_IMSK = 0x000c,
  65. B0_HWE_ISRC = 0x0010,
  66. B0_HWE_IMSK = 0x0014,
  67. B0_SP_ISRC = 0x0018,
  68. B0_XM1_IMSK = 0x0020,
  69. B0_XM1_ISRC = 0x0028,
  70. B0_XM1_PHY_ADDR = 0x0030,
  71. B0_XM1_PHY_DATA = 0x0034,
  72. B0_XM2_IMSK = 0x0040,
  73. B0_XM2_ISRC = 0x0048,
  74. B0_XM2_PHY_ADDR = 0x0050,
  75. B0_XM2_PHY_DATA = 0x0054,
  76. B0_R1_CSR = 0x0060,
  77. B0_R2_CSR = 0x0064,
  78. B0_XS1_CSR = 0x0068,
  79. B0_XA1_CSR = 0x006c,
  80. B0_XS2_CSR = 0x0070,
  81. B0_XA2_CSR = 0x0074,
  82. B2_MAC_1 = 0x0100,
  83. B2_MAC_2 = 0x0108,
  84. B2_MAC_3 = 0x0110,
  85. B2_CONN_TYP = 0x0118,
  86. B2_PMD_TYP = 0x0119,
  87. B2_MAC_CFG = 0x011a,
  88. B2_CHIP_ID = 0x011b,
  89. B2_E_0 = 0x011c,
  90. B2_E_1 = 0x011d,
  91. B2_E_2 = 0x011e,
  92. B2_E_3 = 0x011f,
  93. B2_FAR = 0x0120,
  94. B2_FDP = 0x0124,
  95. B2_LD_CTRL = 0x0128,
  96. B2_LD_TEST = 0x0129,
  97. B2_TI_INI = 0x0130,
  98. B2_TI_VAL = 0x0134,
  99. B2_TI_CTRL = 0x0138,
  100. B2_TI_TEST = 0x0139,
  101. B2_IRQM_INI = 0x0140,
  102. B2_IRQM_VAL = 0x0144,
  103. B2_IRQM_CTRL = 0x0148,
  104. B2_IRQM_TEST = 0x0149,
  105. B2_IRQM_MSK = 0x014c,
  106. B2_IRQM_HWE_MSK = 0x0150,
  107. B2_TST_CTRL1 = 0x0158,
  108. B2_TST_CTRL2 = 0x0159,
  109. B2_GP_IO = 0x015c,
  110. B2_I2C_CTRL = 0x0160,
  111. B2_I2C_DATA = 0x0164,
  112. B2_I2C_IRQ = 0x0168,
  113. B2_I2C_SW = 0x016c,
  114. B2_BSC_INI = 0x0170,
  115. B2_BSC_VAL = 0x0174,
  116. B2_BSC_CTRL = 0x0178,
  117. B2_BSC_STAT = 0x0179,
  118. B2_BSC_TST = 0x017a,
  119. B3_RAM_ADDR = 0x0180,
  120. B3_RAM_DATA_LO = 0x0184,
  121. B3_RAM_DATA_HI = 0x0188,
  122. B3_RI_WTO_R1 = 0x0190,
  123. B3_RI_WTO_XA1 = 0x0191,
  124. B3_RI_WTO_XS1 = 0x0192,
  125. B3_RI_RTO_R1 = 0x0193,
  126. B3_RI_RTO_XA1 = 0x0194,
  127. B3_RI_RTO_XS1 = 0x0195,
  128. B3_RI_WTO_R2 = 0x0196,
  129. B3_RI_WTO_XA2 = 0x0197,
  130. B3_RI_WTO_XS2 = 0x0198,
  131. B3_RI_RTO_R2 = 0x0199,
  132. B3_RI_RTO_XA2 = 0x019a,
  133. B3_RI_RTO_XS2 = 0x019b,
  134. B3_RI_TO_VAL = 0x019c,
  135. B3_RI_CTRL = 0x01a0,
  136. B3_RI_TEST = 0x01a2,
  137. B3_MA_TOINI_RX1 = 0x01b0,
  138. B3_MA_TOINI_RX2 = 0x01b1,
  139. B3_MA_TOINI_TX1 = 0x01b2,
  140. B3_MA_TOINI_TX2 = 0x01b3,
  141. B3_MA_TOVAL_RX1 = 0x01b4,
  142. B3_MA_TOVAL_RX2 = 0x01b5,
  143. B3_MA_TOVAL_TX1 = 0x01b6,
  144. B3_MA_TOVAL_TX2 = 0x01b7,
  145. B3_MA_TO_CTRL = 0x01b8,
  146. B3_MA_TO_TEST = 0x01ba,
  147. B3_MA_RCINI_RX1 = 0x01c0,
  148. B3_MA_RCINI_RX2 = 0x01c1,
  149. B3_MA_RCINI_TX1 = 0x01c2,
  150. B3_MA_RCINI_TX2 = 0x01c3,
  151. B3_MA_RCVAL_RX1 = 0x01c4,
  152. B3_MA_RCVAL_RX2 = 0x01c5,
  153. B3_MA_RCVAL_TX1 = 0x01c6,
  154. B3_MA_RCVAL_TX2 = 0x01c7,
  155. B3_MA_RC_CTRL = 0x01c8,
  156. B3_MA_RC_TEST = 0x01ca,
  157. B3_PA_TOINI_RX1 = 0x01d0,
  158. B3_PA_TOINI_RX2 = 0x01d4,
  159. B3_PA_TOINI_TX1 = 0x01d8,
  160. B3_PA_TOINI_TX2 = 0x01dc,
  161. B3_PA_TOVAL_RX1 = 0x01e0,
  162. B3_PA_TOVAL_RX2 = 0x01e4,
  163. B3_PA_TOVAL_TX1 = 0x01e8,
  164. B3_PA_TOVAL_TX2 = 0x01ec,
  165. B3_PA_CTRL = 0x01f0,
  166. B3_PA_TEST = 0x01f2,
  167. };
  168. /* B0_CTST 16 bit Control/Status register */
  169. enum {
  170. CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
  171. CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
  172. CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
  173. CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
  174. CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
  175. CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
  176. CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
  177. CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
  178. CS_STOP_DONE = 1<<5, /* Stop Master is finished */
  179. CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
  180. CS_MRST_CLR = 1<<3, /* Clear Master reset */
  181. CS_MRST_SET = 1<<2, /* Set Master reset */
  182. CS_RST_CLR = 1<<1, /* Clear Software reset */
  183. CS_RST_SET = 1, /* Set Software reset */
  184. /* B0_LED 8 Bit LED register */
  185. /* Bit 7.. 2: reserved */
  186. LED_STAT_ON = 1<<1, /* Status LED on */
  187. LED_STAT_OFF = 1, /* Status LED off */
  188. /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
  189. PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
  190. PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
  191. PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
  192. PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
  193. PC_VAUX_ON = 1<<3, /* Switch VAUX On */
  194. PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
  195. PC_VCC_ON = 1<<1, /* Switch VCC On */
  196. PC_VCC_OFF = 1<<0, /* Switch VCC Off */
  197. };
  198. /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
  199. enum {
  200. IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
  201. IS_HW_ERR = 1<<31, /* Interrupt HW Error */
  202. /* Bit 30: reserved */
  203. IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
  204. IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
  205. IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
  206. IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
  207. IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
  208. IS_IRQ_SW = 1<<24, /* SW forced IRQ */
  209. IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
  210. /* IRQ from PHY (YUKON only) */
  211. IS_TIMINT = 1<<22, /* IRQ from Timer */
  212. IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
  213. IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
  214. IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
  215. IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
  216. /* Receive Queue 1 */
  217. IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
  218. IS_R1_F = 1<<16, /* Q_R1 End of Frame */
  219. IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
  220. /* Receive Queue 2 */
  221. IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
  222. IS_R2_F = 1<<13, /* Q_R2 End of Frame */
  223. IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
  224. /* Synchronous Transmit Queue 1 */
  225. IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
  226. IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
  227. IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
  228. /* Asynchronous Transmit Queue 1 */
  229. IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
  230. IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
  231. IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
  232. /* Synchronous Transmit Queue 2 */
  233. IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
  234. IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
  235. IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
  236. /* Asynchronous Transmit Queue 2 */
  237. IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
  238. IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
  239. IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
  240. IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
  241. IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
  242. IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
  243. IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
  244. };
  245. /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
  246. enum {
  247. IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
  248. IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
  249. IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
  250. IS_IRQ_STAT = 1<<10, /* IRQ status exception */
  251. IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
  252. IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
  253. IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
  254. IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
  255. IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
  256. IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
  257. IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
  258. IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
  259. IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
  260. IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
  261. IS_ERR_MSK = IS_IRQ_MST_ERR | IS_IRQ_STAT
  262. | IS_RAM_RD_PAR | IS_RAM_WR_PAR
  263. | IS_M1_PAR_ERR | IS_M2_PAR_ERR
  264. | IS_R1_PAR_ERR | IS_R2_PAR_ERR,
  265. };
  266. /* B2_TST_CTRL1 8 bit Test Control Register 1 */
  267. enum {
  268. TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
  269. TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
  270. TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
  271. TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
  272. TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
  273. TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
  274. TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
  275. TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
  276. };
  277. /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
  278. enum {
  279. CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
  280. /* Bit 3.. 2: reserved */
  281. CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
  282. CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
  283. };
  284. /* B2_CHIP_ID 8 bit Chip Identification Number */
  285. enum {
  286. CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
  287. CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
  288. CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
  289. CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
  290. CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
  291. CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
  292. CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
  293. CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
  294. CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
  295. };
  296. /* B2_TI_CTRL 8 bit Timer control */
  297. /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
  298. enum {
  299. TIM_START = 1<<2, /* Start Timer */
  300. TIM_STOP = 1<<1, /* Stop Timer */
  301. TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
  302. };
  303. /* B2_TI_TEST 8 Bit Timer Test */
  304. /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
  305. /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
  306. enum {
  307. TIM_T_ON = 1<<2, /* Test mode on */
  308. TIM_T_OFF = 1<<1, /* Test mode off */
  309. TIM_T_STEP = 1<<0, /* Test step */
  310. };
  311. /* B2_GP_IO 32 bit General Purpose I/O Register */
  312. enum {
  313. GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
  314. GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
  315. GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
  316. GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
  317. GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
  318. GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
  319. GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
  320. GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
  321. GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
  322. GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
  323. GP_IO_9 = 1<<9, /* IO_9 pin */
  324. GP_IO_8 = 1<<8, /* IO_8 pin */
  325. GP_IO_7 = 1<<7, /* IO_7 pin */
  326. GP_IO_6 = 1<<6, /* IO_6 pin */
  327. GP_IO_5 = 1<<5, /* IO_5 pin */
  328. GP_IO_4 = 1<<4, /* IO_4 pin */
  329. GP_IO_3 = 1<<3, /* IO_3 pin */
  330. GP_IO_2 = 1<<2, /* IO_2 pin */
  331. GP_IO_1 = 1<<1, /* IO_1 pin */
  332. GP_IO_0 = 1<<0, /* IO_0 pin */
  333. };
  334. /* Descriptor Bit Definition */
  335. /* TxCtrl Transmit Buffer Control Field */
  336. /* RxCtrl Receive Buffer Control Field */
  337. enum {
  338. BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
  339. BMU_STF = 1<<30, /* Start of Frame */
  340. BMU_EOF = 1<<29, /* End of Frame */
  341. BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
  342. BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
  343. /* TxCtrl specific bits */
  344. BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
  345. BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
  346. BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
  347. /* RxCtrl specific bits */
  348. BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
  349. BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
  350. BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
  351. /* Bit 23..16: BMU Check Opcodes */
  352. BMU_CHECK = 0x55<<16, /* Default BMU check */
  353. BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
  354. BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
  355. BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
  356. };
  357. /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
  358. enum {
  359. BSC_START = 1<<1, /* Start Blink Source Counter */
  360. BSC_STOP = 1<<0, /* Stop Blink Source Counter */
  361. };
  362. /* B2_BSC_STAT 8 bit Blink Source Counter Status */
  363. enum {
  364. BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
  365. };
  366. /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
  367. enum {
  368. BSC_T_ON = 1<<2, /* Test mode on */
  369. BSC_T_OFF = 1<<1, /* Test mode off */
  370. BSC_T_STEP = 1<<0, /* Test step */
  371. };
  372. /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
  373. /* Bit 31..19: reserved */
  374. #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
  375. /* RAM Interface Registers */
  376. /* B3_RI_CTRL 16 bit RAM Iface Control Register */
  377. enum {
  378. RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
  379. RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
  380. RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
  381. RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
  382. };
  383. /* MAC Arbiter Registers */
  384. /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
  385. enum {
  386. MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
  387. MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
  388. MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
  389. MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
  390. };
  391. /* Timeout values */
  392. #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
  393. #define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
  394. #define SK_PKT_TO_MAX 0xffff /* Maximum value */
  395. #define SK_RI_TO_53 36 /* RAM interface timeout */
  396. /* Packet Arbiter Registers */
  397. /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
  398. enum {
  399. PA_CLR_TO_TX2 = 1<<13,/* Clear IRQ Packet Timeout TX2 */
  400. PA_CLR_TO_TX1 = 1<<12,/* Clear IRQ Packet Timeout TX1 */
  401. PA_CLR_TO_RX2 = 1<<11,/* Clear IRQ Packet Timeout RX2 */
  402. PA_CLR_TO_RX1 = 1<<10,/* Clear IRQ Packet Timeout RX1 */
  403. PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
  404. PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
  405. PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
  406. PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
  407. PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
  408. PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
  409. PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
  410. PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
  411. PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
  412. PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
  413. };
  414. #define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
  415. PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
  416. /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
  417. /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
  418. /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
  419. /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
  420. /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
  421. #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
  422. /* TXA_CTRL 8 bit Tx Arbiter Control Register */
  423. enum {
  424. TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
  425. TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
  426. TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
  427. TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
  428. TXA_START_RC = 1<<3, /* Start sync Rate Control */
  429. TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
  430. TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
  431. TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
  432. };
  433. /*
  434. * Bank 4 - 5
  435. */
  436. /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
  437. enum {
  438. TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
  439. TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
  440. TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
  441. TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
  442. TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
  443. TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
  444. TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
  445. };
  446. enum {
  447. B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
  448. B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
  449. B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
  450. B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
  451. B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
  452. B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
  453. B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
  454. B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
  455. B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
  456. };
  457. /* Queue Register Offsets, use Q_ADDR() to access */
  458. enum {
  459. B8_Q_REGS = 0x0400, /* base of Queue registers */
  460. Q_D = 0x00, /* 8*32 bit Current Descriptor */
  461. Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
  462. Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
  463. Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
  464. Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
  465. Q_BC = 0x30, /* 32 bit Current Byte Counter */
  466. Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
  467. Q_F = 0x38, /* 32 bit Flag Register */
  468. Q_T1 = 0x3c, /* 32 bit Test Register 1 */
  469. Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
  470. Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
  471. Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
  472. Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
  473. Q_T2 = 0x40, /* 32 bit Test Register 2 */
  474. Q_T3 = 0x44, /* 32 bit Test Register 3 */
  475. };
  476. #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
  477. /* RAM Buffer Register Offsets */
  478. enum {
  479. RB_START= 0x00,/* 32 bit RAM Buffer Start Address */
  480. RB_END = 0x04,/* 32 bit RAM Buffer End Address */
  481. RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
  482. RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
  483. RB_RX_UTPP= 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
  484. RB_RX_LTPP= 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
  485. RB_RX_UTHP= 0x18,/* 32 bit Rx Upper Threshold, High Prio */
  486. RB_RX_LTHP= 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
  487. /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
  488. RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
  489. RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
  490. RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
  491. RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
  492. RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
  493. };
  494. /* Receive and Transmit Queues */
  495. enum {
  496. Q_R1 = 0x0000, /* Receive Queue 1 */
  497. Q_R2 = 0x0080, /* Receive Queue 2 */
  498. Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
  499. Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
  500. Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
  501. Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
  502. };
  503. /* Different MAC Types */
  504. enum {
  505. SK_MAC_XMAC = 0, /* Xaqti XMAC II */
  506. SK_MAC_GMAC = 1, /* Marvell GMAC */
  507. };
  508. /* Different PHY Types */
  509. enum {
  510. SK_PHY_XMAC = 0,/* integrated in XMAC II */
  511. SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
  512. SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
  513. SK_PHY_NAT = 3,/* National DP83891 [not supported] */
  514. SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
  515. SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
  516. };
  517. /* PHY addresses (bits 12..8 of PHY address reg) */
  518. enum {
  519. PHY_ADDR_XMAC = 0<<8,
  520. PHY_ADDR_BCOM = 1<<8,
  521. /* GPHY address (bits 15..11 of SMI control reg) */
  522. PHY_ADDR_MARV = 0,
  523. };
  524. #define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
  525. /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
  526. enum {
  527. RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
  528. RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
  529. RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
  530. RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
  531. RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
  532. RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
  533. RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
  534. RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
  535. RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
  536. RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
  537. RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
  538. RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
  539. RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
  540. RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
  541. RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
  542. LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
  543. LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
  544. LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
  545. LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
  546. LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
  547. };
  548. /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
  549. /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
  550. enum {
  551. MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
  552. MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
  553. MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
  554. MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
  555. MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
  556. MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
  557. MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
  558. MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
  559. MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
  560. MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
  561. MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
  562. MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
  563. MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
  564. MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
  565. MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
  566. };
  567. /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
  568. enum {
  569. MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
  570. MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
  571. MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
  572. MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
  573. MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
  574. MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
  575. MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
  576. MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
  577. MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
  578. MFF_TX_CTRL_DEF = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
  579. };
  580. /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
  581. /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
  582. enum {
  583. MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
  584. MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
  585. MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
  586. MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
  587. MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
  588. MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
  589. MFF_PC_INC = 1<<0, /* Packet Counter Increment */
  590. };
  591. /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
  592. /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
  593. enum {
  594. MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
  595. MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
  596. MFF_WP_INC = 1<<4, /* Write Pointer Increm */
  597. MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
  598. MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
  599. MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
  600. };
  601. /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
  602. /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
  603. enum {
  604. MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
  605. MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
  606. MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
  607. MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
  608. };
  609. /* Link LED Counter Registers (GENESIS only) */
  610. /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
  611. /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
  612. /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
  613. enum {
  614. LED_START = 1<<2, /* Start Timer */
  615. LED_STOP = 1<<1, /* Stop Timer */
  616. LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
  617. };
  618. /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
  619. /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
  620. /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
  621. enum {
  622. LED_T_ON = 1<<2, /* LED Counter Test mode On */
  623. LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
  624. LED_T_STEP = 1<<0, /* LED Counter Step */
  625. };
  626. /* LNK_LED_REG 8 bit Link LED Register */
  627. enum {
  628. LED_BLK_ON = 1<<5, /* Link LED Blinking On */
  629. LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
  630. LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
  631. LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
  632. LED_ON = 1<<1, /* switch LED on */
  633. LED_OFF = 1<<0, /* switch LED off */
  634. };
  635. /* Receive GMAC FIFO (YUKON) */
  636. enum {
  637. RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
  638. RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
  639. RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
  640. RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
  641. RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
  642. RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
  643. RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
  644. RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
  645. RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
  646. };
  647. /* TXA_TEST 8 bit Tx Arbiter Test Register */
  648. enum {
  649. TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
  650. TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
  651. TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
  652. TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
  653. TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
  654. TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
  655. };
  656. /* TXA_STAT 8 bit Tx Arbiter Status Register */
  657. enum {
  658. TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
  659. };
  660. /* Q_BC 32 bit Current Byte Counter */
  661. /* BMU Control Status Registers */
  662. /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
  663. /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
  664. /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
  665. /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
  666. /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
  667. /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
  668. /* Q_CSR 32 bit BMU Control/Status Register */
  669. enum {
  670. CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
  671. CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
  672. CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
  673. CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
  674. CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
  675. CSR_HPI_RUN = 1<<17, /* Release HPI SM */
  676. CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
  677. CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
  678. CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
  679. CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
  680. CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
  681. CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
  682. CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
  683. CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
  684. CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
  685. CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
  686. CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
  687. CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
  688. CSR_START = 1<<4, /* Start Rx/Tx Queue */
  689. CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
  690. CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
  691. CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
  692. CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
  693. };
  694. #define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
  695. CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
  696. CSR_TRANS_RST)
  697. #define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
  698. CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
  699. CSR_TRANS_RUN)
  700. /* Q_F 32 bit Flag Register */
  701. enum {
  702. F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
  703. F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
  704. F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
  705. F_WM_REACHED = 1<<25, /* Watermark reached */
  706. F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
  707. F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
  708. };
  709. /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
  710. /* RB_START 32 bit RAM Buffer Start Address */
  711. /* RB_END 32 bit RAM Buffer End Address */
  712. /* RB_WP 32 bit RAM Buffer Write Pointer */
  713. /* RB_RP 32 bit RAM Buffer Read Pointer */
  714. /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
  715. /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
  716. /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
  717. /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
  718. /* RB_PC 32 bit RAM Buffer Packet Counter */
  719. /* RB_LEV 32 bit RAM Buffer Level Register */
  720. #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
  721. /* RB_TST2 8 bit RAM Buffer Test Register 2 */
  722. /* RB_TST1 8 bit RAM Buffer Test Register 1 */
  723. /* RB_CTRL 8 bit RAM Buffer Control Register */
  724. enum {
  725. RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
  726. RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
  727. RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
  728. RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
  729. RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
  730. RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
  731. };
  732. /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
  733. enum {
  734. TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
  735. TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
  736. TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
  737. TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
  738. TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
  739. TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
  740. TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
  741. TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
  742. TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
  743. TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
  744. TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
  745. TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
  746. TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
  747. TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
  748. TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
  749. };
  750. /* Counter and Timer constants, for a host clock of 62.5 MHz */
  751. #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
  752. #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
  753. #define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
  754. #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
  755. /* 215 ms at 78.12 MHz */
  756. #define SK_FACT_62 100 /* is given in percent */
  757. #define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
  758. #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
  759. /* Transmit GMAC FIFO (YUKON only) */
  760. enum {
  761. TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
  762. TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
  763. TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
  764. TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
  765. TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
  766. TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
  767. TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
  768. TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
  769. TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
  770. /* Descriptor Poll Timer Registers */
  771. B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
  772. B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
  773. B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
  774. B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
  775. /* Time Stamp Timer Registers (YUKON only) */
  776. GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
  777. GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
  778. GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
  779. };
  780. enum {
  781. LINKLED_OFF = 0x01,
  782. LINKLED_ON = 0x02,
  783. LINKLED_LINKSYNC_OFF = 0x04,
  784. LINKLED_LINKSYNC_ON = 0x08,
  785. LINKLED_BLINK_OFF = 0x10,
  786. LINKLED_BLINK_ON = 0x20,
  787. };
  788. /* GMAC and GPHY Control Registers (YUKON only) */
  789. enum {
  790. GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
  791. GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
  792. GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
  793. GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
  794. GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
  795. /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
  796. WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
  797. WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
  798. WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
  799. WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
  800. WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
  801. WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
  802. /* WOL Pattern Length Registers (YUKON only) */
  803. WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
  804. WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
  805. /* WOL Pattern Counter Registers (YUKON only) */
  806. WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
  807. WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
  808. };
  809. #define WOL_REGS(port, x) (x + (port)*0x80)
  810. enum {
  811. WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
  812. WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
  813. };
  814. #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
  815. enum {
  816. BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
  817. BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
  818. BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
  819. BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
  820. };
  821. /*
  822. * Receive Frame Status Encoding
  823. */
  824. enum {
  825. XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
  826. XMR_FS_LEN_SHIFT = 18,
  827. XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
  828. XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
  829. XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
  830. XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
  831. XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
  832. XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
  833. XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
  834. XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
  835. XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
  836. XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
  837. XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
  838. XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
  839. XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
  840. XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
  841. XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
  842. XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
  843. XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
  844. /*
  845. * XMR_FS_ERR will be set if
  846. * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
  847. * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
  848. * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
  849. * XMR_FS_ERR unless the corresponding bit in the Receive Command
  850. * Register is set.
  851. */
  852. };
  853. /*
  854. ,* XMAC-PHY Registers, indirect addressed over the XMAC
  855. */
  856. enum {
  857. PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
  858. PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
  859. PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
  860. PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
  861. PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
  862. PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
  863. PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
  864. PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
  865. PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
  866. PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
  867. PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
  868. };
  869. /*
  870. * Broadcom-PHY Registers, indirect addressed over XMAC
  871. */
  872. enum {
  873. PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
  874. PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
  875. PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
  876. PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
  877. PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
  878. PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
  879. PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
  880. PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
  881. PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
  882. /* Broadcom-specific registers */
  883. PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
  884. PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
  885. PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
  886. PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
  887. PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
  888. PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
  889. PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
  890. PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
  891. PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
  892. PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
  893. PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
  894. PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
  895. };
  896. /*
  897. * Marvel-PHY Registers, indirect addressed over GMAC
  898. */
  899. enum {
  900. PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
  901. PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
  902. PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
  903. PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
  904. PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
  905. PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
  906. PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
  907. PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
  908. PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
  909. /* Marvel-specific registers */
  910. PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
  911. PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
  912. PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
  913. PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
  914. PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
  915. PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
  916. PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
  917. PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
  918. PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
  919. PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
  920. PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
  921. PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
  922. PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
  923. PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
  924. PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
  925. PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
  926. PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
  927. PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
  928. /* for 10/100 Fast Ethernet PHY (88E3082 only) */
  929. PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
  930. PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
  931. PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
  932. PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
  933. PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
  934. };
  935. enum {
  936. PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
  937. PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
  938. PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
  939. PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
  940. PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
  941. PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
  942. PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
  943. PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
  944. PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
  945. PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
  946. };
  947. enum {
  948. PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
  949. PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
  950. PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
  951. };
  952. enum {
  953. PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
  954. PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
  955. PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
  956. PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occurred */
  957. PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
  958. PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
  959. PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
  960. PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
  961. };
  962. enum {
  963. PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
  964. PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
  965. PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
  966. };
  967. /* different Broadcom PHY Ids */
  968. enum {
  969. PHY_BCOM_ID1_A1 = 0x6041,
  970. PHY_BCOM_ID1_B2 = 0x6043,
  971. PHY_BCOM_ID1_C0 = 0x6044,
  972. PHY_BCOM_ID1_C5 = 0x6047,
  973. };
  974. /* different Marvell PHY Ids */
  975. enum {
  976. PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
  977. PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
  978. PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
  979. PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
  980. PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
  981. };
  982. /* Advertisement register bits */
  983. enum {
  984. PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
  985. PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
  986. PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
  987. PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
  988. PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
  989. PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
  990. PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
  991. PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
  992. PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
  993. PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
  994. PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
  995. PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
  996. PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
  997. PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
  998. PHY_AN_100HALF | PHY_AN_100FULL,
  999. };
  1000. /* Xmac Specific */
  1001. enum {
  1002. PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
  1003. PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
  1004. PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
  1005. PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
  1006. PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
  1007. PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
  1008. };
  1009. /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
  1010. enum {
  1011. PHY_X_P_NO_PAUSE= 0<<7,/* Bit 8..7: no Pause Mode */
  1012. PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
  1013. PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
  1014. PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
  1015. };
  1016. /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/
  1017. enum {
  1018. PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */
  1019. PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */
  1020. };
  1021. /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/
  1022. enum {
  1023. PHY_X_RS_PAUSE = 3<<7, /* Bit 8..7: selected Pause Mode */
  1024. PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
  1025. PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
  1026. PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */
  1027. PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */
  1028. };
  1029. /* Remote Fault Bits (PHY_X_AN_RFB) encoding */
  1030. enum {
  1031. X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */
  1032. X_RFB_LF = 1<<12,/* Bit 13..12 Link Failure */
  1033. X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */
  1034. X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
  1035. };
  1036. /* Broadcom-Specific */
  1037. /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
  1038. enum {
  1039. PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
  1040. PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
  1041. PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
  1042. PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
  1043. PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
  1044. PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
  1045. };
  1046. /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
  1047. /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
  1048. enum {
  1049. PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
  1050. PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
  1051. PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
  1052. PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
  1053. PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
  1054. PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
  1055. /* Bit 9..8: reserved */
  1056. PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
  1057. };
  1058. /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
  1059. enum {
  1060. PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
  1061. PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
  1062. PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
  1063. PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
  1064. };
  1065. /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
  1066. enum {
  1067. PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
  1068. PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
  1069. PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
  1070. PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
  1071. PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
  1072. PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
  1073. PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
  1074. PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
  1075. PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
  1076. PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
  1077. PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
  1078. PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
  1079. PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
  1080. PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
  1081. PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
  1082. PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
  1083. };
  1084. /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
  1085. enum {
  1086. PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
  1087. PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
  1088. PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
  1089. PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
  1090. PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
  1091. PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
  1092. PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
  1093. PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
  1094. PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
  1095. PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
  1096. PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
  1097. PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
  1098. PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
  1099. PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
  1100. };
  1101. /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
  1102. /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
  1103. enum {
  1104. PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
  1105. PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
  1106. PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
  1107. };
  1108. /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
  1109. enum {
  1110. PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
  1111. /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
  1112. PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
  1113. PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
  1114. /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
  1115. PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */
  1116. PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */
  1117. PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */
  1118. /* Bit 11: reserved */
  1119. PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
  1120. /* Bit 9.. 8: reserved */
  1121. PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */
  1122. /* Bit 6: reserved */
  1123. PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
  1124. /* Bit 4: reserved */
  1125. PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
  1126. };
  1127. /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
  1128. enum {
  1129. PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */
  1130. PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */
  1131. PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */
  1132. PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */
  1133. PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
  1134. PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */
  1135. PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */
  1136. PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */
  1137. PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
  1138. PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */
  1139. PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */
  1140. PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */
  1141. PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
  1142. PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
  1143. };
  1144. #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
  1145. /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
  1146. /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
  1147. enum {
  1148. PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */
  1149. PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */
  1150. PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */
  1151. PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
  1152. PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */
  1153. PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */
  1154. PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */
  1155. PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */
  1156. PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */
  1157. PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
  1158. PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */
  1159. PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
  1160. PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */
  1161. PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
  1162. PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
  1163. };
  1164. #define PHY_B_DEF_MSK \
  1165. (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
  1166. PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
  1167. /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
  1168. enum {
  1169. PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
  1170. PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
  1171. PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
  1172. PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
  1173. };
  1174. /*
  1175. * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
  1176. */
  1177. enum {
  1178. PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
  1179. PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
  1180. };
  1181. /** Marvell-Specific */
  1182. enum {
  1183. PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
  1184. PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
  1185. PHY_M_AN_RF = 1<<13, /* Remote Fault */
  1186. PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
  1187. PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
  1188. PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
  1189. PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
  1190. PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
  1191. PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
  1192. PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
  1193. PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
  1194. };
  1195. /* special defines for FIBER (88E1011S only) */
  1196. enum {
  1197. PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
  1198. PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
  1199. PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
  1200. PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
  1201. };
  1202. /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
  1203. enum {
  1204. PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
  1205. PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
  1206. PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
  1207. PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
  1208. };
  1209. /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
  1210. enum {
  1211. PHY_M_1000C_TEST= 7<<13,/* Bit 15..13: Test Modes */
  1212. PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
  1213. PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
  1214. PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
  1215. PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
  1216. PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
  1217. };
  1218. /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
  1219. enum {
  1220. PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
  1221. PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
  1222. PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
  1223. PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
  1224. PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
  1225. PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
  1226. PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
  1227. PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
  1228. PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
  1229. PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
  1230. PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
  1231. PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
  1232. };
  1233. enum {
  1234. PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
  1235. PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
  1236. };
  1237. enum {
  1238. PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
  1239. PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
  1240. PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
  1241. };
  1242. /* for 10/100 Fast Ethernet PHY (88E3082 only) */
  1243. enum {
  1244. PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
  1245. PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
  1246. PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
  1247. PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
  1248. PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
  1249. PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
  1250. PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
  1251. PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
  1252. PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
  1253. };
  1254. /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
  1255. enum {
  1256. PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
  1257. PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
  1258. PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
  1259. PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
  1260. PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
  1261. PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
  1262. PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
  1263. PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
  1264. PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
  1265. PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
  1266. PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
  1267. PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
  1268. PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
  1269. PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
  1270. PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
  1271. PHY_M_PS_JABBER = 1<<0, /* Jabber */
  1272. };
  1273. #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
  1274. /* for 10/100 Fast Ethernet PHY (88E3082 only) */
  1275. enum {
  1276. PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
  1277. PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
  1278. };
  1279. enum {
  1280. PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
  1281. PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
  1282. PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
  1283. PHY_M_IS_AN_PR = 1<<12, /* Page Received */
  1284. PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
  1285. PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
  1286. PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
  1287. PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
  1288. PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
  1289. PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
  1290. PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
  1291. PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
  1292. PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
  1293. PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
  1294. PHY_M_IS_JABBER = 1<<0, /* Jabber */
  1295. PHY_M_IS_DEF_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
  1296. PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
  1297. PHY_M_IS_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
  1298. };
  1299. /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
  1300. enum {
  1301. PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
  1302. PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
  1303. PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
  1304. PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
  1305. /* (88E1011 only) */
  1306. PHY_M_EC_S_DSC_MSK = 3<<8, /* Bit 9.. 8: Slave Downshift Counter */
  1307. /* (88E1011 only) */
  1308. PHY_M_EC_M_DSC_MSK2 = 7<<9, /* Bit 11.. 9: Master Downshift Counter */
  1309. /* (88E1111 only) */
  1310. PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
  1311. /* !!! Errata in spec. (1 = disable) */
  1312. PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
  1313. PHY_M_EC_MAC_S_MSK = 7<<4, /* Bit 6.. 4: Def. MAC interface speed */
  1314. PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
  1315. PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
  1316. PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
  1317. PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
  1318. #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
  1319. #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
  1320. #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
  1321. #define PHY_M_EC_M_DSC_2(x) ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
  1322. /* 100=5x; 101=6x; 110=7x; 111=8x */
  1323. enum {
  1324. MAC_TX_CLK_0_MHZ = 2,
  1325. MAC_TX_CLK_2_5_MHZ = 6,
  1326. MAC_TX_CLK_25_MHZ = 7,
  1327. };
  1328. /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
  1329. enum {
  1330. PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
  1331. PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
  1332. PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
  1333. PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
  1334. PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
  1335. PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
  1336. PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
  1337. /* (88E1111 only) */
  1338. };
  1339. #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
  1340. #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
  1341. enum {
  1342. PHY_M_LEDC_LINK_MSK = 3<<3, /* Bit 4.. 3: Link Control Mask */
  1343. /* (88E1011 only) */
  1344. PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
  1345. PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
  1346. PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
  1347. PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
  1348. PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
  1349. };
  1350. enum {
  1351. PULS_NO_STR = 0, /* no pulse stretching */
  1352. PULS_21MS = 1, /* 21 ms to 42 ms */
  1353. PULS_42MS = 2, /* 42 ms to 84 ms */
  1354. PULS_84MS = 3, /* 84 ms to 170 ms */
  1355. PULS_170MS = 4, /* 170 ms to 340 ms */
  1356. PULS_340MS = 5, /* 340 ms to 670 ms */
  1357. PULS_670MS = 6, /* 670 ms to 1.3 s */
  1358. PULS_1300MS = 7, /* 1.3 s to 2.7 s */
  1359. };
  1360. enum {
  1361. BLINK_42MS = 0, /* 42 ms */
  1362. BLINK_84MS = 1, /* 84 ms */
  1363. BLINK_170MS = 2, /* 170 ms */
  1364. BLINK_340MS = 3, /* 340 ms */
  1365. BLINK_670MS = 4, /* 670 ms */
  1366. };
  1367. /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
  1368. #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
  1369. /* Bit 13..12: reserved */
  1370. #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
  1371. #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
  1372. #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
  1373. #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
  1374. #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
  1375. #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
  1376. enum {
  1377. MO_LED_NORM = 0,
  1378. MO_LED_BLINK = 1,
  1379. MO_LED_OFF = 2,
  1380. MO_LED_ON = 3,
  1381. };
  1382. /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
  1383. enum {
  1384. PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
  1385. PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
  1386. PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
  1387. PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
  1388. PHY_M_EC2_FO_AM_MSK = 7, /* Bit 2.. 0: Fiber Output Amplitude */
  1389. };
  1390. /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
  1391. enum {
  1392. PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
  1393. PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
  1394. PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
  1395. PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
  1396. PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
  1397. PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
  1398. PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
  1399. /* (88E1111 only) */
  1400. /* Bit 9.. 4: reserved (88E1011 only) */
  1401. PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
  1402. PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
  1403. PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
  1404. };
  1405. /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
  1406. enum {
  1407. PHY_M_CABD_ENA_TEST = 1<<15, /* Enable Test (Page 0) */
  1408. PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */
  1409. /* (88E1111 only) */
  1410. PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
  1411. PHY_M_CABD_AMPL_MSK = 0x1f<<8, /* Bit 12.. 8: Amplitude Mask */
  1412. /* (88E1111 only) */
  1413. PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
  1414. };
  1415. /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
  1416. enum {
  1417. CABD_STAT_NORMAL= 0,
  1418. CABD_STAT_SHORT = 1,
  1419. CABD_STAT_OPEN = 2,
  1420. CABD_STAT_FAIL = 3,
  1421. };
  1422. /* for 10/100 Fast Ethernet PHY (88E3082 only) */
  1423. /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
  1424. /* Bit 15..12: reserved (used internally) */
  1425. enum {
  1426. PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
  1427. PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
  1428. PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
  1429. };
  1430. #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
  1431. #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
  1432. #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
  1433. enum {
  1434. LED_PAR_CTRL_COLX = 0x00,
  1435. LED_PAR_CTRL_ERROR = 0x01,
  1436. LED_PAR_CTRL_DUPLEX = 0x02,
  1437. LED_PAR_CTRL_DP_COL = 0x03,
  1438. LED_PAR_CTRL_SPEED = 0x04,
  1439. LED_PAR_CTRL_LINK = 0x05,
  1440. LED_PAR_CTRL_TX = 0x06,
  1441. LED_PAR_CTRL_RX = 0x07,
  1442. LED_PAR_CTRL_ACT = 0x08,
  1443. LED_PAR_CTRL_LNK_RX = 0x09,
  1444. LED_PAR_CTRL_LNK_AC = 0x0a,
  1445. LED_PAR_CTRL_ACT_BL = 0x0b,
  1446. LED_PAR_CTRL_TX_BL = 0x0c,
  1447. LED_PAR_CTRL_RX_BL = 0x0d,
  1448. LED_PAR_CTRL_COL_BL = 0x0e,
  1449. LED_PAR_CTRL_INACT = 0x0f
  1450. };
  1451. /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
  1452. enum {
  1453. PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
  1454. PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
  1455. PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
  1456. };
  1457. /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
  1458. enum {
  1459. PHY_M_LEDC_LOS_MSK = 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
  1460. PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
  1461. PHY_M_LEDC_STA1_MSK = 0xf<<4, /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
  1462. PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
  1463. };
  1464. #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
  1465. #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
  1466. #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
  1467. #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
  1468. /* GMAC registers */
  1469. /* Port Registers */
  1470. enum {
  1471. GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
  1472. GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
  1473. GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
  1474. GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
  1475. GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
  1476. GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
  1477. GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
  1478. /* Source Address Registers */
  1479. GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
  1480. GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
  1481. GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
  1482. GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
  1483. GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
  1484. GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
  1485. /* Multicast Address Hash Registers */
  1486. GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
  1487. GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
  1488. GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
  1489. GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
  1490. /* Interrupt Source Registers */
  1491. GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
  1492. GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
  1493. GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
  1494. /* Interrupt Mask Registers */
  1495. GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
  1496. GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
  1497. GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
  1498. /* Serial Management Interface (SMI) Registers */
  1499. GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
  1500. GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
  1501. GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
  1502. };
  1503. /* MIB Counters */
  1504. #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
  1505. #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
  1506. /*
  1507. * MIB Counters base address definitions (low word) -
  1508. * use offset 4 for access to high word (32 bit r/o)
  1509. */
  1510. enum {
  1511. GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
  1512. GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
  1513. GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
  1514. GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
  1515. GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
  1516. /* GM_MIB_CNT_BASE + 40: reserved */
  1517. GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
  1518. GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
  1519. GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
  1520. GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
  1521. GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
  1522. GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
  1523. GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
  1524. GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
  1525. GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
  1526. GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
  1527. GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
  1528. GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
  1529. GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
  1530. GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
  1531. GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
  1532. /* GM_MIB_CNT_BASE + 168: reserved */
  1533. GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
  1534. /* GM_MIB_CNT_BASE + 184: reserved */
  1535. GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
  1536. GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
  1537. GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
  1538. GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
  1539. GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
  1540. GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
  1541. GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
  1542. GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
  1543. GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
  1544. GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
  1545. GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
  1546. GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
  1547. GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
  1548. GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
  1549. GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
  1550. GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
  1551. GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
  1552. GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
  1553. GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
  1554. };
  1555. /* GMAC Bit Definitions */
  1556. /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
  1557. enum {
  1558. GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
  1559. GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
  1560. GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
  1561. GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
  1562. GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
  1563. GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
  1564. GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occurred */
  1565. GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occurred */
  1566. GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
  1567. GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
  1568. GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
  1569. GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
  1570. GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
  1571. };
  1572. /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
  1573. enum {
  1574. GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
  1575. GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
  1576. GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
  1577. GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
  1578. GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
  1579. GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
  1580. GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
  1581. GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
  1582. GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
  1583. GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
  1584. GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
  1585. GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
  1586. GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
  1587. GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
  1588. GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
  1589. };
  1590. #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
  1591. #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
  1592. /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
  1593. enum {
  1594. GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
  1595. GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
  1596. GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
  1597. GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
  1598. };
  1599. #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
  1600. #define TX_COL_DEF 0x04 /* late collision after 64 byte */
  1601. /* GM_RX_CTRL 16 bit r/w Receive Control Register */
  1602. enum {
  1603. GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
  1604. GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
  1605. GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
  1606. GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
  1607. };
  1608. /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
  1609. enum {
  1610. GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
  1611. GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
  1612. GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
  1613. TX_JAM_LEN_DEF = 0x03,
  1614. TX_JAM_IPG_DEF = 0x0b,
  1615. TX_IPG_JAM_DEF = 0x1c,
  1616. };
  1617. #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
  1618. #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
  1619. #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
  1620. /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
  1621. enum {
  1622. GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
  1623. GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
  1624. GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
  1625. GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
  1626. GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
  1627. };
  1628. #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
  1629. #define DATA_BLIND_DEF 0x04
  1630. #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
  1631. #define IPG_DATA_DEF 0x1e
  1632. /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
  1633. enum {
  1634. GM_SMI_CT_PHY_A_MSK = 0x1f<<11, /* Bit 15..11: PHY Device Address */
  1635. GM_SMI_CT_REG_A_MSK = 0x1f<<6, /* Bit 10.. 6: PHY Register Address */
  1636. GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
  1637. GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
  1638. GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
  1639. };
  1640. #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
  1641. #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
  1642. /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
  1643. enum {
  1644. GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
  1645. GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
  1646. };
  1647. /* Receive Frame Status Encoding */
  1648. enum {
  1649. GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
  1650. GMR_FS_LEN_SHIFT = 16,
  1651. GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
  1652. GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
  1653. GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
  1654. GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
  1655. GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
  1656. GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
  1657. GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
  1658. GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
  1659. GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
  1660. GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
  1661. GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
  1662. GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
  1663. GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
  1664. /*
  1665. * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
  1666. */
  1667. GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
  1668. GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
  1669. GMR_FS_JABBER,
  1670. /* Rx GMAC FIFO Flush Mask (default) */
  1671. RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
  1672. GMR_FS_BAD_FC | GMR_FS_UN_SIZE | GMR_FS_JABBER,
  1673. };
  1674. /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
  1675. enum {
  1676. GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
  1677. GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
  1678. GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
  1679. GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
  1680. GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
  1681. GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
  1682. GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
  1683. GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
  1684. GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
  1685. GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
  1686. GMF_OPER_ON = 1<<3, /* Operational Mode On */
  1687. GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
  1688. GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
  1689. GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
  1690. RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
  1691. };
  1692. /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
  1693. enum {
  1694. GMF_WSP_TST_ON = 1<<18, /* Write Shadow Pointer Test On */
  1695. GMF_WSP_TST_OFF = 1<<17, /* Write Shadow Pointer Test Off */
  1696. GMF_WSP_STEP = 1<<16, /* Write Shadow Pointer Step/Increment */
  1697. GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
  1698. GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
  1699. GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
  1700. };
  1701. /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
  1702. enum {
  1703. GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
  1704. GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
  1705. GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
  1706. };
  1707. /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
  1708. enum {
  1709. GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
  1710. GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
  1711. GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
  1712. GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
  1713. GMC_PAUSE_ON = 1<<3, /* Pause On */
  1714. GMC_PAUSE_OFF = 1<<2, /* Pause Off */
  1715. GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
  1716. GMC_RST_SET = 1<<0, /* Set GMAC Reset */
  1717. };
  1718. /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
  1719. enum {
  1720. GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
  1721. GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
  1722. GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
  1723. GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
  1724. GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
  1725. GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
  1726. GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
  1727. GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
  1728. GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
  1729. GPC_ANEG_0 = 1<<19, /* ANEG[0] */
  1730. GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
  1731. GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
  1732. GPC_ANEG_3 = 1<<16, /* ANEG[3] */
  1733. GPC_ANEG_2 = 1<<15, /* ANEG[2] */
  1734. GPC_ANEG_1 = 1<<14, /* ANEG[1] */
  1735. GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
  1736. GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
  1737. GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
  1738. GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
  1739. GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
  1740. GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
  1741. /* Bits 7..2: reserved */
  1742. GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
  1743. GPC_RST_SET = 1<<0, /* Set GPHY Reset */
  1744. };
  1745. #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
  1746. #define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
  1747. #define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
  1748. /* forced speed and duplex mode (don't mix with other ANEG bits) */
  1749. #define GPC_FRC10MBIT_HALF 0
  1750. #define GPC_FRC10MBIT_FULL GPC_ANEG_0
  1751. #define GPC_FRC100MBIT_HALF GPC_ANEG_1
  1752. #define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1)
  1753. /* auto-negotiation with limited advertised speeds */
  1754. /* mix only with master/slave settings (for copper) */
  1755. #define GPC_ADV_1000_HALF GPC_ANEG_2
  1756. #define GPC_ADV_1000_FULL GPC_ANEG_3
  1757. #define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3)
  1758. /* master/slave settings */
  1759. /* only for copper with 1000 Mbps */
  1760. #define GPC_FORCE_MASTER 0
  1761. #define GPC_FORCE_SLAVE GPC_ANEG_0
  1762. #define GPC_PREF_MASTER GPC_ANEG_1
  1763. #define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0)
  1764. /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
  1765. /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
  1766. enum {
  1767. GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
  1768. GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
  1769. GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
  1770. GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
  1771. GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
  1772. GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
  1773. #define GMAC_DEF_MSK (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
  1774. /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
  1775. /* Bits 15.. 2: reserved */
  1776. GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
  1777. GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
  1778. /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
  1779. WOL_CTL_LINK_CHG_OCC = 1<<15,
  1780. WOL_CTL_MAGIC_PKT_OCC = 1<<14,
  1781. WOL_CTL_PATTERN_OCC = 1<<13,
  1782. WOL_CTL_CLEAR_RESULT = 1<<12,
  1783. WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
  1784. WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
  1785. WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
  1786. WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
  1787. WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
  1788. WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
  1789. WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
  1790. WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
  1791. WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
  1792. WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
  1793. WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
  1794. WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
  1795. };
  1796. #define WOL_CTL_DEFAULT \
  1797. (WOL_CTL_DIS_PME_ON_LINK_CHG | \
  1798. WOL_CTL_DIS_PME_ON_PATTERN | \
  1799. WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
  1800. WOL_CTL_DIS_LINK_CHG_UNIT | \
  1801. WOL_CTL_DIS_PATTERN_UNIT | \
  1802. WOL_CTL_DIS_MAGIC_PKT_UNIT)
  1803. /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
  1804. #define WOL_CTL_PATT_ENA(x) (1 << (x))
  1805. /* XMAC II registers */
  1806. enum {
  1807. XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
  1808. XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
  1809. XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
  1810. XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
  1811. XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
  1812. XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
  1813. XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
  1814. XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
  1815. XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
  1816. XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
  1817. XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
  1818. XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
  1819. XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
  1820. XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
  1821. XM_ISRC = 0x0048, /* 16 bit r/o Interrupt Status Register */
  1822. XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
  1823. XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
  1824. XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
  1825. XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
  1826. XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
  1827. XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
  1828. XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
  1829. XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
  1830. XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
  1831. XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
  1832. XM_EXM_START = 0x0080, /* r/w Start Address of the EXM Regs */
  1833. #define XM_EXM(reg) (XM_EXM_START + ((reg) << 3))
  1834. };
  1835. enum {
  1836. XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
  1837. XM_SA = 0x0108, /* NA reg r/w Station Address Register */
  1838. XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
  1839. XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
  1840. XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
  1841. XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
  1842. XM_DEV_ID = 0x0120, /* 32 bit r/o Device ID Register */
  1843. XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
  1844. XM_LSA = 0x0128, /* NA reg r/o Last Source Register */
  1845. XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */
  1846. XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */
  1847. XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
  1848. XM_RX_CNT_EV = 0x0204, /* 32 bit r/o Rx Counter Event Register */
  1849. XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */
  1850. XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
  1851. XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
  1852. XM_TXF_OK = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
  1853. XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
  1854. XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
  1855. XM_TXF_BC_OK = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
  1856. XM_TXF_MC_OK = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
  1857. XM_TXF_UC_OK = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
  1858. XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
  1859. XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
  1860. XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
  1861. XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
  1862. XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
  1863. XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
  1864. XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
  1865. XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
  1866. XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
  1867. XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
  1868. XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
  1869. XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
  1870. XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */
  1871. XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
  1872. XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
  1873. XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
  1874. XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
  1875. XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
  1876. XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
  1877. XM_RXF_OK = 0x0300, /* 32 bit r/o Frames Received OK */
  1878. XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
  1879. XM_RXO_OK_LO = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
  1880. XM_RXF_BC_OK = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
  1881. XM_RXF_MC_OK = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
  1882. XM_RXF_UC_OK = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
  1883. XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
  1884. XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
  1885. XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
  1886. XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
  1887. XM_RXE_BURST = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
  1888. XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
  1889. XM_RXF_FRA_ERR = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
  1890. XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
  1891. XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
  1892. XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
  1893. XM_RXF_LEN_ERR = 0x0340, /* 32 bit r/o Rx in Range Length Error */
  1894. XM_RXE_SYM_ERR = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
  1895. XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
  1896. XM_RXE_RUNT = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
  1897. XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
  1898. XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
  1899. XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
  1900. XM_RXP_UTIL = 0x0360, /* 32 bit r/o Rx Utilization in % */
  1901. XM_RXF_64B = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
  1902. XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
  1903. XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
  1904. XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
  1905. XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
  1906. XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
  1907. };
  1908. /* XM_MMU_CMD 16 bit r/w MMU Command Register */
  1909. enum {
  1910. XM_MMU_PHY_RDY = 1<<12, /* Bit 12: PHY Read Ready */
  1911. XM_MMU_PHY_BUSY = 1<<11, /* Bit 11: PHY Busy */
  1912. XM_MMU_IGN_PF = 1<<10, /* Bit 10: Ignore Pause Frame */
  1913. XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
  1914. XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
  1915. XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
  1916. XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
  1917. XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
  1918. XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
  1919. XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
  1920. XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
  1921. XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
  1922. };
  1923. /* XM_TX_CMD 16 bit r/w Transmit Command Register */
  1924. enum {
  1925. XM_TX_BK2BK = 1<<6, /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
  1926. XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */
  1927. XM_TX_SAM_LINE = 1<<4, /* Bit 4: (sc) Start utilization calculation */
  1928. XM_TX_NO_GIG_MD = 1<<3, /* Bit 3: Disable Carrier Extension */
  1929. XM_TX_NO_PRE = 1<<2, /* Bit 2: Disable Preamble Generation */
  1930. XM_TX_NO_CRC = 1<<1, /* Bit 1: Disable CRC Generation */
  1931. XM_TX_AUTO_PAD = 1<<0, /* Bit 0: Enable Automatic Padding */
  1932. };
  1933. /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
  1934. #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
  1935. /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
  1936. #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
  1937. /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
  1938. #define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
  1939. /* XM_RX_CMD 16 bit r/w Receive Command Register */
  1940. enum {
  1941. XM_RX_LENERR_OK = 1<<8, /* Bit 8 don't set Rx Err bit for */
  1942. /* inrange error packets */
  1943. XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 don't set Rx Err bit for */
  1944. /* jumbo packets */
  1945. XM_RX_IPG_CAP = 1<<6, /* Bit 6 repl. type field with IPG */
  1946. XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
  1947. XM_RX_STRIP_FCS = 1<<4, /* Bit 4: Enable FCS Stripping */
  1948. XM_RX_SELF_RX = 1<<3, /* Bit 3: Enable Rx of own packets */
  1949. XM_RX_SAM_LINE = 1<<2, /* Bit 2: (sc) Start utilization calculation */
  1950. XM_RX_STRIP_PAD = 1<<1, /* Bit 1: Strip pad bytes of Rx frames */
  1951. XM_RX_DIS_CEXT = 1<<0, /* Bit 0: Disable carrier ext. check */
  1952. };
  1953. /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
  1954. enum {
  1955. XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
  1956. XM_GP_FRC_INT = 1<<5, /* Bit 5: (sc) Force Interrupt */
  1957. XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */
  1958. XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */
  1959. XM_GP_INP_ASS = 1<<0, /* Bit 0: (ro) GP Input Pin asserted */
  1960. };
  1961. /* XM_IMSK 16 bit r/w Interrupt Mask Register */
  1962. /* XM_ISRC 16 bit r/o Interrupt Status Register */
  1963. enum {
  1964. XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */
  1965. XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */
  1966. XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */
  1967. XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */
  1968. XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */
  1969. XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */
  1970. XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */
  1971. XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
  1972. XM_IS_TSC_OV = 1<<6, /* Bit 6: Time Stamp Counter Overflow */
  1973. XM_IS_RXC_OV = 1<<5, /* Bit 5: Rx Counter Event Overflow */
  1974. XM_IS_TXC_OV = 1<<4, /* Bit 4: Tx Counter Event Overflow */
  1975. XM_IS_RXF_OV = 1<<3, /* Bit 3: Receive FIFO Overflow */
  1976. XM_IS_TXF_UR = 1<<2, /* Bit 2: Transmit FIFO Underrun */
  1977. XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */
  1978. XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */
  1979. XM_IMSK_DISABLE = 0xffff,
  1980. };
  1981. /* XM_HW_CFG 16 bit r/w Hardware Config Register */
  1982. enum {
  1983. XM_HW_GEN_EOP = 1<<3, /* Bit 3: generate End of Packet pulse */
  1984. XM_HW_COM4SIG = 1<<2, /* Bit 2: use Comma Detect for Sig. Det.*/
  1985. XM_HW_GMII_MD = 1<<0, /* Bit 0: GMII Interface selected */
  1986. };
  1987. /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
  1988. /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
  1989. #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
  1990. /* XM_TX_THR 16 bit r/w Tx Request Threshold */
  1991. /* XM_HT_THR 16 bit r/w Host Request Threshold */
  1992. /* XM_RX_THR 16 bit r/w Rx Request Threshold */
  1993. #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
  1994. /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
  1995. enum {
  1996. XM_ST_VALID = (1UL<<31), /* Bit 31: Status Valid */
  1997. XM_ST_BYTE_CNT = (0x3fffL<<17), /* Bit 30..17: Tx frame Length */
  1998. XM_ST_RETRY_CNT = (0x1fL<<12), /* Bit 16..12: Retry Count */
  1999. XM_ST_EX_COL = 1<<11, /* Bit 11: Excessive Collisions */
  2000. XM_ST_EX_DEF = 1<<10, /* Bit 10: Excessive Deferral */
  2001. XM_ST_BURST = 1<<9, /* Bit 9: p. xmitted in burst md*/
  2002. XM_ST_DEFER = 1<<8, /* Bit 8: packet was defered */
  2003. XM_ST_BC = 1<<7, /* Bit 7: Broadcast packet */
  2004. XM_ST_MC = 1<<6, /* Bit 6: Multicast packet */
  2005. XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */
  2006. XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occurred */
  2007. XM_ST_CS_ERR = 1<<3, /* Bit 3: Carrier Sense Error */
  2008. XM_ST_LAT_COL = 1<<2, /* Bit 2: Late Collision Error */
  2009. XM_ST_MUL_COL = 1<<1, /* Bit 1: Multiple Collisions */
  2010. XM_ST_SGN_COL = 1<<0, /* Bit 0: Single Collision */
  2011. };
  2012. /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
  2013. /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
  2014. #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
  2015. /* XM_DEV_ID 32 bit r/o Device ID Register */
  2016. #define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
  2017. #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
  2018. /* XM_MODE 32 bit r/w Mode Register */
  2019. enum {
  2020. XM_MD_ENA_REJ = 1<<26, /* Bit 26: Enable Frame Reject */
  2021. XM_MD_SPOE_E = 1<<25, /* Bit 25: Send Pause on Edge */
  2022. /* extern generated */
  2023. XM_MD_TX_REP = 1<<24, /* Bit 24: Transmit Repeater Mode */
  2024. XM_MD_SPOFF_I = 1<<23, /* Bit 23: Send Pause on FIFO full */
  2025. /* intern generated */
  2026. XM_MD_LE_STW = 1<<22, /* Bit 22: Rx Stat Word in Little Endian */
  2027. XM_MD_TX_CONT = 1<<21, /* Bit 21: Send Continuous */
  2028. XM_MD_TX_PAUSE = 1<<20, /* Bit 20: (sc) Send Pause Frame */
  2029. XM_MD_ATS = 1<<19, /* Bit 19: Append Time Stamp */
  2030. XM_MD_SPOL_I = 1<<18, /* Bit 18: Send Pause on Low */
  2031. /* intern generated */
  2032. XM_MD_SPOH_I = 1<<17, /* Bit 17: Send Pause on High */
  2033. /* intern generated */
  2034. XM_MD_CAP = 1<<16, /* Bit 16: Check Address Pair */
  2035. XM_MD_ENA_HASH = 1<<15, /* Bit 15: Enable Hashing */
  2036. XM_MD_CSA = 1<<14, /* Bit 14: Check Station Address */
  2037. XM_MD_CAA = 1<<13, /* Bit 13: Check Address Array */
  2038. XM_MD_RX_MCTRL = 1<<12, /* Bit 12: Rx MAC Control Frame */
  2039. XM_MD_RX_RUNT = 1<<11, /* Bit 11: Rx Runt Frames */
  2040. XM_MD_RX_IRLE = 1<<10, /* Bit 10: Rx in Range Len Err Frame */
  2041. XM_MD_RX_LONG = 1<<9, /* Bit 9: Rx Long Frame */
  2042. XM_MD_RX_CRCE = 1<<8, /* Bit 8: Rx CRC Error Frame */
  2043. XM_MD_RX_ERR = 1<<7, /* Bit 7: Rx Error Frame */
  2044. XM_MD_DIS_UC = 1<<6, /* Bit 6: Disable Rx Unicast */
  2045. XM_MD_DIS_MC = 1<<5, /* Bit 5: Disable Rx Multicast */
  2046. XM_MD_DIS_BC = 1<<4, /* Bit 4: Disable Rx Broadcast */
  2047. XM_MD_ENA_PROM = 1<<3, /* Bit 3: Enable Promiscuous */
  2048. XM_MD_ENA_BE = 1<<2, /* Bit 2: Enable Big Endian */
  2049. XM_MD_FTF = 1<<1, /* Bit 1: (sc) Flush Tx FIFO */
  2050. XM_MD_FRF = 1<<0, /* Bit 0: (sc) Flush Rx FIFO */
  2051. };
  2052. #define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
  2053. #define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
  2054. XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
  2055. /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
  2056. enum {
  2057. XM_SC_SNP_RXC = 1<<5, /* Bit 5: (sc) Snap Rx Counters */
  2058. XM_SC_SNP_TXC = 1<<4, /* Bit 4: (sc) Snap Tx Counters */
  2059. XM_SC_CP_RXC = 1<<3, /* Bit 3: Copy Rx Counters Continuously */
  2060. XM_SC_CP_TXC = 1<<2, /* Bit 2: Copy Tx Counters Continuously */
  2061. XM_SC_CLR_RXC = 1<<1, /* Bit 1: (sc) Clear Rx Counters */
  2062. XM_SC_CLR_TXC = 1<<0, /* Bit 0: (sc) Clear Tx Counters */
  2063. };
  2064. /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
  2065. /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
  2066. enum {
  2067. XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
  2068. XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
  2069. XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
  2070. XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
  2071. XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
  2072. XMR_64B_OV = 1<<26, /* Bit 26: 64 Byte Rx Cnt Ov */
  2073. XMR_UTIL_OV = 1<<25, /* Bit 25: Rx Util Cnt Overflow */
  2074. XMR_UTIL_UR = 1<<24, /* Bit 24: Rx Util Cnt Underrun */
  2075. XMR_CEX_ERR_OV = 1<<23, /* Bit 23: CEXT Err Cnt Ov */
  2076. XMR_FCS_ERR_OV = 1<<21, /* Bit 21: Rx FCS Error Cnt Ov */
  2077. XMR_LNG_ERR_OV = 1<<20, /* Bit 20: Rx too Long Err Cnt Ov*/
  2078. XMR_RUNT_OV = 1<<19, /* Bit 19: Runt Event Cnt Ov */
  2079. XMR_SHT_ERR_OV = 1<<18, /* Bit 18: Rx Short Ev Err Cnt Ov*/
  2080. XMR_SYM_ERR_OV = 1<<17, /* Bit 17: Rx Sym Err Cnt Ov */
  2081. XMR_CAR_ERR_OV = 1<<15, /* Bit 15: Rx Carr Ev Err Cnt Ov */
  2082. XMR_JAB_PKT_OV = 1<<14, /* Bit 14: Rx Jabb Packet Cnt Ov */
  2083. XMR_FIFO_OV = 1<<13, /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
  2084. XMR_FRA_ERR_OV = 1<<12, /* Bit 12: Rx Framing Err Cnt Ov */
  2085. XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */
  2086. XMR_BURST = 1<<10, /* Bit 10: Rx Burst Event Cnt Ov */
  2087. XMR_INV_MOC = 1<<9, /* Bit 9: Rx with inv. MAC OC Ov*/
  2088. XMR_INV_MP = 1<<8, /* Bit 8: Rx inv Pause Frame Ov */
  2089. XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
  2090. XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
  2091. XMR_UC_OK_OV = 1<<5, /* Bit 5: Rx Unicast Frame CntOv*/
  2092. XMR_MC_OK_OV = 1<<4, /* Bit 4: Rx Multicast Cnt Ov */
  2093. XMR_BC_OK_OV = 1<<3, /* Bit 3: Rx Broadcast Cnt Ov */
  2094. XMR_OK_LO_OV = 1<<2, /* Bit 2: Octets Rx OK Low CntOv*/
  2095. XMR_OK_HI_OV = 1<<1, /* Bit 1: Octets Rx OK Hi Cnt Ov*/
  2096. XMR_OK_OV = 1<<0, /* Bit 0: Frames Received Ok Ov */
  2097. };
  2098. #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
  2099. /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
  2100. /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
  2101. enum {
  2102. XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
  2103. XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
  2104. XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
  2105. XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
  2106. XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
  2107. XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */
  2108. XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */
  2109. XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */
  2110. XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/
  2111. XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
  2112. XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */
  2113. XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */
  2114. XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */
  2115. XMT_ABO_COL_OV = 1<<12, /* Bit 12: Tx abo dueto Ex Col Ov*/
  2116. XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */
  2117. XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */
  2118. XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/
  2119. XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
  2120. XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */
  2121. XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */
  2122. XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
  2123. XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */
  2124. XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */
  2125. XMT_OK_LO_OV = 1<<2, /* Bit 2: Octets Tx OK Low CntOv*/
  2126. XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/
  2127. XMT_OK_OV = 1<<0, /* Bit 0: Frames Tx Ok Ov */
  2128. };
  2129. #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
  2130. struct skge_rx_desc {
  2131. u32 control;
  2132. u32 next_offset;
  2133. u32 dma_lo;
  2134. u32 dma_hi;
  2135. u32 status;
  2136. u32 timestamp;
  2137. u16 csum2;
  2138. u16 csum1;
  2139. u16 csum2_start;
  2140. u16 csum1_start;
  2141. };
  2142. struct skge_tx_desc {
  2143. u32 control;
  2144. u32 next_offset;
  2145. u32 dma_lo;
  2146. u32 dma_hi;
  2147. u32 status;
  2148. u32 csum_offs;
  2149. u16 csum_write;
  2150. u16 csum_start;
  2151. u32 rsvd;
  2152. };
  2153. struct skge_element {
  2154. struct skge_element *next;
  2155. void *desc;
  2156. struct io_buffer *iob;
  2157. };
  2158. struct skge_ring {
  2159. struct skge_element *to_clean;
  2160. struct skge_element *to_use;
  2161. struct skge_element *start;
  2162. };
  2163. struct skge_hw {
  2164. unsigned long regs;
  2165. struct pci_device *pdev;
  2166. u32 intr_mask;
  2167. struct net_device *dev[2];
  2168. u8 chip_id;
  2169. u8 chip_rev;
  2170. u8 copper;
  2171. u8 ports;
  2172. u8 phy_type;
  2173. u32 ram_size;
  2174. u32 ram_offset;
  2175. u16 phy_addr;
  2176. };
  2177. enum pause_control {
  2178. FLOW_MODE_NONE = 1, /* No Flow-Control */
  2179. FLOW_MODE_LOC_SEND = 2, /* Local station sends PAUSE */
  2180. FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */
  2181. FLOW_MODE_SYM_OR_REM = 4, /* Both stations may send PAUSE or
  2182. * just the remote station may send PAUSE
  2183. */
  2184. };
  2185. enum pause_status {
  2186. FLOW_STAT_INDETERMINATED=0, /* indeterminated */
  2187. FLOW_STAT_NONE, /* No Flow Control */
  2188. FLOW_STAT_REM_SEND, /* Remote Station sends PAUSE */
  2189. FLOW_STAT_LOC_SEND, /* Local station sends PAUSE */
  2190. FLOW_STAT_SYMMETRIC, /* Both station may send PAUSE */
  2191. };
  2192. struct skge_port {
  2193. struct skge_hw *hw;
  2194. struct net_device *netdev;
  2195. int port;
  2196. struct skge_ring tx_ring;
  2197. struct skge_ring rx_ring;
  2198. enum pause_control flow_control;
  2199. enum pause_status flow_status;
  2200. u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
  2201. u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
  2202. u16 speed; /* SPEED_1000, SPEED_100, ... */
  2203. u32 advertising;
  2204. void *mem; /* PCI memory for rings */
  2205. u32 dma;
  2206. int use_xm_link_timer;
  2207. };
  2208. /* Register accessor for memory mapped device */
  2209. static inline u32 skge_read32(const struct skge_hw *hw, int reg)
  2210. {
  2211. return readl(hw->regs + reg);
  2212. }
  2213. static inline u16 skge_read16(const struct skge_hw *hw, int reg)
  2214. {
  2215. return readw(hw->regs + reg);
  2216. }
  2217. static inline u8 skge_read8(const struct skge_hw *hw, int reg)
  2218. {
  2219. return readb(hw->regs + reg);
  2220. }
  2221. static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
  2222. {
  2223. writel(val, hw->regs + reg);
  2224. }
  2225. static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
  2226. {
  2227. writew(val, hw->regs + reg);
  2228. }
  2229. static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
  2230. {
  2231. writeb(val, hw->regs + reg);
  2232. }
  2233. /* MAC Related Registers inside the device. */
  2234. #define SK_REG(port,reg) (((port)<<7)+(u16)(reg))
  2235. #define SK_XMAC_REG(port, reg) \
  2236. ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
  2237. static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
  2238. {
  2239. u32 v;
  2240. v = skge_read16(hw, SK_XMAC_REG(port, reg));
  2241. v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
  2242. return v;
  2243. }
  2244. static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
  2245. {
  2246. return skge_read16(hw, SK_XMAC_REG(port,reg));
  2247. }
  2248. static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
  2249. {
  2250. skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
  2251. skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
  2252. }
  2253. static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
  2254. {
  2255. skge_write16(hw, SK_XMAC_REG(port,r), v);
  2256. }
  2257. static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
  2258. const u8 *hash)
  2259. {
  2260. xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
  2261. xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
  2262. xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
  2263. xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
  2264. }
  2265. static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
  2266. const u8 *addr)
  2267. {
  2268. xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
  2269. xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
  2270. xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
  2271. }
  2272. #define SK_GMAC_REG(port,reg) \
  2273. (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
  2274. static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
  2275. {
  2276. return skge_read16(hw, SK_GMAC_REG(port,reg));
  2277. }
  2278. static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
  2279. {
  2280. return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
  2281. | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
  2282. }
  2283. static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
  2284. {
  2285. skge_write16(hw, SK_GMAC_REG(port,r), v);
  2286. }
  2287. static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
  2288. const u8 *addr)
  2289. {
  2290. gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
  2291. gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
  2292. gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
  2293. }
  2294. #endif