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realtek.h 9.1KB

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  1. #ifndef _REALTEK_H
  2. #define _REALTEK_H
  3. /** @file
  4. *
  5. * Realtek 10/100/1000 network card driver
  6. *
  7. */
  8. FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
  9. #include <ipxe/spi.h>
  10. #include <ipxe/spi_bit.h>
  11. #include <ipxe/nvo.h>
  12. #include <ipxe/if_ether.h>
  13. /** PCI memory BAR size */
  14. #define RTL_BAR_SIZE 0x100
  15. /** A packet descriptor */
  16. struct realtek_descriptor {
  17. /** Buffer size */
  18. uint16_t length;
  19. /** Flags */
  20. uint16_t flags;
  21. /** Reserved */
  22. uint32_t reserved;
  23. /** Buffer address */
  24. uint64_t address;
  25. } __attribute__ (( packed ));
  26. /** Descriptor buffer size mask */
  27. #define RTL_DESC_SIZE_MASK 0x3fff
  28. /** Packet descriptor flags */
  29. enum realtek_descriptor_flags {
  30. /** Descriptor is owned by NIC */
  31. RTL_DESC_OWN = 0x8000,
  32. /** End of descriptor ring */
  33. RTL_DESC_EOR = 0x4000,
  34. /** First segment descriptor */
  35. RTL_DESC_FS = 0x2000,
  36. /** Last segment descriptor */
  37. RTL_DESC_LS = 0x1000,
  38. /** Receive error summary */
  39. RTL_DESC_RES = 0x0020,
  40. };
  41. /** Descriptor ring alignment */
  42. #define RTL_RING_ALIGN 256
  43. /** A legacy mode receive packet header */
  44. struct realtek_legacy_header {
  45. /** Status */
  46. uint16_t status;
  47. /** Length */
  48. uint16_t length;
  49. /** Packet data */
  50. uint8_t data[0];
  51. } __attribute__ (( packed ));
  52. /** Legacy mode status bits */
  53. enum realtek_legacy_status {
  54. /** Received OK */
  55. RTL_STAT_ROK = 0x0001,
  56. };
  57. /** ID Register 0 (6 bytes) */
  58. #define RTL_IDR0 0x00
  59. /** Multicast Register 0 (dword) */
  60. #define RTL_MAR0 0x08
  61. /** Multicast Register 4 (dword) */
  62. #define RTL_MAR4 0x0c
  63. /** Transmit Status of Descriptor N (dword, 8139 only) */
  64. #define RTL_TSD(n) ( 0x10 + 4 * (n) )
  65. #define RTL_TSD_ERTXTH(x) ( (x) << 16 ) /**< Early TX threshold */
  66. #define RTL_TSD_ERTXTH_DEFAULT RTL_TSD_ERTXTH ( 256 / 32 )
  67. #define RTL_TSD_OWN 0x00002000UL /**< Ownership */
  68. /** Transmit Start Address of Descriptor N (dword, 8139 only) */
  69. #define RTL_TSAD(n) ( 0x20 + 4 * (n) )
  70. /** Transmit Normal Priority Descriptors (qword) */
  71. #define RTL_TNPDS 0x20
  72. /** Number of transmit descriptors
  73. *
  74. * This is a hardware limit when using legacy mode.
  75. */
  76. #define RTL_NUM_TX_DESC 4
  77. /** Receive Buffer Start Address (dword, 8139 only) */
  78. #define RTL_RBSTART 0x30
  79. /** Receive buffer length */
  80. #define RTL_RXBUF_LEN 8192
  81. /** Receive buffer padding */
  82. #define RTL_RXBUF_PAD 2038 /* Allow space for WRAP */
  83. /** Receive buffer alignment */
  84. #define RTL_RXBUF_ALIGN 16
  85. /** Command Register (byte) */
  86. #define RTL_CR 0x37
  87. #define RTL_CR_RST 0x10 /**< Reset */
  88. #define RTL_CR_RE 0x08 /**< Receiver Enable */
  89. #define RTL_CR_TE 0x04 /**< Transmit Enable */
  90. #define RTL_CR_BUFE 0x01 /**< Receive buffer empty */
  91. /** Maximum time to wait for a reset, in milliseconds */
  92. #define RTL_RESET_MAX_WAIT_MS 100
  93. /** Current Address of Packet Read (word, 8139 only) */
  94. #define RTL_CAPR 0x38
  95. /** Transmit Priority Polling Register (byte, 8169 only) */
  96. #define RTL_TPPOLL_8169 0x38
  97. #define RTL_TPPOLL_NPQ 0x40 /**< Normal Priority Queue Polling */
  98. /** Interrupt Mask Register (word) */
  99. #define RTL_IMR 0x3c
  100. #define RTL_IRQ_PUN_LINKCHG 0x0020 /**< Packet underrun / link change */
  101. #define RTL_IRQ_TER 0x0008 /**< Transmit error */
  102. #define RTL_IRQ_TOK 0x0004 /**< Transmit OK */
  103. #define RTL_IRQ_RER 0x0002 /**< Receive error */
  104. #define RTL_IRQ_ROK 0x0001 /**< Receive OK */
  105. /** Interrupt Status Register (word) */
  106. #define RTL_ISR 0x3e
  107. /** Transmit (Tx) Configuration Register (dword) */
  108. #define RTL_TCR 0x40
  109. #define RTL_TCR_MXDMA(x) ( (x) << 8 ) /**< Max DMA burst size */
  110. #define RTL_TCR_MXDMA_MASK RTL_TCR_MXDMA ( 0x7 )
  111. #define RTL_TCR_MXDMA_DEFAULT RTL_TCR_MXDMA ( 0x7 /* Unlimited */ )
  112. /** Receive (Rx) Configuration Register (dword) */
  113. #define RTL_RCR 0x44
  114. #define RTL_RCR_STOP_WORKING 0x01000000UL /**< Here be dragons */
  115. #define RTL_RCR_RXFTH(x) ( (x) << 13 ) /**< Receive FIFO threshold */
  116. #define RTL_RCR_RXFTH_MASK RTL_RCR_RXFTH ( 0x7 )
  117. #define RTL_RCR_RXFTH_DEFAULT RTL_RCR_RXFTH ( 0x7 /* Whole packet */ )
  118. #define RTL_RCR_RBLEN(x) ( (x) << 11 ) /**< Receive buffer length */
  119. #define RTL_RCR_RBLEN_MASK RTL_RCR_RBLEN ( 0x3 )
  120. #define RTL_RCR_RBLEN_DEFAULT RTL_RCR_RBLEN ( 0 /* 8kB */ )
  121. #define RTL_RCR_MXDMA(x) ( (x) << 8 ) /**< Max DMA burst size */
  122. #define RTL_RCR_MXDMA_MASK RTL_RCR_MXDMA ( 0x7 )
  123. #define RTL_RCR_MXDMA_DEFAULT RTL_RCR_MXDMA ( 0x7 /* Unlimited */ )
  124. #define RTL_RCR_WRAP 0x00000080UL /**< Overrun receive buffer */
  125. #define RTL_RCR_9356SEL 0x00000040UL /**< EEPROM is a 93C56 */
  126. #define RTL_RCR_AB 0x00000008UL /**< Accept broadcast packets */
  127. #define RTL_RCR_AM 0x00000004UL /**< Accept multicast packets */
  128. #define RTL_RCR_APM 0x00000002UL /**< Accept physical match */
  129. #define RTL_RCR_AAP 0x00000001UL /**< Accept all packets */
  130. /** 93C46 (93C56) Command Register (byte) */
  131. #define RTL_9346CR 0x50
  132. #define RTL_9346CR_EEM(x) ( (x) << 6 ) /**< Mode select */
  133. #define RTL_9346CR_EEM_EEPROM RTL_9346CR_EEM ( 0x2 ) /**< EEPROM mode */
  134. #define RTL_9346CR_EEM_NORMAL RTL_9346CR_EEM ( 0x0 ) /**< Normal mode */
  135. #define RTL_9346CR_EECS 0x08 /**< Chip select */
  136. #define RTL_9346CR_EESK 0x04 /**< Clock */
  137. #define RTL_9346CR_EEDI 0x02 /**< Data in */
  138. #define RTL_9346CR_EEDO 0x01 /**< Data out */
  139. /** Word offset of ID code word within EEPROM */
  140. #define RTL_EEPROM_ID ( 0x00 / 2 )
  141. /** EEPROM code word magic value */
  142. #define RTL_EEPROM_ID_MAGIC 0x8129
  143. /** Word offset of MAC address within EEPROM */
  144. #define RTL_EEPROM_MAC ( 0x0e / 2 )
  145. /** Word offset of VPD / non-volatile options within EEPROM */
  146. #define RTL_EEPROM_VPD ( 0x40 / 2 )
  147. /** Length of VPD / non-volatile options within EEPROM */
  148. #define RTL_EEPROM_VPD_LEN 0x40
  149. /** Configuration Register 1 (byte) */
  150. #define RTL_CONFIG1 0x52
  151. #define RTL_CONFIG1_VPD 0x02 /**< Vital Product Data enabled */
  152. /** Media Status Register (byte, 8139 only) */
  153. #define RTL_MSR 0x58
  154. #define RTL_MSR_TXFCE 0x80 /**< TX flow control enabled */
  155. #define RTL_MSR_RXFCE 0x40 /**< RX flow control enabled */
  156. #define RTL_MSR_AUX_STATUS 0x10 /**< Aux power present */
  157. #define RTL_MSR_SPEED_10 0x08 /**< 10Mbps */
  158. #define RTL_MSR_LINKB 0x04 /**< Inverse of link status */
  159. #define RTL_MSR_TXPF 0x02 /**< TX pause flag */
  160. #define RTL_MSR_RXPF 0x01 /**< RX pause flag */
  161. /** PHY Access Register (dword, 8169 only) */
  162. #define RTL_PHYAR 0x60
  163. #define RTL_PHYAR_FLAG 0x80000000UL /**< Read/write flag */
  164. /** Construct PHY Access Register value */
  165. #define RTL_PHYAR_VALUE( flag, reg, data ) ( (flag) | ( (reg) << 16 ) | (data) )
  166. /** Extract PHY Access Register data */
  167. #define RTL_PHYAR_DATA( value ) ( (value) & 0xffff )
  168. /** Maximum time to wait for PHY access, in microseconds */
  169. #define RTL_MII_MAX_WAIT_US 500
  170. /** PHY (GMII, MII, or TBI) Status Register (byte, 8169 only) */
  171. #define RTL_PHYSTATUS 0x6c
  172. #define RTL_PHYSTATUS_ENTBI 0x80 /**< TBI / GMII mode */
  173. #define RTL_PHYSTATUS_TXFLOW 0x40 /**< TX flow control enabled */
  174. #define RTL_PHYSTATUS_RXFLOW 0x20 /**< RX flow control enabled */
  175. #define RTL_PHYSTATUS_1000MF 0x10 /**< 1000Mbps full-duplex */
  176. #define RTL_PHYSTATUS_100M 0x08 /**< 100Mbps */
  177. #define RTL_PHYSTATUS_10M 0x04 /**< 10Mbps */
  178. #define RTL_PHYSTATUS_LINKSTS 0x02 /**< Link ok */
  179. #define RTL_PHYSTATUS_FULLDUP 0x01 /**< Full duplex */
  180. /** Transmit Priority Polling Register (byte, 8139C+ only) */
  181. #define RTL_TPPOLL_8139CP 0xd9
  182. /** RX Packet Maximum Size Register (word) */
  183. #define RTL_RMS 0xda
  184. /** C+ Command Register (word) */
  185. #define RTL_CPCR 0xe0
  186. #define RTL_CPCR_DAC 0x0010 /**< PCI Dual Address Cycle Enable */
  187. #define RTL_CPCR_MULRW 0x0008 /**< PCI Multiple Read/Write Enable */
  188. #define RTL_CPCR_CPRX 0x0002 /**< C+ receive enable */
  189. #define RTL_CPCR_CPTX 0x0001 /**< C+ transmit enable */
  190. /** Receive Descriptor Start Address Register (qword) */
  191. #define RTL_RDSAR 0xe4
  192. /** Number of receive descriptors */
  193. #define RTL_NUM_RX_DESC 4
  194. /** Receive buffer length */
  195. #define RTL_RX_MAX_LEN \
  196. ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ + 4 /* extra space */ )
  197. /** A Realtek descriptor ring */
  198. struct realtek_ring {
  199. /** Descriptors */
  200. struct realtek_descriptor *desc;
  201. /** Producer index */
  202. unsigned int prod;
  203. /** Consumer index */
  204. unsigned int cons;
  205. /** Descriptor start address register */
  206. unsigned int reg;
  207. /** Length (in bytes) */
  208. size_t len;
  209. };
  210. /**
  211. * Initialise descriptor ring
  212. *
  213. * @v ring Descriptor ring
  214. * @v count Number of descriptors
  215. * @v reg Descriptor start address register
  216. */
  217. static inline __attribute__ (( always_inline)) void
  218. realtek_init_ring ( struct realtek_ring *ring, unsigned int count,
  219. unsigned int reg ) {
  220. ring->len = ( count * sizeof ( ring->desc[0] ) );
  221. ring->reg = reg;
  222. }
  223. /** A Realtek network card */
  224. struct realtek_nic {
  225. /** Registers */
  226. void *regs;
  227. /** SPI bit-bashing interface */
  228. struct spi_bit_basher spibit;
  229. /** EEPROM */
  230. struct spi_device eeprom;
  231. /** Non-volatile options */
  232. struct nvo_block nvo;
  233. /** MII interface */
  234. struct mii_interface mdio;
  235. /** MII device */
  236. struct mii_device mii;
  237. /** Legacy datapath mode */
  238. int legacy;
  239. /** PHYAR and PHYSTATUS registers are present */
  240. int have_phy_regs;
  241. /** TPPoll register offset */
  242. unsigned int tppoll;
  243. /** Transmit descriptor ring */
  244. struct realtek_ring tx;
  245. /** Receive descriptor ring */
  246. struct realtek_ring rx;
  247. /** Receive I/O buffers */
  248. struct io_buffer *rx_iobuf[RTL_NUM_RX_DESC];
  249. /** Receive buffer (legacy mode) */
  250. void *rx_buffer;
  251. /** Offset within receive buffer (legacy mode) */
  252. unsigned int rx_offset;
  253. };
  254. #endif /* _REALTEK_H */