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  1. /*
  2. * JMicron JMC2x0 series PCIe Ethernet gPXE Device Driver
  3. *
  4. * Copyright 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  18. * 02110-1301, USA.
  19. *
  20. */
  21. FILE_LICENCE ( GPL2_OR_LATER );
  22. #ifndef __JME_H_INCLUDED__
  23. #define __JME_H_INCLUDED__
  24. #define PCI_VENDOR_ID_JMICRON 0x197b
  25. #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
  26. #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
  27. /*
  28. * Extra PCI Configuration space interface
  29. */
  30. #define PCI_DCSR_MRRS 0x59
  31. #define PCI_DCSR_MRRS_MASK 0x70
  32. enum pci_dcsr_mrrs_vals {
  33. MRRS_128B = 0x00,
  34. MRRS_256B = 0x10,
  35. MRRS_512B = 0x20,
  36. MRRS_1024B = 0x30,
  37. MRRS_2048B = 0x40,
  38. MRRS_4096B = 0x50,
  39. };
  40. /*
  41. * TX/RX Descriptors
  42. *
  43. * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
  44. */
  45. #define RING_DESC_ALIGN 16 /* Descriptor alignment */
  46. #define TX_DESC_SIZE 16
  47. struct txdesc {
  48. union {
  49. uint8_t all[16];
  50. uint32_t dw[4];
  51. struct {
  52. /* DW0 */
  53. uint16_t vlan;
  54. uint8_t rsv1;
  55. uint8_t flags;
  56. /* DW1 */
  57. uint16_t datalen;
  58. uint16_t mss;
  59. /* DW2 */
  60. uint16_t pktsize;
  61. uint16_t rsv2;
  62. /* DW3 */
  63. uint32_t bufaddr;
  64. } desc1;
  65. struct {
  66. /* DW0 */
  67. uint16_t rsv1;
  68. uint8_t rsv2;
  69. uint8_t flags;
  70. /* DW1 */
  71. uint16_t datalen;
  72. uint16_t rsv3;
  73. /* DW2 */
  74. uint32_t bufaddrh;
  75. /* DW3 */
  76. uint32_t bufaddrl;
  77. } desc2;
  78. struct {
  79. /* DW0 */
  80. uint8_t ehdrsz;
  81. uint8_t rsv1;
  82. uint8_t rsv2;
  83. uint8_t flags;
  84. /* DW1 */
  85. uint16_t trycnt;
  86. uint16_t segcnt;
  87. /* DW2 */
  88. uint16_t pktsz;
  89. uint16_t rsv3;
  90. /* DW3 */
  91. uint32_t bufaddrl;
  92. } descwb;
  93. };
  94. };
  95. enum jme_txdesc_flags_bits {
  96. TXFLAG_OWN = 0x80,
  97. TXFLAG_INT = 0x40,
  98. TXFLAG_64BIT = 0x20,
  99. TXFLAG_TCPCS = 0x10,
  100. TXFLAG_UDPCS = 0x08,
  101. TXFLAG_IPCS = 0x04,
  102. TXFLAG_LSEN = 0x02,
  103. TXFLAG_TAGON = 0x01,
  104. };
  105. #define TXDESC_MSS_SHIFT 2
  106. enum jme_txwbdesc_flags_bits {
  107. TXWBFLAG_OWN = 0x80,
  108. TXWBFLAG_INT = 0x40,
  109. TXWBFLAG_TMOUT = 0x20,
  110. TXWBFLAG_TRYOUT = 0x10,
  111. TXWBFLAG_COL = 0x08,
  112. TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
  113. TXWBFLAG_TRYOUT |
  114. TXWBFLAG_COL,
  115. };
  116. #define RX_DESC_SIZE 16
  117. #define RX_BUF_DMA_ALIGN 8
  118. #define RX_PREPAD_SIZE 10
  119. #define ETH_CRC_LEN 2
  120. #define RX_VLANHDR_LEN 2
  121. #define RX_EXTRA_LEN (ETH_HLEN + \
  122. ETH_CRC_LEN + \
  123. RX_VLANHDR_LEN + \
  124. RX_BUF_DMA_ALIGN)
  125. #define FIXED_MTU 1500
  126. #define RX_ALLOC_LEN (FIXED_MTU + RX_EXTRA_LEN)
  127. struct rxdesc {
  128. union {
  129. uint8_t all[16];
  130. uint32_t dw[4];
  131. struct {
  132. /* DW0 */
  133. uint16_t rsv2;
  134. uint8_t rsv1;
  135. uint8_t flags;
  136. /* DW1 */
  137. uint16_t datalen;
  138. uint16_t wbcpl;
  139. /* DW2 */
  140. uint32_t bufaddrh;
  141. /* DW3 */
  142. uint32_t bufaddrl;
  143. } desc1;
  144. struct {
  145. /* DW0 */
  146. uint16_t vlan;
  147. uint16_t flags;
  148. /* DW1 */
  149. uint16_t framesize;
  150. uint8_t errstat;
  151. uint8_t desccnt;
  152. /* DW2 */
  153. uint32_t rsshash;
  154. /* DW3 */
  155. uint8_t hashfun;
  156. uint8_t hashtype;
  157. uint16_t resrv;
  158. } descwb;
  159. };
  160. };
  161. enum jme_rxdesc_flags_bits {
  162. RXFLAG_OWN = 0x80,
  163. RXFLAG_INT = 0x40,
  164. RXFLAG_64BIT = 0x20,
  165. };
  166. enum jme_rxwbdesc_flags_bits {
  167. RXWBFLAG_OWN = 0x8000,
  168. RXWBFLAG_INT = 0x4000,
  169. RXWBFLAG_MF = 0x2000,
  170. RXWBFLAG_64BIT = 0x2000,
  171. RXWBFLAG_TCPON = 0x1000,
  172. RXWBFLAG_UDPON = 0x0800,
  173. RXWBFLAG_IPCS = 0x0400,
  174. RXWBFLAG_TCPCS = 0x0200,
  175. RXWBFLAG_UDPCS = 0x0100,
  176. RXWBFLAG_TAGON = 0x0080,
  177. RXWBFLAG_IPV4 = 0x0040,
  178. RXWBFLAG_IPV6 = 0x0020,
  179. RXWBFLAG_PAUSE = 0x0010,
  180. RXWBFLAG_MAGIC = 0x0008,
  181. RXWBFLAG_WAKEUP = 0x0004,
  182. RXWBFLAG_DEST = 0x0003,
  183. RXWBFLAG_DEST_UNI = 0x0001,
  184. RXWBFLAG_DEST_MUL = 0x0002,
  185. RXWBFLAG_DEST_BRO = 0x0003,
  186. };
  187. enum jme_rxwbdesc_desccnt_mask {
  188. RXWBDCNT_WBCPL = 0x80,
  189. RXWBDCNT_DCNT = 0x7F,
  190. };
  191. enum jme_rxwbdesc_errstat_bits {
  192. RXWBERR_LIMIT = 0x80,
  193. RXWBERR_MIIER = 0x40,
  194. RXWBERR_NIBON = 0x20,
  195. RXWBERR_COLON = 0x10,
  196. RXWBERR_ABORT = 0x08,
  197. RXWBERR_SHORT = 0x04,
  198. RXWBERR_OVERUN = 0x02,
  199. RXWBERR_CRCERR = 0x01,
  200. RXWBERR_ALLERR = 0xFF,
  201. };
  202. /*
  203. * The structure holding buffer information and ring descriptors all together.
  204. */
  205. struct jme_ring {
  206. void *desc; /* pointer to ring memory */
  207. unsigned long dma; /* phys address for ring dma */
  208. /* Buffer information corresponding to each descriptor */
  209. struct io_buffer **bufinf;
  210. int next_to_clean;
  211. int next_to_fill;
  212. int next_to_use;
  213. int nr_free;
  214. };
  215. /*
  216. * Jmac Adapter Private data
  217. */
  218. struct jme_adapter {
  219. void *regs;
  220. struct mii_if_info mii_if;
  221. struct pci_device *pdev;
  222. unsigned int fpgaver;
  223. unsigned int chiprev;
  224. uint32_t reg_ghc;
  225. uint32_t reg_txcs;
  226. uint32_t reg_rxcs;
  227. uint32_t reg_rxmcs;
  228. uint32_t phylink;
  229. struct jme_ring rxring;
  230. uint32_t rx_ring_size;
  231. uint32_t rx_ring_mask;
  232. struct jme_ring txring;
  233. uint32_t tx_ring_size;
  234. uint32_t tx_ring_mask;
  235. };
  236. /*
  237. * I/O Resters
  238. */
  239. enum jme_iomap_regs_value {
  240. JME_REGS_SIZE = 0x1000,
  241. };
  242. enum jme_iomap_offsets {
  243. JME_MAC = 0x0000,
  244. JME_PHY = 0x0400,
  245. JME_MISC = 0x0800,
  246. JME_RSS = 0x0C00,
  247. };
  248. enum jme_iomap_lens {
  249. JME_MAC_LEN = 0x80,
  250. JME_PHY_LEN = 0x58,
  251. JME_MISC_LEN = 0x98,
  252. JME_RSS_LEN = 0xFF,
  253. };
  254. enum jme_iomap_regs {
  255. JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
  256. JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
  257. JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
  258. JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
  259. JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
  260. JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
  261. JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
  262. JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
  263. JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
  264. JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
  265. JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
  266. JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
  267. JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
  268. JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
  269. JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
  270. JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
  271. JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
  272. JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
  273. JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
  274. JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
  275. JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
  276. JME_GHC = JME_MAC | 0x54, /* Global Host Control */
  277. JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
  278. JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
  279. JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
  280. JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
  281. JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
  282. JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
  283. JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
  284. JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
  285. JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
  286. JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
  287. JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
  288. JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
  289. JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
  290. JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
  291. JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
  292. JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
  293. JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
  294. JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
  295. JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
  296. JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
  297. JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
  298. };
  299. /*
  300. * TX Control/Status Bits
  301. */
  302. enum jme_txcs_bits {
  303. TXCS_QUEUE7S = 0x00008000,
  304. TXCS_QUEUE6S = 0x00004000,
  305. TXCS_QUEUE5S = 0x00002000,
  306. TXCS_QUEUE4S = 0x00001000,
  307. TXCS_QUEUE3S = 0x00000800,
  308. TXCS_QUEUE2S = 0x00000400,
  309. TXCS_QUEUE1S = 0x00000200,
  310. TXCS_QUEUE0S = 0x00000100,
  311. TXCS_FIFOTH = 0x000000C0,
  312. TXCS_DMASIZE = 0x00000030,
  313. TXCS_BURST = 0x00000004,
  314. TXCS_ENABLE = 0x00000001,
  315. };
  316. enum jme_txcs_value {
  317. TXCS_FIFOTH_16QW = 0x000000C0,
  318. TXCS_FIFOTH_12QW = 0x00000080,
  319. TXCS_FIFOTH_8QW = 0x00000040,
  320. TXCS_FIFOTH_4QW = 0x00000000,
  321. TXCS_DMASIZE_64B = 0x00000000,
  322. TXCS_DMASIZE_128B = 0x00000010,
  323. TXCS_DMASIZE_256B = 0x00000020,
  324. TXCS_DMASIZE_512B = 0x00000030,
  325. TXCS_SELECT_QUEUE0 = 0x00000000,
  326. TXCS_SELECT_QUEUE1 = 0x00010000,
  327. TXCS_SELECT_QUEUE2 = 0x00020000,
  328. TXCS_SELECT_QUEUE3 = 0x00030000,
  329. TXCS_SELECT_QUEUE4 = 0x00040000,
  330. TXCS_SELECT_QUEUE5 = 0x00050000,
  331. TXCS_SELECT_QUEUE6 = 0x00060000,
  332. TXCS_SELECT_QUEUE7 = 0x00070000,
  333. TXCS_DEFAULT = TXCS_FIFOTH_4QW |
  334. TXCS_BURST,
  335. };
  336. #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
  337. /*
  338. * TX MAC Control/Status Bits
  339. */
  340. enum jme_txmcs_bit_masks {
  341. TXMCS_IFG2 = 0xC0000000,
  342. TXMCS_IFG1 = 0x30000000,
  343. TXMCS_TTHOLD = 0x00000300,
  344. TXMCS_FBURST = 0x00000080,
  345. TXMCS_CARRIEREXT = 0x00000040,
  346. TXMCS_DEFER = 0x00000020,
  347. TXMCS_BACKOFF = 0x00000010,
  348. TXMCS_CARRIERSENSE = 0x00000008,
  349. TXMCS_COLLISION = 0x00000004,
  350. TXMCS_CRC = 0x00000002,
  351. TXMCS_PADDING = 0x00000001,
  352. };
  353. enum jme_txmcs_values {
  354. TXMCS_IFG2_6_4 = 0x00000000,
  355. TXMCS_IFG2_8_5 = 0x40000000,
  356. TXMCS_IFG2_10_6 = 0x80000000,
  357. TXMCS_IFG2_12_7 = 0xC0000000,
  358. TXMCS_IFG1_8_4 = 0x00000000,
  359. TXMCS_IFG1_12_6 = 0x10000000,
  360. TXMCS_IFG1_16_8 = 0x20000000,
  361. TXMCS_IFG1_20_10 = 0x30000000,
  362. TXMCS_TTHOLD_1_8 = 0x00000000,
  363. TXMCS_TTHOLD_1_4 = 0x00000100,
  364. TXMCS_TTHOLD_1_2 = 0x00000200,
  365. TXMCS_TTHOLD_FULL = 0x00000300,
  366. TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
  367. TXMCS_IFG1_16_8 |
  368. TXMCS_TTHOLD_FULL |
  369. TXMCS_DEFER |
  370. TXMCS_CRC |
  371. TXMCS_PADDING,
  372. };
  373. enum jme_txpfc_bits_masks {
  374. TXPFC_VLAN_TAG = 0xFFFF0000,
  375. TXPFC_VLAN_EN = 0x00008000,
  376. TXPFC_PF_EN = 0x00000001,
  377. };
  378. enum jme_txtrhd_bits_masks {
  379. TXTRHD_TXPEN = 0x80000000,
  380. TXTRHD_TXP = 0x7FFFFF00,
  381. TXTRHD_TXREN = 0x00000080,
  382. TXTRHD_TXRL = 0x0000007F,
  383. };
  384. enum jme_txtrhd_shifts {
  385. TXTRHD_TXP_SHIFT = 8,
  386. TXTRHD_TXRL_SHIFT = 0,
  387. };
  388. /*
  389. * RX Control/Status Bits
  390. */
  391. enum jme_rxcs_bit_masks {
  392. /* FIFO full threshold for transmitting Tx Pause Packet */
  393. RXCS_FIFOTHTP = 0x30000000,
  394. /* FIFO threshold for processing next packet */
  395. RXCS_FIFOTHNP = 0x0C000000,
  396. RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
  397. RXCS_QUEUESEL = 0x00030000, /* Queue selection */
  398. RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
  399. RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
  400. RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
  401. RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
  402. RXCS_SHORT = 0x00000010, /* Enable receive short packet */
  403. RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
  404. RXCS_QST = 0x00000004, /* Receive queue start */
  405. RXCS_SUSPEND = 0x00000002,
  406. RXCS_ENABLE = 0x00000001,
  407. };
  408. enum jme_rxcs_values {
  409. RXCS_FIFOTHTP_16T = 0x00000000,
  410. RXCS_FIFOTHTP_32T = 0x10000000,
  411. RXCS_FIFOTHTP_64T = 0x20000000,
  412. RXCS_FIFOTHTP_128T = 0x30000000,
  413. RXCS_FIFOTHNP_16QW = 0x00000000,
  414. RXCS_FIFOTHNP_32QW = 0x04000000,
  415. RXCS_FIFOTHNP_64QW = 0x08000000,
  416. RXCS_FIFOTHNP_128QW = 0x0C000000,
  417. RXCS_DMAREQSZ_16B = 0x00000000,
  418. RXCS_DMAREQSZ_32B = 0x01000000,
  419. RXCS_DMAREQSZ_64B = 0x02000000,
  420. RXCS_DMAREQSZ_128B = 0x03000000,
  421. RXCS_QUEUESEL_Q0 = 0x00000000,
  422. RXCS_QUEUESEL_Q1 = 0x00010000,
  423. RXCS_QUEUESEL_Q2 = 0x00020000,
  424. RXCS_QUEUESEL_Q3 = 0x00030000,
  425. RXCS_RETRYGAP_256ns = 0x00000000,
  426. RXCS_RETRYGAP_512ns = 0x00001000,
  427. RXCS_RETRYGAP_1024ns = 0x00002000,
  428. RXCS_RETRYGAP_2048ns = 0x00003000,
  429. RXCS_RETRYGAP_4096ns = 0x00004000,
  430. RXCS_RETRYGAP_8192ns = 0x00005000,
  431. RXCS_RETRYGAP_16384ns = 0x00006000,
  432. RXCS_RETRYGAP_32768ns = 0x00007000,
  433. RXCS_RETRYCNT_0 = 0x00000000,
  434. RXCS_RETRYCNT_4 = 0x00000100,
  435. RXCS_RETRYCNT_8 = 0x00000200,
  436. RXCS_RETRYCNT_12 = 0x00000300,
  437. RXCS_RETRYCNT_16 = 0x00000400,
  438. RXCS_RETRYCNT_20 = 0x00000500,
  439. RXCS_RETRYCNT_24 = 0x00000600,
  440. RXCS_RETRYCNT_28 = 0x00000700,
  441. RXCS_RETRYCNT_32 = 0x00000800,
  442. RXCS_RETRYCNT_36 = 0x00000900,
  443. RXCS_RETRYCNT_40 = 0x00000A00,
  444. RXCS_RETRYCNT_44 = 0x00000B00,
  445. RXCS_RETRYCNT_48 = 0x00000C00,
  446. RXCS_RETRYCNT_52 = 0x00000D00,
  447. RXCS_RETRYCNT_56 = 0x00000E00,
  448. RXCS_RETRYCNT_60 = 0x00000F00,
  449. RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
  450. RXCS_FIFOTHNP_128QW |
  451. RXCS_DMAREQSZ_128B |
  452. RXCS_RETRYGAP_256ns |
  453. RXCS_RETRYCNT_32,
  454. };
  455. #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
  456. /*
  457. * RX MAC Control/Status Bits
  458. */
  459. enum jme_rxmcs_bits {
  460. RXMCS_ALLFRAME = 0x00000800,
  461. RXMCS_BRDFRAME = 0x00000400,
  462. RXMCS_MULFRAME = 0x00000200,
  463. RXMCS_UNIFRAME = 0x00000100,
  464. RXMCS_ALLMULFRAME = 0x00000080,
  465. RXMCS_MULFILTERED = 0x00000040,
  466. RXMCS_RXCOLLDEC = 0x00000020,
  467. RXMCS_FLOWCTRL = 0x00000008,
  468. RXMCS_VTAGRM = 0x00000004,
  469. RXMCS_PREPAD = 0x00000002,
  470. RXMCS_CHECKSUM = 0x00000001,
  471. RXMCS_DEFAULT = RXMCS_VTAGRM |
  472. RXMCS_FLOWCTRL |
  473. RXMCS_CHECKSUM,
  474. };
  475. /*
  476. * Wakeup Frame setup interface registers
  477. */
  478. #define WAKEUP_FRAME_NR 8
  479. #define WAKEUP_FRAME_MASK_DWNR 4
  480. enum jme_wfoi_bit_masks {
  481. WFOI_MASK_SEL = 0x00000070,
  482. WFOI_CRC_SEL = 0x00000008,
  483. WFOI_FRAME_SEL = 0x00000007,
  484. };
  485. enum jme_wfoi_shifts {
  486. WFOI_MASK_SHIFT = 4,
  487. };
  488. /*
  489. * SMI Related definitions
  490. */
  491. enum jme_smi_bit_mask {
  492. SMI_DATA_MASK = 0xFFFF0000,
  493. SMI_REG_ADDR_MASK = 0x0000F800,
  494. SMI_PHY_ADDR_MASK = 0x000007C0,
  495. SMI_OP_WRITE = 0x00000020,
  496. /* Set to 1, after req done it'll be cleared to 0 */
  497. SMI_OP_REQ = 0x00000010,
  498. SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
  499. SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
  500. SMI_OP_MDC = 0x00000002, /* Software CLK Control */
  501. SMI_OP_MDEN = 0x00000001, /* Software access Enable */
  502. };
  503. enum jme_smi_bit_shift {
  504. SMI_DATA_SHIFT = 16,
  505. SMI_REG_ADDR_SHIFT = 11,
  506. SMI_PHY_ADDR_SHIFT = 6,
  507. };
  508. static inline uint32_t smi_reg_addr(int x)
  509. {
  510. return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
  511. }
  512. static inline uint32_t smi_phy_addr(int x)
  513. {
  514. return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
  515. }
  516. #define JME_PHY_TIMEOUT 100 /* 100 msec */
  517. #define JME_PHY_REG_NR 32
  518. /*
  519. * Global Host Control
  520. */
  521. enum jme_ghc_bit_mask {
  522. GHC_SWRST = 0x40000000,
  523. GHC_DPX = 0x00000040,
  524. GHC_SPEED = 0x00000030,
  525. GHC_LINK_POLL = 0x00000001,
  526. };
  527. enum jme_ghc_speed_val {
  528. GHC_SPEED_10M = 0x00000010,
  529. GHC_SPEED_100M = 0x00000020,
  530. GHC_SPEED_1000M = 0x00000030,
  531. };
  532. enum jme_ghc_to_clk {
  533. GHC_TO_CLK_OFF = 0x00000000,
  534. GHC_TO_CLK_GPHY = 0x00400000,
  535. GHC_TO_CLK_PCIE = 0x00800000,
  536. GHC_TO_CLK_INVALID = 0x00C00000,
  537. };
  538. enum jme_ghc_txmac_clk {
  539. GHC_TXMAC_CLK_OFF = 0x00000000,
  540. GHC_TXMAC_CLK_GPHY = 0x00100000,
  541. GHC_TXMAC_CLK_PCIE = 0x00200000,
  542. GHC_TXMAC_CLK_INVALID = 0x00300000,
  543. };
  544. /*
  545. * Power management control and status register
  546. */
  547. enum jme_pmcs_bit_masks {
  548. PMCS_WF7DET = 0x80000000,
  549. PMCS_WF6DET = 0x40000000,
  550. PMCS_WF5DET = 0x20000000,
  551. PMCS_WF4DET = 0x10000000,
  552. PMCS_WF3DET = 0x08000000,
  553. PMCS_WF2DET = 0x04000000,
  554. PMCS_WF1DET = 0x02000000,
  555. PMCS_WF0DET = 0x01000000,
  556. PMCS_LFDET = 0x00040000,
  557. PMCS_LRDET = 0x00020000,
  558. PMCS_MFDET = 0x00010000,
  559. PMCS_WF7EN = 0x00008000,
  560. PMCS_WF6EN = 0x00004000,
  561. PMCS_WF5EN = 0x00002000,
  562. PMCS_WF4EN = 0x00001000,
  563. PMCS_WF3EN = 0x00000800,
  564. PMCS_WF2EN = 0x00000400,
  565. PMCS_WF1EN = 0x00000200,
  566. PMCS_WF0EN = 0x00000100,
  567. PMCS_LFEN = 0x00000004,
  568. PMCS_LREN = 0x00000002,
  569. PMCS_MFEN = 0x00000001,
  570. };
  571. /*
  572. * Giga PHY Status Registers
  573. */
  574. enum jme_phy_link_bit_mask {
  575. PHY_LINK_SPEED_MASK = 0x0000C000,
  576. PHY_LINK_DUPLEX = 0x00002000,
  577. PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
  578. PHY_LINK_UP = 0x00000400,
  579. PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
  580. PHY_LINK_MDI_STAT = 0x00000040,
  581. };
  582. enum jme_phy_link_speed_val {
  583. PHY_LINK_SPEED_10M = 0x00000000,
  584. PHY_LINK_SPEED_100M = 0x00004000,
  585. PHY_LINK_SPEED_1000M = 0x00008000,
  586. };
  587. #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
  588. /*
  589. * SMB Control and Status
  590. */
  591. enum jme_smbcsr_bit_mask {
  592. SMBCSR_CNACK = 0x00020000,
  593. SMBCSR_RELOAD = 0x00010000,
  594. SMBCSR_EEPROMD = 0x00000020,
  595. SMBCSR_INITDONE = 0x00000010,
  596. SMBCSR_BUSY = 0x0000000F,
  597. };
  598. enum jme_smbintf_bit_mask {
  599. SMBINTF_HWDATR = 0xFF000000,
  600. SMBINTF_HWDATW = 0x00FF0000,
  601. SMBINTF_HWADDR = 0x0000FF00,
  602. SMBINTF_HWRWN = 0x00000020,
  603. SMBINTF_HWCMD = 0x00000010,
  604. SMBINTF_FASTM = 0x00000008,
  605. SMBINTF_GPIOSCL = 0x00000004,
  606. SMBINTF_GPIOSDA = 0x00000002,
  607. SMBINTF_GPIOEN = 0x00000001,
  608. };
  609. enum jme_smbintf_vals {
  610. SMBINTF_HWRWN_READ = 0x00000020,
  611. SMBINTF_HWRWN_WRITE = 0x00000000,
  612. };
  613. enum jme_smbintf_shifts {
  614. SMBINTF_HWDATR_SHIFT = 24,
  615. SMBINTF_HWDATW_SHIFT = 16,
  616. SMBINTF_HWADDR_SHIFT = 8,
  617. };
  618. #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
  619. #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
  620. #define JME_SMB_LEN 256
  621. #define JME_EEPROM_MAGIC 0x250
  622. /*
  623. * Timer Control/Status Register
  624. */
  625. enum jme_tmcsr_bit_masks {
  626. TMCSR_SWIT = 0x80000000,
  627. TMCSR_EN = 0x01000000,
  628. TMCSR_CNT = 0x00FFFFFF,
  629. };
  630. /*
  631. * General Purpose REG-0
  632. */
  633. enum jme_gpreg0_masks {
  634. GPREG0_DISSH = 0xFF000000,
  635. GPREG0_PCIRLMT = 0x00300000,
  636. GPREG0_PCCNOMUTCLR = 0x00040000,
  637. GPREG0_LNKINTPOLL = 0x00001000,
  638. GPREG0_PCCTMR = 0x00000300,
  639. GPREG0_PHYADDR = 0x0000001F,
  640. };
  641. enum jme_gpreg0_vals {
  642. GPREG0_DISSH_DW7 = 0x80000000,
  643. GPREG0_DISSH_DW6 = 0x40000000,
  644. GPREG0_DISSH_DW5 = 0x20000000,
  645. GPREG0_DISSH_DW4 = 0x10000000,
  646. GPREG0_DISSH_DW3 = 0x08000000,
  647. GPREG0_DISSH_DW2 = 0x04000000,
  648. GPREG0_DISSH_DW1 = 0x02000000,
  649. GPREG0_DISSH_DW0 = 0x01000000,
  650. GPREG0_DISSH_ALL = 0xFF000000,
  651. GPREG0_PCIRLMT_8 = 0x00000000,
  652. GPREG0_PCIRLMT_6 = 0x00100000,
  653. GPREG0_PCIRLMT_5 = 0x00200000,
  654. GPREG0_PCIRLMT_4 = 0x00300000,
  655. GPREG0_PCCTMR_16ns = 0x00000000,
  656. GPREG0_PCCTMR_256ns = 0x00000100,
  657. GPREG0_PCCTMR_1us = 0x00000200,
  658. GPREG0_PCCTMR_1ms = 0x00000300,
  659. GPREG0_PHYADDR_1 = 0x00000001,
  660. GPREG0_DEFAULT = GPREG0_DISSH_ALL |
  661. GPREG0_PCIRLMT_4 |
  662. GPREG0_PCCTMR_1us |
  663. GPREG0_PHYADDR_1,
  664. };
  665. /*
  666. * General Purpose REG-1
  667. * Note: All theses bits defined here are for
  668. * Chip mode revision 0x11 only
  669. */
  670. enum jme_gpreg1_masks {
  671. GPREG1_INTRDELAYUNIT = 0x00000018,
  672. GPREG1_INTRDELAYENABLE = 0x00000007,
  673. };
  674. enum jme_gpreg1_vals {
  675. GPREG1_RSSPATCH = 0x00000040,
  676. GPREG1_HALFMODEPATCH = 0x00000020,
  677. GPREG1_INTDLYUNIT_16NS = 0x00000000,
  678. GPREG1_INTDLYUNIT_256NS = 0x00000008,
  679. GPREG1_INTDLYUNIT_1US = 0x00000010,
  680. GPREG1_INTDLYUNIT_16US = 0x00000018,
  681. GPREG1_INTDLYEN_1U = 0x00000001,
  682. GPREG1_INTDLYEN_2U = 0x00000002,
  683. GPREG1_INTDLYEN_3U = 0x00000003,
  684. GPREG1_INTDLYEN_4U = 0x00000004,
  685. GPREG1_INTDLYEN_5U = 0x00000005,
  686. GPREG1_INTDLYEN_6U = 0x00000006,
  687. GPREG1_INTDLYEN_7U = 0x00000007,
  688. GPREG1_DEFAULT = 0x00000000,
  689. };
  690. /*
  691. * Interrupt Status Bits
  692. */
  693. enum jme_interrupt_bits {
  694. INTR_SWINTR = 0x80000000,
  695. INTR_TMINTR = 0x40000000,
  696. INTR_LINKCH = 0x20000000,
  697. INTR_PAUSERCV = 0x10000000,
  698. INTR_MAGICRCV = 0x08000000,
  699. INTR_WAKERCV = 0x04000000,
  700. INTR_PCCRX0TO = 0x02000000,
  701. INTR_PCCRX1TO = 0x01000000,
  702. INTR_PCCRX2TO = 0x00800000,
  703. INTR_PCCRX3TO = 0x00400000,
  704. INTR_PCCTXTO = 0x00200000,
  705. INTR_PCCRX0 = 0x00100000,
  706. INTR_PCCRX1 = 0x00080000,
  707. INTR_PCCRX2 = 0x00040000,
  708. INTR_PCCRX3 = 0x00020000,
  709. INTR_PCCTX = 0x00010000,
  710. INTR_RX3EMP = 0x00008000,
  711. INTR_RX2EMP = 0x00004000,
  712. INTR_RX1EMP = 0x00002000,
  713. INTR_RX0EMP = 0x00001000,
  714. INTR_RX3 = 0x00000800,
  715. INTR_RX2 = 0x00000400,
  716. INTR_RX1 = 0x00000200,
  717. INTR_RX0 = 0x00000100,
  718. INTR_TX7 = 0x00000080,
  719. INTR_TX6 = 0x00000040,
  720. INTR_TX5 = 0x00000020,
  721. INTR_TX4 = 0x00000010,
  722. INTR_TX3 = 0x00000008,
  723. INTR_TX2 = 0x00000004,
  724. INTR_TX1 = 0x00000002,
  725. INTR_TX0 = 0x00000001,
  726. };
  727. static const uint32_t INTR_ENABLE = INTR_LINKCH |
  728. INTR_RX0EMP |
  729. INTR_RX0 |
  730. INTR_TX0;
  731. /*
  732. * PCC Control Registers
  733. */
  734. enum jme_pccrx_masks {
  735. PCCRXTO_MASK = 0xFFFF0000,
  736. PCCRX_MASK = 0x0000FF00,
  737. };
  738. enum jme_pcctx_masks {
  739. PCCTXTO_MASK = 0xFFFF0000,
  740. PCCTX_MASK = 0x0000FF00,
  741. PCCTX_QS_MASK = 0x000000FF,
  742. };
  743. enum jme_pccrx_shifts {
  744. PCCRXTO_SHIFT = 16,
  745. PCCRX_SHIFT = 8,
  746. };
  747. enum jme_pcctx_shifts {
  748. PCCTXTO_SHIFT = 16,
  749. PCCTX_SHIFT = 8,
  750. };
  751. enum jme_pcctx_bits {
  752. PCCTXQ0_EN = 0x00000001,
  753. PCCTXQ1_EN = 0x00000002,
  754. PCCTXQ2_EN = 0x00000004,
  755. PCCTXQ3_EN = 0x00000008,
  756. PCCTXQ4_EN = 0x00000010,
  757. PCCTXQ5_EN = 0x00000020,
  758. PCCTXQ6_EN = 0x00000040,
  759. PCCTXQ7_EN = 0x00000080,
  760. };
  761. /*
  762. * Chip Mode Register
  763. */
  764. enum jme_chipmode_bit_masks {
  765. CM_FPGAVER_MASK = 0xFFFF0000,
  766. CM_CHIPREV_MASK = 0x0000FF00,
  767. CM_CHIPMODE_MASK = 0x0000000F,
  768. };
  769. enum jme_chipmode_shifts {
  770. CM_FPGAVER_SHIFT = 16,
  771. CM_CHIPREV_SHIFT = 8,
  772. };
  773. /*
  774. * Workaround
  775. */
  776. static inline int is_buggy250(unsigned short device, unsigned int chiprev)
  777. {
  778. return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
  779. }
  780. /*
  781. * Read/Write I/O Registers
  782. */
  783. static inline uint32_t jread32(struct jme_adapter *jme, uint32_t reg)
  784. {
  785. return readl(jme->regs + reg);
  786. }
  787. static inline void jwrite32(struct jme_adapter *jme, uint32_t reg, uint32_t val)
  788. {
  789. writel(val, jme->regs + reg);
  790. }
  791. static void jwrite32f(struct jme_adapter *jme, uint32_t reg, uint32_t val)
  792. {
  793. /*
  794. * Read after write should cause flush
  795. */
  796. writel(val, jme->regs + reg);
  797. readl(jme->regs + reg);
  798. }
  799. #endif