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  1. /*
  2. * Copyright(c) 2007 Atheros Corporation. All rights reserved.
  3. * Copyright(c) 2007 xiong huang <xiong.huang@atheros.com>
  4. *
  5. * Derived from Intel e1000 driver
  6. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  7. *
  8. * Modified for iPXE, October 2009 by Joshua Oreman <oremanj@rwcr.net>
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the Free
  12. * Software Foundation; either version 2 of the License, or (at your option)
  13. * any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful, but WITHOUT
  16. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18. * more details.
  19. *
  20. * You should have received a copy of the GNU General Public License along with
  21. * this program; if not, write to the Free Software Foundation, Inc., 51
  22. * Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  23. */
  24. FILE_LICENCE ( GPL2_OR_LATER );
  25. #ifndef _ATL1E_H_
  26. #define _ATL1E_H_
  27. #include <mii.h>
  28. #include <stdlib.h>
  29. #include <string.h>
  30. #include <unistd.h>
  31. #include <byteswap.h>
  32. #include <errno.h>
  33. #include <ipxe/malloc.h>
  34. #include <ipxe/pci.h>
  35. #include <ipxe/pci_io.h>
  36. #include <ipxe/iobuf.h>
  37. #include <ipxe/netdevice.h>
  38. #include <ipxe/ethernet.h>
  39. #include <ipxe/if_ether.h>
  40. #include <ipxe/io.h>
  41. #define ETH_FCS_LEN 4
  42. #define VLAN_HLEN 4
  43. #define NET_IP_ALIGN 2
  44. #define SPEED_0 0xffff
  45. #define SPEED_10 10
  46. #define SPEED_100 100
  47. #define SPEED_1000 1000
  48. #define HALF_DUPLEX 1
  49. #define FULL_DUPLEX 2
  50. /* Error Codes */
  51. #define AT_ERR_EEPROM 1
  52. #define AT_ERR_PHY 2
  53. #define AT_ERR_CONFIG 3
  54. #define AT_ERR_PARAM 4
  55. #define AT_ERR_MAC_TYPE 5
  56. #define AT_ERR_PHY_TYPE 6
  57. #define AT_ERR_PHY_SPEED 7
  58. #define AT_ERR_PHY_RES 8
  59. #define AT_ERR_TIMEOUT 9
  60. #define AT_MAX_RECEIVE_QUEUE 4
  61. #define AT_PAGE_NUM_PER_QUEUE 2
  62. #define AT_TWSI_EEPROM_TIMEOUT 100
  63. #define AT_HW_MAX_IDLE_DELAY 10
  64. #define AT_REGS_LEN 75
  65. #define AT_EEPROM_LEN 512
  66. /* tpd word 2 */
  67. #define TPD_BUFLEN_MASK 0x3FFF
  68. #define TPD_BUFLEN_SHIFT 0
  69. /* tpd word 3 bits 0:4 */
  70. #define TPD_EOP_MASK 0x0001
  71. #define TPD_EOP_SHIFT 0
  72. struct atl1e_tpd_desc {
  73. u64 buffer_addr;
  74. u32 word2;
  75. u32 word3;
  76. };
  77. #define MAX_TX_BUF_LEN 0x2000
  78. #define MAX_TX_BUF_SHIFT 13
  79. /* rrs word 1 bit 0:31 */
  80. #define RRS_RX_CSUM_MASK 0xFFFF
  81. #define RRS_RX_CSUM_SHIFT 0
  82. #define RRS_PKT_SIZE_MASK 0x3FFF
  83. #define RRS_PKT_SIZE_SHIFT 16
  84. #define RRS_CPU_NUM_MASK 0x0003
  85. #define RRS_CPU_NUM_SHIFT 30
  86. #define RRS_IS_RSS_IPV4 0x0001
  87. #define RRS_IS_RSS_IPV4_TCP 0x0002
  88. #define RRS_IS_RSS_IPV6 0x0004
  89. #define RRS_IS_RSS_IPV6_TCP 0x0008
  90. #define RRS_IS_IPV6 0x0010
  91. #define RRS_IS_IP_FRAG 0x0020
  92. #define RRS_IS_IP_DF 0x0040
  93. #define RRS_IS_802_3 0x0080
  94. #define RRS_IS_VLAN_TAG 0x0100
  95. #define RRS_IS_ERR_FRAME 0x0200
  96. #define RRS_IS_IPV4 0x0400
  97. #define RRS_IS_UDP 0x0800
  98. #define RRS_IS_TCP 0x1000
  99. #define RRS_IS_BCAST 0x2000
  100. #define RRS_IS_MCAST 0x4000
  101. #define RRS_IS_PAUSE 0x8000
  102. #define RRS_ERR_BAD_CRC 0x0001
  103. #define RRS_ERR_CODE 0x0002
  104. #define RRS_ERR_DRIBBLE 0x0004
  105. #define RRS_ERR_RUNT 0x0008
  106. #define RRS_ERR_RX_OVERFLOW 0x0010
  107. #define RRS_ERR_TRUNC 0x0020
  108. #define RRS_ERR_IP_CSUM 0x0040
  109. #define RRS_ERR_L4_CSUM 0x0080
  110. #define RRS_ERR_LENGTH 0x0100
  111. #define RRS_ERR_DES_ADDR 0x0200
  112. struct atl1e_recv_ret_status {
  113. u16 seq_num;
  114. u16 hash_lo;
  115. u32 word1;
  116. u16 pkt_flag;
  117. u16 err_flag;
  118. u16 hash_hi;
  119. u16 vtag;
  120. };
  121. enum atl1e_dma_req_block {
  122. atl1e_dma_req_128 = 0,
  123. atl1e_dma_req_256 = 1,
  124. atl1e_dma_req_512 = 2,
  125. atl1e_dma_req_1024 = 3,
  126. atl1e_dma_req_2048 = 4,
  127. atl1e_dma_req_4096 = 5
  128. };
  129. enum atl1e_nic_type {
  130. athr_l1e = 0,
  131. athr_l2e_revA = 1,
  132. athr_l2e_revB = 2
  133. };
  134. struct atl1e_hw {
  135. u8 *hw_addr; /* inner register address */
  136. struct atl1e_adapter *adapter;
  137. enum atl1e_nic_type nic_type;
  138. u8 mac_addr[ETH_ALEN];
  139. u8 perm_mac_addr[ETH_ALEN];
  140. u16 mii_autoneg_adv_reg;
  141. u16 mii_1000t_ctrl_reg;
  142. enum atl1e_dma_req_block dmar_block;
  143. enum atl1e_dma_req_block dmaw_block;
  144. int phy_configured;
  145. int re_autoneg;
  146. int emi_ca;
  147. };
  148. /*
  149. * wrapper around a pointer to a socket buffer,
  150. * so a DMA handle can be stored along with the buffer
  151. */
  152. struct atl1e_tx_buffer {
  153. struct io_buffer *iob;
  154. u16 length;
  155. u32 dma;
  156. };
  157. struct atl1e_rx_page {
  158. u32 dma; /* receive rage DMA address */
  159. u8 *addr; /* receive rage virtual address */
  160. u32 write_offset_dma; /* the DMA address which contain the
  161. receive data offset in the page */
  162. u32 *write_offset_addr; /* the virtaul address which contain
  163. the receive data offset in the page */
  164. u32 read_offset; /* the offset where we have read */
  165. };
  166. struct atl1e_rx_page_desc {
  167. struct atl1e_rx_page rx_page[AT_PAGE_NUM_PER_QUEUE];
  168. u8 rx_using;
  169. u16 rx_nxseq;
  170. };
  171. /* transmit packet descriptor (tpd) ring */
  172. struct atl1e_tx_ring {
  173. struct atl1e_tpd_desc *desc; /* descriptor ring virtual address */
  174. u32 dma; /* descriptor ring physical address */
  175. u16 count; /* the count of transmit rings */
  176. u16 next_to_use;
  177. u16 next_to_clean;
  178. struct atl1e_tx_buffer *tx_buffer;
  179. u32 cmb_dma;
  180. u32 *cmb;
  181. };
  182. /* receive packet descriptor ring */
  183. struct atl1e_rx_ring {
  184. void *desc;
  185. u32 dma;
  186. int size;
  187. u32 page_size; /* bytes length of rxf page */
  188. u32 real_page_size; /* real_page_size = page_size + jumbo + aliagn */
  189. struct atl1e_rx_page_desc rx_page_desc;
  190. };
  191. /* board specific private data structure */
  192. struct atl1e_adapter {
  193. struct net_device *netdev;
  194. struct pci_device *pdev;
  195. struct mii_if_info mii; /* MII interface info */
  196. struct atl1e_hw hw;
  197. u16 link_speed;
  198. u16 link_duplex;
  199. /* All Descriptor memory */
  200. u32 ring_dma;
  201. void *ring_vir_addr;
  202. u32 ring_size;
  203. struct atl1e_tx_ring tx_ring;
  204. struct atl1e_rx_ring rx_ring;
  205. int bd_number; /* board number;*/
  206. };
  207. #define AT_WRITE_REG(a, reg, value) \
  208. writel((value), ((a)->hw_addr + reg))
  209. #define AT_WRITE_FLUSH(a) \
  210. readl((a)->hw_addr)
  211. #define AT_READ_REG(a, reg) \
  212. readl((a)->hw_addr + reg)
  213. #define AT_WRITE_REGB(a, reg, value) \
  214. writeb((value), ((a)->hw_addr + reg))
  215. #define AT_READ_REGB(a, reg) \
  216. readb((a)->hw_addr + reg)
  217. #define AT_WRITE_REGW(a, reg, value) \
  218. writew((value), ((a)->hw_addr + reg))
  219. #define AT_READ_REGW(a, reg) \
  220. readw((a)->hw_addr + reg)
  221. #define AT_WRITE_REG_ARRAY(a, reg, offset, value) \
  222. writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))
  223. #define AT_READ_REG_ARRAY(a, reg, offset) \
  224. readl(((a)->hw_addr + reg) + ((offset) << 2))
  225. extern int atl1e_up(struct atl1e_adapter *adapter);
  226. extern void atl1e_down(struct atl1e_adapter *adapter);
  227. extern s32 atl1e_reset_hw(struct atl1e_hw *hw);
  228. /********** Hardware-level functionality: **********/
  229. /* function prototype */
  230. s32 atl1e_reset_hw(struct atl1e_hw *hw);
  231. s32 atl1e_read_mac_addr(struct atl1e_hw *hw);
  232. s32 atl1e_init_hw(struct atl1e_hw *hw);
  233. s32 atl1e_phy_commit(struct atl1e_hw *hw);
  234. s32 atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex);
  235. u32 atl1e_auto_get_fc(struct atl1e_adapter *adapter, u16 duplex);
  236. s32 atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data);
  237. s32 atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data);
  238. s32 atl1e_validate_mdi_setting(struct atl1e_hw *hw);
  239. void atl1e_hw_set_mac_addr(struct atl1e_hw *hw);
  240. s32 atl1e_phy_enter_power_saving(struct atl1e_hw *hw);
  241. s32 atl1e_phy_leave_power_saving(struct atl1e_hw *hw);
  242. s32 atl1e_phy_init(struct atl1e_hw *hw);
  243. int atl1e_check_eeprom_exist(struct atl1e_hw *hw);
  244. void atl1e_force_ps(struct atl1e_hw *hw);
  245. s32 atl1e_restart_autoneg(struct atl1e_hw *hw);
  246. /* register definition */
  247. #define REG_PM_CTRLSTAT 0x44
  248. #define REG_PCIE_CAP_LIST 0x58
  249. #define REG_DEVICE_CAP 0x5C
  250. #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
  251. #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
  252. #define REG_DEVICE_CTRL 0x60
  253. #define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
  254. #define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
  255. #define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
  256. #define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
  257. #define REG_VPD_CAP 0x6C
  258. #define VPD_CAP_ID_MASK 0xff
  259. #define VPD_CAP_ID_SHIFT 0
  260. #define VPD_CAP_NEXT_PTR_MASK 0xFF
  261. #define VPD_CAP_NEXT_PTR_SHIFT 8
  262. #define VPD_CAP_VPD_ADDR_MASK 0x7FFF
  263. #define VPD_CAP_VPD_ADDR_SHIFT 16
  264. #define VPD_CAP_VPD_FLAG 0x80000000
  265. #define REG_VPD_DATA 0x70
  266. #define REG_SPI_FLASH_CTRL 0x200
  267. #define SPI_FLASH_CTRL_STS_NON_RDY 0x1
  268. #define SPI_FLASH_CTRL_STS_WEN 0x2
  269. #define SPI_FLASH_CTRL_STS_WPEN 0x80
  270. #define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
  271. #define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
  272. #define SPI_FLASH_CTRL_INS_MASK 0x7
  273. #define SPI_FLASH_CTRL_INS_SHIFT 8
  274. #define SPI_FLASH_CTRL_START 0x800
  275. #define SPI_FLASH_CTRL_EN_VPD 0x2000
  276. #define SPI_FLASH_CTRL_LDSTART 0x8000
  277. #define SPI_FLASH_CTRL_CS_HI_MASK 0x3
  278. #define SPI_FLASH_CTRL_CS_HI_SHIFT 16
  279. #define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
  280. #define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
  281. #define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
  282. #define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
  283. #define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
  284. #define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
  285. #define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
  286. #define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
  287. #define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
  288. #define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
  289. #define SPI_FLASH_CTRL_WAIT_READY 0x10000000
  290. #define REG_SPI_ADDR 0x204
  291. #define REG_SPI_DATA 0x208
  292. #define REG_SPI_FLASH_CONFIG 0x20C
  293. #define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
  294. #define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
  295. #define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
  296. #define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
  297. #define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
  298. #define REG_SPI_FLASH_OP_PROGRAM 0x210
  299. #define REG_SPI_FLASH_OP_SC_ERASE 0x211
  300. #define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
  301. #define REG_SPI_FLASH_OP_RDID 0x213
  302. #define REG_SPI_FLASH_OP_WREN 0x214
  303. #define REG_SPI_FLASH_OP_RDSR 0x215
  304. #define REG_SPI_FLASH_OP_WRSR 0x216
  305. #define REG_SPI_FLASH_OP_READ 0x217
  306. #define REG_TWSI_CTRL 0x218
  307. #define TWSI_CTRL_LD_OFFSET_MASK 0xFF
  308. #define TWSI_CTRL_LD_OFFSET_SHIFT 0
  309. #define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
  310. #define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
  311. #define TWSI_CTRL_SW_LDSTART 0x800
  312. #define TWSI_CTRL_HW_LDSTART 0x1000
  313. #define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x0x7F
  314. #define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
  315. #define TWSI_CTRL_LD_EXIST 0x400000
  316. #define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
  317. #define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
  318. #define TWSI_CTRL_FREQ_SEL_100K 0
  319. #define TWSI_CTRL_FREQ_SEL_200K 1
  320. #define TWSI_CTRL_FREQ_SEL_300K 2
  321. #define TWSI_CTRL_FREQ_SEL_400K 3
  322. #define TWSI_CTRL_SMB_SLV_ADDR
  323. #define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
  324. #define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
  325. #define REG_PCIE_DEV_MISC_CTRL 0x21C
  326. #define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
  327. #define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
  328. #define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
  329. #define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
  330. #define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
  331. #define REG_PCIE_PHYMISC 0x1000
  332. #define PCIE_PHYMISC_FORCE_RCV_DET 0x4
  333. #define REG_LTSSM_TEST_MODE 0x12FC
  334. #define LTSSM_TEST_MODE_DEF 0xE000
  335. /* Selene Master Control Register */
  336. #define REG_MASTER_CTRL 0x1400
  337. #define MASTER_CTRL_SOFT_RST 0x1
  338. #define MASTER_CTRL_MTIMER_EN 0x2
  339. #define MASTER_CTRL_ITIMER_EN 0x4
  340. #define MASTER_CTRL_MANUAL_INT 0x8
  341. #define MASTER_CTRL_ITIMER2_EN 0x20
  342. #define MASTER_CTRL_INT_RDCLR 0x40
  343. #define MASTER_CTRL_LED_MODE 0x200
  344. #define MASTER_CTRL_REV_NUM_SHIFT 16
  345. #define MASTER_CTRL_REV_NUM_MASK 0xff
  346. #define MASTER_CTRL_DEV_ID_SHIFT 24
  347. #define MASTER_CTRL_DEV_ID_MASK 0xff
  348. /* Timer Initial Value Register */
  349. #define REG_MANUAL_TIMER_INIT 0x1404
  350. /* IRQ ModeratorTimer Initial Value Register */
  351. #define REG_IRQ_MODU_TIMER_INIT 0x1408 /* w */
  352. #define REG_IRQ_MODU_TIMER2_INIT 0x140A /* w */
  353. #define REG_GPHY_CTRL 0x140C
  354. #define GPHY_CTRL_EXT_RESET 1
  355. #define GPHY_CTRL_PIPE_MOD 2
  356. #define GPHY_CTRL_TEST_MODE_MASK 3
  357. #define GPHY_CTRL_TEST_MODE_SHIFT 2
  358. #define GPHY_CTRL_BERT_START 0x10
  359. #define GPHY_CTRL_GATE_25M_EN 0x20
  360. #define GPHY_CTRL_LPW_EXIT 0x40
  361. #define GPHY_CTRL_PHY_IDDQ 0x80
  362. #define GPHY_CTRL_PHY_IDDQ_DIS 0x100
  363. #define GPHY_CTRL_PCLK_SEL_DIS 0x200
  364. #define GPHY_CTRL_HIB_EN 0x400
  365. #define GPHY_CTRL_HIB_PULSE 0x800
  366. #define GPHY_CTRL_SEL_ANA_RST 0x1000
  367. #define GPHY_CTRL_PHY_PLL_ON 0x2000
  368. #define GPHY_CTRL_PWDOWN_HW 0x4000
  369. #define GPHY_CTRL_DEFAULT (\
  370. GPHY_CTRL_PHY_PLL_ON |\
  371. GPHY_CTRL_SEL_ANA_RST |\
  372. GPHY_CTRL_HIB_PULSE |\
  373. GPHY_CTRL_HIB_EN)
  374. #define GPHY_CTRL_PW_WOL_DIS (\
  375. GPHY_CTRL_PHY_PLL_ON |\
  376. GPHY_CTRL_SEL_ANA_RST |\
  377. GPHY_CTRL_HIB_PULSE |\
  378. GPHY_CTRL_HIB_EN |\
  379. GPHY_CTRL_PWDOWN_HW |\
  380. GPHY_CTRL_PCLK_SEL_DIS |\
  381. GPHY_CTRL_PHY_IDDQ)
  382. /* IRQ Anti-Lost Timer Initial Value Register */
  383. #define REG_CMBDISDMA_TIMER 0x140E
  384. /* Block IDLE Status Register */
  385. #define REG_IDLE_STATUS 0x1410
  386. #define IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */
  387. #define IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */
  388. #define IDLE_STATUS_RXQ 4 /* 1: RXQ state machine is in non-IDLE state. 0: RXQ is idling */
  389. #define IDLE_STATUS_TXQ 8 /* 1: TXQ state machine is in non-IDLE state. 0: TXQ is idling */
  390. #define IDLE_STATUS_DMAR 0x10 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */
  391. #define IDLE_STATUS_DMAW 0x20 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */
  392. #define IDLE_STATUS_SMB 0x40 /* 1: SMB state machine is in non-IDLE state. 0: SMB is idling */
  393. #define IDLE_STATUS_CMB 0x80 /* 1: CMB state machine is in non-IDLE state. 0: CMB is idling */
  394. /* MDIO Control Register */
  395. #define REG_MDIO_CTRL 0x1414
  396. #define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */
  397. #define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register*/
  398. #define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
  399. #define MDIO_REG_ADDR_SHIFT 16
  400. #define MDIO_RW 0x200000 /* 1: read, 0: write */
  401. #define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
  402. #define MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle*/
  403. #define MDIO_CLK_SEL_SHIFT 24
  404. #define MDIO_CLK_25_4 0
  405. #define MDIO_CLK_25_6 2
  406. #define MDIO_CLK_25_8 3
  407. #define MDIO_CLK_25_10 4
  408. #define MDIO_CLK_25_14 5
  409. #define MDIO_CLK_25_20 6
  410. #define MDIO_CLK_25_28 7
  411. #define MDIO_BUSY 0x8000000
  412. #define MDIO_AP_EN 0x10000000
  413. #define MDIO_WAIT_TIMES 10
  414. /* MII PHY Status Register */
  415. #define REG_PHY_STATUS 0x1418
  416. #define PHY_STATUS_100M 0x20000
  417. #define PHY_STATUS_EMI_CA 0x40000
  418. /* BIST Control and Status Register0 (for the Packet Memory) */
  419. #define REG_BIST0_CTRL 0x141c
  420. #define BIST0_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
  421. /* BIST process and reset to zero when BIST is done */
  422. #define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */
  423. /* decoder failure or more than 1 cell stuck-to-x failure */
  424. #define BIST0_FUSE_FLAG 0x4 /* 1: Indicating one cell has been fixed */
  425. /* BIST Control and Status Register1(for the retry buffer of PCI Express) */
  426. #define REG_BIST1_CTRL 0x1420
  427. #define BIST1_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
  428. /* BIST process and reset to zero when BIST is done */
  429. #define BIST1_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */
  430. /* decoder failure or more than 1 cell stuck-to-x failure.*/
  431. #define BIST1_FUSE_FLAG 0x4
  432. /* SerDes Lock Detect Control and Status Register */
  433. #define REG_SERDES_LOCK 0x1424
  434. #define SERDES_LOCK_DETECT 1 /* 1: SerDes lock detected . This signal comes from Analog SerDes */
  435. #define SERDES_LOCK_DETECT_EN 2 /* 1: Enable SerDes Lock detect function */
  436. /* MAC Control Register */
  437. #define REG_MAC_CTRL 0x1480
  438. #define MAC_CTRL_TX_EN 1 /* 1: Transmit Enable */
  439. #define MAC_CTRL_RX_EN 2 /* 1: Receive Enable */
  440. #define MAC_CTRL_TX_FLOW 4 /* 1: Transmit Flow Control Enable */
  441. #define MAC_CTRL_RX_FLOW 8 /* 1: Receive Flow Control Enable */
  442. #define MAC_CTRL_LOOPBACK 0x10 /* 1: Loop back at G/MII Interface */
  443. #define MAC_CTRL_DUPLX 0x20 /* 1: Full-duplex mode 0: Half-duplex mode */
  444. #define MAC_CTRL_ADD_CRC 0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */
  445. #define MAC_CTRL_PAD 0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */
  446. #define MAC_CTRL_LENCHK 0x100 /* 1: Instruct MAC to check if length field matches the real packet length */
  447. #define MAC_CTRL_HUGE_EN 0x200 /* 1: receive Jumbo frame enable */
  448. #define MAC_CTRL_PRMLEN_SHIFT 10 /* Preamble length */
  449. #define MAC_CTRL_PRMLEN_MASK 0xf
  450. #define MAC_CTRL_RMV_VLAN 0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */
  451. #define MAC_CTRL_PROMIS_EN 0x8000 /* 1: Promiscuous Mode Enable */
  452. #define MAC_CTRL_TX_PAUSE 0x10000 /* 1: transmit test pause */
  453. #define MAC_CTRL_SCNT 0x20000 /* 1: shortcut slot time counter */
  454. #define MAC_CTRL_SRST_TX 0x40000 /* 1: synchronized reset Transmit MAC module */
  455. #define MAC_CTRL_TX_SIMURST 0x80000 /* 1: transmit simulation reset */
  456. #define MAC_CTRL_SPEED_SHIFT 20 /* 10: gigabit 01:10M/100M */
  457. #define MAC_CTRL_SPEED_MASK 0x300000
  458. #define MAC_CTRL_SPEED_1000 2
  459. #define MAC_CTRL_SPEED_10_100 1
  460. #define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 /* 1: transmit maximum backoff (half-duplex test bit) */
  461. #define MAC_CTRL_TX_HUGE 0x800000 /* 1: transmit huge enable */
  462. #define MAC_CTRL_RX_CHKSUM_EN 0x1000000 /* 1: RX checksum enable */
  463. #define MAC_CTRL_MC_ALL_EN 0x2000000 /* 1: upload all multicast frame without error to system */
  464. #define MAC_CTRL_BC_EN 0x4000000 /* 1: upload all broadcast frame without error to system */
  465. #define MAC_CTRL_DBG 0x8000000 /* 1: upload all received frame to system (Debug Mode) */
  466. /* MAC IPG/IFG Control Register */
  467. #define REG_MAC_IPG_IFG 0x1484
  468. #define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back inter-packet gap. The default is 96-bit time */
  469. #define MAC_IPG_IFG_IPGT_MASK 0x7f
  470. #define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to enforce in between RX frames */
  471. #define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
  472. #define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
  473. #define MAC_IPG_IFG_IPGR1_MASK 0x7f
  474. #define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
  475. #define MAC_IPG_IFG_IPGR2_MASK 0x7f
  476. /* MAC STATION ADDRESS */
  477. #define REG_MAC_STA_ADDR 0x1488
  478. /* Hash table for multicast address */
  479. #define REG_RX_HASH_TABLE 0x1490
  480. /* MAC Half-Duplex Control Register */
  481. #define REG_MAC_HALF_DUPLX_CTRL 0x1498
  482. #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
  483. #define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
  484. #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 /* Retransmission maximum, afterwards the packet will be discarded */
  485. #define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
  486. #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */
  487. #define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 /* 1: No back-off on collision, immediately start the retransmission */
  488. #define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */
  489. #define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
  490. #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */
  491. #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
  492. #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
  493. #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
  494. /* Maximum Frame Length Control Register */
  495. #define REG_MTU 0x149c
  496. /* Wake-On-Lan control register */
  497. #define REG_WOL_CTRL 0x14a0
  498. #define WOL_PATTERN_EN 0x00000001
  499. #define WOL_PATTERN_PME_EN 0x00000002
  500. #define WOL_MAGIC_EN 0x00000004
  501. #define WOL_MAGIC_PME_EN 0x00000008
  502. #define WOL_LINK_CHG_EN 0x00000010
  503. #define WOL_LINK_CHG_PME_EN 0x00000020
  504. #define WOL_PATTERN_ST 0x00000100
  505. #define WOL_MAGIC_ST 0x00000200
  506. #define WOL_LINKCHG_ST 0x00000400
  507. #define WOL_CLK_SWITCH_EN 0x00008000
  508. #define WOL_PT0_EN 0x00010000
  509. #define WOL_PT1_EN 0x00020000
  510. #define WOL_PT2_EN 0x00040000
  511. #define WOL_PT3_EN 0x00080000
  512. #define WOL_PT4_EN 0x00100000
  513. #define WOL_PT5_EN 0x00200000
  514. #define WOL_PT6_EN 0x00400000
  515. /* WOL Length ( 2 DWORD ) */
  516. #define REG_WOL_PATTERN_LEN 0x14a4
  517. #define WOL_PT_LEN_MASK 0x7f
  518. #define WOL_PT0_LEN_SHIFT 0
  519. #define WOL_PT1_LEN_SHIFT 8
  520. #define WOL_PT2_LEN_SHIFT 16
  521. #define WOL_PT3_LEN_SHIFT 24
  522. #define WOL_PT4_LEN_SHIFT 0
  523. #define WOL_PT5_LEN_SHIFT 8
  524. #define WOL_PT6_LEN_SHIFT 16
  525. /* Internal SRAM Partition Register */
  526. #define REG_SRAM_TRD_ADDR 0x1518
  527. #define REG_SRAM_TRD_LEN 0x151C
  528. #define REG_SRAM_RXF_ADDR 0x1520
  529. #define REG_SRAM_RXF_LEN 0x1524
  530. #define REG_SRAM_TXF_ADDR 0x1528
  531. #define REG_SRAM_TXF_LEN 0x152C
  532. #define REG_SRAM_TCPH_ADDR 0x1530
  533. #define REG_SRAM_PKTH_ADDR 0x1532
  534. /* Load Ptr Register */
  535. #define REG_LOAD_PTR 0x1534 /* Software sets this bit after the initialization of the head and tail */
  536. /*
  537. * addresses of all descriptors, as well as the following descriptor
  538. * control register, which triggers each function block to load the head
  539. * pointer to prepare for the operation. This bit is then self-cleared
  540. * after one cycle.
  541. */
  542. /* Descriptor Control register */
  543. #define REG_RXF3_BASE_ADDR_HI 0x153C
  544. #define REG_DESC_BASE_ADDR_HI 0x1540
  545. #define REG_RXF0_BASE_ADDR_HI 0x1540 /* share with DESC BASE ADDR HI */
  546. #define REG_HOST_RXF0_PAGE0_LO 0x1544
  547. #define REG_HOST_RXF0_PAGE1_LO 0x1548
  548. #define REG_TPD_BASE_ADDR_LO 0x154C
  549. #define REG_RXF1_BASE_ADDR_HI 0x1550
  550. #define REG_RXF2_BASE_ADDR_HI 0x1554
  551. #define REG_HOST_RXFPAGE_SIZE 0x1558
  552. #define REG_TPD_RING_SIZE 0x155C
  553. /* RSS about */
  554. #define REG_RSS_KEY0 0x14B0
  555. #define REG_RSS_KEY1 0x14B4
  556. #define REG_RSS_KEY2 0x14B8
  557. #define REG_RSS_KEY3 0x14BC
  558. #define REG_RSS_KEY4 0x14C0
  559. #define REG_RSS_KEY5 0x14C4
  560. #define REG_RSS_KEY6 0x14C8
  561. #define REG_RSS_KEY7 0x14CC
  562. #define REG_RSS_KEY8 0x14D0
  563. #define REG_RSS_KEY9 0x14D4
  564. #define REG_IDT_TABLE4 0x14E0
  565. #define REG_IDT_TABLE5 0x14E4
  566. #define REG_IDT_TABLE6 0x14E8
  567. #define REG_IDT_TABLE7 0x14EC
  568. #define REG_IDT_TABLE0 0x1560
  569. #define REG_IDT_TABLE1 0x1564
  570. #define REG_IDT_TABLE2 0x1568
  571. #define REG_IDT_TABLE3 0x156C
  572. #define REG_IDT_TABLE REG_IDT_TABLE0
  573. #define REG_RSS_HASH_VALUE 0x1570
  574. #define REG_RSS_HASH_FLAG 0x1574
  575. #define REG_BASE_CPU_NUMBER 0x157C
  576. /* TXQ Control Register */
  577. #define REG_TXQ_CTRL 0x1580
  578. #define TXQ_CTRL_NUM_TPD_BURST_MASK 0xF
  579. #define TXQ_CTRL_NUM_TPD_BURST_SHIFT 0
  580. #define TXQ_CTRL_EN 0x20 /* 1: Enable TXQ */
  581. #define TXQ_CTRL_ENH_MODE 0x40 /* Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched. */
  582. #define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */
  583. #define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
  584. /* Jumbo packet Threshold for task offload */
  585. #define REG_TX_EARLY_TH 0x1584 /* Jumbo frame threshold in QWORD unit. Packet greater than */
  586. /* JUMBO_TASK_OFFLOAD_THRESHOLD will not be task offloaded. */
  587. #define TX_TX_EARLY_TH_MASK 0x7ff
  588. #define TX_TX_EARLY_TH_SHIFT 0
  589. /* RXQ Control Register */
  590. #define REG_RXQ_CTRL 0x15A0
  591. #define RXQ_CTRL_PBA_ALIGN_32 0 /* rx-packet alignment */
  592. #define RXQ_CTRL_PBA_ALIGN_64 1
  593. #define RXQ_CTRL_PBA_ALIGN_128 2
  594. #define RXQ_CTRL_PBA_ALIGN_256 3
  595. #define RXQ_CTRL_Q1_EN 0x10
  596. #define RXQ_CTRL_Q2_EN 0x20
  597. #define RXQ_CTRL_Q3_EN 0x40
  598. #define RXQ_CTRL_IPV6_XSUM_VERIFY_EN 0x80
  599. #define RXQ_CTRL_HASH_TLEN_SHIFT 8
  600. #define RXQ_CTRL_HASH_TLEN_MASK 0xFF
  601. #define RXQ_CTRL_HASH_TYPE_IPV4 0x10000
  602. #define RXQ_CTRL_HASH_TYPE_IPV4_TCP 0x20000
  603. #define RXQ_CTRL_HASH_TYPE_IPV6 0x40000
  604. #define RXQ_CTRL_HASH_TYPE_IPV6_TCP 0x80000
  605. #define RXQ_CTRL_RSS_MODE_DISABLE 0
  606. #define RXQ_CTRL_RSS_MODE_SQSINT 0x4000000
  607. #define RXQ_CTRL_RSS_MODE_MQUESINT 0x8000000
  608. #define RXQ_CTRL_RSS_MODE_MQUEMINT 0xC000000
  609. #define RXQ_CTRL_NIP_QUEUE_SEL_TBL 0x10000000
  610. #define RXQ_CTRL_HASH_ENABLE 0x20000000
  611. #define RXQ_CTRL_CUT_THRU_EN 0x40000000
  612. #define RXQ_CTRL_EN 0x80000000
  613. /* Rx jumbo packet threshold and rrd retirement timer */
  614. #define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
  615. /*
  616. * Jumbo packet threshold for non-VLAN packet, in QWORD (64-bit) unit.
  617. * When the packet length greater than or equal to this value, RXQ
  618. * shall start cut-through forwarding of the received packet.
  619. */
  620. #define RXQ_JMBOSZ_TH_MASK 0x7ff
  621. #define RXQ_JMBOSZ_TH_SHIFT 0 /* RRD retirement timer. Decrement by 1 after every 512ns passes*/
  622. #define RXQ_JMBO_LKAH_MASK 0xf
  623. #define RXQ_JMBO_LKAH_SHIFT 11
  624. /* RXF flow control register */
  625. #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
  626. #define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
  627. #define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
  628. #define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
  629. #define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
  630. /* DMA Engine Control Register */
  631. #define REG_DMA_CTRL 0x15C0
  632. #define DMA_CTRL_DMAR_IN_ORDER 0x1
  633. #define DMA_CTRL_DMAR_ENH_ORDER 0x2
  634. #define DMA_CTRL_DMAR_OUT_ORDER 0x4
  635. #define DMA_CTRL_RCB_VALUE 0x8
  636. #define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
  637. #define DMA_CTRL_DMAR_BURST_LEN_MASK 7
  638. #define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
  639. #define DMA_CTRL_DMAW_BURST_LEN_MASK 7
  640. #define DMA_CTRL_DMAR_REQ_PRI 0x400
  641. #define DMA_CTRL_DMAR_DLY_CNT_MASK 0x1F
  642. #define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
  643. #define DMA_CTRL_DMAW_DLY_CNT_MASK 0xF
  644. #define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
  645. #define DMA_CTRL_TXCMB_EN 0x100000
  646. #define DMA_CTRL_RXCMB_EN 0x200000
  647. /* CMB/SMB Control Register */
  648. #define REG_SMB_STAT_TIMER 0x15C4
  649. #define REG_TRIG_RRD_THRESH 0x15CA
  650. #define REG_TRIG_TPD_THRESH 0x15C8
  651. #define REG_TRIG_TXTIMER 0x15CC
  652. #define REG_TRIG_RXTIMER 0x15CE
  653. /* HOST RXF Page 1,2,3 address */
  654. #define REG_HOST_RXF1_PAGE0_LO 0x15D0
  655. #define REG_HOST_RXF1_PAGE1_LO 0x15D4
  656. #define REG_HOST_RXF2_PAGE0_LO 0x15D8
  657. #define REG_HOST_RXF2_PAGE1_LO 0x15DC
  658. #define REG_HOST_RXF3_PAGE0_LO 0x15E0
  659. #define REG_HOST_RXF3_PAGE1_LO 0x15E4
  660. /* Mail box */
  661. #define REG_MB_RXF1_RADDR 0x15B4
  662. #define REG_MB_RXF2_RADDR 0x15B8
  663. #define REG_MB_RXF3_RADDR 0x15BC
  664. #define REG_MB_TPD_PROD_IDX 0x15F0
  665. /* RXF-Page 0-3 PageNo & Valid bit */
  666. #define REG_HOST_RXF0_PAGE0_VLD 0x15F4
  667. #define HOST_RXF_VALID 1
  668. #define HOST_RXF_PAGENO_SHIFT 1
  669. #define HOST_RXF_PAGENO_MASK 0x7F
  670. #define REG_HOST_RXF0_PAGE1_VLD 0x15F5
  671. #define REG_HOST_RXF1_PAGE0_VLD 0x15F6
  672. #define REG_HOST_RXF1_PAGE1_VLD 0x15F7
  673. #define REG_HOST_RXF2_PAGE0_VLD 0x15F8
  674. #define REG_HOST_RXF2_PAGE1_VLD 0x15F9
  675. #define REG_HOST_RXF3_PAGE0_VLD 0x15FA
  676. #define REG_HOST_RXF3_PAGE1_VLD 0x15FB
  677. /* Interrupt Status Register */
  678. #define REG_ISR 0x1600
  679. #define ISR_SMB 1
  680. #define ISR_TIMER 2 /* Interrupt when Timer is counted down to zero */
  681. /*
  682. * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
  683. * in Table 51 Selene Master Control Register (Offset 0x1400).
  684. */
  685. #define ISR_MANUAL 4
  686. #define ISR_HW_RXF_OV 8 /* RXF overflow interrupt */
  687. #define ISR_HOST_RXF0_OV 0x10
  688. #define ISR_HOST_RXF1_OV 0x20
  689. #define ISR_HOST_RXF2_OV 0x40
  690. #define ISR_HOST_RXF3_OV 0x80
  691. #define ISR_TXF_UN 0x100
  692. #define ISR_RX0_PAGE_FULL 0x200
  693. #define ISR_DMAR_TO_RST 0x400
  694. #define ISR_DMAW_TO_RST 0x800
  695. #define ISR_GPHY 0x1000
  696. #define ISR_TX_CREDIT 0x2000
  697. #define ISR_GPHY_LPW 0x4000 /* GPHY low power state interrupt */
  698. #define ISR_RX_PKT 0x10000 /* One packet received, triggered by RFD */
  699. #define ISR_TX_PKT 0x20000 /* One packet transmitted, triggered by TPD */
  700. #define ISR_TX_DMA 0x40000
  701. #define ISR_RX_PKT_1 0x80000
  702. #define ISR_RX_PKT_2 0x100000
  703. #define ISR_RX_PKT_3 0x200000
  704. #define ISR_MAC_RX 0x400000
  705. #define ISR_MAC_TX 0x800000
  706. #define ISR_UR_DETECTED 0x1000000
  707. #define ISR_FERR_DETECTED 0x2000000
  708. #define ISR_NFERR_DETECTED 0x4000000
  709. #define ISR_CERR_DETECTED 0x8000000
  710. #define ISR_PHY_LINKDOWN 0x10000000
  711. #define ISR_DIS_INT 0x80000000
  712. /* Interrupt Mask Register */
  713. #define REG_IMR 0x1604
  714. #define IMR_NORMAL_MASK (\
  715. ISR_SMB |\
  716. ISR_TXF_UN |\
  717. ISR_HW_RXF_OV |\
  718. ISR_HOST_RXF0_OV|\
  719. ISR_MANUAL |\
  720. ISR_GPHY |\
  721. ISR_GPHY_LPW |\
  722. ISR_DMAR_TO_RST |\
  723. ISR_DMAW_TO_RST |\
  724. ISR_PHY_LINKDOWN|\
  725. ISR_RX_PKT |\
  726. ISR_TX_PKT)
  727. #define ISR_TX_EVENT (ISR_TXF_UN | ISR_TX_PKT)
  728. #define ISR_RX_EVENT (ISR_HOST_RXF0_OV | ISR_HW_RXF_OV | ISR_RX_PKT)
  729. #define REG_MAC_RX_STATUS_BIN 0x1700
  730. #define REG_MAC_RX_STATUS_END 0x175c
  731. #define REG_MAC_TX_STATUS_BIN 0x1760
  732. #define REG_MAC_TX_STATUS_END 0x17c0
  733. /* Hardware Offset Register */
  734. #define REG_HOST_RXF0_PAGEOFF 0x1800
  735. #define REG_TPD_CONS_IDX 0x1804
  736. #define REG_HOST_RXF1_PAGEOFF 0x1808
  737. #define REG_HOST_RXF2_PAGEOFF 0x180C
  738. #define REG_HOST_RXF3_PAGEOFF 0x1810
  739. /* RXF-Page 0-3 Offset DMA Address */
  740. #define REG_HOST_RXF0_MB0_LO 0x1820
  741. #define REG_HOST_RXF0_MB1_LO 0x1824
  742. #define REG_HOST_RXF1_MB0_LO 0x1828
  743. #define REG_HOST_RXF1_MB1_LO 0x182C
  744. #define REG_HOST_RXF2_MB0_LO 0x1830
  745. #define REG_HOST_RXF2_MB1_LO 0x1834
  746. #define REG_HOST_RXF3_MB0_LO 0x1838
  747. #define REG_HOST_RXF3_MB1_LO 0x183C
  748. /* Tpd CMB DMA Address */
  749. #define REG_HOST_TX_CMB_LO 0x1840
  750. #define REG_HOST_SMB_ADDR_LO 0x1844
  751. /* DEBUG ADDR */
  752. #define REG_DEBUG_DATA0 0x1900
  753. #define REG_DEBUG_DATA1 0x1904
  754. /***************************** MII definition ***************************************/
  755. /* PHY Common Register */
  756. #define MII_BMCR 0x00
  757. #define MII_BMSR 0x01
  758. #define MII_PHYSID1 0x02
  759. #define MII_PHYSID2 0x03
  760. #define MII_ADVERTISE 0x04
  761. #define MII_LPA 0x05
  762. #define MII_EXPANSION 0x06
  763. #define MII_AT001_CR 0x09
  764. #define MII_AT001_SR 0x0A
  765. #define MII_AT001_ESR 0x0F
  766. #define MII_AT001_PSCR 0x10
  767. #define MII_AT001_PSSR 0x11
  768. #define MII_INT_CTRL 0x12
  769. #define MII_INT_STATUS 0x13
  770. #define MII_SMARTSPEED 0x14
  771. #define MII_RERRCOUNTER 0x15
  772. #define MII_SREVISION 0x16
  773. #define MII_RESV1 0x17
  774. #define MII_LBRERROR 0x18
  775. #define MII_PHYADDR 0x19
  776. #define MII_RESV2 0x1a
  777. #define MII_TPISTATUS 0x1b
  778. #define MII_NCONFIG 0x1c
  779. #define MII_DBG_ADDR 0x1D
  780. #define MII_DBG_DATA 0x1E
  781. /* PHY Control Register */
  782. #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
  783. #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
  784. #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
  785. #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
  786. #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
  787. #define MII_CR_POWER_DOWN 0x0800 /* Power down */
  788. #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
  789. #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
  790. #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
  791. #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
  792. #define MII_CR_SPEED_MASK 0x2040
  793. #define MII_CR_SPEED_1000 0x0040
  794. #define MII_CR_SPEED_100 0x2000
  795. #define MII_CR_SPEED_10 0x0000
  796. /* PHY Status Register */
  797. #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
  798. #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
  799. #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
  800. #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
  801. #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
  802. #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
  803. #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
  804. #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
  805. #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
  806. #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
  807. #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
  808. #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
  809. #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
  810. #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
  811. #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
  812. /* Link partner ability register. */
  813. #define MII_LPA_SLCT 0x001f /* Same as advertise selector */
  814. #define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
  815. #define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
  816. #define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
  817. #define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
  818. #define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
  819. #define MII_LPA_PAUSE 0x0400 /* PAUSE */
  820. #define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
  821. #define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
  822. #define MII_LPA_LPACK 0x4000 /* Link partner acked us */
  823. #define MII_LPA_NPAGE 0x8000 /* Next page bit */
  824. /* Autoneg Advertisement Register */
  825. #define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
  826. #define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
  827. #define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
  828. #define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
  829. #define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
  830. #define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
  831. #define MII_AR_PAUSE 0x0400 /* Pause operation desired */
  832. #define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
  833. #define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
  834. #define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
  835. #define MII_AR_SPEED_MASK 0x01E0
  836. #define MII_AR_DEFAULT_CAP_MASK 0x0DE0
  837. /* 1000BASE-T Control Register */
  838. #define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
  839. #define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
  840. #define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
  841. /* 0=DTE device */
  842. #define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
  843. /* 0=Configure PHY as Slave */
  844. #define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
  845. /* 0=Automatic Master/Slave config */
  846. #define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
  847. #define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
  848. #define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
  849. #define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
  850. #define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
  851. #define MII_AT001_CR_1000T_SPEED_MASK 0x0300
  852. #define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300
  853. /* 1000BASE-T Status Register */
  854. #define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
  855. #define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
  856. #define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
  857. #define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
  858. #define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
  859. #define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
  860. #define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
  861. #define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
  862. /* Extended Status Register */
  863. #define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
  864. #define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
  865. #define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
  866. #define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
  867. /* AT001 PHY Specific Control Register */
  868. #define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
  869. #define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
  870. #define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
  871. #define MII_AT001_PSCR_MAC_POWERDOWN 0x0008
  872. #define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
  873. * 0=CLK125 toggling
  874. */
  875. #define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
  876. /* Manual MDI configuration */
  877. #define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
  878. #define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
  879. * 100BASE-TX/10BASE-T:
  880. * MDI Mode
  881. */
  882. #define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
  883. * all speeds.
  884. */
  885. #define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080
  886. /* 1=Enable Extended 10BASE-T distance
  887. * (Lower 10BASE-T RX Threshold)
  888. * 0=Normal 10BASE-T RX Threshold */
  889. #define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100
  890. /* 1=5-Bit interface in 100BASE-TX
  891. * 0=MII interface in 100BASE-TX */
  892. #define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
  893. #define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
  894. #define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
  895. #define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1
  896. #define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5
  897. #define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
  898. /* AT001 PHY Specific Status Register */
  899. #define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
  900. #define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
  901. #define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
  902. #define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */
  903. #define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */
  904. #define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
  905. #endif /* _ATL1_E_H_ */