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  1. /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
  2. * Copyright (C) 2004 Advanced Micro Devices
  3. * Copyright (C) 2005 Liu Tao <liutao1980@gmail.com> [etherboot port]
  4. *
  5. * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
  6. * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
  7. * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
  8. * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
  9. * Copyright 1993 United States Government as represented by the
  10. * Director, National Security Agency.[ pcnet32.c ]
  11. * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
  12. * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
  13. *
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  28. * 02110-1301, USA.
  29. * USA
  30. */
  31. FILE_LICENCE ( GPL2_OR_LATER );
  32. #include "etherboot.h"
  33. #include "nic.h"
  34. #include "mii.h"
  35. #include <ipxe/pci.h>
  36. #include <ipxe/ethernet.h>
  37. #include "string.h"
  38. #include "stdint.h"
  39. #include "amd8111e.h"
  40. /* driver definitions */
  41. #define NUM_TX_SLOTS 2
  42. #define NUM_RX_SLOTS 4
  43. #define TX_SLOTS_MASK 1
  44. #define RX_SLOTS_MASK 3
  45. #define TX_BUF_LEN 1536
  46. #define RX_BUF_LEN 1536
  47. #define TX_PKT_LEN_MAX (ETH_FRAME_LEN - ETH_HLEN)
  48. #define RX_PKT_LEN_MIN 60
  49. #define RX_PKT_LEN_MAX ETH_FRAME_LEN
  50. #define TX_TIMEOUT 3000
  51. #define TX_PROCESS_TIME 10
  52. #define TX_RETRY (TX_TIMEOUT / TX_PROCESS_TIME)
  53. #define PHY_RW_RETRY 10
  54. struct amd8111e_tx_desc {
  55. u16 buf_len;
  56. u16 tx_flags;
  57. u16 tag_ctrl_info;
  58. u16 tag_ctrl_cmd;
  59. u32 buf_phy_addr;
  60. u32 reserved;
  61. };
  62. struct amd8111e_rx_desc {
  63. u32 reserved;
  64. u16 msg_len;
  65. u16 tag_ctrl_info;
  66. u16 buf_len;
  67. u16 rx_flags;
  68. u32 buf_phy_addr;
  69. };
  70. struct eth_frame {
  71. u8 dst_addr[ETH_ALEN];
  72. u8 src_addr[ETH_ALEN];
  73. u16 type;
  74. u8 data[ETH_FRAME_LEN - ETH_HLEN];
  75. } __attribute__((packed));
  76. struct amd8111e_priv {
  77. struct amd8111e_tx_desc tx_ring[NUM_TX_SLOTS];
  78. struct amd8111e_rx_desc rx_ring[NUM_RX_SLOTS];
  79. unsigned char tx_buf[NUM_TX_SLOTS][TX_BUF_LEN];
  80. unsigned char rx_buf[NUM_RX_SLOTS][RX_BUF_LEN];
  81. unsigned long tx_idx, rx_idx;
  82. int tx_consistent;
  83. char opened;
  84. char link;
  85. char speed;
  86. char duplex;
  87. int ext_phy_addr;
  88. u32 ext_phy_id;
  89. struct pci_device *pdev;
  90. struct nic *nic;
  91. void *mmio;
  92. };
  93. static struct amd8111e_priv amd8111e;
  94. /********************************************************
  95. * locale functions *
  96. ********************************************************/
  97. static void amd8111e_init_hw_default(struct amd8111e_priv *lp);
  98. static int amd8111e_start(struct amd8111e_priv *lp);
  99. static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val);
  100. #if 0
  101. static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val);
  102. #endif
  103. static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp);
  104. static void amd8111e_disable_interrupt(struct amd8111e_priv *lp);
  105. static void amd8111e_enable_interrupt(struct amd8111e_priv *lp);
  106. static void amd8111e_force_interrupt(struct amd8111e_priv *lp);
  107. static int amd8111e_get_mac_address(struct amd8111e_priv *lp);
  108. static int amd8111e_init_rx_ring(struct amd8111e_priv *lp);
  109. static int amd8111e_init_tx_ring(struct amd8111e_priv *lp);
  110. static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index);
  111. static void amd8111e_wait_link(struct amd8111e_priv *lp);
  112. static void amd8111e_poll_link(struct amd8111e_priv *lp);
  113. static void amd8111e_restart(struct amd8111e_priv *lp);
  114. /*
  115. * This function clears necessary the device registers.
  116. */
  117. static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
  118. {
  119. unsigned int reg_val;
  120. void *mmio = lp->mmio;
  121. /* stop the chip */
  122. writel(RUN, mmio + CMD0);
  123. /* Clear RCV_RING_BASE_ADDR */
  124. writel(0, mmio + RCV_RING_BASE_ADDR0);
  125. /* Clear XMT_RING_BASE_ADDR */
  126. writel(0, mmio + XMT_RING_BASE_ADDR0);
  127. writel(0, mmio + XMT_RING_BASE_ADDR1);
  128. writel(0, mmio + XMT_RING_BASE_ADDR2);
  129. writel(0, mmio + XMT_RING_BASE_ADDR3);
  130. /* Clear CMD0 */
  131. writel(CMD0_CLEAR, mmio + CMD0);
  132. /* Clear CMD2 */
  133. writel(CMD2_CLEAR, mmio + CMD2);
  134. /* Clear CMD7 */
  135. writel(CMD7_CLEAR, mmio + CMD7);
  136. /* Clear DLY_INT_A and DLY_INT_B */
  137. writel(0x0, mmio + DLY_INT_A);
  138. writel(0x0, mmio + DLY_INT_B);
  139. /* Clear FLOW_CONTROL */
  140. writel(0x0, mmio + FLOW_CONTROL);
  141. /* Clear INT0 write 1 to clear register */
  142. reg_val = readl(mmio + INT0);
  143. writel(reg_val, mmio + INT0);
  144. /* Clear STVAL */
  145. writel(0x0, mmio + STVAL);
  146. /* Clear INTEN0 */
  147. writel(INTEN0_CLEAR, mmio + INTEN0);
  148. /* Clear LADRF */
  149. writel(0x0, mmio + LADRF);
  150. /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
  151. writel(0x80010, mmio + SRAM_SIZE);
  152. /* Clear RCV_RING0_LEN */
  153. writel(0x0, mmio + RCV_RING_LEN0);
  154. /* Clear XMT_RING0/1/2/3_LEN */
  155. writel(0x0, mmio + XMT_RING_LEN0);
  156. writel(0x0, mmio + XMT_RING_LEN1);
  157. writel(0x0, mmio + XMT_RING_LEN2);
  158. writel(0x0, mmio + XMT_RING_LEN3);
  159. /* Clear XMT_RING_LIMIT */
  160. writel(0x0, mmio + XMT_RING_LIMIT);
  161. /* Clear MIB */
  162. writew(MIB_CLEAR, mmio + MIB_ADDR);
  163. /* Clear LARF */
  164. writel( 0, mmio + LADRF);
  165. writel( 0, mmio + LADRF + 4);
  166. /* SRAM_SIZE register */
  167. reg_val = readl(mmio + SRAM_SIZE);
  168. /* Set default value to CTRL1 Register */
  169. writel(CTRL1_DEFAULT, mmio + CTRL1);
  170. /* To avoid PCI posting bug */
  171. readl(mmio + CMD2);
  172. }
  173. /*
  174. * This function initializes the device registers and starts the device.
  175. */
  176. static int amd8111e_start(struct amd8111e_priv *lp)
  177. {
  178. struct nic *nic = lp->nic;
  179. void *mmio = lp->mmio;
  180. int i, reg_val;
  181. /* stop the chip */
  182. writel(RUN, mmio + CMD0);
  183. /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
  184. writew(0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
  185. /* enable the port manager and set auto negotiation always */
  186. writel(VAL1 | EN_PMGR, mmio + CMD3 );
  187. writel(XPHYANE | XPHYRST, mmio + CTRL2);
  188. /* set control registers */
  189. reg_val = readl(mmio + CTRL1);
  190. reg_val &= ~XMTSP_MASK;
  191. writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
  192. /* initialize tx and rx ring base addresses */
  193. amd8111e_init_tx_ring(lp);
  194. amd8111e_init_rx_ring(lp);
  195. writel(virt_to_bus(lp->tx_ring), mmio + XMT_RING_BASE_ADDR0);
  196. writel(virt_to_bus(lp->rx_ring), mmio + RCV_RING_BASE_ADDR0);
  197. writew(NUM_TX_SLOTS, mmio + XMT_RING_LEN0);
  198. writew(NUM_RX_SLOTS, mmio + RCV_RING_LEN0);
  199. /* set default IPG to 96 */
  200. writew(DEFAULT_IPG, mmio + IPG);
  201. writew(DEFAULT_IPG - IFS1_DELTA, mmio + IFS1);
  202. /* AutoPAD transmit, Retransmit on Underflow */
  203. writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
  204. /* JUMBO disabled */
  205. writel(JUMBO, mmio + CMD3);
  206. /* Setting the MAC address to the device */
  207. for(i = 0; i < ETH_ALEN; i++)
  208. writeb(nic->node_addr[i], mmio + PADR + i);
  209. /* set RUN bit to start the chip, interrupt not enabled */
  210. writel(VAL2 | RDMD0 | VAL0 | RUN, mmio + CMD0);
  211. /* To avoid PCI posting bug */
  212. readl(mmio + CMD0);
  213. return 0;
  214. }
  215. /*
  216. This function will read the PHY registers.
  217. */
  218. static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val)
  219. {
  220. void *mmio = lp->mmio;
  221. unsigned int reg_val;
  222. unsigned int retry = PHY_RW_RETRY;
  223. reg_val = readl(mmio + PHY_ACCESS);
  224. while (reg_val & PHY_CMD_ACTIVE)
  225. reg_val = readl(mmio + PHY_ACCESS);
  226. writel(PHY_RD_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16),
  227. mmio + PHY_ACCESS);
  228. do {
  229. reg_val = readl(mmio + PHY_ACCESS);
  230. udelay(30); /* It takes 30 us to read/write data */
  231. } while (--retry && (reg_val & PHY_CMD_ACTIVE));
  232. if (reg_val & PHY_RD_ERR) {
  233. *val = 0;
  234. return -1;
  235. }
  236. *val = reg_val & 0xffff;
  237. return 0;
  238. }
  239. /*
  240. This function will write into PHY registers.
  241. */
  242. #if 0
  243. static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val)
  244. {
  245. void *mmio = lp->mmio;
  246. unsigned int reg_val;
  247. unsigned int retry = PHY_RW_RETRY;
  248. reg_val = readl(mmio + PHY_ACCESS);
  249. while (reg_val & PHY_CMD_ACTIVE)
  250. reg_val = readl(mmio + PHY_ACCESS);
  251. writel(PHY_WR_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16) | val,
  252. mmio + PHY_ACCESS);
  253. do {
  254. reg_val = readl(mmio + PHY_ACCESS);
  255. udelay(30); /* It takes 30 us to read/write the data */
  256. } while (--retry && (reg_val & PHY_CMD_ACTIVE));
  257. if(reg_val & PHY_RD_ERR)
  258. return -1;
  259. return 0;
  260. }
  261. #endif
  262. static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp)
  263. {
  264. int i;
  265. lp->ext_phy_id = 0;
  266. lp->ext_phy_addr = 1;
  267. for (i = 0x1e; i >= 0; i--) {
  268. u32 id1, id2;
  269. if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
  270. continue;
  271. if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
  272. continue;
  273. lp->ext_phy_id = (id1 << 16) | id2;
  274. lp->ext_phy_addr = i;
  275. break;
  276. }
  277. if (lp->ext_phy_id)
  278. printf("Found MII PHY ID 0x%08x at address 0x%02x\n",
  279. (unsigned int) lp->ext_phy_id, lp->ext_phy_addr);
  280. else
  281. printf("Couldn't detect MII PHY, assuming address 0x01\n");
  282. }
  283. static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
  284. {
  285. void *mmio = lp->mmio;
  286. unsigned int int0;
  287. writel(INTREN, mmio + CMD0);
  288. writel(INTEN0_CLEAR, mmio + INTEN0);
  289. int0 = readl(mmio + INT0);
  290. writel(int0, mmio + INT0);
  291. readl(mmio + INT0);
  292. }
  293. static void amd8111e_enable_interrupt(struct amd8111e_priv *lp)
  294. {
  295. void *mmio = lp->mmio;
  296. writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
  297. writel(VAL0 | INTREN, mmio + CMD0);
  298. readl(mmio + CMD0);
  299. }
  300. static void amd8111e_force_interrupt(struct amd8111e_priv *lp)
  301. {
  302. void *mmio = lp->mmio;
  303. writel(VAL0 | UINTCMD, mmio + CMD0);
  304. readl(mmio + CMD0);
  305. }
  306. static int amd8111e_get_mac_address(struct amd8111e_priv *lp)
  307. {
  308. struct nic *nic = lp->nic;
  309. void *mmio = lp->mmio;
  310. int i;
  311. /* BIOS should have set mac address to PADR register,
  312. * so we read PADR to get it.
  313. */
  314. for (i = 0; i < ETH_ALEN; i++)
  315. nic->node_addr[i] = readb(mmio + PADR + i);
  316. DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) );
  317. return 0;
  318. }
  319. static int amd8111e_init_rx_ring(struct amd8111e_priv *lp)
  320. {
  321. int i;
  322. lp->rx_idx = 0;
  323. /* Initilaizing receive descriptors */
  324. for (i = 0; i < NUM_RX_SLOTS; i++) {
  325. lp->rx_ring[i].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[i]));
  326. lp->rx_ring[i].buf_len = cpu_to_le16(RX_BUF_LEN);
  327. wmb();
  328. lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
  329. }
  330. return 0;
  331. }
  332. static int amd8111e_init_tx_ring(struct amd8111e_priv *lp)
  333. {
  334. int i;
  335. lp->tx_idx = 0;
  336. lp->tx_consistent = 1;
  337. /* Initializing transmit descriptors */
  338. for (i = 0; i < NUM_TX_SLOTS; i++) {
  339. lp->tx_ring[i].tx_flags = 0;
  340. lp->tx_ring[i].buf_phy_addr = 0;
  341. lp->tx_ring[i].buf_len = 0;
  342. }
  343. return 0;
  344. }
  345. static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index)
  346. {
  347. volatile u16 status;
  348. int retry = TX_RETRY;
  349. status = le16_to_cpu(lp->tx_ring[index].tx_flags);
  350. while (--retry && (status & OWN_BIT)) {
  351. mdelay(TX_PROCESS_TIME);
  352. status = le16_to_cpu(lp->tx_ring[index].tx_flags);
  353. }
  354. if (status & OWN_BIT) {
  355. printf("Error: tx slot %d timeout, stat = 0x%x\n", index, status);
  356. amd8111e_restart(lp);
  357. return -1;
  358. }
  359. return 0;
  360. }
  361. static void amd8111e_wait_link(struct amd8111e_priv *lp)
  362. {
  363. unsigned int status;
  364. u32 reg_val;
  365. do {
  366. /* read phy to update STAT0 register */
  367. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
  368. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
  369. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
  370. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
  371. status = readl(lp->mmio + STAT0);
  372. } while (!(status & AUTONEG_COMPLETE) || !(status & LINK_STATS));
  373. }
  374. static void amd8111e_poll_link(struct amd8111e_priv *lp)
  375. {
  376. unsigned int status, speed;
  377. u32 reg_val;
  378. if (!lp->link) {
  379. /* read phy to update STAT0 register */
  380. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
  381. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
  382. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
  383. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
  384. status = readl(lp->mmio + STAT0);
  385. if (status & LINK_STATS) {
  386. lp->link = 1;
  387. speed = (status & SPEED_MASK) >> 7;
  388. if (speed == PHY_SPEED_100)
  389. lp->speed = 1;
  390. else
  391. lp->speed = 0;
  392. if (status & FULL_DPLX)
  393. lp->duplex = 1;
  394. else
  395. lp->duplex = 0;
  396. printf("Link is up: %s Mbps %s duplex\n",
  397. lp->speed ? "100" : "10", lp->duplex ? "full" : "half");
  398. }
  399. } else {
  400. status = readl(lp->mmio + STAT0);
  401. if (!(status & LINK_STATS)) {
  402. lp->link = 0;
  403. printf("Link is down\n");
  404. }
  405. }
  406. }
  407. static void amd8111e_restart(struct amd8111e_priv *lp)
  408. {
  409. printf("\nStarting nic...\n");
  410. amd8111e_disable_interrupt(lp);
  411. amd8111e_init_hw_default(lp);
  412. amd8111e_probe_ext_phy(lp);
  413. amd8111e_get_mac_address(lp);
  414. amd8111e_start(lp);
  415. printf("Waiting link up...\n");
  416. lp->link = 0;
  417. amd8111e_wait_link(lp);
  418. amd8111e_poll_link(lp);
  419. }
  420. /********************************************************
  421. * Interface Functions *
  422. ********************************************************/
  423. static void amd8111e_transmit(struct nic *nic, const char *dst_addr,
  424. unsigned int type, unsigned int size, const char *packet)
  425. {
  426. struct amd8111e_priv *lp = nic->priv_data;
  427. struct eth_frame *frame;
  428. unsigned int index;
  429. /* check packet size */
  430. if (size > TX_PKT_LEN_MAX) {
  431. printf("amd8111e_transmit(): too large packet, drop\n");
  432. return;
  433. }
  434. /* get tx slot */
  435. index = lp->tx_idx;
  436. if (amd8111e_wait_tx_ring(lp, index))
  437. return;
  438. /* fill frame */
  439. frame = (struct eth_frame *)lp->tx_buf[index];
  440. memset(frame->data, 0, TX_PKT_LEN_MAX);
  441. memcpy(frame->dst_addr, dst_addr, ETH_ALEN);
  442. memcpy(frame->src_addr, nic->node_addr, ETH_ALEN);
  443. frame->type = htons(type);
  444. memcpy(frame->data, packet, size);
  445. /* start xmit */
  446. lp->tx_ring[index].buf_len = cpu_to_le16(ETH_HLEN + size);
  447. lp->tx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(frame));
  448. wmb();
  449. lp->tx_ring[index].tx_flags =
  450. cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT | ADD_FCS_BIT | LTINT_BIT);
  451. writel(VAL1 | TDMD0, lp->mmio + CMD0);
  452. readl(lp->mmio + CMD0);
  453. /* update slot pointer */
  454. lp->tx_idx = (lp->tx_idx + 1) & TX_SLOTS_MASK;
  455. }
  456. static int amd8111e_poll(struct nic *nic, int retrieve)
  457. {
  458. /* return true if there's an ethernet packet ready to read */
  459. /* nic->packet should contain data on return */
  460. /* nic->packetlen should contain length of data */
  461. struct amd8111e_priv *lp = nic->priv_data;
  462. u16 status, pkt_len;
  463. unsigned int index, pkt_ok;
  464. amd8111e_poll_link(lp);
  465. index = lp->rx_idx;
  466. status = le16_to_cpu(lp->rx_ring[index].rx_flags);
  467. pkt_len = le16_to_cpu(lp->rx_ring[index].msg_len) - 4; /* remove 4bytes FCS */
  468. if (status & OWN_BIT)
  469. return 0;
  470. if (status & ERR_BIT)
  471. pkt_ok = 0;
  472. else if (!(status & STP_BIT))
  473. pkt_ok = 0;
  474. else if (!(status & ENP_BIT))
  475. pkt_ok = 0;
  476. else if (pkt_len < RX_PKT_LEN_MIN)
  477. pkt_ok = 0;
  478. else if (pkt_len > RX_PKT_LEN_MAX)
  479. pkt_ok = 0;
  480. else
  481. pkt_ok = 1;
  482. if (pkt_ok) {
  483. if (!retrieve)
  484. return 1;
  485. nic->packetlen = pkt_len;
  486. memcpy(nic->packet, lp->rx_buf[index], nic->packetlen);
  487. }
  488. lp->rx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[index]));
  489. lp->rx_ring[index].buf_len = cpu_to_le16(RX_BUF_LEN);
  490. wmb();
  491. lp->rx_ring[index].rx_flags = cpu_to_le16(OWN_BIT);
  492. writel(VAL2 | RDMD0, lp->mmio + CMD0);
  493. readl(lp->mmio + CMD0);
  494. lp->rx_idx = (lp->rx_idx + 1) & RX_SLOTS_MASK;
  495. return pkt_ok;
  496. }
  497. static void amd8111e_disable(struct nic *nic)
  498. {
  499. struct amd8111e_priv *lp = nic->priv_data;
  500. /* disable interrupt */
  501. amd8111e_disable_interrupt(lp);
  502. /* stop chip */
  503. amd8111e_init_hw_default(lp);
  504. /* unmap mmio */
  505. iounmap(lp->mmio);
  506. /* update status */
  507. lp->opened = 0;
  508. }
  509. static void amd8111e_irq(struct nic *nic, irq_action_t action)
  510. {
  511. struct amd8111e_priv *lp = nic->priv_data;
  512. switch (action) {
  513. case DISABLE:
  514. amd8111e_disable_interrupt(lp);
  515. break;
  516. case ENABLE:
  517. amd8111e_enable_interrupt(lp);
  518. break;
  519. case FORCE:
  520. amd8111e_force_interrupt(lp);
  521. break;
  522. }
  523. }
  524. static struct nic_operations amd8111e_operations = {
  525. .connect = dummy_connect,
  526. .poll = amd8111e_poll,
  527. .transmit = amd8111e_transmit,
  528. .irq = amd8111e_irq,
  529. };
  530. static int amd8111e_probe(struct nic *nic, struct pci_device *pdev)
  531. {
  532. struct amd8111e_priv *lp = &amd8111e;
  533. unsigned long mmio_start, mmio_len;
  534. nic->ioaddr = pdev->ioaddr;
  535. nic->irqno = pdev->irq;
  536. mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
  537. mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_0);
  538. memset(lp, 0, sizeof(*lp));
  539. lp->pdev = pdev;
  540. lp->nic = nic;
  541. lp->mmio = ioremap(mmio_start, mmio_len);
  542. lp->opened = 1;
  543. adjust_pci_device(pdev);
  544. nic->priv_data = lp;
  545. amd8111e_restart(lp);
  546. nic->nic_op = &amd8111e_operations;
  547. return 1;
  548. }
  549. static struct pci_device_id amd8111e_nics[] = {
  550. PCI_ROM(0x1022, 0x7462, "amd8111e", "AMD8111E", 0),
  551. };
  552. PCI_DRIVER ( amd8111e_driver, amd8111e_nics, PCI_NO_CLASS );
  553. DRIVER ( "AMD8111E", nic_driver, pci_driver, amd8111e_driver,
  554. amd8111e_probe, amd8111e_disable );
  555. /*
  556. * Local variables:
  557. * c-basic-offset: 8
  558. * c-indent-level: 8
  559. * tab-width: 8
  560. * End:
  561. */