Commit f58cc3f introduced a temporary workaround for a bug in current
prototype silicon, but failed to apply it to all eight PCI functions
within the device.

Conjecture: The hardware issues 64-bit DMA writes of status descriptors,
which some PCI bridges seem to split into two 32-bit writes in reverse
order (i.e. dword 1 first).  This means that we sometimes observe a
partial status descriptor.  Add an explicit check to ensure that the
descriptor is complete before processing it.

Also ensure that the RDS consumer counter is incremented only when we
know that we have actually consumed an RX descriptor.