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+/*
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+ * Data types and structure for HAL - NIC interface.
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+ *
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+ */
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+
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+#ifndef _NXHAL_NIC_INTERFACE_H_
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+#define _NXHAL_NIC_INTERFACE_H_
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+
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+/*****************************************************************************
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+ * Simple Types
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+ *****************************************************************************/
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+
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+typedef U32 nx_reg_addr_t;
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+
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+/*****************************************************************************
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+ * Root crb-based firmware commands
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+ *****************************************************************************/
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+
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+/* CRB Root Command
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+
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+ A single set of crbs is used across all physical/virtual
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+ functions for capability queries, initialization, and
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+ context creation/destruction.
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+
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+ There are 4 CRBS:
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+ Command/Response CRB
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+ Argument1 CRB
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+ Argument2 CRB
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+ Argument3 CRB
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+ Signature CRB
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+
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+ The cmd/rsp crb is always intiated by the host via
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+ a command code and always responded by the card with
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+ a response code. The cmd and rsp codes are disjoint.
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+ The sequence of use is always CMD, RSP, CLEAR CMD.
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+
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+ The arguments are for passing in command specific
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+ and response specific parameters/data.
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+
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+ The signature is composed of a magic value, the
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+ pci function id, and a command sequence id:
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+ [7:0] = pci function
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+ [15:8] = version
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+ [31:16] = magic of 0xcafe
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+
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+ The pci function allows the card to take correct
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+ action for the given particular commands.
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+ The firmware will attempt to detect
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+ an errant driver that has died while holding
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+ the root crb hardware lock. Such an error condition
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+ shows up as the cmd/rsp crb stuck in a non-clear state.
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+
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+ Interface Sequence:
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+ Host always makes requests and firmware always responds.
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+ Note that data field is always set prior to command field.
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+
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+ [READ] CMD/RSP CRB ARGUMENT FIELD
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+ Host grab lock
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+ Host -> CMD optional parameter
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+ FW <- (Good) RSP-OK DATA
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+ FW <- (Fail) RSP-FAIL optional failure code
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+ Host -> CLEAR
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+ Host release lock
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+
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+ [WRITE] CMD/RSP CRB ARGUMENT FIELD
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+ Host grab lock
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+ Host -> CMD DATA
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+ FW <- (Good) RSP-OK optional write status
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+ FW <- (Write) RSP-FAIL optional failure code
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+ Host -> CLEAR
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+ Host release lock
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+
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+*/
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+
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+
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+/*****************************************************************************
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+ * CMD/RSP
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+ *****************************************************************************/
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+
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+#define NX_CDRP_SIGNATURE_TO_PCIFN(sign) ((sign) & 0xff)
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+#define NX_CDRP_SIGNATURE_TO_VERSION(sign) (((sign)>>8) & 0xff)
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+#define NX_CDRP_SIGNATURE_TO_MAGIC(sign) (((sign)>>16) & 0xffff)
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+#define NX_CDRP_SIGNATURE_VALID(sign) \
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+ ( NX_CDRP_SIGNATURE_TO_MAGIC(sign) == 0xcafe && \
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+ NX_CDRP_SIGNATURE_TO_PCIFN(sign) < 8)
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+#define NX_CDRP_SIGNATURE_MAKE(pcifn,version) \
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+ ( ((pcifn) & 0xff) | \
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+ (((version) & 0xff) << 8) | \
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+ (0xcafe << 16) )
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+
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+#define NX_CDRP_CLEAR 0x00000000
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+#define NX_CDRP_CMD_BIT 0x80000000
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+
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+/* All responses must have the NX_CDRP_CMD_BIT cleared
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+ * in the crb NX_CDRP_CRB_OFFSET. */
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+#define NX_CDRP_FORM_RSP(rsp) (rsp)
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+#define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
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+
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+#define NX_CDRP_RSP_OK 0x00000001
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+#define NX_CDRP_RSP_FAIL 0x00000002
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+#define NX_CDRP_RSP_TIMEOUT 0x00000003
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+
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+/* All commands must have the NX_CDRP_CMD_BIT set in
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+ * the crb NX_CDRP_CRB_OFFSET.
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+ * The macros below do not have it explicitly set to
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+ * allow their use in lookup tables */
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+#define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
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+#define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
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+
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+/* [CMD] Capability Vector [RSP] Capability Vector */
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+#define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
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+
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+/* [CMD] - [RSP] Query Value */
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+#define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
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+
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+/* [CMD] - [RSP] Query Value */
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+#define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
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+
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+/* [CMD] - [RSP] Query Value */
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+#define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
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+
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+/* [CMD] - [RSP] Query Value */
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+#define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
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+
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+/* [CMD] - [RSP] Query Value */
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+#define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
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+
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+/* [CMD] Rx Config DMA Addr [RSP] rcode */
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+#define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
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+
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+/* [CMD] Rx Context Handle, Reset Kind [RSP] rcode */
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+#define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
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+
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+/* [CMD] Tx Config DMA Addr [RSP] rcode */
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+#define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
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+
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+/* [CMD] Tx Context Handle, Reset Kind [RSP] rcode */
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+#define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
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+
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+/* [CMD] Stat setup dma addr - [RSP] Handle, rcode */
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+#define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
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+
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+/* [CMD] Handle - [RSP] rcode */
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+#define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
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+
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+/* [CMD] Handle - [RSP] rcode */
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+#define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
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+
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+#define NX_CDRP_CMD_MAX 0x00000011
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+
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+/*****************************************************************************
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+ * Capabilities
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+ *****************************************************************************/
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+
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+#define NX_CAP_BIT(class, bit) (1 << bit)
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+
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+/* Class 0 (i.e. ARGS 1)
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+ */
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+#define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
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+#define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
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+#define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
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+#define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
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+#define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
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+#define NX_CAP0_LRO NX_CAP_BIT(0, 5)
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+#define NX_CAP0_LSO NX_CAP_BIT(0, 6)
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+
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+/* Class 1 (i.e. ARGS 2)
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+ */
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+#define NX_CAP1_NIC NX_CAP_BIT(1, 0)
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+#define NX_CAP1_PXE NX_CAP_BIT(1, 1)
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+#define NX_CAP1_CHIMNEY NX_CAP_BIT(1, 2)
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+#define NX_CAP1_LSA NX_CAP_BIT(1, 3)
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+#define NX_CAP1_RDMA NX_CAP_BIT(1, 4)
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+#define NX_CAP1_ISCSI NX_CAP_BIT(1, 5)
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+#define NX_CAP1_FCOE NX_CAP_BIT(1, 6)
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+
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+/* Class 2 (i.e. ARGS 3)
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+ */
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+
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+/*****************************************************************************
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+ * Rules
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+ *****************************************************************************/
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+
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+typedef U32 nx_rx_rule_type_t;
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+
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+#define NX_RX_RULETYPE_DEFAULT 0
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+#define NX_RX_RULETYPE_MAC 1
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+#define NX_RX_RULETYPE_MAC_VLAN 2
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+#define NX_RX_RULETYPE_MAC_RSS 3
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+#define NX_RX_RULETYPE_MAC_VLAN_RSS 4
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+#define NX_RX_RULETYPE_MAX 5
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+
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+typedef U32 nx_rx_rule_cmd_t;
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+
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+#define NX_RX_RULECMD_ADD 0
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+#define NX_RX_RULECMD_REMOVE 1
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+#define NX_RX_RULECMD_MAX 2
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+
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+typedef struct nx_rx_rule_arg_s {
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+ union {
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+ struct {
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+ char mac[6];
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+ } m;
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+ struct {
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+ char mac[6];
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+ char vlan;
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+ } mv;
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+ struct {
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+ char mac[6];
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+ } mr;
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+ struct {
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+ char mac[6];
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+ char vlan;
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+ } mvr;
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+ };
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+ /* will be union of all the different args for rules */
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+ U64 data;
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+} nx_rx_rule_arg_t;
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+
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+typedef struct nx_rx_rule_s {
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+ U32 id;
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+ U32 active;
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+ nx_rx_rule_arg_t arg;
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+ nx_rx_rule_type_t type;
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+} nx_rx_rule_t;
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+
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+/* MSG - REQUIRES TX CONTEXT */
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+
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+/* The rules can be added/deleted from both the
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+ * host and card sides so rq/rsp are similar.
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+ */
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+typedef struct nx_hostmsg_rx_rule_s {
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+ nx_rx_rule_cmd_t cmd;
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+ nx_rx_rule_t rule;
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+} nx_hostmsg_rx_rule_t;
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+
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+typedef struct nx_cardmsg_rx_rule_s {
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+ nx_rcode_t rcode;
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+ nx_rx_rule_cmd_t cmd;
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+ nx_rx_rule_t rule;
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+} nx_cardmsg_rx_rule_t;
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+
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+
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+/*****************************************************************************
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+ * Common to Rx/Tx contexts
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+ *****************************************************************************/
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+
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+/*
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+ * Context states
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+ */
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+
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+typedef U32 nx_host_ctx_state_t;
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+
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+#define NX_HOST_CTX_STATE_FREED 0 /* Invalid state */
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+#define NX_HOST_CTX_STATE_ALLOCATED 1 /* Not committed */
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+/* The following states imply FW is aware of context */
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+#define NX_HOST_CTX_STATE_ACTIVE 2
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+#define NX_HOST_CTX_STATE_DISABLED 3
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+#define NX_HOST_CTX_STATE_QUIESCED 4
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+#define NX_HOST_CTX_STATE_MAX 5
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+
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+/*
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+ * Interrupt mask crb use must be set identically on the Tx
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+ * and Rx context configs across a pci function
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+ */
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+
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+/* Rx and Tx have unique interrupt/crb */
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+#define NX_HOST_INT_CRB_MODE_UNIQUE 0
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+/* Rx and Tx share a common interrupt/crb */
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+#define NX_HOST_INT_CRB_MODE_SHARED 1 /* <= LEGACY */
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+/* Rx does not use a crb */
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+#define NX_HOST_INT_CRB_MODE_NORX 2
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+/* Tx does not use a crb */
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+#define NX_HOST_INT_CRB_MODE_NOTX 3
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+/* Neither Rx nor Tx use a crb */
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+#define NX_HOST_INT_CRB_MODE_NORXTX 4
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+
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+/*
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+ * Destroy Rx/Tx
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+ */
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+
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+#define NX_DESTROY_CTX_RESET 0
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+#define NX_DESTROY_CTX_D3_RESET 1
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+#define NX_DESTROY_CTX_MAX 2
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+
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+
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+/*****************************************************************************
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+ * Tx
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+ *****************************************************************************/
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+
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+/*
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+ * Components of the host-request for Tx context creation.
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+ * CRB - DOES NOT REQUIRE Rx/TX CONTEXT
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+ */
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+
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+typedef struct nx_hostrq_cds_ring_s {
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+ U64 host_phys_addr; /* Ring base addr */
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+ U32 ring_size; /* Ring entries */
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+ U32 rsvd; /* Padding */
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+} nx_hostrq_cds_ring_t;
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+
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+typedef struct nx_hostrq_tx_ctx_s {
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+ U64 host_rsp_dma_addr; /* Response dma'd here */
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+ U64 cmd_cons_dma_addr; /* */
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+ U64 dummy_dma_addr; /* */
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+ U32 capabilities[4]; /* Flag bit vector */
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+ U32 host_int_crb_mode; /* Interrupt crb usage */
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+ U32 rsvd1; /* Padding */
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+ U16 rsvd2; /* Padding */
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+ U16 interrupt_ctl;
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+ U16 msi_index;
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+ U16 rsvd3; /* Padding */
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+ nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
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+ U8 reserved[128]; /* future expansion */
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+} nx_hostrq_tx_ctx_t;
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+
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+typedef struct nx_cardrsp_cds_ring_s {
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+ U32 host_producer_crb; /* Crb to use */
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+ U32 interrupt_crb; /* Crb to use */
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+} nx_cardrsp_cds_ring_t;
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+
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+typedef struct nx_cardrsp_tx_ctx_s {
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+ U32 host_ctx_state; /* Starting state */
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+ U16 context_id; /* Handle for context */
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+ U8 phys_port; /* Physical id of port */
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+ U8 virt_port; /* Virtual/Logical id of port */
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+ nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
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+ U8 reserved[128]; /* future expansion */
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+} nx_cardrsp_tx_ctx_t;
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+
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+#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) \
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+ ( sizeof(HOSTRQ_TX))
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+
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+#define SIZEOF_CARDRSP_TX(CARDRSP_TX) \
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+ ( sizeof(CARDRSP_TX))
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+
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+/*****************************************************************************
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+ * Rx
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+ *****************************************************************************/
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|
340
|
+
|
|
341
|
+/*
|
|
342
|
+ * RDS ring mapping to producer crbs
|
|
343
|
+ */
|
|
344
|
+
|
|
345
|
+/* Each ring has a unique crb */
|
|
346
|
+#define NX_HOST_RDS_CRB_MODE_UNIQUE 0 /* <= LEGACY */
|
|
347
|
+
|
|
348
|
+/* All configured RDS Rings share common crb:
|
|
349
|
+ 1 Ring - same as unique
|
|
350
|
+ 2 Rings - 16, 16
|
|
351
|
+ 3 Rings - 10, 10, 10 */
|
|
352
|
+#define NX_HOST_RDS_CRB_MODE_SHARED 1
|
|
353
|
+
|
|
354
|
+/* Bit usage is specified per-ring using the
|
|
355
|
+ ring's size. Sum of bit lengths must be <= 32.
|
|
356
|
+ Packing is [Ring N] ... [Ring 1][Ring 0] */
|
|
357
|
+#define NX_HOST_RDS_CRB_MODE_CUSTOM 2
|
|
358
|
+#define NX_HOST_RDS_CRB_MODE_MAX 3
|
|
359
|
+
|
|
360
|
+
|
|
361
|
+/*
|
|
362
|
+ * RDS Ting Types
|
|
363
|
+ */
|
|
364
|
+
|
|
365
|
+#define NX_RDS_RING_TYPE_NORMAL 0
|
|
366
|
+#define NX_RDS_RING_TYPE_JUMBO 1
|
|
367
|
+#define NX_RDS_RING_TYPE_LRO 2
|
|
368
|
+#define NX_RDS_RING_TYPE_MAX 3
|
|
369
|
+
|
|
370
|
+/*
|
|
371
|
+ * Components of the host-request for Rx context creation.
|
|
372
|
+ * CRB - DOES NOT REQUIRE Rx/TX CONTEXT
|
|
373
|
+ */
|
|
374
|
+
|
|
375
|
+typedef struct nx_hostrq_sds_ring_s {
|
|
376
|
+ U64 host_phys_addr; /* Ring base addr */
|
|
377
|
+ U32 ring_size; /* Ring entries */
|
|
378
|
+ U16 msi_index;
|
|
379
|
+ U16 rsvd; /* Padding */
|
|
380
|
+} nx_hostrq_sds_ring_t;
|
|
381
|
+
|
|
382
|
+typedef struct nx_hostrq_rds_ring_s {
|
|
383
|
+ U64 host_phys_addr; /* Ring base addr */
|
|
384
|
+ U64 buff_size; /* Packet buffer size */
|
|
385
|
+ U32 ring_size; /* Ring entries */
|
|
386
|
+ U32 ring_kind; /* Class of ring */
|
|
387
|
+} nx_hostrq_rds_ring_t;
|
|
388
|
+
|
|
389
|
+typedef struct nx_hostrq_rx_ctx_s {
|
|
390
|
+ U64 host_rsp_dma_addr; /* Response dma'd here */
|
|
391
|
+ U32 capabilities[4]; /* Flag bit vector */
|
|
392
|
+ U32 host_int_crb_mode; /* Interrupt crb usage */
|
|
393
|
+ U32 host_rds_crb_mode; /* RDS crb usage */
|
|
394
|
+ /* These ring offsets are relative to data[0] below */
|
|
395
|
+ U32 rds_ring_offset; /* Offset to RDS config */
|
|
396
|
+ U32 sds_ring_offset; /* Offset to SDS config */
|
|
397
|
+ U16 num_rds_rings; /* Count of RDS rings */
|
|
398
|
+ U16 num_sds_rings; /* Count of SDS rings */
|
|
399
|
+ U16 rsvd1; /* Padding */
|
|
400
|
+ U16 rsvd2; /* Padding */
|
|
401
|
+ U8 reserved[128]; /* reserve space for future expansion*/
|
|
402
|
+ /* MUST BE 64-bit aligned.
|
|
403
|
+ The following is packed:
|
|
404
|
+ - N hostrq_rds_rings
|
|
405
|
+ - N hostrq_sds_rings */
|
|
406
|
+ char data[0];
|
|
407
|
+} nx_hostrq_rx_ctx_t;
|
|
408
|
+
|
|
409
|
+typedef struct nx_cardrsp_rds_ring_s {
|
|
410
|
+ U32 host_producer_crb; /* Crb to use */
|
|
411
|
+ U32 rsvd1; /* Padding */
|
|
412
|
+} nx_cardrsp_rds_ring_t;
|
|
413
|
+
|
|
414
|
+typedef struct nx_cardrsp_sds_ring_s {
|
|
415
|
+ U32 host_consumer_crb; /* Crb to use */
|
|
416
|
+ U32 interrupt_crb; /* Crb to use */
|
|
417
|
+} nx_cardrsp_sds_ring_t;
|
|
418
|
+
|
|
419
|
+typedef struct nx_cardrsp_rx_ctx_s {
|
|
420
|
+ /* These ring offsets are relative to data[0] below */
|
|
421
|
+ U32 rds_ring_offset; /* Offset to RDS config */
|
|
422
|
+ U32 sds_ring_offset; /* Offset to SDS config */
|
|
423
|
+ U32 host_ctx_state; /* Starting State */
|
|
424
|
+ U32 num_fn_per_port; /* How many PCI fn share the port */
|
|
425
|
+ U16 num_rds_rings; /* Count of RDS rings */
|
|
426
|
+ U16 num_sds_rings; /* Count of SDS rings */
|
|
427
|
+ U16 context_id; /* Handle for context */
|
|
428
|
+ U8 phys_port; /* Physical id of port */
|
|
429
|
+ U8 virt_port; /* Virtual/Logical id of port */
|
|
430
|
+ U8 reserved[128]; /* save space for future expansion */
|
|
431
|
+ /* MUST BE 64-bit aligned.
|
|
432
|
+ The following is packed:
|
|
433
|
+ - N cardrsp_rds_rings
|
|
434
|
+ - N cardrs_sds_rings */
|
|
435
|
+ char data[0];
|
|
436
|
+} nx_cardrsp_rx_ctx_t;
|
|
437
|
+
|
|
438
|
+#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
|
|
439
|
+ ( sizeof(HOSTRQ_RX) + \
|
|
440
|
+ (rds_rings)*(sizeof (nx_hostrq_rds_ring_t)) + \
|
|
441
|
+ (sds_rings)*(sizeof (nx_hostrq_sds_ring_t)) )
|
|
442
|
+
|
|
443
|
+#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
|
|
444
|
+ ( sizeof(CARDRSP_RX) + \
|
|
445
|
+ (rds_rings)*(sizeof (nx_cardrsp_rds_ring_t)) + \
|
|
446
|
+ (sds_rings)*(sizeof (nx_cardrsp_sds_ring_t)) )
|
|
447
|
+
|
|
448
|
+
|
|
449
|
+/*****************************************************************************
|
|
450
|
+ * Statistics
|
|
451
|
+ *****************************************************************************/
|
|
452
|
+
|
|
453
|
+/*
|
|
454
|
+ * The model of statistics update to use
|
|
455
|
+ */
|
|
456
|
+
|
|
457
|
+#define NX_STATISTICS_MODE_INVALID 0
|
|
458
|
+
|
|
459
|
+/* Permanent setup; Updates are only sent on explicit request
|
|
460
|
+ (NX_CDRP_CMD_GET_STATISTICS) */
|
|
461
|
+#define NX_STATISTICS_MODE_PULL 1
|
|
462
|
+
|
|
463
|
+/* Permanent setup; Updates are sent automatically and on
|
|
464
|
+ explicit request (NX_CDRP_CMD_GET_STATISTICS) */
|
|
465
|
+#define NX_STATISTICS_MODE_PUSH 2
|
|
466
|
+
|
|
467
|
+/* One time stat update. */
|
|
468
|
+#define NX_STATISTICS_MODE_SINGLE_SHOT 3
|
|
469
|
+
|
|
470
|
+#define NX_STATISTICS_MODE_MAX 4
|
|
471
|
+
|
|
472
|
+/*
|
|
473
|
+ * What set of stats
|
|
474
|
+ */
|
|
475
|
+#define NX_STATISTICS_TYPE_INVALID 0
|
|
476
|
+#define NX_STATISTICS_TYPE_NIC_RX_CORE 1
|
|
477
|
+#define NX_STATISTICS_TYPE_NIC_TX_CORE 2
|
|
478
|
+#define NX_STATISTICS_TYPE_NIC_RX_ALL 3
|
|
479
|
+#define NX_STATISTICS_TYPE_NIC_TX_ALL 4
|
|
480
|
+#define NX_STATISTICS_TYPE_MAX 5
|
|
481
|
+
|
|
482
|
+
|
|
483
|
+/*
|
|
484
|
+ * Request to setup statistics gathering.
|
|
485
|
+ * CRB - DOES NOT REQUIRE Rx/TX CONTEXT
|
|
486
|
+ */
|
|
487
|
+
|
|
488
|
+typedef struct nx_hostrq_stat_setup_s {
|
|
489
|
+ U64 host_stat_buffer; /* Where to dma stats */
|
|
490
|
+ U32 host_stat_size; /* Size of stat buffer */
|
|
491
|
+ U16 context_id; /* Which context */
|
|
492
|
+ U16 stat_type; /* What class of stats */
|
|
493
|
+ U16 stat_mode; /* When to update */
|
|
494
|
+ U16 stat_interval; /* Frequency of update */
|
|
495
|
+} nx_hostrq_stat_setup_t;
|
|
496
|
+
|
|
497
|
+
|
|
498
|
+
|
|
499
|
+#endif /* _NXHAL_NIC_INTERFACE_H_ */
|