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@@ -73,25 +73,6 @@ static u32 ioaddr;
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73
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73
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#define RTL8169_USE_IO
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74
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74
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75
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75
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76
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-#ifdef RTL8169_DEBUG
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77
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-
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78
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-#if 0
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79
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-#define assert(expr) \
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80
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- if(!(expr)) { printk( "Assertion failed! %s,%s,%s,line=%d\n", #expr,__FILE__,__FUNCTION__,__LINE__); }
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81
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-#endif
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82
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-
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83
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-#define DBG_PRINTF( fmt, args...) printk("r8169: " fmt, ## args);
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84
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-
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85
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-#else
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86
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-
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87
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-#if 0
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88
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-#define assert(expr) do {} while (0)
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89
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-#endif
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90
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-
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91
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-#define DBG_PRINTF( fmt, args...) ;
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92
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-
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93
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-#endif // end of #ifdef RTL8169_DEBUG
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94
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-
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95
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76
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/* media options
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96
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77
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_10_Half = 0x01,
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97
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78
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_10_Full = 0x02,
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@@ -759,11 +740,11 @@ static void rtl8169_hw_start(struct nic *nic)
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759
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740
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if (tpc->mcfg == MCFG_METHOD_2 || tpc->mcfg == MCFG_METHOD_3) {
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760
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741
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RTL_W16(CPlusCmd,
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761
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742
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(RTL_R16(CPlusCmd) | (1 << 14) | (1 << 3)));
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762
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- DBG_PRINTF
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743
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+ DBG
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763
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744
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("Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n");
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764
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745
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} else {
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765
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746
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RTL_W16(CPlusCmd, (RTL_R16(CPlusCmd) | (1 << 3)));
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766
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- DBG_PRINTF("Set MAC Reg C+CR Offset 0xE0: bit-3.\n");
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747
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+ DBG("Set MAC Reg C+CR Offset 0xE0: bit-3.\n");
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767
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748
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}
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768
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749
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769
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750
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{
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@@ -919,18 +900,18 @@ static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
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919
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900
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/* Config PHY */
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920
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901
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rtl8169_hw_PHY_config(nic);
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921
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902
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922
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- DBG_PRINTF("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
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903
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+ DBG("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
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923
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904
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RTL_W8(0x82, 0x01);
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924
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905
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925
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906
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if (tpc->mcfg < MCFG_METHOD_3) {
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926
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- DBG_PRINTF("Set PCI Latency=0x40\n");
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907
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+ DBG("Set PCI Latency=0x40\n");
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927
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908
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pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0x40);
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928
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909
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}
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929
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910
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930
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911
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if (tpc->mcfg == MCFG_METHOD_2) {
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931
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- DBG_PRINTF("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
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912
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+ DBG("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
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932
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913
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RTL_W8(0x82, 0x01);
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933
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- DBG_PRINTF("Set PHY Reg 0x0bh = 0x00h\n");
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914
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+ DBG("Set PHY Reg 0x0bh = 0x00h\n");
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934
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915
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RTL8169_WRITE_GMII_REG(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
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935
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916
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}
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936
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917
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@@ -1049,7 +1030,7 @@ static void rtl8169_hw_PHY_reset(struct nic *nic __unused)
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1049
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1030
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struct rtl8169_private *priv = dev->priv;
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1050
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1031
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unsigned long ioaddr = priv->ioaddr;
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1051
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1032
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1052
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- DBG_PRINTF("%s: Reset RTL8169s PHY\n", dev->name);
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1033
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+ DBG("%s: Reset RTL8169s PHY\n", dev->name);
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1053
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1034
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1054
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1035
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val = ( RTL8169_READ_GMII_REG( ioaddr, 0 ) | 0x8000 ) & 0xffff;
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1055
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1036
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RTL8169_WRITE_GMII_REG( ioaddr, 0, val );
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@@ -1074,7 +1055,7 @@ static void rtl8169_hw_PHY_reset(struct nic *nic __unused)
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1074
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1055
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static void rtl8169_hw_PHY_config(struct nic *nic __unused)
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1075
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1056
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{
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1076
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1057
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1077
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- DBG_PRINTF("priv->mcfg=%d, priv->pcfg=%d\n", tpc->mcfg, tpc->pcfg);
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1058
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+ DBG("priv->mcfg=%d, priv->pcfg=%d\n", tpc->mcfg, tpc->pcfg);
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1078
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1059
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1079
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1060
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if (tpc->mcfg == MCFG_METHOD_4) {
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1080
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1061
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/*
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@@ -1175,7 +1156,7 @@ static void rtl8169_hw_PHY_config(struct nic *nic __unused)
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1175
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1156
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RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x0B,
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1176
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1157
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0x0000);
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1177
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1158
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} else {
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1178
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- DBG_PRINTF("tpc->mcfg=%d. Discard hw PHY config.\n",
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1159
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+ DBG("tpc->mcfg=%d. Discard hw PHY config.\n",
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1179
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1160
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tpc->mcfg);
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1180
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1161
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}
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1181
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1162
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}
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