Forward-port event queue fixes from 5.4 tree.

src/drivers/net/etherfabric.c

 #define EF1_TX_ENGINE_EN_WIDTH 1
 #define EF1_RX_ENGINE_EN_LBN 18
 #define EF1_RX_ENGINE_EN_WIDTH 1
+#define EF1_TURBO2_LBN 17
+#define EF1_TURBO2_WIDTH 1
+#define EF1_TURBO1_LBN 16
+#define EF1_TURBO1_WIDTH 1
+#define EF1_TURBO3_LBN 14
+#define EF1_TURBO3_WIDTH 1
 #define EF1_LB_RESET_LBN 3
 #define EF1_LB_RESET_WIDTH 1
 #define EF1_MAC_RESET_LBN 2
 #define EF1_EV_CODE_WIDTH 8
 #define EF1_RX_EV_DECODE 0x01
 #define EF1_TX_EV_DECODE 0x02
+#define EF1_TIMER_EV_DECODE 0x0b
 #define EF1_DRV_GEN_EV_DECODE 0x0f
 
 /* Receive events */
 	EFAB_SET_DWORD_FIELD ( reg, EF1_MASTER_EVENTS, 0 );
 	EFAB_SET_DWORD_FIELD ( reg, EF1_TX_ENGINE_EN, 0 );
 	EFAB_SET_DWORD_FIELD ( reg, EF1_RX_ENGINE_EN, 0 );
+	EFAB_SET_DWORD_FIELD ( reg, EF1_TURBO2, 1 );
+	EFAB_SET_DWORD_FIELD ( reg, EF1_TURBO1, 1 );
+	EFAB_SET_DWORD_FIELD ( reg, EF1_TURBO3, 1 );
 	EFAB_SET_DWORD_FIELD ( reg, EF1_CAM_ENABLE, 1 );
 	ef1002_writel ( efab, &reg, EF1_CTR_GEN_STATUS0_REG );
 	udelay ( 1000 );
 				EF1_RX_KER_BUF_ADR,
 				virt_to_bus ( rx_buf->addr ) );
 	ef1002_writel ( efab, &rxd.dword[0], EF1_RX_DESC_FIFO + 0 );
+	wmb();
 	ef1002_writel ( efab, &rxd.dword[1], EF1_RX_DESC_FIFO + 4 );
 	udelay ( 10 );
 }
 
 	ef1002_writel ( efab, &txd.dword[0], EF1_TX_DESC_FIFO + 0 );
 	ef1002_writel ( efab, &txd.dword[1], EF1_TX_DESC_FIFO + 4 );
+	wmb();
 	ef1002_writel ( efab, &txd.dword[2], EF1_TX_DESC_FIFO + 8 );
 	udelay ( 10 );
 }
 		/* RX len not available via event FIFO */
 		event->rx_len = ETH_FRAME_LEN;
 		break;
+	case EF1_TIMER_EV_DECODE:
+		/* These are safe to ignore.  We seem to get some at
+		 * start of day, presumably due to the timers starting
+		 * up with random contents.
+		 */
+		event->type = EFAB_EV_NONE;
+		break;
 	default:
 		printf ( "Unknown event type %d data %08lx\n", ev_code,
 			 EFAB_DWORD_FIELD ( reg, EFAB_DWORD_0 ) );
 	if ( ! retrieve )
 		return 1;
 
+	/* There seems to be a hardware race.  The event can show up
+	 * on the event FIFO before the DMA has completed, so we
+	 * insert a tiny delay.  If this proves unreliable, we should
+	 * switch to using event DMA rather than the event FIFO, since
+	 * event DMA ordering is guaranteed.
+	 */
+	udelay ( 1 );
+
 	/* Copy packet contents */
 	nic->packetlen = rx_buf->len;
 	memcpy ( nic->packet, rx_buf->addr, nic->packetlen );