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@@ -746,6 +746,12 @@ static int mentormac_mdio_read ( struct efab_nic *efab, int phy_id,
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746
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746
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#define EF1_TX_ENGINE_EN_WIDTH 1
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747
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747
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#define EF1_RX_ENGINE_EN_LBN 18
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748
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748
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#define EF1_RX_ENGINE_EN_WIDTH 1
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749
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+#define EF1_TURBO2_LBN 17
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750
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+#define EF1_TURBO2_WIDTH 1
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751
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+#define EF1_TURBO1_LBN 16
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752
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+#define EF1_TURBO1_WIDTH 1
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753
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+#define EF1_TURBO3_LBN 14
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754
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+#define EF1_TURBO3_WIDTH 1
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749
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755
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#define EF1_LB_RESET_LBN 3
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750
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756
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#define EF1_LB_RESET_WIDTH 1
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751
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757
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#define EF1_MAC_RESET_LBN 2
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@@ -900,6 +906,7 @@ static int mentormac_mdio_read ( struct efab_nic *efab, int phy_id,
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900
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906
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#define EF1_EV_CODE_WIDTH 8
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901
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907
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#define EF1_RX_EV_DECODE 0x01
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902
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908
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#define EF1_TX_EV_DECODE 0x02
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909
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+#define EF1_TIMER_EV_DECODE 0x0b
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903
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910
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#define EF1_DRV_GEN_EV_DECODE 0x0f
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904
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911
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905
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912
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/* Receive events */
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@@ -1097,6 +1104,9 @@ static int ef1002_init_nic ( struct efab_nic *efab ) {
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1097
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1104
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EFAB_SET_DWORD_FIELD ( reg, EF1_MASTER_EVENTS, 0 );
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1098
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1105
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EFAB_SET_DWORD_FIELD ( reg, EF1_TX_ENGINE_EN, 0 );
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1099
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1106
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EFAB_SET_DWORD_FIELD ( reg, EF1_RX_ENGINE_EN, 0 );
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1107
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+ EFAB_SET_DWORD_FIELD ( reg, EF1_TURBO2, 1 );
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1108
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+ EFAB_SET_DWORD_FIELD ( reg, EF1_TURBO1, 1 );
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1109
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+ EFAB_SET_DWORD_FIELD ( reg, EF1_TURBO3, 1 );
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1100
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1110
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EFAB_SET_DWORD_FIELD ( reg, EF1_CAM_ENABLE, 1 );
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1101
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1111
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ef1002_writel ( efab, ®, EF1_CTR_GEN_STATUS0_REG );
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1102
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1112
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udelay ( 1000 );
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@@ -1184,6 +1194,7 @@ static void ef1002_build_rx_desc ( struct efab_nic *efab,
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1184
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1194
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EF1_RX_KER_BUF_ADR,
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1185
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1195
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virt_to_bus ( rx_buf->addr ) );
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1186
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1196
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ef1002_writel ( efab, &rxd.dword[0], EF1_RX_DESC_FIFO + 0 );
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1197
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+ wmb();
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1187
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1198
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ef1002_writel ( efab, &rxd.dword[1], EF1_RX_DESC_FIFO + 4 );
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1188
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1199
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udelay ( 10 );
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1189
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1200
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}
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@@ -1219,6 +1230,7 @@ static void ef1002_build_tx_desc ( struct efab_nic *efab,
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1219
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1230
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1220
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1231
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ef1002_writel ( efab, &txd.dword[0], EF1_TX_DESC_FIFO + 0 );
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1221
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1232
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ef1002_writel ( efab, &txd.dword[1], EF1_TX_DESC_FIFO + 4 );
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1233
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+ wmb();
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1222
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1234
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ef1002_writel ( efab, &txd.dword[2], EF1_TX_DESC_FIFO + 8 );
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1223
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1235
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udelay ( 10 );
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1224
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1236
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}
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@@ -1266,6 +1278,13 @@ static int ef1002_fetch_event ( struct efab_nic *efab,
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1266
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1278
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/* RX len not available via event FIFO */
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1267
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1279
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event->rx_len = ETH_FRAME_LEN;
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1268
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1280
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break;
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1281
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+ case EF1_TIMER_EV_DECODE:
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1282
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+ /* These are safe to ignore. We seem to get some at
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1283
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+ * start of day, presumably due to the timers starting
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1284
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+ * up with random contents.
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1285
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+ */
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1286
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+ event->type = EFAB_EV_NONE;
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1287
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+ break;
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1269
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1288
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default:
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1270
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1289
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printf ( "Unknown event type %d data %08lx\n", ev_code,
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1271
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1290
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EFAB_DWORD_FIELD ( reg, EFAB_DWORD_0 ) );
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@@ -2717,6 +2736,14 @@ static int etherfabric_poll ( struct nic *nic, int retrieve ) {
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2717
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2736
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if ( ! retrieve )
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2718
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2737
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return 1;
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2719
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2738
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2739
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+ /* There seems to be a hardware race. The event can show up
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2740
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+ * on the event FIFO before the DMA has completed, so we
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2741
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+ * insert a tiny delay. If this proves unreliable, we should
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2742
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+ * switch to using event DMA rather than the event FIFO, since
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2743
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+ * event DMA ordering is guaranteed.
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2744
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+ */
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2745
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+ udelay ( 1 );
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2746
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+
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2720
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2747
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/* Copy packet contents */
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2721
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2748
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nic->packetlen = rx_buf->len;
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2722
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2749
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memcpy ( nic->packet, rx_buf->addr, nic->packetlen );
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