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+/* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
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+ * Copyright (C) 2004 Advanced Micro Devices
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+ * Copyright (C) 2005 Liu Tao <liutao1980@gmail.com> [etherboot port]
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+ *
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+ * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
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+ * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
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+ * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
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+ * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
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+ * Copyright 1993 United States Government as represented by the
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+ * Director, National Security Agency.[ pcnet32.c ]
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+ * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
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+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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+ *
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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+ * USA
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+ */
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+
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+#include "etherboot.h"
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+#include "nic.h"
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+#include "mii.h"
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+#include "pci.h"
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+#include "timer.h"
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+#include "string.h"
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+#include "stdint.h"
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+#include "amd8111e.h"
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+
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+
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+/* driver definitions */
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+#define NUM_TX_SLOTS 2
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+#define NUM_RX_SLOTS 4
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+#define TX_SLOTS_MASK 1
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+#define RX_SLOTS_MASK 3
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+
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+#define TX_BUF_LEN 1536
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+#define RX_BUF_LEN 1536
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+
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+#define TX_PKT_LEN_MAX (ETH_FRAME_LEN - ETH_HLEN)
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+#define RX_PKT_LEN_MIN 60
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+#define RX_PKT_LEN_MAX ETH_FRAME_LEN
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+
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+#define TX_TIMEOUT 3000
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+#define TX_PROCESS_TIME 10
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+#define TX_RETRY (TX_TIMEOUT / TX_PROCESS_TIME)
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+
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+#define PHY_RW_RETRY 10
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+
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+
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+struct amd8111e_tx_desc {
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+ u16 buf_len;
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+ u16 tx_flags;
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+ u16 tag_ctrl_info;
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+ u16 tag_ctrl_cmd;
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+ u32 buf_phy_addr;
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+ u32 reserved;
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+};
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+
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+struct amd8111e_rx_desc {
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+ u32 reserved;
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+ u16 msg_len;
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+ u16 tag_ctrl_info;
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+ u16 buf_len;
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+ u16 rx_flags;
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+ u32 buf_phy_addr;
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+};
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+
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+struct eth_frame {
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+ u8 dst_addr[ETH_ALEN];
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+ u8 src_addr[ETH_ALEN];
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+ u16 type;
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+ u8 data[ETH_FRAME_LEN - ETH_HLEN];
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+} __attribute__((packed));
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+
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+struct amd8111e_priv {
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+ struct amd8111e_tx_desc tx_ring[NUM_TX_SLOTS];
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+ struct amd8111e_rx_desc rx_ring[NUM_RX_SLOTS];
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+ unsigned char tx_buf[NUM_TX_SLOTS][TX_BUF_LEN];
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+ unsigned char rx_buf[NUM_RX_SLOTS][RX_BUF_LEN];
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+ unsigned long tx_idx, rx_idx;
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+ int tx_consistent;
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+
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+ char opened;
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+ char link;
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+ char speed;
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+ char duplex;
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+ int ext_phy_addr;
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+ u32 ext_phy_id;
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+
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+ struct pci_device *pdev;
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+ struct nic *nic;
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+ void *mmio;
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+};
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+
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+static struct amd8111e_priv amd8111e;
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+
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+
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+/********************************************************
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+ * locale functions *
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+ ********************************************************/
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+static void amd8111e_init_hw_default(struct amd8111e_priv *lp);
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+static int amd8111e_start(struct amd8111e_priv *lp);
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+static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val);
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+#if 0
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+static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val);
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+#endif
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+static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp);
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+static void amd8111e_disable_interrupt(struct amd8111e_priv *lp);
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+static void amd8111e_enable_interrupt(struct amd8111e_priv *lp);
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+static void amd8111e_force_interrupt(struct amd8111e_priv *lp);
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+static int amd8111e_get_mac_address(struct amd8111e_priv *lp);
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+static int amd8111e_init_rx_ring(struct amd8111e_priv *lp);
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+static int amd8111e_init_tx_ring(struct amd8111e_priv *lp);
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+static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index);
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+static void amd8111e_wait_link(struct amd8111e_priv *lp);
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+static void amd8111e_poll_link(struct amd8111e_priv *lp);
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+static void amd8111e_restart(struct amd8111e_priv *lp);
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+
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+
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+/*
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+ * This function clears necessary the device registers.
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+ */
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+static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
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+{
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+ unsigned int reg_val;
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+ unsigned int logic_filter[2] = {0,};
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+ void *mmio = lp->mmio;
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+
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+ /* stop the chip */
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+ writel(RUN, mmio + CMD0);
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+
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+ /* Clear RCV_RING_BASE_ADDR */
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+ writel(0, mmio + RCV_RING_BASE_ADDR0);
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+
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+ /* Clear XMT_RING_BASE_ADDR */
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+ writel(0, mmio + XMT_RING_BASE_ADDR0);
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+ writel(0, mmio + XMT_RING_BASE_ADDR1);
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+ writel(0, mmio + XMT_RING_BASE_ADDR2);
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+ writel(0, mmio + XMT_RING_BASE_ADDR3);
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+
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+ /* Clear CMD0 */
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+ writel(CMD0_CLEAR, mmio + CMD0);
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+
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+ /* Clear CMD2 */
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+ writel(CMD2_CLEAR, mmio + CMD2);
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+
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+ /* Clear CMD7 */
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+ writel(CMD7_CLEAR, mmio + CMD7);
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+
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+ /* Clear DLY_INT_A and DLY_INT_B */
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+ writel(0x0, mmio + DLY_INT_A);
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+ writel(0x0, mmio + DLY_INT_B);
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+
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+ /* Clear FLOW_CONTROL */
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+ writel(0x0, mmio + FLOW_CONTROL);
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+
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+ /* Clear INT0 write 1 to clear register */
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+ reg_val = readl(mmio + INT0);
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+ writel(reg_val, mmio + INT0);
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+
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+ /* Clear STVAL */
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+ writel(0x0, mmio + STVAL);
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+
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+ /* Clear INTEN0 */
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+ writel(INTEN0_CLEAR, mmio + INTEN0);
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+
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+ /* Clear LADRF */
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+ writel(0x0, mmio + LADRF);
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+
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+ /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
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+ writel(0x80010, mmio + SRAM_SIZE);
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+
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+ /* Clear RCV_RING0_LEN */
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+ writel(0x0, mmio + RCV_RING_LEN0);
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+
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+ /* Clear XMT_RING0/1/2/3_LEN */
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+ writel(0x0, mmio + XMT_RING_LEN0);
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+ writel(0x0, mmio + XMT_RING_LEN1);
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+ writel(0x0, mmio + XMT_RING_LEN2);
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+ writel(0x0, mmio + XMT_RING_LEN3);
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+
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+ /* Clear XMT_RING_LIMIT */
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+ writel(0x0, mmio + XMT_RING_LIMIT);
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+
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+ /* Clear MIB */
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+ writew(MIB_CLEAR, mmio + MIB_ADDR);
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+
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+ /* Clear LARF */
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+ amd8111e_writeq(*(u64*)logic_filter, mmio + LADRF);
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+
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+ /* SRAM_SIZE register */
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+ reg_val = readl(mmio + SRAM_SIZE);
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+
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+ /* Set default value to CTRL1 Register */
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+ writel(CTRL1_DEFAULT, mmio + CTRL1);
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+
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+ /* To avoid PCI posting bug */
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+ readl(mmio + CMD2);
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+}
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+
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+/*
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+ * This function initializes the device registers and starts the device.
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+ */
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+static int amd8111e_start(struct amd8111e_priv *lp)
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+{
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+ struct nic *nic = lp->nic;
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+ void *mmio = lp->mmio;
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+ int i, reg_val;
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+
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+ /* stop the chip */
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+ writel(RUN, mmio + CMD0);
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+
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+ /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
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+ writew(0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
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+
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+ /* enable the port manager and set auto negotiation always */
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+ writel(VAL1 | EN_PMGR, mmio + CMD3 );
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+ writel(XPHYANE | XPHYRST, mmio + CTRL2);
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+
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+ /* set control registers */
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+ reg_val = readl(mmio + CTRL1);
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+ reg_val &= ~XMTSP_MASK;
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+ writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
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+
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+ /* initialize tx and rx ring base addresses */
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+ amd8111e_init_tx_ring(lp);
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+ amd8111e_init_rx_ring(lp);
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+ writel(virt_to_bus(lp->tx_ring), mmio + XMT_RING_BASE_ADDR0);
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+ writel(virt_to_bus(lp->rx_ring), mmio + RCV_RING_BASE_ADDR0);
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+ writew(NUM_TX_SLOTS, mmio + XMT_RING_LEN0);
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+ writew(NUM_RX_SLOTS, mmio + RCV_RING_LEN0);
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+
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+ /* set default IPG to 96 */
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+ writew(DEFAULT_IPG, mmio + IPG);
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+ writew(DEFAULT_IPG - IFS1_DELTA, mmio + IFS1);
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+
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+ /* AutoPAD transmit, Retransmit on Underflow */
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+ writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
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+
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+ /* JUMBO disabled */
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+ writel(JUMBO, mmio + CMD3);
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+
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+ /* Setting the MAC address to the device */
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+ for(i = 0; i < ETH_ALEN; i++)
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+ writeb(nic->node_addr[i], mmio + PADR + i);
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+
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+ /* set RUN bit to start the chip, interrupt not enabled */
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+ writel(VAL2 | RDMD0 | VAL0 | RUN, mmio + CMD0);
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+
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+ /* To avoid PCI posting bug */
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+ readl(mmio + CMD0);
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+ return 0;
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+}
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+
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266
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+/*
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+This function will read the PHY registers.
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+*/
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269
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+static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val)
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+{
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+ void *mmio = lp->mmio;
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+ unsigned int reg_val;
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+ unsigned int retry = PHY_RW_RETRY;
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+
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+ reg_val = readl(mmio + PHY_ACCESS);
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+ while (reg_val & PHY_CMD_ACTIVE)
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+ reg_val = readl(mmio + PHY_ACCESS);
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+
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+ writel(PHY_RD_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16),
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+ mmio + PHY_ACCESS);
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+ do {
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+ reg_val = readl(mmio + PHY_ACCESS);
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+ udelay(30); /* It takes 30 us to read/write data */
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+ } while (--retry && (reg_val & PHY_CMD_ACTIVE));
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285
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+
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286
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+ if (reg_val & PHY_RD_ERR) {
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+ *val = 0;
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+ return -1;
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289
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+ }
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290
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+
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291
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+ *val = reg_val & 0xffff;
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+ return 0;
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293
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+}
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+
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295
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+/*
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296
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+This function will write into PHY registers.
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297
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+*/
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298
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+#if 0
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299
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+static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val)
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300
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+{
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301
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+ void *mmio = lp->mmio;
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302
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+ unsigned int reg_val;
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+ unsigned int retry = PHY_RW_RETRY;
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+
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+ reg_val = readl(mmio + PHY_ACCESS);
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+ while (reg_val & PHY_CMD_ACTIVE)
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+ reg_val = readl(mmio + PHY_ACCESS);
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+
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+ writel(PHY_WR_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16) | val,
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+ mmio + PHY_ACCESS);
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+ do {
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+ reg_val = readl(mmio + PHY_ACCESS);
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+ udelay(30); /* It takes 30 us to read/write the data */
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+ } while (--retry && (reg_val & PHY_CMD_ACTIVE));
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+
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316
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+ if(reg_val & PHY_RD_ERR)
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+ return -1;
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+
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319
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+ return 0;
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320
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+}
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321
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+#endif
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322
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+
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323
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+static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp)
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324
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+{
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325
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+ int i;
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326
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+
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327
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+ lp->ext_phy_id = 0;
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328
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+ lp->ext_phy_addr = 1;
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329
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+
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330
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+ for (i = 0x1e; i >= 0; i--) {
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331
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+ u32 id1, id2;
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332
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+
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333
|
+ if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
|
|
334
|
+ continue;
|
|
335
|
+ if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
|
|
336
|
+ continue;
|
|
337
|
+ lp->ext_phy_id = (id1 << 16) | id2;
|
|
338
|
+ lp->ext_phy_addr = i;
|
|
339
|
+ break;
|
|
340
|
+ }
|
|
341
|
+
|
|
342
|
+ if (lp->ext_phy_id)
|
|
343
|
+ printf("Found MII PHY ID 0x%08x at address 0x%02x\n",
|
|
344
|
+ lp->ext_phy_id, lp->ext_phy_addr);
|
|
345
|
+ else
|
|
346
|
+ printf("Couldn't detect MII PHY, assuming address 0x01\n");
|
|
347
|
+}
|
|
348
|
+
|
|
349
|
+static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
|
|
350
|
+{
|
|
351
|
+ void *mmio = lp->mmio;
|
|
352
|
+ unsigned int int0;
|
|
353
|
+
|
|
354
|
+ writel(INTREN, mmio + CMD0);
|
|
355
|
+ writel(INTEN0_CLEAR, mmio + INTEN0);
|
|
356
|
+ int0 = readl(mmio + INT0);
|
|
357
|
+ writel(int0, mmio + INT0);
|
|
358
|
+ readl(mmio + INT0);
|
|
359
|
+}
|
|
360
|
+
|
|
361
|
+static void amd8111e_enable_interrupt(struct amd8111e_priv *lp)
|
|
362
|
+{
|
|
363
|
+ void *mmio = lp->mmio;
|
|
364
|
+
|
|
365
|
+ writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
|
|
366
|
+ writel(VAL0 | INTREN, mmio + CMD0);
|
|
367
|
+ readl(mmio + CMD0);
|
|
368
|
+}
|
|
369
|
+
|
|
370
|
+static void amd8111e_force_interrupt(struct amd8111e_priv *lp)
|
|
371
|
+{
|
|
372
|
+ void *mmio = lp->mmio;
|
|
373
|
+
|
|
374
|
+ writel(VAL0 | UINTCMD, mmio + CMD0);
|
|
375
|
+ readl(mmio + CMD0);
|
|
376
|
+}
|
|
377
|
+
|
|
378
|
+static int amd8111e_get_mac_address(struct amd8111e_priv *lp)
|
|
379
|
+{
|
|
380
|
+ struct nic *nic = lp->nic;
|
|
381
|
+ void *mmio = lp->mmio;
|
|
382
|
+ int i;
|
|
383
|
+
|
|
384
|
+ /* BIOS should have set mac address to PADR register,
|
|
385
|
+ * so we read PADR to get it.
|
|
386
|
+ */
|
|
387
|
+ for (i = 0; i < ETH_ALEN; i++)
|
|
388
|
+ nic->node_addr[i] = readb(mmio + PADR + i);
|
|
389
|
+ printf("Ethernet addr: %!\n", nic->node_addr);
|
|
390
|
+
|
|
391
|
+ return 0;
|
|
392
|
+}
|
|
393
|
+
|
|
394
|
+static int amd8111e_init_rx_ring(struct amd8111e_priv *lp)
|
|
395
|
+{
|
|
396
|
+ int i;
|
|
397
|
+
|
|
398
|
+ lp->rx_idx = 0;
|
|
399
|
+
|
|
400
|
+ /* Initilaizing receive descriptors */
|
|
401
|
+ for (i = 0; i < NUM_RX_SLOTS; i++) {
|
|
402
|
+ lp->rx_ring[i].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[i]));
|
|
403
|
+ lp->rx_ring[i].buf_len = cpu_to_le16(RX_BUF_LEN);
|
|
404
|
+ wmb();
|
|
405
|
+ lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
|
|
406
|
+ }
|
|
407
|
+
|
|
408
|
+ return 0;
|
|
409
|
+}
|
|
410
|
+
|
|
411
|
+static int amd8111e_init_tx_ring(struct amd8111e_priv *lp)
|
|
412
|
+{
|
|
413
|
+ int i;
|
|
414
|
+
|
|
415
|
+ lp->tx_idx = 0;
|
|
416
|
+ lp->tx_consistent = 1;
|
|
417
|
+
|
|
418
|
+ /* Initializing transmit descriptors */
|
|
419
|
+ for (i = 0; i < NUM_TX_SLOTS; i++) {
|
|
420
|
+ lp->tx_ring[i].tx_flags = 0;
|
|
421
|
+ lp->tx_ring[i].buf_phy_addr = 0;
|
|
422
|
+ lp->tx_ring[i].buf_len = 0;
|
|
423
|
+ }
|
|
424
|
+
|
|
425
|
+ return 0;
|
|
426
|
+}
|
|
427
|
+
|
|
428
|
+static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index)
|
|
429
|
+{
|
|
430
|
+ volatile u16 status;
|
|
431
|
+ int retry = TX_RETRY;
|
|
432
|
+
|
|
433
|
+ status = le16_to_cpu(lp->tx_ring[index].tx_flags);
|
|
434
|
+ while (--retry && (status & OWN_BIT)) {
|
|
435
|
+ mdelay(TX_PROCESS_TIME);
|
|
436
|
+ status = le16_to_cpu(lp->tx_ring[index].tx_flags);
|
|
437
|
+ }
|
|
438
|
+ if (status & OWN_BIT) {
|
|
439
|
+ printf("Error: tx slot %d timeout, stat = 0x%x\n", index, status);
|
|
440
|
+ amd8111e_restart(lp);
|
|
441
|
+ return -1;
|
|
442
|
+ }
|
|
443
|
+
|
|
444
|
+ return 0;
|
|
445
|
+}
|
|
446
|
+
|
|
447
|
+static void amd8111e_wait_link(struct amd8111e_priv *lp)
|
|
448
|
+{
|
|
449
|
+ unsigned int status;
|
|
450
|
+ u32 reg_val;
|
|
451
|
+
|
|
452
|
+ do {
|
|
453
|
+ /* read phy to update STAT0 register */
|
|
454
|
+ amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, ®_val);
|
|
455
|
+ amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, ®_val);
|
|
456
|
+ amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, ®_val);
|
|
457
|
+ amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, ®_val);
|
|
458
|
+ status = readl(lp->mmio + STAT0);
|
|
459
|
+ } while (!(status & AUTONEG_COMPLETE) || !(status & LINK_STATS));
|
|
460
|
+}
|
|
461
|
+
|
|
462
|
+static void amd8111e_poll_link(struct amd8111e_priv *lp)
|
|
463
|
+{
|
|
464
|
+ unsigned int status, speed;
|
|
465
|
+ u32 reg_val;
|
|
466
|
+
|
|
467
|
+ if (!lp->link) {
|
|
468
|
+ /* read phy to update STAT0 register */
|
|
469
|
+ amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, ®_val);
|
|
470
|
+ amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, ®_val);
|
|
471
|
+ amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, ®_val);
|
|
472
|
+ amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, ®_val);
|
|
473
|
+ status = readl(lp->mmio + STAT0);
|
|
474
|
+
|
|
475
|
+ if (status & LINK_STATS) {
|
|
476
|
+ lp->link = 1;
|
|
477
|
+ speed = (status & SPEED_MASK) >> 7;
|
|
478
|
+ if (speed == PHY_SPEED_100)
|
|
479
|
+ lp->speed = 1;
|
|
480
|
+ else
|
|
481
|
+ lp->speed = 0;
|
|
482
|
+ if (status & FULL_DPLX)
|
|
483
|
+ lp->duplex = 1;
|
|
484
|
+ else
|
|
485
|
+ lp->duplex = 0;
|
|
486
|
+
|
|
487
|
+ printf("Link is up: %s Mbps %s duplex\n",
|
|
488
|
+ lp->speed ? "100" : "10", lp->duplex ? "full" : "half");
|
|
489
|
+ }
|
|
490
|
+ } else {
|
|
491
|
+ status = readl(lp->mmio + STAT0);
|
|
492
|
+ if (!(status & LINK_STATS)) {
|
|
493
|
+ lp->link = 0;
|
|
494
|
+ printf("Link is down\n");
|
|
495
|
+ }
|
|
496
|
+ }
|
|
497
|
+}
|
|
498
|
+
|
|
499
|
+static void amd8111e_restart(struct amd8111e_priv *lp)
|
|
500
|
+{
|
|
501
|
+ printf("\nStarting nic...\n");
|
|
502
|
+ amd8111e_disable_interrupt(lp);
|
|
503
|
+ amd8111e_init_hw_default(lp);
|
|
504
|
+ amd8111e_probe_ext_phy(lp);
|
|
505
|
+ amd8111e_get_mac_address(lp);
|
|
506
|
+ amd8111e_start(lp);
|
|
507
|
+
|
|
508
|
+ printf("Waiting link up...\n");
|
|
509
|
+ lp->link = 0;
|
|
510
|
+ amd8111e_wait_link(lp);
|
|
511
|
+ amd8111e_poll_link(lp);
|
|
512
|
+}
|
|
513
|
+
|
|
514
|
+
|
|
515
|
+/********************************************************
|
|
516
|
+ * Interface Functions *
|
|
517
|
+ ********************************************************/
|
|
518
|
+
|
|
519
|
+static void amd8111e_transmit(struct nic *nic, const char *dst_addr,
|
|
520
|
+ unsigned int type, unsigned int size, const char *packet)
|
|
521
|
+{
|
|
522
|
+ struct amd8111e_priv *lp = nic->priv_data;
|
|
523
|
+ struct eth_frame *frame;
|
|
524
|
+ unsigned int index;
|
|
525
|
+
|
|
526
|
+ /* check packet size */
|
|
527
|
+ if (size > TX_PKT_LEN_MAX) {
|
|
528
|
+ printf("amd8111e_transmit(): too large packet, drop\n");
|
|
529
|
+ return;
|
|
530
|
+ }
|
|
531
|
+
|
|
532
|
+ /* get tx slot */
|
|
533
|
+ index = lp->tx_idx;
|
|
534
|
+ if (amd8111e_wait_tx_ring(lp, index))
|
|
535
|
+ return;
|
|
536
|
+
|
|
537
|
+ /* fill frame */
|
|
538
|
+ frame = (struct eth_frame *)lp->tx_buf[index];
|
|
539
|
+ memset(frame->data, 0, TX_PKT_LEN_MAX);
|
|
540
|
+ memcpy(frame->dst_addr, dst_addr, ETH_ALEN);
|
|
541
|
+ memcpy(frame->src_addr, nic->node_addr, ETH_ALEN);
|
|
542
|
+ frame->type = htons(type);
|
|
543
|
+ memcpy(frame->data, packet, size);
|
|
544
|
+
|
|
545
|
+ /* start xmit */
|
|
546
|
+ lp->tx_ring[index].buf_len = cpu_to_le16(ETH_HLEN + size);
|
|
547
|
+ lp->tx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(frame));
|
|
548
|
+ wmb();
|
|
549
|
+ lp->tx_ring[index].tx_flags =
|
|
550
|
+ cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT | ADD_FCS_BIT | LTINT_BIT);
|
|
551
|
+ writel(VAL1 | TDMD0, lp->mmio + CMD0);
|
|
552
|
+ readl(lp->mmio + CMD0);
|
|
553
|
+
|
|
554
|
+ /* update slot pointer */
|
|
555
|
+ lp->tx_idx = (lp->tx_idx + 1) & TX_SLOTS_MASK;
|
|
556
|
+}
|
|
557
|
+
|
|
558
|
+static int amd8111e_poll(struct nic *nic, int retrieve)
|
|
559
|
+{
|
|
560
|
+ /* return true if there's an ethernet packet ready to read */
|
|
561
|
+ /* nic->packet should contain data on return */
|
|
562
|
+ /* nic->packetlen should contain length of data */
|
|
563
|
+
|
|
564
|
+ struct amd8111e_priv *lp = nic->priv_data;
|
|
565
|
+ u16 status, pkt_len;
|
|
566
|
+ unsigned int index, pkt_ok;
|
|
567
|
+
|
|
568
|
+ amd8111e_poll_link(lp);
|
|
569
|
+
|
|
570
|
+ index = lp->rx_idx;
|
|
571
|
+ status = le16_to_cpu(lp->rx_ring[index].rx_flags);
|
|
572
|
+ pkt_len = le16_to_cpu(lp->rx_ring[index].msg_len) - 4; /* remove 4bytes FCS */
|
|
573
|
+
|
|
574
|
+ if (status & OWN_BIT)
|
|
575
|
+ return 0;
|
|
576
|
+
|
|
577
|
+ if (status & ERR_BIT)
|
|
578
|
+ pkt_ok = 0;
|
|
579
|
+ else if (!(status & STP_BIT))
|
|
580
|
+ pkt_ok = 0;
|
|
581
|
+ else if (!(status & ENP_BIT))
|
|
582
|
+ pkt_ok = 0;
|
|
583
|
+ else if (pkt_len < RX_PKT_LEN_MIN)
|
|
584
|
+ pkt_ok = 0;
|
|
585
|
+ else if (pkt_len > RX_PKT_LEN_MAX)
|
|
586
|
+ pkt_ok = 0;
|
|
587
|
+ else
|
|
588
|
+ pkt_ok = 1;
|
|
589
|
+
|
|
590
|
+ if (pkt_ok) {
|
|
591
|
+ if (!retrieve)
|
|
592
|
+ return 1;
|
|
593
|
+ nic->packetlen = pkt_len;
|
|
594
|
+ memcpy(nic->packet, lp->rx_buf[index], nic->packetlen);
|
|
595
|
+ }
|
|
596
|
+
|
|
597
|
+ lp->rx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[index]));
|
|
598
|
+ lp->rx_ring[index].buf_len = cpu_to_le16(RX_BUF_LEN);
|
|
599
|
+ wmb();
|
|
600
|
+ lp->rx_ring[index].rx_flags = cpu_to_le16(OWN_BIT);
|
|
601
|
+ writel(VAL2 | RDMD0, lp->mmio + CMD0);
|
|
602
|
+ readl(lp->mmio + CMD0);
|
|
603
|
+
|
|
604
|
+ lp->rx_idx = (lp->rx_idx + 1) & RX_SLOTS_MASK;
|
|
605
|
+ return pkt_ok;
|
|
606
|
+}
|
|
607
|
+
|
|
608
|
+static void amd8111e_disable(struct nic *nic)
|
|
609
|
+{
|
|
610
|
+ struct amd8111e_priv *lp = nic->priv_data;
|
|
611
|
+
|
|
612
|
+ /* disable interrupt */
|
|
613
|
+ amd8111e_disable_interrupt(lp);
|
|
614
|
+
|
|
615
|
+ /* stop chip */
|
|
616
|
+ amd8111e_init_hw_default(lp);
|
|
617
|
+
|
|
618
|
+ /* unmap mmio */
|
|
619
|
+ iounmap(lp->mmio);
|
|
620
|
+
|
|
621
|
+ /* update status */
|
|
622
|
+ lp->opened = 0;
|
|
623
|
+}
|
|
624
|
+
|
|
625
|
+static void amd8111e_irq(struct nic *nic, irq_action_t action)
|
|
626
|
+{
|
|
627
|
+ struct amd8111e_priv *lp = nic->priv_data;
|
|
628
|
+
|
|
629
|
+ switch (action) {
|
|
630
|
+ case DISABLE:
|
|
631
|
+ amd8111e_disable_interrupt(lp);
|
|
632
|
+ break;
|
|
633
|
+ case ENABLE:
|
|
634
|
+ amd8111e_enable_interrupt(lp);
|
|
635
|
+ break;
|
|
636
|
+ case FORCE:
|
|
637
|
+ amd8111e_force_interrupt(lp);
|
|
638
|
+ break;
|
|
639
|
+ }
|
|
640
|
+}
|
|
641
|
+
|
|
642
|
+static struct nic_operations amd8111e_operations = {
|
|
643
|
+ .connect = dummy_connect,
|
|
644
|
+ .poll = amd8111e_poll,
|
|
645
|
+ .transmit = amd8111e_transmit,
|
|
646
|
+ .irq = amd8111e_irq,
|
|
647
|
+};
|
|
648
|
+
|
|
649
|
+static int amd8111e_probe(struct nic *nic, struct pci_device *pdev)
|
|
650
|
+{
|
|
651
|
+ struct amd8111e_priv *lp = &amd8111e;
|
|
652
|
+ unsigned long mmio_start, mmio_len;
|
|
653
|
+
|
|
654
|
+ pci_fill_nic ( nic, pdev );
|
|
655
|
+
|
|
656
|
+ mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
|
|
657
|
+ mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_0);
|
|
658
|
+
|
|
659
|
+ memset(lp, 0, sizeof(*lp));
|
|
660
|
+ lp->pdev = pdev;
|
|
661
|
+ lp->nic = nic;
|
|
662
|
+ lp->mmio = ioremap(mmio_start, mmio_len);
|
|
663
|
+ lp->opened = 1;
|
|
664
|
+ adjust_pci_device(pdev);
|
|
665
|
+
|
|
666
|
+ nic->priv_data = lp;
|
|
667
|
+
|
|
668
|
+ amd8111e_restart(lp);
|
|
669
|
+
|
|
670
|
+ nic->nic_op = &amd8111e_operations;
|
|
671
|
+ return 1;
|
|
672
|
+}
|
|
673
|
+
|
|
674
|
+static struct pci_id amd8111e_nics[] = {
|
|
675
|
+ PCI_ROM(0x1022, 0x7462, "amd8111e", "AMD8111E"),
|
|
676
|
+};
|
|
677
|
+
|
|
678
|
+PCI_DRIVER ( amd8111e_driver, amd8111e_nics, PCI_NO_CLASS );
|
|
679
|
+
|
|
680
|
+DRIVER ( "AMD8111E", nic_driver, pci_driver, amd8111e_driver,
|
|
681
|
+ amd8111e_probe, amd8111e_disable );
|