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[smsc75xx] Use common SMSC USB device functionality

Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown 6 yıl önce
ebeveyn
işleme
b1df34d7bd
2 değiştirilmiş dosya ile 127 ekleme ve 721 silme
  1. 118
    607
      src/drivers/net/smsc75xx.c
  2. 9
    114
      src/drivers/net/smsc75xx.h

+ 118
- 607
src/drivers/net/smsc75xx.c
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+ 9
- 114
src/drivers/net/smsc75xx.h Dosyayı Görüntüle

9
 
9
 
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 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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11
 
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-#include <ipxe/usb.h>
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-#include <ipxe/usbnet.h>
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-#include <ipxe/if_ether.h>
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-#include <ipxe/mii.h>
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-
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-/** Register write command */
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-#define SMSC75XX_REGISTER_WRITE					\
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-	( USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE |	\
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-	  USB_REQUEST_TYPE ( 0xa0 ) )
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-
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-/** Register read command */
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-#define SMSC75XX_REGISTER_READ					\
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-	( USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE |	\
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-	  USB_REQUEST_TYPE ( 0xa1 ) )
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-
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-/** Get statistics command */
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-#define SMSC75XX_GET_STATISTICS					\
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-	( USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE |	\
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-	  USB_REQUEST_TYPE ( 0xa2 ) )
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+#include "smscusb.h"
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 /** Interrupt status register */
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 /** Interrupt status register */
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 #define SMSC75XX_INT_STS 0x00c
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 #define SMSC75XX_INT_STS 0x00c
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 #define SMSC75XX_BULK_IN_DLY 0x03c
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 #define SMSC75XX_BULK_IN_DLY 0x03c
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 #define SMSC75XX_BULK_IN_DLY_SET(ticks)	( (ticks) << 0 ) /**< Delay / 16.7ns */
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 #define SMSC75XX_BULK_IN_DLY_SET(ticks)	( (ticks) << 0 ) /**< Delay / 16.7ns */
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-/** EEPROM command register */
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-#define SMSC75XX_E2P_CMD 0x040
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-#define SMSC75XX_E2P_CMD_EPC_BSY	0x80000000UL	/**< EPC busy */
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-#define SMSC75XX_E2P_CMD_EPC_CMD_READ	0x00000000UL	/**< READ command */
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-#define SMSC75XX_E2P_CMD_EPC_ADDR(addr) ( (addr) << 0 )	/**< EPC address */
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-
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-/** EEPROM data register */
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-#define SMSC75XX_E2P_DATA 0x044
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-#define SMSC75XX_E2P_DATA_GET(e2p_data) \
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-	( ( (e2p_data) >> 0 ) & 0xff )			/**< EEPROM data */
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-
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-/** MAC address EEPROM address */
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-#define SMSC75XX_EEPROM_MAC 0x01
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+/** EEPROM register base */
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+#define SMSC75XX_E2P_BASE 0x040
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 /** Receive filtering engine control register */
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 /** Receive filtering engine control register */
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 #define SMSC75XX_RFE_CTL 0x060
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 #define SMSC75XX_RFE_CTL 0x060
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 #define SMSC75XX_MAC_TX 0x108
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 #define SMSC75XX_MAC_TX 0x108
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 #define SMSC75XX_MAC_TX_EN		0x00000001UL	/**< TX enable */
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 #define SMSC75XX_MAC_TX_EN		0x00000001UL	/**< TX enable */
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62
 
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-/** MAC receive address high register */
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-#define SMSC75XX_RX_ADDRH 0x118
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-
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-/** MAC receive address low register */
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-#define SMSC75XX_RX_ADDRL 0x11c
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-
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-/** MII access register */
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-#define SMSC75XX_MII_ACCESS 0x120
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-#define SMSC75XX_MII_ACCESS_PHY_ADDRESS	0x00000800UL	/**< PHY address */
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-#define SMSC75XX_MII_ACCESS_MIIRINDA(addr) ( (addr) << 6 ) /**< MII register */
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-#define SMSC75XX_MII_ACCESS_MIIWNR	0x00000002UL	/**< MII write */
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-#define SMSC75XX_MII_ACCESS_MIIBZY	0x00000001UL	/**< MII busy */
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-
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-/** MII data register */
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-#define SMSC75XX_MII_DATA 0x124
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-#define SMSC75XX_MII_DATA_SET(data)	( (data) << 0 )	/**< Set data */
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-#define SMSC75XX_MII_DATA_GET(mii_data) \
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-	( ( (mii_data) >> 0 ) & 0xffff )		/**< Get data */
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-
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-/** PHY interrupt source MII register */
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-#define SMSC75XX_MII_PHY_INTR_SOURCE 29
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-
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-/** PHY interrupt mask MII register */
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-#define SMSC75XX_MII_PHY_INTR_MASK 30
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-
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-/** PHY interrupt: auto-negotiation complete */
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-#define SMSC75XX_PHY_INTR_ANEG_DONE	0x0040
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+/** MAC receive address register base */
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+#define SMSC75XX_RX_ADDR_BASE 0x118
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-/** PHY interrupt: link down */
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-#define SMSC75XX_PHY_INTR_LINK_DOWN	0x0010
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+/** MII register base */
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+#define SMSC75XX_MII_BASE 0x120
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-/** MAC address perfect filter N high register */
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-#define SMSC75XX_ADDR_FILTH(n) ( 0x300 + ( 8 * (n) ) )
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-#define SMSC75XX_ADDR_FILTH_VALID	0x80000000UL	/**< Address valid */
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-
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-/** MAC address perfect filter N low register */
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-#define SMSC75XX_ADDR_FILTL(n) ( 0x304 + ( 8 * (n) ) )
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-
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-/** MAC address */
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-union smsc75xx_mac {
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-	/** MAC receive address registers */
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-	struct {
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-		/** MAC receive address low register */
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-		uint32_t l;
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-		/** MAC receive address high register */
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-		uint32_t h;
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-	} __attribute__ (( packed )) addr;
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-	/** Raw MAC address */
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-	uint8_t raw[ETH_ALEN];
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-};
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+/** MAC address perfect filter register base */
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+#define SMSC75XX_ADDR_FILT_BASE 0x300
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 /** Receive packet header */
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 /** Receive packet header */
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 struct smsc75xx_rx_header {
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 struct smsc75xx_rx_header {
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 /** Insert frame checksum and pad */
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 /** Insert frame checksum and pad */
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 #define SMSC75XX_TX_FCS 0x00400000UL
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 #define SMSC75XX_TX_FCS 0x00400000UL
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-/** Interrupt packet format */
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-struct smsc75xx_interrupt {
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-	/** Current value of INT_STS register */
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-	uint32_t int_sts;
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-} __attribute__ (( packed ));
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-
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 /** Byte count statistics */
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 /** Byte count statistics */
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 struct smsc75xx_byte_statistics {
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 struct smsc75xx_byte_statistics {
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 	/** Unicast byte count */
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 	/** Unicast byte count */
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 	struct smsc75xx_tx_statistics tx;
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 	struct smsc75xx_tx_statistics tx;
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 } __attribute__ (( packed ));
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 } __attribute__ (( packed ));
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189
 
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-/** A SMSC75xx network device */
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-struct smsc75xx_device {
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-	/** USB device */
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-	struct usb_device *usb;
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-	/** USB bus */
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-	struct usb_bus *bus;
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-	/** Network device */
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-	struct net_device *netdev;
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-	/** USB network device */
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-	struct usbnet_device usbnet;
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-	/** MII interface */
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-	struct mii_interface mii;
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-	/** Interrupt status */
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-	uint32_t int_sts;
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-};
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-
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 /** Maximum time to wait for reset (in milliseconds) */
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 /** Maximum time to wait for reset (in milliseconds) */
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 #define SMSC75XX_RESET_MAX_WAIT_MS 100
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 #define SMSC75XX_RESET_MAX_WAIT_MS 100
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-/** Maximum time to wait for EEPROM (in milliseconds) */
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-#define SMSC75XX_EEPROM_MAX_WAIT_MS 100
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-
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-/** Maximum time to wait for MII (in milliseconds) */
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-#define SMSC75XX_MII_MAX_WAIT_MS 100
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-
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-/** Interrupt maximum fill level
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- *
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- * This is a policy decision.
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- */
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-#define SMSC75XX_INTR_MAX_FILL 2
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-
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 /** Bulk IN maximum fill level
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 /** Bulk IN maximum fill level
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  *
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  *
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  * This is a policy decision.
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  * This is a policy decision.

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