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[smsc75xx] Use common SMSC USB device functionality

Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown 7年前
コミット
b1df34d7bd
2個のファイルの変更127行の追加721行の削除
  1. 118
    607
      src/drivers/net/smsc75xx.c
  2. 9
    114
      src/drivers/net/smsc75xx.h

+ 118
- 607
src/drivers/net/smsc75xx.c
ファイル差分が大きすぎるため省略します
ファイルの表示


+ 9
- 114
src/drivers/net/smsc75xx.h ファイルの表示

@@ -9,25 +9,7 @@
9 9
 
10 10
 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11 11
 
12
-#include <ipxe/usb.h>
13
-#include <ipxe/usbnet.h>
14
-#include <ipxe/if_ether.h>
15
-#include <ipxe/mii.h>
16
-
17
-/** Register write command */
18
-#define SMSC75XX_REGISTER_WRITE					\
19
-	( USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE |	\
20
-	  USB_REQUEST_TYPE ( 0xa0 ) )
21
-
22
-/** Register read command */
23
-#define SMSC75XX_REGISTER_READ					\
24
-	( USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE |	\
25
-	  USB_REQUEST_TYPE ( 0xa1 ) )
26
-
27
-/** Get statistics command */
28
-#define SMSC75XX_GET_STATISTICS					\
29
-	( USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE |	\
30
-	  USB_REQUEST_TYPE ( 0xa2 ) )
12
+#include "smscusb.h"
31 13
 
32 14
 /** Interrupt status register */
33 15
 #define SMSC75XX_INT_STS 0x00c
@@ -48,19 +30,8 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
48 30
 #define SMSC75XX_BULK_IN_DLY 0x03c
49 31
 #define SMSC75XX_BULK_IN_DLY_SET(ticks)	( (ticks) << 0 ) /**< Delay / 16.7ns */
50 32
 
51
-/** EEPROM command register */
52
-#define SMSC75XX_E2P_CMD 0x040
53
-#define SMSC75XX_E2P_CMD_EPC_BSY	0x80000000UL	/**< EPC busy */
54
-#define SMSC75XX_E2P_CMD_EPC_CMD_READ	0x00000000UL	/**< READ command */
55
-#define SMSC75XX_E2P_CMD_EPC_ADDR(addr) ( (addr) << 0 )	/**< EPC address */
56
-
57
-/** EEPROM data register */
58
-#define SMSC75XX_E2P_DATA 0x044
59
-#define SMSC75XX_E2P_DATA_GET(e2p_data) \
60
-	( ( (e2p_data) >> 0 ) & 0xff )			/**< EEPROM data */
61
-
62
-/** MAC address EEPROM address */
63
-#define SMSC75XX_EEPROM_MAC 0x01
33
+/** EEPROM register base */
34
+#define SMSC75XX_E2P_BASE 0x040
64 35
 
65 36
 /** Receive filtering engine control register */
66 37
 #define SMSC75XX_RFE_CTL 0x060
@@ -89,56 +60,14 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
89 60
 #define SMSC75XX_MAC_TX 0x108
90 61
 #define SMSC75XX_MAC_TX_EN		0x00000001UL	/**< TX enable */
91 62
 
92
-/** MAC receive address high register */
93
-#define SMSC75XX_RX_ADDRH 0x118
94
-
95
-/** MAC receive address low register */
96
-#define SMSC75XX_RX_ADDRL 0x11c
97
-
98
-/** MII access register */
99
-#define SMSC75XX_MII_ACCESS 0x120
100
-#define SMSC75XX_MII_ACCESS_PHY_ADDRESS	0x00000800UL	/**< PHY address */
101
-#define SMSC75XX_MII_ACCESS_MIIRINDA(addr) ( (addr) << 6 ) /**< MII register */
102
-#define SMSC75XX_MII_ACCESS_MIIWNR	0x00000002UL	/**< MII write */
103
-#define SMSC75XX_MII_ACCESS_MIIBZY	0x00000001UL	/**< MII busy */
104
-
105
-/** MII data register */
106
-#define SMSC75XX_MII_DATA 0x124
107
-#define SMSC75XX_MII_DATA_SET(data)	( (data) << 0 )	/**< Set data */
108
-#define SMSC75XX_MII_DATA_GET(mii_data) \
109
-	( ( (mii_data) >> 0 ) & 0xffff )		/**< Get data */
110
-
111
-/** PHY interrupt source MII register */
112
-#define SMSC75XX_MII_PHY_INTR_SOURCE 29
113
-
114
-/** PHY interrupt mask MII register */
115
-#define SMSC75XX_MII_PHY_INTR_MASK 30
116
-
117
-/** PHY interrupt: auto-negotiation complete */
118
-#define SMSC75XX_PHY_INTR_ANEG_DONE	0x0040
63
+/** MAC receive address register base */
64
+#define SMSC75XX_RX_ADDR_BASE 0x118
119 65
 
120
-/** PHY interrupt: link down */
121
-#define SMSC75XX_PHY_INTR_LINK_DOWN	0x0010
66
+/** MII register base */
67
+#define SMSC75XX_MII_BASE 0x120
122 68
 
123
-/** MAC address perfect filter N high register */
124
-#define SMSC75XX_ADDR_FILTH(n) ( 0x300 + ( 8 * (n) ) )
125
-#define SMSC75XX_ADDR_FILTH_VALID	0x80000000UL	/**< Address valid */
126
-
127
-/** MAC address perfect filter N low register */
128
-#define SMSC75XX_ADDR_FILTL(n) ( 0x304 + ( 8 * (n) ) )
129
-
130
-/** MAC address */
131
-union smsc75xx_mac {
132
-	/** MAC receive address registers */
133
-	struct {
134
-		/** MAC receive address low register */
135
-		uint32_t l;
136
-		/** MAC receive address high register */
137
-		uint32_t h;
138
-	} __attribute__ (( packed )) addr;
139
-	/** Raw MAC address */
140
-	uint8_t raw[ETH_ALEN];
141
-};
69
+/** MAC address perfect filter register base */
70
+#define SMSC75XX_ADDR_FILT_BASE 0x300
142 71
 
143 72
 /** Receive packet header */
144 73
 struct smsc75xx_rx_header {
@@ -168,12 +97,6 @@ struct smsc75xx_tx_header {
168 97
 /** Insert frame checksum and pad */
169 98
 #define SMSC75XX_TX_FCS 0x00400000UL
170 99
 
171
-/** Interrupt packet format */
172
-struct smsc75xx_interrupt {
173
-	/** Current value of INT_STS register */
174
-	uint32_t int_sts;
175
-} __attribute__ (( packed ));
176
-
177 100
 /** Byte count statistics */
178 101
 struct smsc75xx_byte_statistics {
179 102
 	/** Unicast byte count */
@@ -264,37 +187,9 @@ struct smsc75xx_statistics {
264 187
 	struct smsc75xx_tx_statistics tx;
265 188
 } __attribute__ (( packed ));
266 189
 
267
-/** A SMSC75xx network device */
268
-struct smsc75xx_device {
269
-	/** USB device */
270
-	struct usb_device *usb;
271
-	/** USB bus */
272
-	struct usb_bus *bus;
273
-	/** Network device */
274
-	struct net_device *netdev;
275
-	/** USB network device */
276
-	struct usbnet_device usbnet;
277
-	/** MII interface */
278
-	struct mii_interface mii;
279
-	/** Interrupt status */
280
-	uint32_t int_sts;
281
-};
282
-
283 190
 /** Maximum time to wait for reset (in milliseconds) */
284 191
 #define SMSC75XX_RESET_MAX_WAIT_MS 100
285 192
 
286
-/** Maximum time to wait for EEPROM (in milliseconds) */
287
-#define SMSC75XX_EEPROM_MAX_WAIT_MS 100
288
-
289
-/** Maximum time to wait for MII (in milliseconds) */
290
-#define SMSC75XX_MII_MAX_WAIT_MS 100
291
-
292
-/** Interrupt maximum fill level
293
- *
294
- * This is a policy decision.
295
- */
296
-#define SMSC75XX_INTR_MAX_FILL 2
297
-
298 193
 /** Bulk IN maximum fill level
299 194
  *
300 195
  * This is a policy decision.

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