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@@ -141,17 +141,17 @@ static const struct intelxl_admin_offsets intelxl_admin_offsets = {
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*/
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static int intelxl_create_admin ( struct intelxl_nic *intelxl,
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struct intelxl_admin *admin ) {
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+ size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
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size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
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const struct intelxl_admin_offsets *regs = admin->regs;
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void *admin_regs = ( intelxl->regs + admin->base );
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physaddr_t address;
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/* Allocate admin queue */
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- admin->desc = malloc_dma ( ( len + sizeof ( *admin->buffer ) ),
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- INTELXL_ALIGN );
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- if ( ! admin->desc )
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+ admin->buf = malloc_dma ( ( buf_len + len ), INTELXL_ALIGN );
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+ if ( ! admin->buf )
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return -ENOMEM;
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- admin->buffer = ( ( ( void * ) admin->desc ) + len );
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+ admin->desc = ( ( ( void * ) admin->buf ) + buf_len );
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/* Initialise admin queue */
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memset ( admin->desc, 0, len );
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@@ -183,9 +183,9 @@ static int intelxl_create_admin ( struct intelxl_nic *intelxl,
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( ( admin == &intelxl->command ) ? 'T' : 'R' ),
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( ( unsigned long long ) address ),
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( ( unsigned long long ) address + len ),
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- ( ( unsigned long long ) virt_to_bus ( admin->buffer ) ),
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- ( ( unsigned long long ) ( virt_to_bus ( admin->buffer ) +
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- sizeof ( admin->buffer[0] ) ) ) );
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+ ( ( unsigned long long ) virt_to_bus ( admin->buf ) ),
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+ ( ( unsigned long long ) ( virt_to_bus ( admin->buf ) +
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+ buf_len ) ) );
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return 0;
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}
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@@ -197,6 +197,7 @@ static int intelxl_create_admin ( struct intelxl_nic *intelxl,
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*/
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static void intelxl_destroy_admin ( struct intelxl_nic *intelxl,
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struct intelxl_admin *admin ) {
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+ size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
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size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
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const struct intelxl_admin_offsets *regs = admin->regs;
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void *admin_regs = ( intelxl->regs + admin->base );
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@@ -205,23 +206,80 @@ static void intelxl_destroy_admin ( struct intelxl_nic *intelxl,
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writel ( 0, admin_regs + regs->len );
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/* Free queue */
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- free_dma ( admin->desc, ( len + sizeof ( *admin->buffer ) ) );
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+ free_dma ( admin->buf, ( buf_len + len ) );
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+}
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+
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+/**
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+ * Get next admin command queue descriptor
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+ *
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+ * @v intelxl Intel device
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+ * @ret cmd Command descriptor
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+ */
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+static struct intelxl_admin_descriptor *
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+intelxl_admin_command_descriptor ( struct intelxl_nic *intelxl ) {
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+ struct intelxl_admin *admin = &intelxl->command;
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+ struct intelxl_admin_descriptor *cmd;
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+
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+ /* Get and initialise next descriptor */
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+ cmd = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
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+ memset ( cmd, 0, sizeof ( *cmd ) );
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+ return cmd;
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+}
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+
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+/**
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+ * Get next admin command queue data buffer
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+ *
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+ * @v intelxl Intel device
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+ * @ret buf Data buffer
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+ */
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+static union intelxl_admin_buffer *
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+intelxl_admin_command_buffer ( struct intelxl_nic *intelxl ) {
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+ struct intelxl_admin *admin = &intelxl->command;
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+ union intelxl_admin_buffer *buf;
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+
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+ /* Get next data buffer */
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241
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+ buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
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+ memset ( buf, 0, sizeof ( *buf ) );
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+ return buf;
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+}
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+
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+/**
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247
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+ * Initialise admin event queue descriptor
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+ *
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+ * @v intelxl Intel device
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+ * @v index Event queue index
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+ */
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252
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+static void intelxl_admin_event_init ( struct intelxl_nic *intelxl,
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+ unsigned int index ) {
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254
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+ struct intelxl_admin *admin = &intelxl->event;
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255
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+ struct intelxl_admin_descriptor *evt;
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256
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+ union intelxl_admin_buffer *buf;
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257
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+ uint64_t address;
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+
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+ /* Initialise descriptor */
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260
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+ evt = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
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261
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+ buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
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+ address = virt_to_bus ( buf );
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263
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+ evt->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
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+ evt->len = cpu_to_le16 ( sizeof ( *buf ) );
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+ evt->params.buffer.high = cpu_to_le32 ( address >> 32 );
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+ evt->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
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}
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/**
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212
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270
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* Issue admin queue command
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271
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*
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272
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* @v intelxl Intel device
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- * @v cmd Command descriptor
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216
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273
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* @ret rc Return status code
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217
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274
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*/
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218
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-static int intelxl_admin_command ( struct intelxl_nic *intelxl,
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219
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- struct intelxl_admin_descriptor *cmd ) {
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275
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+static int intelxl_admin_command ( struct intelxl_nic *intelxl ) {
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220
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276
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struct intelxl_admin *admin = &intelxl->command;
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221
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277
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const struct intelxl_admin_offsets *regs = admin->regs;
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222
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278
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void *admin_regs = ( intelxl->regs + admin->base );
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223
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- struct intelxl_admin_descriptor *desc;
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224
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- uint64_t buffer;
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|
279
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+ struct intelxl_admin_descriptor *cmd;
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|
280
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+ union intelxl_admin_buffer *buf;
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281
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+ uint64_t address;
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282
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+ uint32_t cookie;
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225
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283
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unsigned int index;
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226
|
284
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unsigned int tail;
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227
|
285
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unsigned int i;
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@@ -230,32 +288,36 @@ static int intelxl_admin_command ( struct intelxl_nic *intelxl,
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230
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288
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/* Get next queue entry */
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231
|
289
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index = admin->index++;
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232
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290
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tail = ( admin->index % INTELXL_ADMIN_NUM_DESC );
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233
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- desc = &admin->desc[index % INTELXL_ADMIN_NUM_DESC];
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234
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-
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235
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- /* Clear must-be-zero flags */
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236
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- cmd->flags &= ~cpu_to_le16 ( INTELXL_ADMIN_FL_DD |
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237
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- INTELXL_ADMIN_FL_CMP |
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238
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- INTELXL_ADMIN_FL_ERR );
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239
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-
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240
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- /* Clear return value */
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241
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- cmd->ret = 0;
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291
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+ cmd = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
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|
292
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+ buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
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293
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+ DBGC2 ( intelxl, "INTELXL %p admin command %#x opcode %#04x:\n",
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294
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+ intelxl, index, le16_to_cpu ( cmd->opcode ) );
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242
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295
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|
243
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- /* Populate cookie */
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244
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- cmd->cookie = cpu_to_le32 ( index );
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|
296
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+ /* Sanity checks */
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|
297
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+ assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_DD ) ) );
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|
298
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+ assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_CMP ) ) );
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|
299
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+ assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_ERR ) ) );
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|
300
|
+ assert ( cmd->ret == 0 );
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245
|
301
|
|
246
|
302
|
/* Populate data buffer address if applicable */
|
247
|
303
|
if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
|
248
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- buffer = virt_to_bus ( admin->buffer );
|
249
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- cmd->params.buffer.high = cpu_to_le32 ( buffer >> 32 );
|
250
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- cmd->params.buffer.low = cpu_to_le32 ( buffer & 0xffffffffUL );
|
|
304
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+ address = virt_to_bus ( buf );
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|
305
|
+ cmd->params.buffer.high = cpu_to_le32 ( address >> 32 );
|
|
306
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+ cmd->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
|
251
|
307
|
}
|
252
|
308
|
|
253
|
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- /* Copy command descriptor to queue entry */
|
254
|
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- memcpy ( desc, cmd, sizeof ( *desc ) );
|
255
|
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- DBGC2 ( intelxl, "INTELXL %p admin command %#x:\n", intelxl, index );
|
256
|
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- DBGC2_HDA ( intelxl, virt_to_phys ( desc ), desc, sizeof ( *desc ) );
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|
309
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+ /* Populate cookie */
|
|
310
|
+ cmd->cookie = cpu_to_le32 ( index );
|
|
311
|
+
|
|
312
|
+ /* Record cookie */
|
|
313
|
+ cookie = cmd->cookie;
|
257
|
314
|
|
258
|
315
|
/* Post command descriptor */
|
|
316
|
+ DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
|
|
317
|
+ if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
|
|
318
|
+ DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
|
|
319
|
+ le16_to_cpu ( cmd->len ) );
|
|
320
|
+ }
|
259
|
321
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wmb();
|
260
|
322
|
writel ( tail, admin_regs + regs->tail );
|
261
|
323
|
|
|
@@ -263,36 +325,33 @@ static int intelxl_admin_command ( struct intelxl_nic *intelxl,
|
263
|
325
|
for ( i = 0 ; i < INTELXL_ADMIN_MAX_WAIT_MS ; i++ ) {
|
264
|
326
|
|
265
|
327
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/* If response is not complete, delay 1ms and retry */
|
266
|
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- if ( ! ( desc->flags & INTELXL_ADMIN_FL_DD ) ) {
|
|
328
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+ if ( ! ( cmd->flags & INTELXL_ADMIN_FL_DD ) ) {
|
267
|
329
|
mdelay ( 1 );
|
268
|
330
|
continue;
|
269
|
331
|
}
|
270
|
332
|
DBGC2 ( intelxl, "INTELXL %p admin command %#x response:\n",
|
271
|
333
|
intelxl, index );
|
272
|
|
- DBGC2_HDA ( intelxl, virt_to_phys ( desc ), desc,
|
273
|
|
- sizeof ( *desc ) );
|
|
334
|
+ DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd,
|
|
335
|
+ sizeof ( *cmd ) );
|
274
|
336
|
|
275
|
337
|
/* Check for cookie mismatch */
|
276
|
|
- if ( desc->cookie != cmd->cookie ) {
|
|
338
|
+ if ( cmd->cookie != cookie ) {
|
277
|
339
|
DBGC ( intelxl, "INTELXL %p admin command %#x bad "
|
278
|
340
|
"cookie %#x\n", intelxl, index,
|
279
|
|
- le32_to_cpu ( desc->cookie ) );
|
|
341
|
+ le32_to_cpu ( cmd->cookie ) );
|
280
|
342
|
rc = -EPROTO;
|
281
|
343
|
goto err;
|
282
|
344
|
}
|
283
|
345
|
|
284
|
346
|
/* Check for errors */
|
285
|
|
- if ( desc->ret != 0 ) {
|
|
347
|
+ if ( cmd->ret != 0 ) {
|
286
|
348
|
DBGC ( intelxl, "INTELXL %p admin command %#x error "
|
287
|
349
|
"%d\n", intelxl, index,
|
288
|
|
- le16_to_cpu ( desc->ret ) );
|
|
350
|
+ le16_to_cpu ( cmd->ret ) );
|
289
|
351
|
rc = -EIO;
|
290
|
352
|
goto err;
|
291
|
353
|
}
|
292
|
354
|
|
293
|
|
- /* Copy response back to command descriptor */
|
294
|
|
- memcpy ( cmd, desc, sizeof ( *cmd ) );
|
295
|
|
-
|
296
|
355
|
/* Success */
|
297
|
356
|
return 0;
|
298
|
357
|
}
|
|
@@ -301,8 +360,7 @@ static int intelxl_admin_command ( struct intelxl_nic *intelxl,
|
301
|
360
|
DBGC ( intelxl, "INTELXL %p timed out waiting for admin command %#x:\n",
|
302
|
361
|
intelxl, index );
|
303
|
362
|
err:
|
304
|
|
- DBGC_HDA ( intelxl, virt_to_phys ( desc ), cmd, sizeof ( *cmd ) );
|
305
|
|
- DBGC_HDA ( intelxl, virt_to_phys ( desc ), desc, sizeof ( *desc ) );
|
|
363
|
+ DBGC_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
|
306
|
364
|
return rc;
|
307
|
365
|
}
|
308
|
366
|
|
|
@@ -313,17 +371,18 @@ static int intelxl_admin_command ( struct intelxl_nic *intelxl,
|
313
|
371
|
* @ret rc Return status code
|
314
|
372
|
*/
|
315
|
373
|
static int intelxl_admin_version ( struct intelxl_nic *intelxl ) {
|
316
|
|
- struct intelxl_admin_descriptor cmd;
|
317
|
|
- struct intelxl_admin_version_params *version = &cmd.params.version;
|
|
374
|
+ struct intelxl_admin_descriptor *cmd;
|
|
375
|
+ struct intelxl_admin_version_params *version;
|
318
|
376
|
unsigned int api;
|
319
|
377
|
int rc;
|
320
|
378
|
|
321
|
379
|
/* Populate descriptor */
|
322
|
|
- memset ( &cmd, 0, sizeof ( cmd ) );
|
323
|
|
- cmd.opcode = cpu_to_le16 ( INTELXL_ADMIN_VERSION );
|
|
380
|
+ cmd = intelxl_admin_command_descriptor ( intelxl );
|
|
381
|
+ cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VERSION );
|
|
382
|
+ version = &cmd->params.version;
|
324
|
383
|
|
325
|
384
|
/* Issue command */
|
326
|
|
- if ( ( rc = intelxl_admin_command ( intelxl, &cmd ) ) != 0 )
|
|
385
|
+ if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
|
327
|
386
|
return rc;
|
328
|
387
|
api = le16_to_cpu ( version->api.major );
|
329
|
388
|
DBGC ( intelxl, "INTELXL %p firmware v%d.%d API v%d.%d\n",
|
|
@@ -348,24 +407,25 @@ static int intelxl_admin_version ( struct intelxl_nic *intelxl ) {
|
348
|
407
|
* @ret rc Return status code
|
349
|
408
|
*/
|
350
|
409
|
static int intelxl_admin_driver ( struct intelxl_nic *intelxl ) {
|
351
|
|
- struct intelxl_admin_descriptor cmd;
|
352
|
|
- struct intelxl_admin_driver_params *driver = &cmd.params.driver;
|
353
|
|
- struct intelxl_admin_driver_buffer *buf =
|
354
|
|
- &intelxl->command.buffer->driver;
|
|
410
|
+ struct intelxl_admin_descriptor *cmd;
|
|
411
|
+ struct intelxl_admin_driver_params *driver;
|
|
412
|
+ union intelxl_admin_buffer *buf;
|
355
|
413
|
int rc;
|
356
|
414
|
|
357
|
415
|
/* Populate descriptor */
|
358
|
|
- memset ( &cmd, 0, sizeof ( cmd ) );
|
359
|
|
- cmd.opcode = cpu_to_le16 ( INTELXL_ADMIN_DRIVER );
|
360
|
|
- cmd.flags = cpu_to_le16 ( INTELXL_ADMIN_FL_RD | INTELXL_ADMIN_FL_BUF );
|
361
|
|
- cmd.len = cpu_to_le16 ( sizeof ( *buf ) );
|
|
416
|
+ cmd = intelxl_admin_command_descriptor ( intelxl );
|
|
417
|
+ cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_DRIVER );
|
|
418
|
+ cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_RD | INTELXL_ADMIN_FL_BUF );
|
|
419
|
+ cmd->len = cpu_to_le16 ( sizeof ( buf->driver ) );
|
|
420
|
+ driver = &cmd->params.driver;
|
362
|
421
|
driver->major = product_major_version;
|
363
|
422
|
driver->minor = product_minor_version;
|
364
|
|
- snprintf ( buf->name, sizeof ( buf->name ), "%s",
|
|
423
|
+ buf = intelxl_admin_command_buffer ( intelxl );
|
|
424
|
+ snprintf ( buf->driver.name, sizeof ( buf->driver.name ), "%s",
|
365
|
425
|
( product_name[0] ? product_name : product_short_name ) );
|
366
|
426
|
|
367
|
427
|
/* Issue command */
|
368
|
|
- if ( ( rc = intelxl_admin_command ( intelxl, &cmd ) ) != 0 )
|
|
428
|
+ if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
|
369
|
429
|
return rc;
|
370
|
430
|
|
371
|
431
|
return 0;
|
|
@@ -378,17 +438,18 @@ static int intelxl_admin_driver ( struct intelxl_nic *intelxl ) {
|
378
|
438
|
* @ret rc Return status code
|
379
|
439
|
*/
|
380
|
440
|
static int intelxl_admin_shutdown ( struct intelxl_nic *intelxl ) {
|
381
|
|
- struct intelxl_admin_descriptor cmd;
|
382
|
|
- struct intelxl_admin_shutdown_params *shutdown = &cmd.params.shutdown;
|
|
441
|
+ struct intelxl_admin_descriptor *cmd;
|
|
442
|
+ struct intelxl_admin_shutdown_params *shutdown;
|
383
|
443
|
int rc;
|
384
|
444
|
|
385
|
445
|
/* Populate descriptor */
|
386
|
|
- memset ( &cmd, 0, sizeof ( cmd ) );
|
387
|
|
- cmd.opcode = cpu_to_le16 ( INTELXL_ADMIN_SHUTDOWN );
|
|
446
|
+ cmd = intelxl_admin_command_descriptor ( intelxl );
|
|
447
|
+ cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SHUTDOWN );
|
|
448
|
+ shutdown = &cmd->params.shutdown;
|
388
|
449
|
shutdown->unloading = INTELXL_ADMIN_SHUTDOWN_UNLOADING;
|
389
|
450
|
|
390
|
451
|
/* Issue command */
|
391
|
|
- if ( ( rc = intelxl_admin_command ( intelxl, &cmd ) ) != 0 )
|
|
452
|
+ if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
|
392
|
453
|
return rc;
|
393
|
454
|
|
394
|
455
|
return 0;
|
|
@@ -401,36 +462,38 @@ static int intelxl_admin_shutdown ( struct intelxl_nic *intelxl ) {
|
401
|
462
|
* @ret rc Return status code
|
402
|
463
|
*/
|
403
|
464
|
static int intelxl_admin_switch ( struct intelxl_nic *intelxl ) {
|
404
|
|
- struct intelxl_admin_descriptor cmd;
|
405
|
|
- struct intelxl_admin_switch_params *sw = &cmd.params.sw;
|
406
|
|
- struct intelxl_admin_switch_buffer *buf = &intelxl->command.buffer->sw;
|
407
|
|
- struct intelxl_admin_switch_config *cfg = &buf->cfg;
|
|
465
|
+ struct intelxl_admin_descriptor *cmd;
|
|
466
|
+ struct intelxl_admin_switch_params *sw;
|
|
467
|
+ union intelxl_admin_buffer *buf;
|
408
|
468
|
int rc;
|
409
|
469
|
|
410
|
470
|
/* Populate descriptor */
|
411
|
|
- memset ( &cmd, 0, sizeof ( cmd ) );
|
412
|
|
- cmd.opcode = cpu_to_le16 ( INTELXL_ADMIN_SWITCH );
|
413
|
|
- cmd.flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
|
414
|
|
- cmd.len = cpu_to_le16 ( sizeof ( *buf ) );
|
|
471
|
+ cmd = intelxl_admin_command_descriptor ( intelxl );
|
|
472
|
+ cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SWITCH );
|
|
473
|
+ cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
|
|
474
|
+ cmd->len = cpu_to_le16 ( sizeof ( buf->sw ) );
|
|
475
|
+ sw = &cmd->params.sw;
|
|
476
|
+ buf = intelxl_admin_command_buffer ( intelxl );
|
415
|
477
|
|
416
|
478
|
/* Get each configuration in turn */
|
417
|
479
|
do {
|
418
|
480
|
/* Issue command */
|
419
|
|
- if ( ( rc = intelxl_admin_command ( intelxl, &cmd ) ) != 0 )
|
|
481
|
+ if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
|
420
|
482
|
return rc;
|
421
|
483
|
|
422
|
484
|
/* Dump raw configuration */
|
423
|
485
|
DBGC2 ( intelxl, "INTELXL %p SEID %#04x:\n",
|
424
|
|
- intelxl, le16_to_cpu ( cfg->seid ) );
|
425
|
|
- DBGC2_HDA ( intelxl, 0, cfg, sizeof ( *cfg ) );
|
|
486
|
+ intelxl, le16_to_cpu ( buf->sw.cfg.seid ) );
|
|
487
|
+ DBGC2_HDA ( intelxl, 0, &buf->sw.cfg, sizeof ( buf->sw.cfg ) );
|
426
|
488
|
|
427
|
489
|
/* Parse response */
|
428
|
|
- if ( cfg->type == INTELXL_ADMIN_SWITCH_TYPE_VSI ) {
|
429
|
|
- intelxl->vsi = le16_to_cpu ( cfg->seid );
|
|
490
|
+ if ( buf->sw.cfg.type == INTELXL_ADMIN_SWITCH_TYPE_VSI ) {
|
|
491
|
+ intelxl->vsi = le16_to_cpu ( buf->sw.cfg.seid );
|
430
|
492
|
DBGC ( intelxl, "INTELXL %p VSI %#04x uplink %#04x "
|
431
|
493
|
"downlink %#04x conn %#02x\n", intelxl,
|
432
|
|
- intelxl->vsi, le16_to_cpu ( cfg->uplink ),
|
433
|
|
- le16_to_cpu ( cfg->downlink ), cfg->connection );
|
|
494
|
+ intelxl->vsi, le16_to_cpu ( buf->sw.cfg.uplink ),
|
|
495
|
+ le16_to_cpu ( buf->sw.cfg.downlink ),
|
|
496
|
+ buf->sw.cfg.connection );
|
434
|
497
|
}
|
435
|
498
|
|
436
|
499
|
} while ( sw->next );
|
|
@@ -451,25 +514,27 @@ static int intelxl_admin_switch ( struct intelxl_nic *intelxl ) {
|
451
|
514
|
* @ret rc Return status code
|
452
|
515
|
*/
|
453
|
516
|
static int intelxl_admin_vsi ( struct intelxl_nic *intelxl ) {
|
454
|
|
- struct intelxl_admin_descriptor cmd;
|
455
|
|
- struct intelxl_admin_vsi_params *vsi = &cmd.params.vsi;
|
456
|
|
- struct intelxl_admin_vsi_buffer *buf = &intelxl->command.buffer->vsi;
|
|
517
|
+ struct intelxl_admin_descriptor *cmd;
|
|
518
|
+ struct intelxl_admin_vsi_params *vsi;
|
|
519
|
+ union intelxl_admin_buffer *buf;
|
457
|
520
|
int rc;
|
458
|
521
|
|
459
|
522
|
/* Populate descriptor */
|
460
|
|
- memset ( &cmd, 0, sizeof ( cmd ) );
|
461
|
|
- cmd.opcode = cpu_to_le16 ( INTELXL_ADMIN_VSI );
|
462
|
|
- cmd.flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
|
463
|
|
- cmd.len = cpu_to_le16 ( sizeof ( *buf ) );
|
|
523
|
+ cmd = intelxl_admin_command_descriptor ( intelxl );
|
|
524
|
+ cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VSI );
|
|
525
|
+ cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
|
|
526
|
+ cmd->len = cpu_to_le16 ( sizeof ( buf->vsi ) );
|
|
527
|
+ vsi = &cmd->params.vsi;
|
464
|
528
|
vsi->vsi = cpu_to_le16 ( intelxl->vsi );
|
|
529
|
+ buf = intelxl_admin_command_buffer ( intelxl );
|
465
|
530
|
|
466
|
531
|
/* Issue command */
|
467
|
|
- if ( ( rc = intelxl_admin_command ( intelxl, &cmd ) ) != 0 )
|
|
532
|
+ if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
|
468
|
533
|
return rc;
|
469
|
534
|
|
470
|
535
|
/* Parse response */
|
471
|
|
- intelxl->queue = le16_to_cpu ( buf->queue[0] );
|
472
|
|
- intelxl->qset = le16_to_cpu ( buf->qset[0] );
|
|
536
|
+ intelxl->queue = le16_to_cpu ( buf->vsi.queue[0] );
|
|
537
|
+ intelxl->qset = le16_to_cpu ( buf->vsi.qset[0] );
|
473
|
538
|
DBGC ( intelxl, "INTELXL %p VSI %#04x queue %#04x qset %#04x\n",
|
474
|
539
|
intelxl, intelxl->vsi, intelxl->queue, intelxl->qset );
|
475
|
540
|
|
|
@@ -483,24 +548,25 @@ static int intelxl_admin_vsi ( struct intelxl_nic *intelxl ) {
|
483
|
548
|
* @ret rc Return status code
|
484
|
549
|
*/
|
485
|
550
|
static int intelxl_admin_promisc ( struct intelxl_nic *intelxl ) {
|
486
|
|
- struct intelxl_admin_descriptor cmd;
|
487
|
|
- struct intelxl_admin_promisc_params *promisc = &cmd.params.promisc;
|
|
551
|
+ struct intelxl_admin_descriptor *cmd;
|
|
552
|
+ struct intelxl_admin_promisc_params *promisc;
|
488
|
553
|
uint16_t flags;
|
489
|
554
|
int rc;
|
490
|
555
|
|
491
|
556
|
/* Populate descriptor */
|
492
|
|
- memset ( &cmd, 0, sizeof ( cmd ) );
|
493
|
|
- cmd.opcode = cpu_to_le16 ( INTELXL_ADMIN_PROMISC );
|
|
557
|
+ cmd = intelxl_admin_command_descriptor ( intelxl );
|
|
558
|
+ cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_PROMISC );
|
494
|
559
|
flags = ( INTELXL_ADMIN_PROMISC_FL_UNICAST |
|
495
|
560
|
INTELXL_ADMIN_PROMISC_FL_MULTICAST |
|
496
|
561
|
INTELXL_ADMIN_PROMISC_FL_BROADCAST |
|
497
|
562
|
INTELXL_ADMIN_PROMISC_FL_VLAN );
|
|
563
|
+ promisc = &cmd->params.promisc;
|
498
|
564
|
promisc->flags = cpu_to_le16 ( flags );
|
499
|
565
|
promisc->valid = cpu_to_le16 ( flags );
|
500
|
566
|
promisc->vsi = cpu_to_le16 ( intelxl->vsi );
|
501
|
567
|
|
502
|
568
|
/* Issue command */
|
503
|
|
- if ( ( rc = intelxl_admin_command ( intelxl, &cmd ) ) != 0 )
|
|
569
|
+ if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
|
504
|
570
|
return rc;
|
505
|
571
|
|
506
|
572
|
return 0;
|
|
@@ -513,18 +579,19 @@ static int intelxl_admin_promisc ( struct intelxl_nic *intelxl ) {
|
513
|
579
|
* @ret rc Return status code
|
514
|
580
|
*/
|
515
|
581
|
static int intelxl_admin_autoneg ( struct intelxl_nic *intelxl ) {
|
516
|
|
- struct intelxl_admin_descriptor cmd;
|
517
|
|
- struct intelxl_admin_autoneg_params *autoneg = &cmd.params.autoneg;
|
|
582
|
+ struct intelxl_admin_descriptor *cmd;
|
|
583
|
+ struct intelxl_admin_autoneg_params *autoneg;
|
518
|
584
|
int rc;
|
519
|
585
|
|
520
|
586
|
/* Populate descriptor */
|
521
|
|
- memset ( &cmd, 0, sizeof ( cmd ) );
|
522
|
|
- cmd.opcode = cpu_to_le16 ( INTELXL_ADMIN_AUTONEG );
|
|
587
|
+ cmd = intelxl_admin_command_descriptor ( intelxl );
|
|
588
|
+ cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_AUTONEG );
|
|
589
|
+ autoneg = &cmd->params.autoneg;
|
523
|
590
|
autoneg->flags = ( INTELXL_ADMIN_AUTONEG_FL_RESTART |
|
524
|
591
|
INTELXL_ADMIN_AUTONEG_FL_ENABLE );
|
525
|
592
|
|
526
|
593
|
/* Issue command */
|
527
|
|
- if ( ( rc = intelxl_admin_command ( intelxl, &cmd ) ) != 0 )
|
|
594
|
+ if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
|
528
|
595
|
return rc;
|
529
|
596
|
|
530
|
597
|
return 0;
|
|
@@ -538,17 +605,18 @@ static int intelxl_admin_autoneg ( struct intelxl_nic *intelxl ) {
|
538
|
605
|
*/
|
539
|
606
|
static int intelxl_admin_link ( struct net_device *netdev ) {
|
540
|
607
|
struct intelxl_nic *intelxl = netdev->priv;
|
541
|
|
- struct intelxl_admin_descriptor cmd;
|
542
|
|
- struct intelxl_admin_link_params *link = &cmd.params.link;
|
|
608
|
+ struct intelxl_admin_descriptor *cmd;
|
|
609
|
+ struct intelxl_admin_link_params *link;
|
543
|
610
|
int rc;
|
544
|
611
|
|
545
|
612
|
/* Populate descriptor */
|
546
|
|
- memset ( &cmd, 0, sizeof ( cmd ) );
|
547
|
|
- cmd.opcode = cpu_to_le16 ( INTELXL_ADMIN_LINK );
|
|
613
|
+ cmd = intelxl_admin_command_descriptor ( intelxl );
|
|
614
|
+ cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_LINK );
|
|
615
|
+ link = &cmd->params.link;
|
548
|
616
|
link->notify = INTELXL_ADMIN_LINK_NOTIFY;
|
549
|
617
|
|
550
|
618
|
/* Issue command */
|
551
|
|
- if ( ( rc = intelxl_admin_command ( intelxl, &cmd ) ) != 0 )
|
|
619
|
+ if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
|
552
|
620
|
return rc;
|
553
|
621
|
DBGC ( intelxl, "INTELXL %p PHY %#02x speed %#02x status %#02x\n",
|
554
|
622
|
intelxl, link->phy, link->speed, link->status );
|
|
@@ -577,6 +645,7 @@ static void intelxl_refill_admin ( struct intelxl_nic *intelxl ) {
|
577
|
645
|
/* Update tail pointer */
|
578
|
646
|
tail = ( ( admin->index + INTELXL_ADMIN_NUM_DESC - 1 ) %
|
579
|
647
|
INTELXL_ADMIN_NUM_DESC );
|
|
648
|
+ wmb();
|
580
|
649
|
writel ( tail, admin_regs + regs->tail );
|
581
|
650
|
}
|
582
|
651
|
|
|
@@ -588,39 +657,42 @@ static void intelxl_refill_admin ( struct intelxl_nic *intelxl ) {
|
588
|
657
|
static void intelxl_poll_admin ( struct net_device *netdev ) {
|
589
|
658
|
struct intelxl_nic *intelxl = netdev->priv;
|
590
|
659
|
struct intelxl_admin *admin = &intelxl->event;
|
591
|
|
- struct intelxl_admin_descriptor *desc;
|
|
660
|
+ struct intelxl_admin_descriptor *evt;
|
|
661
|
+ union intelxl_admin_buffer *buf;
|
592
|
662
|
|
593
|
663
|
/* Check for events */
|
594
|
664
|
while ( 1 ) {
|
595
|
665
|
|
596
|
|
- /* Get next event descriptor */
|
597
|
|
- desc = &admin->desc[admin->index % INTELXL_ADMIN_NUM_DESC];
|
|
666
|
+ /* Get next event descriptor and data buffer */
|
|
667
|
+ evt = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
|
|
668
|
+ buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
|
598
|
669
|
|
599
|
670
|
/* Stop if descriptor is not yet completed */
|
600
|
|
- if ( ! ( desc->flags & INTELXL_ADMIN_FL_DD ) )
|
|
671
|
+ if ( ! ( evt->flags & INTELXL_ADMIN_FL_DD ) )
|
601
|
672
|
return;
|
602
|
673
|
DBGC2 ( intelxl, "INTELXL %p admin event %#x:\n",
|
603
|
674
|
intelxl, admin->index );
|
604
|
|
- DBGC2_HDA ( intelxl, virt_to_phys ( desc ), desc,
|
605
|
|
- sizeof ( *desc ) );
|
|
675
|
+ DBGC2_HDA ( intelxl, virt_to_phys ( evt ), evt,
|
|
676
|
+ sizeof ( *evt ) );
|
|
677
|
+ if ( evt->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
|
|
678
|
+ DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
|
|
679
|
+ le16_to_cpu ( evt->len ) );
|
|
680
|
+ }
|
606
|
681
|
|
607
|
682
|
/* Handle event */
|
608
|
|
- switch ( desc->opcode ) {
|
|
683
|
+ switch ( evt->opcode ) {
|
609
|
684
|
case cpu_to_le16 ( INTELXL_ADMIN_LINK ):
|
610
|
685
|
intelxl_admin_link ( netdev );
|
611
|
686
|
break;
|
612
|
687
|
default:
|
613
|
688
|
DBGC ( intelxl, "INTELXL %p admin event %#x "
|
614
|
689
|
"unrecognised opcode %#04x\n", intelxl,
|
615
|
|
- admin->index, le16_to_cpu ( desc->opcode ) );
|
|
690
|
+ admin->index, le16_to_cpu ( evt->opcode ) );
|
616
|
691
|
break;
|
617
|
692
|
}
|
618
|
693
|
|
619
|
|
- /* Clear event completion flag */
|
620
|
|
- desc->flags = 0;
|
621
|
|
- wmb();
|
622
|
|
-
|
623
|
|
- /* Update index and refill queue */
|
|
694
|
+ /* Reset descriptor and refill queue */
|
|
695
|
+ intelxl_admin_event_init ( intelxl, admin->index );
|
624
|
696
|
admin->index++;
|
625
|
697
|
intelxl_refill_admin ( intelxl );
|
626
|
698
|
}
|
|
@@ -633,6 +705,7 @@ static void intelxl_poll_admin ( struct net_device *netdev ) {
|
633
|
705
|
* @ret rc Return status code
|
634
|
706
|
*/
|
635
|
707
|
static int intelxl_open_admin ( struct intelxl_nic *intelxl ) {
|
|
708
|
+ unsigned int i;
|
636
|
709
|
int rc;
|
637
|
710
|
|
638
|
711
|
/* Create admin event queue */
|
|
@@ -643,6 +716,10 @@ static int intelxl_open_admin ( struct intelxl_nic *intelxl ) {
|
643
|
716
|
if ( ( rc = intelxl_create_admin ( intelxl, &intelxl->command ) ) != 0 )
|
644
|
717
|
goto err_create_command;
|
645
|
718
|
|
|
719
|
+ /* Initialise all admin event queue descriptors */
|
|
720
|
+ for ( i = 0 ; i < INTELXL_ADMIN_NUM_DESC ; i++ )
|
|
721
|
+ intelxl_admin_event_init ( intelxl, i );
|
|
722
|
+
|
646
|
723
|
/* Post all descriptors to event queue */
|
647
|
724
|
intelxl_refill_admin ( intelxl );
|
648
|
725
|
|