Browse Source

[phantom] Add support for NetXen Phantom NICs

tags/v0.9.4
Michael Brown 16 years ago
parent
commit
3ad348e55a

+ 1
- 0
src/Makefile View File

@@ -146,6 +146,7 @@ SRCDIRS		+= image
146 146
 SRCDIRS		+= drivers/bus
147 147
 SRCDIRS		+= drivers/net
148 148
 SRCDIRS		+= drivers/net/e1000
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+SRCDIRS		+= drivers/net/phantom
149 150
 SRCDIRS		+= drivers/block
150 151
 SRCDIRS		+= drivers/nvs
151 152
 SRCDIRS		+= drivers/bitbash

+ 192
- 0
src/drivers/net/phantom/nx_bitops.h View File

@@ -0,0 +1,192 @@
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+#ifndef _NX_BITOPS_H
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+#define _NX_BITOPS_H
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+
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+/*
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+ * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful, but
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+ * WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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+ * General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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+ */
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+
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+/**
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+ * @file
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+ *
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+ * NetXen bit operations
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+ *
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+ */
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+
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+/** Datatype used to represent a bit in the pseudo-structures */
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+typedef unsigned char pseudo_bit_t;
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+
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+/**
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+ * Wrapper structure for pseudo_bit_t structures
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+ *
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+ * This structure provides a wrapper around pseudo_bit_t structures.
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+ * It has the correct size, and also encapsulates type information
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+ * about the underlying pseudo_bit_t-based structure, which allows the
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+ * NX_FILL etc. macros to work without requiring explicit type
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+ * information.
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+ */
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+#define NX_PSEUDO_BIT_STRUCT( _structure )				     \
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+	union {								     \
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+		uint8_t bytes[ sizeof ( _structure ) / 8 ];		     \
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+		uint64_t qwords[ sizeof ( _structure ) / 64 ];		     \
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+		_structure *dummy[0];					     \
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+	} u;
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+
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+/** Get pseudo_bit_t structure type from wrapper structure pointer */
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+#define NX_PSEUDO_STRUCT( _ptr )					     \
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+	typeof ( *((_ptr)->u.dummy[0]) )
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+
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+/** Bit offset of a field within a pseudo_bit_t structure */
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+#define NX_BIT_OFFSET( _ptr, _field )					     \
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+	offsetof ( NX_PSEUDO_STRUCT ( _ptr ), _field )
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+
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+/** Bit width of a field within a pseudo_bit_t structure */
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+#define NX_BIT_WIDTH( _ptr, _field )					     \
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+	sizeof ( ( ( NX_PSEUDO_STRUCT ( _ptr ) * ) NULL )->_field )
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+
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+/** Qword offset of a field within a pseudo_bit_t structure */
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+#define NX_QWORD_OFFSET( _ptr, _field )					     \
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+	( NX_BIT_OFFSET ( _ptr, _field ) / 64 )
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+
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+/** Qword bit offset of a field within a pseudo_bit_t structure
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+ *
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+ * Yes, using mod-64 would work, but would lose the check for the
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+ * error of specifying a mismatched field name and qword index.
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+ */
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+#define NX_QWORD_BIT_OFFSET( _ptr, _index, _field )			     \
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+	( NX_BIT_OFFSET ( _ptr, _field ) - ( 64 * (_index) ) )
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+
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+/** Bit mask for a field within a pseudo_bit_t structure */
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+#define NX_BIT_MASK( _ptr, _field )					     \
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+	( ( ~( ( uint64_t ) 0 ) ) >>					     \
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+	  ( 64 - NX_BIT_WIDTH ( _ptr, _field ) ) )
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+
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+/*
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+ * Assemble native-endian qword from named fields and values
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+ *
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+ */
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+
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+#define NX_ASSEMBLE_1( _ptr, _index, _field, _value )			     \
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+	( ( ( uint64_t) (_value) ) <<					     \
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+	  NX_QWORD_BIT_OFFSET ( _ptr, _index, _field ) )
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+
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+#define NX_ASSEMBLE_2( _ptr, _index, _field, _value, ... )		     \
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+	( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) |		     \
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+	  NX_ASSEMBLE_1 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_ASSEMBLE_3( _ptr, _index, _field, _value, ... )		     \
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+	( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) |		     \
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+	  NX_ASSEMBLE_2 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_ASSEMBLE_4( _ptr, _index, _field, _value, ... )		     \
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+	( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) |		     \
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+	  NX_ASSEMBLE_3 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_ASSEMBLE_5( _ptr, _index, _field, _value, ... )		     \
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+	( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) |		     \
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+	  NX_ASSEMBLE_4 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_ASSEMBLE_6( _ptr, _index, _field, _value, ... )		     \
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+	( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) |		     \
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+	  NX_ASSEMBLE_5 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_ASSEMBLE_7( _ptr, _index, _field, _value, ... )		     \
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+	( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) |		     \
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+	  NX_ASSEMBLE_6 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+/*
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+ * Build native-endian (positive) qword bitmasks from named fields
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+ *
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+ */
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+
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+#define NX_MASK_1( _ptr, _index, _field )			     \
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+	( NX_BIT_MASK ( _ptr, _field ) <<			     \
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+	  NX_QWORD_BIT_OFFSET ( _ptr, _index, _field ) )
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+
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+#define NX_MASK_2( _ptr, _index, _field, ... )			     \
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+	( NX_MASK_1 ( _ptr, _index, _field ) |			     \
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+	  NX_MASK_1 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_MASK_3( _ptr, _index, _field, ... )			     \
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+	( NX_MASK_1 ( _ptr, _index, _field ) |			     \
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+	  NX_MASK_2 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_MASK_4( _ptr, _index, _field, ... )			     \
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+	( NX_MASK_1 ( _ptr, _index, _field ) |			     \
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+	  NX_MASK_3 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_MASK_5( _ptr, _index, _field, ... )			     \
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+	( NX_MASK_1 ( _ptr, _index, _field ) |			     \
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+	  NX_MASK_4 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_MASK_6( _ptr, _index, _field, ... )			     \
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+	( NX_MASK_1 ( _ptr, _index, _field ) |			     \
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+	  NX_MASK_5 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_MASK_7( _ptr, _index, _field, ... )			     \
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+	( NX_MASK_1 ( _ptr, _index, _field ) |			     \
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+	  NX_MASK_6 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+/*
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+ * Populate big-endian qwords from named fields and values
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+ *
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+ */
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+
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+#define NX_FILL( _ptr, _index, _assembled )				     \
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+	do {								     \
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+		uint64_t *__ptr = &(_ptr)->u.qwords[(_index)];		     \
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+		uint64_t __assembled = (_assembled);			     \
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+		*__ptr = cpu_to_le64 ( __assembled );			     \
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+	} while ( 0 )
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+
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+#define NX_FILL_1( _ptr, _index, ... )					     \
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+	NX_FILL ( _ptr, _index, NX_ASSEMBLE_1 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_FILL_2( _ptr, _index, ... )					     \
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+	NX_FILL ( _ptr, _index, NX_ASSEMBLE_2 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_FILL_3( _ptr, _index, ... )					     \
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+	NX_FILL ( _ptr, _index, NX_ASSEMBLE_3 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_FILL_4( _ptr, _index, ... )					     \
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+	NX_FILL ( _ptr, _index, NX_ASSEMBLE_4 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_FILL_5( _ptr, _index, ... )					     \
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+	NX_FILL ( _ptr, _index, NX_ASSEMBLE_5 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_FILL_6( _ptr, _index, ... )					     \
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+	NX_FILL ( _ptr, _index, NX_ASSEMBLE_6 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+#define NX_FILL_7( _ptr, _index, ... )					     \
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+	NX_FILL ( _ptr, _index, NX_ASSEMBLE_7 ( _ptr, _index, __VA_ARGS__ ) )
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+
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+/** Extract value of named field */
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+#define NX_GET64( _ptr, _field )					     \
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+	( {								     \
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+		unsigned int __index = NX_QWORD_OFFSET ( _ptr, _field );     \
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+		uint64_t *__ptr = &(_ptr)->u.qwords[__index];		     \
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+		uint64_t __value = le64_to_cpu ( *__ptr );		     \
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+		__value >>=						     \
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+		    NX_QWORD_BIT_OFFSET ( _ptr, __index, _field );	     \
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+		__value &= NX_BIT_MASK ( _ptr, _field );		     \
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+		__value;						     \
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+	} )
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+
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+/** Extract value of named field (for fields up to the size of a long) */
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+#define NX_GET( _ptr, _field )						     \
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+	( ( unsigned long ) NX_GET64 ( _ptr, _field ) )
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+
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+#endif /* _NX_BITOPS_H */

+ 499
- 0
src/drivers/net/phantom/nxhal_nic_interface.h View File

@@ -0,0 +1,499 @@
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+/*
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+ * Data types and structure for HAL - NIC interface.
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+ *
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+ */
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+
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+#ifndef _NXHAL_NIC_INTERFACE_H_
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+#define _NXHAL_NIC_INTERFACE_H_
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+
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+/*****************************************************************************
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+ *        Simple Types
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+ *****************************************************************************/
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+
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+typedef U32     nx_reg_addr_t;
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+
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+/*****************************************************************************
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+ *        Root crb-based firmware commands
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+ *****************************************************************************/
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+
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+/* CRB Root Command
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+
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+   A single set of crbs is used across all physical/virtual
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+   functions for capability queries, initialization, and
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+   context creation/destruction. 
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+
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+   There are 4 CRBS:
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+       Command/Response CRB
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+       Argument1 CRB
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+       Argument2 CRB
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+       Argument3 CRB
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+       Signature CRB 
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+
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+       The cmd/rsp crb is always intiated by the host via
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+       a command code and always responded by the card with
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+       a response code. The cmd and rsp codes are disjoint.
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+       The sequence of use is always CMD, RSP, CLEAR CMD.
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+
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+       The arguments are for passing in command specific
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+       and response specific parameters/data. 
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+
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+       The signature is composed of a magic value, the
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+       pci function id, and a command sequence id:
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+          [7:0]  = pci function
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+         [15:8]  = version
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+         [31:16] = magic of 0xcafe
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+
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+       The pci function allows the card to take correct
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+       action for the given particular commands. 
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+       The firmware will attempt to detect
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+       an errant driver that has died while holding  
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+       the root crb hardware lock. Such an error condition
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+       shows up as the cmd/rsp crb stuck in a non-clear state.
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+
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+   Interface Sequence:
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+     Host always makes requests and firmware always responds.
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+     Note that data field is always set prior to command field.
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+
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+     [READ]             CMD/RSP CRB      ARGUMENT FIELD
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+     Host grab lock
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+     Host  ->           CMD              optional parameter
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+     FW   <-  (Good)    RSP-OK           DATA
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+     FW   <-  (Fail)    RSP-FAIL         optional failure code
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+     Host ->            CLEAR
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+     Host release lock
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+
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+     [WRITE]            CMD/RSP CRB      ARGUMENT FIELD
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+     Host grab lock
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+     Host  ->           CMD              DATA
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+     FW   <-  (Good)    RSP-OK           optional write status
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+     FW   <-  (Write)   RSP-FAIL         optional failure code
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+     Host ->            CLEAR
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+     Host release lock
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+
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+*/
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+
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+
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+/*****************************************************************************
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+ *        CMD/RSP
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+ *****************************************************************************/
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+
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+#define NX_CDRP_SIGNATURE_TO_PCIFN(sign)    ((sign) & 0xff)
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+#define NX_CDRP_SIGNATURE_TO_VERSION(sign)  (((sign)>>8) & 0xff)
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+#define NX_CDRP_SIGNATURE_TO_MAGIC(sign)    (((sign)>>16) & 0xffff)
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+#define NX_CDRP_SIGNATURE_VALID(sign)       \
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+	( NX_CDRP_SIGNATURE_TO_MAGIC(sign) == 0xcafe && \
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+	  NX_CDRP_SIGNATURE_TO_PCIFN(sign) < 8)
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+#define NX_CDRP_SIGNATURE_MAKE(pcifn,version) \
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+	( ((pcifn) & 0xff) |		      \
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+	  (((version) & 0xff) << 8) |	      \
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+	  (0xcafe << 16) )
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+
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+#define	NX_CDRP_CLEAR                       0x00000000
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+#define	NX_CDRP_CMD_BIT                     0x80000000
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+
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+/* All responses must have the NX_CDRP_CMD_BIT cleared
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+ * in the crb NX_CDRP_CRB_OFFSET. */
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+#define NX_CDRP_FORM_RSP(rsp)              (rsp)
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+#define NX_CDRP_IS_RSP(rsp)                (((rsp) & NX_CDRP_CMD_BIT) == 0)
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+
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+#define	NX_CDRP_RSP_OK                      0x00000001
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+#define	NX_CDRP_RSP_FAIL                    0x00000002
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+#define	NX_CDRP_RSP_TIMEOUT                 0x00000003
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+
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+/* All commands must have the NX_CDRP_CMD_BIT set in
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+ * the crb NX_CDRP_CRB_OFFSET.
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+ * The macros below do not have it explicitly set to
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+ * allow their use in lookup tables */
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+#define NX_CDRP_FORM_CMD(cmd)               (NX_CDRP_CMD_BIT | (cmd))
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+#define NX_CDRP_IS_CMD(cmd)                 (((cmd) & NX_CDRP_CMD_BIT) != 0)
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+
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+/* [CMD] Capability Vector [RSP] Capability Vector */
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+#define NX_CDRP_CMD_SUBMIT_CAPABILITIES     0x00000001
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+
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+/* [CMD] - [RSP] Query Value */
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+#define	NX_CDRP_CMD_READ_MAX_RDS_PER_CTX    0x00000002
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+
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+/* [CMD] - [RSP] Query Value */
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+#define	NX_CDRP_CMD_READ_MAX_SDS_PER_CTX    0x00000003
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+
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+/* [CMD] - [RSP] Query Value */
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+#define	NX_CDRP_CMD_READ_MAX_RULES_PER_CTX  0x00000004
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+
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+/* [CMD] - [RSP] Query Value */
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+#define	NX_CDRP_CMD_READ_MAX_RX_CTX         0x00000005
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+
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+/* [CMD] - [RSP] Query Value */
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+#define	NX_CDRP_CMD_READ_MAX_TX_CTX         0x00000006
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+
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+/* [CMD] Rx Config DMA Addr [RSP] rcode */
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+#define	NX_CDRP_CMD_CREATE_RX_CTX           0x00000007
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+
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+/* [CMD] Rx Context Handle, Reset Kind [RSP] rcode */
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+#define	NX_CDRP_CMD_DESTROY_RX_CTX          0x00000008
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+
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+/* [CMD] Tx Config DMA Addr [RSP] rcode */
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+#define	NX_CDRP_CMD_CREATE_TX_CTX           0x00000009
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+
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+/* [CMD] Tx Context Handle, Reset Kind [RSP] rcode */
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+#define	NX_CDRP_CMD_DESTROY_TX_CTX          0x0000000a
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+
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+/* [CMD] Stat setup dma addr - [RSP] Handle, rcode */
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+#define NX_CDRP_CMD_SETUP_STATISTICS        0x0000000e
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+
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+/* [CMD] Handle - [RSP] rcode */
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+#define NX_CDRP_CMD_GET_STATISTICS          0x0000000f
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+
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+/* [CMD] Handle - [RSP] rcode */
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+#define NX_CDRP_CMD_DELETE_STATISTICS       0x00000010
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+
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+#define NX_CDRP_CMD_MAX                     0x00000011
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+
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+/*****************************************************************************
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+ *        Capabilities
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+ *****************************************************************************/
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+
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+#define NX_CAP_BIT(class, bit)              (1 << bit)
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+
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+/* Class 0 (i.e. ARGS 1)
158
+ */
159
+#define NX_CAP0_LEGACY_CONTEXT              NX_CAP_BIT(0, 0)
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+#define NX_CAP0_MULTI_CONTEXT               NX_CAP_BIT(0, 1)
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+#define NX_CAP0_LEGACY_MN                   NX_CAP_BIT(0, 2)
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+#define NX_CAP0_LEGACY_MS                   NX_CAP_BIT(0, 3)
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+#define NX_CAP0_CUT_THROUGH                 NX_CAP_BIT(0, 4)
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+#define NX_CAP0_LRO                         NX_CAP_BIT(0, 5)
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+#define NX_CAP0_LSO                         NX_CAP_BIT(0, 6)
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+
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+/* Class 1 (i.e. ARGS 2)
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+ */
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+#define NX_CAP1_NIC                         NX_CAP_BIT(1, 0)
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+#define NX_CAP1_PXE                         NX_CAP_BIT(1, 1)
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+#define NX_CAP1_CHIMNEY                     NX_CAP_BIT(1, 2)
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+#define NX_CAP1_LSA                         NX_CAP_BIT(1, 3)
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+#define NX_CAP1_RDMA                        NX_CAP_BIT(1, 4)
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+#define NX_CAP1_ISCSI                       NX_CAP_BIT(1, 5)
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+#define NX_CAP1_FCOE                        NX_CAP_BIT(1, 6)
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+
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+/* Class 2 (i.e. ARGS 3)
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+ */
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+
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+/*****************************************************************************
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+ *        Rules
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+ *****************************************************************************/
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+
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+typedef U32 nx_rx_rule_type_t;
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+
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+#define	NX_RX_RULETYPE_DEFAULT              0
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+#define	NX_RX_RULETYPE_MAC                  1
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+#define	NX_RX_RULETYPE_MAC_VLAN             2
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+#define	NX_RX_RULETYPE_MAC_RSS              3
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+#define	NX_RX_RULETYPE_MAC_VLAN_RSS         4
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+#define	NX_RX_RULETYPE_MAX                  5
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+
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+typedef U32 nx_rx_rule_cmd_t;
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+
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+#define	NX_RX_RULECMD_ADD                   0
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+#define	NX_RX_RULECMD_REMOVE                1
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+#define	NX_RX_RULECMD_MAX                   2
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+
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+typedef struct nx_rx_rule_arg_s {
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+	union {
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+		struct {
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+			char mac[6];
203
+		} m;
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+		struct {
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+			char mac[6];
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+			char vlan;
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+		} mv;
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+		struct {
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+			char mac[6];
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+		} mr;
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+		struct {
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+			char mac[6];
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+			char vlan;
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+		} mvr;
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+	};
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+	/* will be union of all the different args for rules */
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+	U64 data;
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+} nx_rx_rule_arg_t;
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+
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+typedef struct nx_rx_rule_s {
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+	U32 id;
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+	U32 active;
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+	nx_rx_rule_arg_t arg;
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+	nx_rx_rule_type_t type;
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+} nx_rx_rule_t;
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+
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+/* MSG - REQUIRES TX CONTEXT */
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+
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+/* The rules can be added/deleted from both the
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+ *  host and card sides so rq/rsp are similar. 
231
+ */
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+typedef struct nx_hostmsg_rx_rule_s {
233
+	nx_rx_rule_cmd_t cmd;
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+	nx_rx_rule_t rule;
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+} nx_hostmsg_rx_rule_t;
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+
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+typedef struct nx_cardmsg_rx_rule_s {
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+	nx_rcode_t rcode;
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+	nx_rx_rule_cmd_t cmd;
240
+	nx_rx_rule_t rule;
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+} nx_cardmsg_rx_rule_t;
242
+
243
+
244
+/*****************************************************************************
245
+ *        Common to Rx/Tx contexts
246
+ *****************************************************************************/
247
+
248
+/*
249
+ * Context states
250
+ */
251
+
252
+typedef U32 nx_host_ctx_state_t;
253
+
254
+#define	NX_HOST_CTX_STATE_FREED             0	/* Invalid state */
255
+#define	NX_HOST_CTX_STATE_ALLOCATED         1	/* Not committed */
256
+/* The following states imply FW is aware of context */
257
+#define	NX_HOST_CTX_STATE_ACTIVE            2
258
+#define	NX_HOST_CTX_STATE_DISABLED          3
259
+#define	NX_HOST_CTX_STATE_QUIESCED          4
260
+#define	NX_HOST_CTX_STATE_MAX               5
261
+
262
+/*
263
+ * Interrupt mask crb use must be set identically on the Tx 
264
+ * and Rx context configs across a pci function 
265
+ */
266
+
267
+/* Rx and Tx have unique interrupt/crb */
268
+#define NX_HOST_INT_CRB_MODE_UNIQUE         0
269
+/* Rx and Tx share a common interrupt/crb */
270
+#define NX_HOST_INT_CRB_MODE_SHARED         1	/* <= LEGACY */
271
+/* Rx does not use a crb */
272
+#define NX_HOST_INT_CRB_MODE_NORX           2
273
+/* Tx does not use a crb */
274
+#define NX_HOST_INT_CRB_MODE_NOTX           3
275
+/* Neither Rx nor Tx use a crb */
276
+#define NX_HOST_INT_CRB_MODE_NORXTX         4
277
+
278
+/*
279
+ * Destroy Rx/Tx
280
+ */
281
+
282
+#define NX_DESTROY_CTX_RESET                0
283
+#define NX_DESTROY_CTX_D3_RESET             1
284
+#define NX_DESTROY_CTX_MAX                  2
285
+
286
+
287
+/*****************************************************************************
288
+ *        Tx
289
+ *****************************************************************************/
290
+
291
+/*
292
+ * Components of the host-request for Tx context creation.
293
+ * CRB - DOES NOT REQUIRE Rx/TX CONTEXT 
294
+ */
295
+
296
+typedef struct nx_hostrq_cds_ring_s {
297
+	U64 host_phys_addr;	/* Ring base addr */
298
+	U32 ring_size;		/* Ring entries */
299
+	U32 rsvd;		/* Padding */
300
+} nx_hostrq_cds_ring_t;
301
+
302
+typedef struct nx_hostrq_tx_ctx_s {
303
+	U64 host_rsp_dma_addr;	/* Response dma'd here */
304
+	U64 cmd_cons_dma_addr;	/*  */
305
+	U64 dummy_dma_addr;	/*  */
306
+	U32 capabilities[4];	/* Flag bit vector */
307
+	U32 host_int_crb_mode;	/* Interrupt crb usage */
308
+	U32 rsvd1;		/* Padding */
309
+	U16 rsvd2;		/* Padding */
310
+	U16 interrupt_ctl;
311
+	U16 msi_index;
312
+	U16 rsvd3;		/* Padding */
313
+	nx_hostrq_cds_ring_t cds_ring;	/* Desc of cds ring */
314
+	U8  reserved[128];	/* future expansion */
315
+} nx_hostrq_tx_ctx_t;
316
+
317
+typedef struct nx_cardrsp_cds_ring_s {
318
+	U32 host_producer_crb;	/* Crb to use */
319
+	U32 interrupt_crb;	/* Crb to use */
320
+} nx_cardrsp_cds_ring_t;
321
+
322
+typedef struct nx_cardrsp_tx_ctx_s {
323
+	U32 host_ctx_state;	/* Starting state */
324
+	U16 context_id;		/* Handle for context */
325
+	U8  phys_port;		/* Physical id of port */
326
+	U8  virt_port;		/* Virtual/Logical id of port */
327
+	nx_cardrsp_cds_ring_t cds_ring;	/* Card cds settings */
328
+	U8  reserved[128];	/* future expansion */
329
+} nx_cardrsp_tx_ctx_t;
330
+
331
+#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) 			\
332
+		( sizeof(HOSTRQ_TX))
333
+
334
+#define SIZEOF_CARDRSP_TX(CARDRSP_TX) 			\
335
+		( sizeof(CARDRSP_TX)) 
336
+
337
+/*****************************************************************************
338
+ *        Rx
339
+ *****************************************************************************/
340
+
341
+/*
342
+ * RDS ring mapping to producer crbs
343
+ */
344
+
345
+/* Each ring has a unique crb */
346
+#define NX_HOST_RDS_CRB_MODE_UNIQUE    0	/* <= LEGACY */
347
+
348
+/* All configured RDS Rings share common crb:
349
+     1 Ring  - same as unique
350
+     2 Rings - 16, 16
351
+     3 Rings - 10, 10, 10 */
352
+#define NX_HOST_RDS_CRB_MODE_SHARED    1
353
+
354
+/* Bit usage is specified per-ring using the
355
+   ring's size. Sum of bit lengths must be <= 32. 
356
+   Packing is [Ring N] ... [Ring 1][Ring 0] */
357
+#define NX_HOST_RDS_CRB_MODE_CUSTOM    2
358
+#define NX_HOST_RDS_CRB_MODE_MAX       3
359
+
360
+
361
+/*
362
+ * RDS Ting Types 
363
+ */
364
+
365
+#define NX_RDS_RING_TYPE_NORMAL       0
366
+#define NX_RDS_RING_TYPE_JUMBO        1
367
+#define NX_RDS_RING_TYPE_LRO          2
368
+#define NX_RDS_RING_TYPE_MAX          3
369
+
370
+/*
371
+ * Components of the host-request for Rx context creation.
372
+ * CRB - DOES NOT REQUIRE Rx/TX CONTEXT 
373
+ */
374
+
375
+typedef struct nx_hostrq_sds_ring_s {
376
+	U64 host_phys_addr;	/* Ring base addr */
377
+	U32 ring_size;		/* Ring entries */
378
+	U16 msi_index;
379
+	U16 rsvd;		/* Padding */
380
+} nx_hostrq_sds_ring_t;
381
+
382
+typedef struct nx_hostrq_rds_ring_s {
383
+	U64 host_phys_addr;	/* Ring base addr */
384
+	U64 buff_size;		/* Packet buffer size */
385
+	U32 ring_size;		/* Ring entries */
386
+	U32 ring_kind;		/* Class of ring */
387
+} nx_hostrq_rds_ring_t;
388
+
389
+typedef struct nx_hostrq_rx_ctx_s {
390
+	U64 host_rsp_dma_addr;	/* Response dma'd here */
391
+	U32 capabilities[4];	/* Flag bit vector */
392
+	U32 host_int_crb_mode;	/* Interrupt crb usage */
393
+	U32 host_rds_crb_mode;	/* RDS crb usage */
394
+	/* These ring offsets are relative to data[0] below */
395
+	U32 rds_ring_offset;	/* Offset to RDS config */
396
+	U32 sds_ring_offset;	/* Offset to SDS config */
397
+	U16 num_rds_rings;	/* Count of RDS rings */
398
+	U16 num_sds_rings;	/* Count of SDS rings */
399
+	U16 rsvd1;		/* Padding */
400
+	U16 rsvd2;		/* Padding */
401
+	U8  reserved[128]; 	/* reserve space for future expansion*/
402
+	/* MUST BE 64-bit aligned.
403
+	   The following is packed:
404
+	   - N hostrq_rds_rings
405
+	   - N hostrq_sds_rings */
406
+	char data[0];
407
+} nx_hostrq_rx_ctx_t;
408
+
409
+typedef struct nx_cardrsp_rds_ring_s {
410
+	U32 host_producer_crb;	/* Crb to use */
411
+	U32 rsvd1;		/* Padding */
412
+} nx_cardrsp_rds_ring_t;
413
+
414
+typedef struct nx_cardrsp_sds_ring_s {
415
+	U32 host_consumer_crb;	/* Crb to use */
416
+	U32 interrupt_crb;	/* Crb to use */
417
+} nx_cardrsp_sds_ring_t;
418
+
419
+typedef struct nx_cardrsp_rx_ctx_s {
420
+	/* These ring offsets are relative to data[0] below */
421
+	U32 rds_ring_offset;	/* Offset to RDS config */
422
+	U32 sds_ring_offset;	/* Offset to SDS config */
423
+	U32 host_ctx_state;	/* Starting State */
424
+	U32 num_fn_per_port;	/* How many PCI fn share the port */
425
+	U16 num_rds_rings;	/* Count of RDS rings */
426
+	U16 num_sds_rings;	/* Count of SDS rings */
427
+	U16 context_id;		/* Handle for context */
428
+	U8  phys_port;		/* Physical id of port */
429
+	U8  virt_port;		/* Virtual/Logical id of port */
430
+	U8  reserved[128];	/* save space for future expansion */
431
+	/*  MUST BE 64-bit aligned.
432
+	   The following is packed:
433
+	   - N cardrsp_rds_rings
434
+	   - N cardrs_sds_rings */
435
+	char data[0];
436
+} nx_cardrsp_rx_ctx_t;
437
+
438
+#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings)	\
439
+	( sizeof(HOSTRQ_RX) + 					\
440
+	(rds_rings)*(sizeof (nx_hostrq_rds_ring_t)) +		\
441
+	(sds_rings)*(sizeof (nx_hostrq_sds_ring_t)) )
442
+
443
+#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) 	\
444
+	( sizeof(CARDRSP_RX) + 					\
445
+	(rds_rings)*(sizeof (nx_cardrsp_rds_ring_t)) + 		\
446
+	(sds_rings)*(sizeof (nx_cardrsp_sds_ring_t)) )
447
+
448
+
449
+/*****************************************************************************
450
+ *        Statistics
451
+ *****************************************************************************/
452
+
453
+/*
454
+ * The model of statistics update to use 
455
+ */
456
+
457
+#define NX_STATISTICS_MODE_INVALID       0
458
+
459
+/* Permanent setup; Updates are only sent on explicit request 
460
+   (NX_CDRP_CMD_GET_STATISTICS) */
461
+#define NX_STATISTICS_MODE_PULL          1
462
+
463
+/* Permanent setup; Updates are sent automatically and on 
464
+   explicit request (NX_CDRP_CMD_GET_STATISTICS) */
465
+#define NX_STATISTICS_MODE_PUSH          2
466
+
467
+/* One time stat update. */
468
+#define NX_STATISTICS_MODE_SINGLE_SHOT   3
469
+
470
+#define NX_STATISTICS_MODE_MAX           4
471
+
472
+/*
473
+ * What set of stats 
474
+ */
475
+#define NX_STATISTICS_TYPE_INVALID       0
476
+#define NX_STATISTICS_TYPE_NIC_RX_CORE   1
477
+#define NX_STATISTICS_TYPE_NIC_TX_CORE   2
478
+#define NX_STATISTICS_TYPE_NIC_RX_ALL    3
479
+#define NX_STATISTICS_TYPE_NIC_TX_ALL    4
480
+#define NX_STATISTICS_TYPE_MAX           5
481
+
482
+
483
+/*
484
+ * Request to setup statistics gathering.
485
+ * CRB - DOES NOT REQUIRE Rx/TX CONTEXT 
486
+ */
487
+
488
+typedef struct nx_hostrq_stat_setup_s {
489
+	U64 host_stat_buffer;	/* Where to dma stats */
490
+	U32 host_stat_size;	/* Size of stat buffer */
491
+	U16 context_id;		/* Which context */
492
+	U16 stat_type;		/* What class of stats */
493
+	U16 stat_mode;		/* When to update */
494
+	U16 stat_interval;	/* Frequency of update */
495
+} nx_hostrq_stat_setup_t;
496
+
497
+
498
+
499
+#endif /* _NXHAL_NIC_INTERFACE_H_ */

+ 1941
- 0
src/drivers/net/phantom/phantom.c
File diff suppressed because it is too large
View File


+ 252
- 0
src/drivers/net/phantom/phantom.h View File

@@ -0,0 +1,252 @@
1
+#ifndef _PHANTOM_H
2
+#define _PHANTOM_H
3
+
4
+/**
5
+ * @file
6
+ *
7
+ * NetXen Phantom NICs
8
+ *
9
+ */
10
+
11
+#include <stdint.h>
12
+
13
+/* Drag in hardware definitions */
14
+#include "nx_bitops.h"
15
+#include "phantom_hw.h"
16
+struct phantom_rds { NX_PSEUDO_BIT_STRUCT ( struct phantom_rds_pb ) };
17
+struct phantom_sds { NX_PSEUDO_BIT_STRUCT ( struct phantom_sds_pb ) };
18
+union phantom_cds { NX_PSEUDO_BIT_STRUCT ( union phantom_cds_pb ) };
19
+
20
+/* Drag in firmware interface definitions */
21
+typedef uint8_t U8;
22
+typedef uint16_t U16;
23
+typedef uint32_t U32;
24
+typedef uint64_t U64;
25
+typedef uint32_t nx_rcode_t;
26
+#define NXHAL_VERSION 1
27
+#include "nxhal_nic_interface.h"
28
+
29
+/** SPI controller maximum block size */
30
+#define UNM_SPI_BLKSIZE 4
31
+
32
+/** DMA buffer alignment */
33
+#define UNM_DMA_BUFFER_ALIGN 16
34
+
35
+/** Mark structure as DMA-aligned */
36
+#define __unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) ))
37
+
38
+/** Dummy DMA buffer size */
39
+#define UNM_DUMMY_DMA_SIZE 1024
40
+
41
+/******************************************************************************
42
+ *
43
+ * Register definitions
44
+ *
45
+ */
46
+
47
+#define UNM_128M_CRB_WINDOW		0x6110210UL
48
+#define UNM_32M_CRB_WINDOW		0x0110210UL
49
+#define UNM_2M_CRB_WINDOW		0x0130060UL
50
+
51
+/**
52
+ * Phantom register blocks
53
+ *
54
+ * The upper address bits vary between cards.  We define an abstract
55
+ * address space in which the upper 8 bits of the 32-bit register
56
+ * address encode the register block.  This gets translated to a bus
57
+ * address by the phantom_crb_access_xxx() methods.
58
+ */
59
+enum unm_reg_blocks {
60
+	UNM_CRB_BLK_PCIE,
61
+	UNM_CRB_BLK_CAM,
62
+	UNM_CRB_BLK_ROMUSB,
63
+	UNM_CRB_BLK_TEST,
64
+};
65
+#define UNM_CRB_BASE(blk)		( (blk) << 24 )
66
+#define UNM_CRB_BLK(reg)		( (reg) >> 24 )
67
+#define UNM_CRB_OFFSET(reg)		( (reg) & 0x00ffffff )
68
+
69
+#define UNM_CRB_PCIE			UNM_CRB_BASE ( UNM_CRB_BLK_PCIE )
70
+#define UNM_PCIE_SEM2_LOCK		( UNM_CRB_PCIE + 0x1c010 )
71
+#define UNM_PCIE_SEM2_UNLOCK		( UNM_CRB_PCIE + 0x1c014 )
72
+
73
+#define UNM_CRB_CAM			UNM_CRB_BASE ( UNM_CRB_BLK_CAM )
74
+
75
+#define UNM_CAM_RAM			( UNM_CRB_CAM + 0x02000 )
76
+#define UNM_CAM_RAM_PORT_MODE		( UNM_CAM_RAM + 0x00024 )
77
+#define UNM_CAM_RAM_PORT_MODE_AUTO_NEG		4
78
+#define UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G	5
79
+#define UNM_CAM_RAM_DMESG_HEAD(n)	( UNM_CAM_RAM + 0x00030 + (n) * 0x10 )
80
+#define UNM_CAM_RAM_DMESG_LEN(n)	( UNM_CAM_RAM + 0x00034 + (n) * 0x10 )
81
+#define UNM_CAM_RAM_DMESG_TAIL(n)	( UNM_CAM_RAM + 0x00038 + (n) * 0x10 )
82
+#define UNM_CAM_RAM_DMESG_SIG(n)	( UNM_CAM_RAM + 0x0003c + (n) * 0x10 )
83
+#define UNM_CAM_RAM_DMESG_SIG_MAGIC		0xcafebabeUL
84
+#define UNM_CAM_RAM_NUM_DMESG_BUFFERS		5
85
+#define UNM_CAM_RAM_WOL_PORT_MODE	( UNM_CAM_RAM + 0x00198 )
86
+#define UNM_CAM_RAM_MAC_ADDRS		( UNM_CAM_RAM + 0x001c0 )
87
+#define UNM_CAM_RAM_COLD_BOOT		( UNM_CAM_RAM + 0x001fc )
88
+#define UNM_CAM_RAM_COLD_BOOT_MAGIC		0x55555555UL
89
+
90
+#define UNM_NIC_REG			( UNM_CRB_CAM + 0x02200 )
91
+#define UNM_NIC_REG_NX_CDRP		( UNM_NIC_REG + 0x00018 )
92
+#define UNM_NIC_REG_NX_ARG1		( UNM_NIC_REG + 0x0001c )
93
+#define UNM_NIC_REG_NX_ARG2		( UNM_NIC_REG + 0x00020 )
94
+#define UNM_NIC_REG_NX_ARG3		( UNM_NIC_REG + 0x00024 )
95
+#define UNM_NIC_REG_NX_SIGN		( UNM_NIC_REG + 0x00028 )
96
+#define UNM_NIC_REG_DUMMY_BUF_ADDR_HI	( UNM_NIC_REG + 0x0003c )
97
+#define UNM_NIC_REG_DUMMY_BUF_ADDR_LO	( UNM_NIC_REG + 0x00040 )
98
+#define UNM_NIC_REG_CMDPEG_STATE	( UNM_NIC_REG + 0x00050 )
99
+#define UNM_NIC_REG_CMDPEG_STATE_INITIALIZED	0xff01
100
+#define UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK	0xf00f
101
+#define UNM_NIC_REG_DUMMY_BUF		( UNM_NIC_REG + 0x000fc )
102
+#define UNM_NIC_REG_DUMMY_BUF_INIT		0
103
+#define UNM_NIC_REG_XG_STATE_P3		( UNM_NIC_REG + 0x00098 )
104
+#define UNM_NIC_REG_XG_STATE_P3_LINK( port, state_p3 ) \
105
+	( ( (state_p3) >> ( (port) * 4 ) ) & 0x0f )
106
+#define UNM_NIC_REG_XG_STATE_P3_LINK_UP		0x01
107
+#define UNM_NIC_REG_XG_STATE_P3_LINK_DOWN	0x02
108
+#define UNM_NIC_REG_RCVPEG_STATE	( UNM_NIC_REG + 0x0013c )
109
+#define UNM_NIC_REG_RCVPEG_STATE_INITIALIZED	0xff01
110
+#define UNM_NIC_REG_SW_INT_MASK_0	( UNM_NIC_REG + 0x001d8 )
111
+#define UNM_NIC_REG_SW_INT_MASK_1	( UNM_NIC_REG + 0x001e0 )
112
+#define UNM_NIC_REG_SW_INT_MASK_2	( UNM_NIC_REG + 0x001e4 )
113
+#define UNM_NIC_REG_SW_INT_MASK_3	( UNM_NIC_REG + 0x001e8 )
114
+
115
+#define UNM_CRB_ROMUSB			UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB )
116
+
117
+#define UNM_ROMUSB_GLB			( UNM_CRB_ROMUSB + 0x00000 )
118
+#define UNM_ROMUSB_GLB_STATUS		( UNM_ROMUSB_GLB + 0x00004 )
119
+#define UNM_ROMUSB_GLB_STATUS_ROM_DONE		( 1 << 1 )
120
+#define UNM_ROMUSB_GLB_SW_RESET		( UNM_ROMUSB_GLB + 0x00008 )
121
+#define UNM_ROMUSB_GLB_SW_RESET_MAGIC		0x0080000fUL
122
+#define UNM_ROMUSB_GLB_PEGTUNE_DONE	( UNM_ROMUSB_GLB + 0x0005c )
123
+
124
+#define UNM_ROMUSB_ROM			( UNM_CRB_ROMUSB + 0x10000 )
125
+#define UNM_ROMUSB_ROM_INSTR_OPCODE	( UNM_ROMUSB_ROM + 0x00004 )
126
+#define UNM_ROMUSB_ROM_ADDRESS		( UNM_ROMUSB_ROM + 0x00008 )
127
+#define UNM_ROMUSB_ROM_WDATA		( UNM_ROMUSB_ROM + 0x0000c )
128
+#define UNM_ROMUSB_ROM_ABYTE_CNT	( UNM_ROMUSB_ROM + 0x00010 )
129
+#define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT	( UNM_ROMUSB_ROM + 0x00014 )
130
+#define UNM_ROMUSB_ROM_RDATA		( UNM_ROMUSB_ROM + 0x00018 )
131
+
132
+#define UNM_CRB_TEST			UNM_CRB_BASE ( UNM_CRB_BLK_TEST )
133
+
134
+#define UNM_TEST_CONTROL		( UNM_CRB_TEST + 0x00090 )
135
+#define UNM_TEST_CONTROL_START			0x01
136
+#define UNM_TEST_CONTROL_ENABLE			0x02
137
+#define UNM_TEST_CONTROL_BUSY			0x08
138
+#define UNM_TEST_ADDR_LO		( UNM_CRB_TEST + 0x00094 )
139
+#define UNM_TEST_ADDR_HI		( UNM_CRB_TEST + 0x00098 )
140
+#define UNM_TEST_RDDATA_LO		( UNM_CRB_TEST + 0x000a8 )
141
+#define UNM_TEST_RDDATA_HI		( UNM_CRB_TEST + 0x000ac )
142
+
143
+/******************************************************************************
144
+ *
145
+ * Flash layout
146
+ *
147
+ */
148
+
149
+/* Board configuration */
150
+
151
+#define UNM_BRDCFG_START		0x4000
152
+
153
+struct unm_board_info {
154
+	uint32_t header_version;
155
+	uint32_t board_mfg;
156
+	uint32_t board_type;
157
+	uint32_t board_num;
158
+	uint32_t chip_id;
159
+	uint32_t chip_minor;
160
+	uint32_t chip_major;
161
+	uint32_t chip_pkg;
162
+	uint32_t chip_lot;
163
+	uint32_t port_mask;
164
+	uint32_t peg_mask;
165
+	uint32_t icache_ok;
166
+	uint32_t dcache_ok;
167
+	uint32_t casper_ok;
168
+	uint32_t mac_addr_lo_0;
169
+	uint32_t mac_addr_lo_1;
170
+	uint32_t mac_addr_lo_2;
171
+	uint32_t mac_addr_lo_3;
172
+	uint32_t mn_sync_mode;
173
+	uint32_t mn_sync_shift_cclk;
174
+	uint32_t mn_sync_shift_mclk;
175
+	uint32_t mn_wb_en;
176
+	uint32_t mn_crystal_freq;
177
+	uint32_t mn_speed;
178
+	uint32_t mn_org;
179
+	uint32_t mn_depth;
180
+	uint32_t mn_ranks_0;
181
+	uint32_t mn_ranks_1;
182
+	uint32_t mn_rd_latency_0;
183
+	uint32_t mn_rd_latency_1;
184
+	uint32_t mn_rd_latency_2;
185
+	uint32_t mn_rd_latency_3;
186
+	uint32_t mn_rd_latency_4;
187
+	uint32_t mn_rd_latency_5;
188
+	uint32_t mn_rd_latency_6;
189
+	uint32_t mn_rd_latency_7;
190
+	uint32_t mn_rd_latency_8;
191
+	uint32_t mn_dll_val[18];
192
+	uint32_t mn_mode_reg;
193
+	uint32_t mn_ext_mode_reg;
194
+	uint32_t mn_timing_0;
195
+	uint32_t mn_timing_1;
196
+	uint32_t mn_timing_2;
197
+	uint32_t sn_sync_mode;
198
+	uint32_t sn_pt_mode;
199
+	uint32_t sn_ecc_en;
200
+	uint32_t sn_wb_en;
201
+	uint32_t sn_crystal_freq;
202
+	uint32_t sn_speed;
203
+	uint32_t sn_org;
204
+	uint32_t sn_depth;
205
+	uint32_t sn_dll_tap;
206
+	uint32_t sn_rd_latency;
207
+	uint32_t mac_addr_hi_0;
208
+	uint32_t mac_addr_hi_1;
209
+	uint32_t mac_addr_hi_2;
210
+	uint32_t mac_addr_hi_3;
211
+	uint32_t magic;
212
+	uint32_t mn_rdimm;
213
+	uint32_t mn_dll_override;
214
+};
215
+
216
+#define UNM_BDINFO_VERSION		1
217
+#define UNM_BRDTYPE_P3_HMEZ		0x0022
218
+#define UNM_BRDTYPE_P3_10G_CX4_LP	0x0023
219
+#define UNM_BRDTYPE_P3_4_GB		0x0024
220
+#define UNM_BRDTYPE_P3_IMEZ		0x0025
221
+#define UNM_BRDTYPE_P3_10G_SFP_PLUS	0x0026
222
+#define UNM_BRDTYPE_P3_10000_BASE_T	0x0027
223
+#define UNM_BRDTYPE_P3_XG_LOM		0x0028
224
+#define UNM_BRDTYPE_P3_10G_CX4		0x0031
225
+#define UNM_BRDTYPE_P3_10G_XFP		0x0032
226
+#define UNM_BDINFO_MAGIC		0x12345678
227
+
228
+/* User defined region */
229
+
230
+#define UNM_USER_START			0x3e8000
231
+
232
+#define UNM_FLASH_NUM_PORTS		4
233
+#define UNM_FLASH_NUM_MAC_PER_PORT	32
234
+
235
+struct unm_user_info {
236
+	uint8_t  flash_md5[16 * 64];
237
+	uint32_t bootld_version;
238
+	uint32_t bootld_size;
239
+	uint32_t image_version;
240
+	uint32_t image_size;
241
+	uint32_t primary_status;
242
+	uint32_t secondary_present;
243
+	/* MAC address , 4 ports, 32 address per port */
244
+	uint64_t mac_addr[UNM_FLASH_NUM_PORTS * UNM_FLASH_NUM_MAC_PER_PORT];
245
+	uint32_t sub_sys_id;
246
+	uint8_t  serial_num[32];
247
+	uint32_t bios_version;
248
+	uint32_t pxe_enable;
249
+	uint32_t vlan_tag[UNM_FLASH_NUM_PORTS];
250
+};
251
+
252
+#endif /* _PHANTOM_H */

+ 181
- 0
src/drivers/net/phantom/phantom_hw.h View File

@@ -0,0 +1,181 @@
1
+#ifndef _PHANTOM_HW_H
2
+#define _PHANTOM_HW_H
3
+
4
+/*
5
+ * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
+ */
21
+
22
+/**
23
+ * @file
24
+ *
25
+ * Phantom hardware definitions
26
+ *
27
+ */
28
+
29
+/** A Phantom RX descriptor */
30
+struct phantom_rds_pb {
31
+	pseudo_bit_t handle[16];		/**< Reference handle */
32
+	pseudo_bit_t flags[16];			/**< Flags */
33
+	pseudo_bit_t length[32];		/**< Buffer length */
34
+
35
+	/* --------------------------------------------------------------- */
36
+
37
+	pseudo_bit_t dma_addr[64];		/**< Buffer DMA address */
38
+
39
+};
40
+
41
+/** A Phantom RX status descriptor */
42
+struct phantom_sds_pb {
43
+	pseudo_bit_t port[4];			/**< Port number */
44
+	pseudo_bit_t status[4];			/**< Checksum status */
45
+	pseudo_bit_t type[4];			/**< Type */
46
+	pseudo_bit_t total_length[16];		/**< Total packet length */
47
+	pseudo_bit_t handle[16];		/**< Reference handle */
48
+	pseudo_bit_t protocol[4];		/**< Protocol */
49
+	pseudo_bit_t pkt_offset[5];		/**< Offset to packet start */
50
+	pseudo_bit_t desc_cnt[3];		/**< Descriptor count */
51
+	pseudo_bit_t owner[2];			/**< Owner */
52
+	pseudo_bit_t opcode[6];			/**< Opcode */
53
+
54
+	/* --------------------------------------------------------------- */
55
+
56
+	pseudo_bit_t hash_value[32];		/**< RSS hash value */
57
+	pseudo_bit_t hash_type[8];		/**< RSS hash type */
58
+	pseudo_bit_t lro[8];			/**< LRO data */
59
+};
60
+
61
+/** Phantom RX status opcodes */
62
+enum phantom_sds_opcode {
63
+	UNM_SYN_OFFLOAD = 0x03,
64
+	UNM_RXPKT_DESC = 0x04,
65
+};
66
+
67
+/** A Phantom TX descriptor */
68
+struct phantom_tx_cds_pb {
69
+	pseudo_bit_t tcp_hdr_offset[8];		/**< TCP header offset (LSO) */
70
+        pseudo_bit_t ip_hdr_offset[8];		/**< IP header offset (LSO) */
71
+	pseudo_bit_t flags[7];			/**< Flags */
72
+	pseudo_bit_t opcode[6];			/**< Opcode */
73
+	pseudo_bit_t hw_rsvd_0[3];		/**< (Reserved) */
74
+	pseudo_bit_t num_buffers[8];		/**< Total number of buffers */
75
+	pseudo_bit_t length[24];		/**< Total length */
76
+
77
+	/* --------------------------------------------------------------- */
78
+
79
+	pseudo_bit_t buffer2_dma_addr[64];	/**< Buffer 2 DMA address */
80
+
81
+	/* --------------------------------------------------------------- */
82
+
83
+	pseudo_bit_t handle[16];		/**< Reference handle (n/a) */
84
+	pseudo_bit_t port_mss[16];		/**< TCP MSS (LSO) */
85
+	pseudo_bit_t port[4];			/**< Port */
86
+	pseudo_bit_t context_id[4];		/**< Context ID */
87
+	pseudo_bit_t total_hdr_length[8];	/**< MAC+IP+TCP header (LSO) */
88
+	pseudo_bit_t conn_id[16];		/**< IPSec connection ID */
89
+
90
+	/* --------------------------------------------------------------- */
91
+
92
+	pseudo_bit_t buffer3_dma_addr[64];	/**< Buffer 3 DMA address */
93
+
94
+	/* --------------------------------------------------------------- */
95
+
96
+	pseudo_bit_t buffer1_dma_addr[64];	/**< Buffer 1 DMA address */
97
+
98
+	/* --------------------------------------------------------------- */
99
+
100
+	pseudo_bit_t buffer1_length[16];	/**< Buffer 1 length */
101
+	pseudo_bit_t buffer2_length[16];	/**< Buffer 2 length */
102
+	pseudo_bit_t buffer3_length[16];	/**< Buffer 3 length */
103
+	pseudo_bit_t buffer4_length[16];	/**< Buffer 4 length */
104
+
105
+	/* --------------------------------------------------------------- */
106
+
107
+	pseudo_bit_t buffer4_dma_addr[64];	/**< Buffer 4 DMA address */
108
+
109
+	/* --------------------------------------------------------------- */
110
+
111
+	pseudo_bit_t hw_rsvd_1[64];		/**< (Reserved) */
112
+};
113
+
114
+/** A Phantom MAC address request body */
115
+struct phantom_nic_request_body_mac_request_pb {
116
+	pseudo_bit_t opcode[8];			/**< Opcode */
117
+	pseudo_bit_t tag[8];			/**< Tag */
118
+	pseudo_bit_t mac_addr_0[8];		/**< MAC address byte 0 */
119
+	pseudo_bit_t mac_addr_1[8];		/**< MAC address byte 1 */
120
+	pseudo_bit_t mac_addr_2[8];		/**< MAC address byte 2 */
121
+	pseudo_bit_t mac_addr_3[8];		/**< MAC address byte 3 */
122
+	pseudo_bit_t mac_addr_4[8];		/**< MAC address byte 4 */
123
+	pseudo_bit_t mac_addr_5[8];		/**< MAC address byte 5 */
124
+};
125
+
126
+/** Phantom MAC request opcodes */
127
+enum phantom_mac_request_opcode {
128
+	UNM_MAC_ADD = 0x01,			/**< Add MAC address */
129
+	UNM_MAC_DEL = 0x02,			/**< Delete MAC address */
130
+};
131
+
132
+/** A Phantom NIC request command descriptor */
133
+struct phantom_nic_request_cds_pb {
134
+	struct {
135
+		pseudo_bit_t dst_minor[18];
136
+		pseudo_bit_t dst_subq[1];
137
+		pseudo_bit_t dst_major[4];
138
+		pseudo_bit_t opcode[6];
139
+		pseudo_bit_t hw_rsvd_0[3];
140
+		pseudo_bit_t msginfo[24];
141
+		pseudo_bit_t hw_rsvd_1[2];
142
+		pseudo_bit_t qmsg_type[6];
143
+	} common;
144
+
145
+	/* --------------------------------------------------------------- */
146
+
147
+	struct {
148
+		pseudo_bit_t opcode[8];
149
+		pseudo_bit_t comp_id [8];
150
+		pseudo_bit_t context_id[16];
151
+		pseudo_bit_t need_completion[1];
152
+		pseudo_bit_t hw_rsvd_0[23];
153
+		pseudo_bit_t sub_opcode[8];
154
+	} header;
155
+
156
+	/* --------------------------------------------------------------- */
157
+
158
+	union {
159
+		struct phantom_nic_request_body_mac_request_pb mac_request;
160
+		pseudo_bit_t padding[384];
161
+	} body;
162
+};
163
+
164
+/** Phantom NIC request opcodes */
165
+enum phantom_nic_request_opcode {
166
+	UNM_MAC_EVENT = 0x01,			/**< Add/delete MAC address */
167
+};
168
+
169
+/** A Phantom command descriptor */
170
+union phantom_cds_pb {
171
+	struct phantom_tx_cds_pb tx;
172
+	struct phantom_nic_request_cds_pb nic_request;
173
+};
174
+
175
+/** Phantom command descriptor opcodes */
176
+enum phantom_cds_opcode {
177
+	UNM_TX_ETHER_PKT = 0x01,		/**< Transmit raw Ethernet */
178
+	UNM_NIC_REQUEST = 0x14,			/**< NIC request */
179
+};
180
+
181
+#endif /* _PHANTOM_HW_H */

+ 1
- 0
src/include/gpxe/errfile.h View File

@@ -105,6 +105,7 @@
105 105
 #define ERRFILE_e1000		     ( ERRFILE_DRIVER | 0x00480000 )
106 106
 #define ERRFILE_e1000_hw	     ( ERRFILE_DRIVER | 0x00490000 )
107 107
 #define ERRFILE_mtnic		     ( ERRFILE_DRIVER | 0x004a0000 )
108
+#define ERRFILE_phantom		     ( ERRFILE_DRIVER | 0x004b0000 )
108 109
 
109 110
 #define ERRFILE_scsi		     ( ERRFILE_DRIVER | 0x00700000 )
110 111
 #define ERRFILE_arbel		     ( ERRFILE_DRIVER | 0x00710000 )

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