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e1000_hw.c 313KB

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  1. /*******************************************************************************
  2. Intel PRO/1000 Linux driver
  3. Copyright(c) 1999 - 2006 Intel Corporation.
  4. This program is free software; you can redistribute it and/or modify it
  5. under the terms and conditions of the GNU General Public License,
  6. version 2, as published by the Free Software Foundation.
  7. This program is distributed in the hope it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc.,
  13. 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  14. The full GNU General Public License is included in this distribution in
  15. the file called "COPYING".
  16. Contact Information:
  17. Linux NICS <linux.nics@intel.com>
  18. e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20. *******************************************************************************/
  21. /* e1000_hw.c
  22. * Shared functions for accessing and configuring the MAC
  23. */
  24. #include "e1000_hw.h"
  25. static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
  26. static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
  27. static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
  28. static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
  29. static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
  30. static void e1000_release_software_semaphore(struct e1000_hw *hw);
  31. static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
  32. static int32_t e1000_check_downshift(struct e1000_hw *hw);
  33. static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
  34. static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
  35. static void e1000_clear_vfta(struct e1000_hw *hw);
  36. static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
  37. static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
  38. static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
  39. static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
  40. static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
  41. static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
  42. static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
  43. static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
  44. static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
  45. static int32_t e1000_get_software_flag(struct e1000_hw *hw);
  46. static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
  47. static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
  48. static int32_t e1000_id_led_init(struct e1000_hw *hw);
  49. static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
  50. static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
  51. static void e1000_init_rx_addrs(struct e1000_hw *hw);
  52. static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
  53. static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
  54. static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
  55. static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
  56. static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
  57. static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
  58. static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
  59. static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
  60. static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
  61. static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
  62. static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
  63. static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
  64. static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
  65. static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
  66. static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data);
  67. static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
  68. static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
  69. static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data);
  70. static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
  71. static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
  72. static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
  73. static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
  74. static void e1000_release_software_flag(struct e1000_hw *hw);
  75. static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
  76. static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
  77. static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
  78. static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
  79. static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
  80. static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
  81. static int32_t e1000_set_phy_type(struct e1000_hw *hw);
  82. static void e1000_phy_init_script(struct e1000_hw *hw);
  83. static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
  84. static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
  85. static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
  86. static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
  87. static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
  88. static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
  89. static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
  90. static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
  91. uint16_t count);
  92. static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
  93. static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
  94. static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
  95. uint16_t words, uint16_t *data);
  96. static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
  97. uint16_t offset, uint16_t words,
  98. uint16_t *data);
  99. static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
  100. static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
  101. static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
  102. static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
  103. uint16_t count);
  104. static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
  105. uint16_t phy_data);
  106. static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
  107. uint16_t *phy_data);
  108. static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
  109. static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
  110. static void e1000_release_eeprom(struct e1000_hw *hw);
  111. static void e1000_standby_eeprom(struct e1000_hw *hw);
  112. static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
  113. static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
  114. static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
  115. static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
  116. static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
  117. static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
  118. uint16_t duplex);
  119. static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
  120. /* IGP cable length table */
  121. static const
  122. uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
  123. { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
  124. 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
  125. 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
  126. 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
  127. 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
  128. 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
  129. 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
  130. 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
  131. static const
  132. uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
  133. { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
  134. 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
  135. 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
  136. 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
  137. 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
  138. 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
  139. 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
  140. 104, 109, 114, 118, 121, 124};
  141. /******************************************************************************
  142. * Set the phy type member in the hw struct.
  143. *
  144. * hw - Struct containing variables accessed by shared code
  145. *****************************************************************************/
  146. static int32_t
  147. e1000_set_phy_type(struct e1000_hw *hw)
  148. {
  149. DEBUGFUNC("e1000_set_phy_type");
  150. if (hw->mac_type == e1000_undefined)
  151. return -E1000_ERR_PHY_TYPE;
  152. switch (hw->phy_id) {
  153. case M88E1000_E_PHY_ID:
  154. case M88E1000_I_PHY_ID:
  155. case M88E1011_I_PHY_ID:
  156. case M88E1111_I_PHY_ID:
  157. hw->phy_type = e1000_phy_m88;
  158. break;
  159. case IGP01E1000_I_PHY_ID:
  160. if (hw->mac_type == e1000_82541 ||
  161. hw->mac_type == e1000_82541_rev_2 ||
  162. hw->mac_type == e1000_82547 ||
  163. hw->mac_type == e1000_82547_rev_2) {
  164. hw->phy_type = e1000_phy_igp;
  165. break;
  166. }
  167. case IGP03E1000_E_PHY_ID:
  168. hw->phy_type = e1000_phy_igp_3;
  169. break;
  170. case IFE_E_PHY_ID:
  171. case IFE_PLUS_E_PHY_ID:
  172. case IFE_C_E_PHY_ID:
  173. hw->phy_type = e1000_phy_ife;
  174. break;
  175. case GG82563_E_PHY_ID:
  176. if (hw->mac_type == e1000_80003es2lan) {
  177. hw->phy_type = e1000_phy_gg82563;
  178. break;
  179. }
  180. /* Fall Through */
  181. default:
  182. /* Should never have loaded on this device */
  183. hw->phy_type = e1000_phy_undefined;
  184. return -E1000_ERR_PHY_TYPE;
  185. }
  186. return E1000_SUCCESS;
  187. }
  188. /******************************************************************************
  189. * IGP phy init script - initializes the GbE PHY
  190. *
  191. * hw - Struct containing variables accessed by shared code
  192. *****************************************************************************/
  193. static void
  194. e1000_phy_init_script(struct e1000_hw *hw)
  195. {
  196. uint32_t ret_val;
  197. uint16_t phy_saved_data;
  198. DEBUGFUNC("e1000_phy_init_script");
  199. if (hw->phy_init_script) {
  200. msleep(20);
  201. /* Save off the current value of register 0x2F5B to be restored at
  202. * the end of this routine. */
  203. ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
  204. /* Disabled the PHY transmitter */
  205. e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
  206. msleep(20);
  207. e1000_write_phy_reg(hw,0x0000,0x0140);
  208. msleep(5);
  209. switch (hw->mac_type) {
  210. case e1000_82541:
  211. case e1000_82547:
  212. e1000_write_phy_reg(hw, 0x1F95, 0x0001);
  213. e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
  214. e1000_write_phy_reg(hw, 0x1F79, 0x0018);
  215. e1000_write_phy_reg(hw, 0x1F30, 0x1600);
  216. e1000_write_phy_reg(hw, 0x1F31, 0x0014);
  217. e1000_write_phy_reg(hw, 0x1F32, 0x161C);
  218. e1000_write_phy_reg(hw, 0x1F94, 0x0003);
  219. e1000_write_phy_reg(hw, 0x1F96, 0x003F);
  220. e1000_write_phy_reg(hw, 0x2010, 0x0008);
  221. break;
  222. case e1000_82541_rev_2:
  223. case e1000_82547_rev_2:
  224. e1000_write_phy_reg(hw, 0x1F73, 0x0099);
  225. break;
  226. default:
  227. break;
  228. }
  229. e1000_write_phy_reg(hw, 0x0000, 0x3300);
  230. msleep(20);
  231. /* Now enable the transmitter */
  232. e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
  233. if (hw->mac_type == e1000_82547) {
  234. uint16_t fused, fine, coarse;
  235. /* Move to analog registers page */
  236. e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
  237. if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
  238. e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
  239. fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
  240. coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
  241. if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
  242. coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
  243. fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
  244. } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
  245. fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
  246. fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
  247. (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
  248. (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
  249. e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
  250. e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
  251. IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
  252. }
  253. }
  254. }
  255. }
  256. /******************************************************************************
  257. * Set the mac type member in the hw struct.
  258. *
  259. * hw - Struct containing variables accessed by shared code
  260. *****************************************************************************/
  261. int32_t
  262. e1000_set_mac_type(struct e1000_hw *hw)
  263. {
  264. DEBUGFUNC("e1000_set_mac_type");
  265. switch (hw->device_id) {
  266. case E1000_DEV_ID_82542:
  267. switch (hw->revision_id) {
  268. case E1000_82542_2_0_REV_ID:
  269. hw->mac_type = e1000_82542_rev2_0;
  270. break;
  271. case E1000_82542_2_1_REV_ID:
  272. hw->mac_type = e1000_82542_rev2_1;
  273. break;
  274. default:
  275. /* Invalid 82542 revision ID */
  276. return -E1000_ERR_MAC_TYPE;
  277. }
  278. break;
  279. case E1000_DEV_ID_82543GC_FIBER:
  280. case E1000_DEV_ID_82543GC_COPPER:
  281. hw->mac_type = e1000_82543;
  282. break;
  283. case E1000_DEV_ID_82544EI_COPPER:
  284. case E1000_DEV_ID_82544EI_FIBER:
  285. case E1000_DEV_ID_82544GC_COPPER:
  286. case E1000_DEV_ID_82544GC_LOM:
  287. hw->mac_type = e1000_82544;
  288. break;
  289. case E1000_DEV_ID_82540EM:
  290. case E1000_DEV_ID_82540EM_LOM:
  291. case E1000_DEV_ID_82540EP:
  292. case E1000_DEV_ID_82540EP_LOM:
  293. case E1000_DEV_ID_82540EP_LP:
  294. hw->mac_type = e1000_82540;
  295. break;
  296. case E1000_DEV_ID_82545EM_COPPER:
  297. case E1000_DEV_ID_82545EM_FIBER:
  298. hw->mac_type = e1000_82545;
  299. break;
  300. case E1000_DEV_ID_82545GM_COPPER:
  301. case E1000_DEV_ID_82545GM_FIBER:
  302. case E1000_DEV_ID_82545GM_SERDES:
  303. hw->mac_type = e1000_82545_rev_3;
  304. break;
  305. case E1000_DEV_ID_82546EB_COPPER:
  306. case E1000_DEV_ID_82546EB_FIBER:
  307. case E1000_DEV_ID_82546EB_QUAD_COPPER:
  308. hw->mac_type = e1000_82546;
  309. break;
  310. case E1000_DEV_ID_82546GB_COPPER:
  311. case E1000_DEV_ID_82546GB_FIBER:
  312. case E1000_DEV_ID_82546GB_SERDES:
  313. case E1000_DEV_ID_82546GB_PCIE:
  314. case E1000_DEV_ID_82546GB_QUAD_COPPER:
  315. case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
  316. hw->mac_type = e1000_82546_rev_3;
  317. break;
  318. case E1000_DEV_ID_82541EI:
  319. case E1000_DEV_ID_82541EI_MOBILE:
  320. case E1000_DEV_ID_82541ER_LOM:
  321. hw->mac_type = e1000_82541;
  322. break;
  323. case E1000_DEV_ID_82541ER:
  324. case E1000_DEV_ID_82541GI:
  325. case E1000_DEV_ID_82541GI_LF:
  326. case E1000_DEV_ID_82541GI_MOBILE:
  327. hw->mac_type = e1000_82541_rev_2;
  328. break;
  329. case E1000_DEV_ID_82547EI:
  330. case E1000_DEV_ID_82547EI_MOBILE:
  331. hw->mac_type = e1000_82547;
  332. break;
  333. case E1000_DEV_ID_82547GI:
  334. hw->mac_type = e1000_82547_rev_2;
  335. break;
  336. case E1000_DEV_ID_82571EB_COPPER:
  337. case E1000_DEV_ID_82571EB_FIBER:
  338. case E1000_DEV_ID_82571EB_SERDES:
  339. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  340. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  341. case E1000_DEV_ID_82571EB_QUAD_COPPER:
  342. case E1000_DEV_ID_82571EB_QUAD_FIBER:
  343. case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
  344. hw->mac_type = e1000_82571;
  345. break;
  346. case E1000_DEV_ID_82572EI_COPPER:
  347. case E1000_DEV_ID_82572EI_FIBER:
  348. case E1000_DEV_ID_82572EI_SERDES:
  349. case E1000_DEV_ID_82572EI:
  350. hw->mac_type = e1000_82572;
  351. break;
  352. case E1000_DEV_ID_82573E:
  353. case E1000_DEV_ID_82573E_IAMT:
  354. case E1000_DEV_ID_82573L:
  355. hw->mac_type = e1000_82573;
  356. break;
  357. case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
  358. case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
  359. case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
  360. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  361. hw->mac_type = e1000_80003es2lan;
  362. break;
  363. case E1000_DEV_ID_ICH8_IGP_M_AMT:
  364. case E1000_DEV_ID_ICH8_IGP_AMT:
  365. case E1000_DEV_ID_ICH8_IGP_C:
  366. case E1000_DEV_ID_ICH8_IFE:
  367. case E1000_DEV_ID_ICH8_IFE_GT:
  368. case E1000_DEV_ID_ICH8_IFE_G:
  369. case E1000_DEV_ID_ICH8_IGP_M:
  370. hw->mac_type = e1000_ich8lan;
  371. break;
  372. default:
  373. /* Should never have loaded on this device */
  374. return -E1000_ERR_MAC_TYPE;
  375. }
  376. switch (hw->mac_type) {
  377. case e1000_ich8lan:
  378. hw->swfwhw_semaphore_present = TRUE;
  379. hw->asf_firmware_present = TRUE;
  380. break;
  381. case e1000_80003es2lan:
  382. hw->swfw_sync_present = TRUE;
  383. /* fall through */
  384. case e1000_82571:
  385. case e1000_82572:
  386. case e1000_82573:
  387. hw->eeprom_semaphore_present = TRUE;
  388. /* fall through */
  389. case e1000_82541:
  390. case e1000_82547:
  391. case e1000_82541_rev_2:
  392. case e1000_82547_rev_2:
  393. hw->asf_firmware_present = TRUE;
  394. break;
  395. default:
  396. break;
  397. }
  398. /* The 82543 chip does not count tx_carrier_errors properly in
  399. * FD mode
  400. */
  401. if (hw->mac_type == e1000_82543)
  402. hw->bad_tx_carr_stats_fd = TRUE;
  403. /* capable of receiving management packets to the host */
  404. if (hw->mac_type >= e1000_82571)
  405. hw->has_manc2h = TRUE;
  406. /* In rare occasions, ESB2 systems would end up started without
  407. * the RX unit being turned on.
  408. */
  409. if (hw->mac_type == e1000_80003es2lan)
  410. hw->rx_needs_kicking = TRUE;
  411. if (hw->mac_type > e1000_82544)
  412. hw->has_smbus = TRUE;
  413. return E1000_SUCCESS;
  414. }
  415. /*****************************************************************************
  416. * Set media type and TBI compatibility.
  417. *
  418. * hw - Struct containing variables accessed by shared code
  419. * **************************************************************************/
  420. void
  421. e1000_set_media_type(struct e1000_hw *hw)
  422. {
  423. uint32_t status;
  424. DEBUGFUNC("e1000_set_media_type");
  425. if (hw->mac_type != e1000_82543) {
  426. /* tbi_compatibility is only valid on 82543 */
  427. hw->tbi_compatibility_en = FALSE;
  428. }
  429. switch (hw->device_id) {
  430. case E1000_DEV_ID_82545GM_SERDES:
  431. case E1000_DEV_ID_82546GB_SERDES:
  432. case E1000_DEV_ID_82571EB_SERDES:
  433. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  434. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  435. case E1000_DEV_ID_82572EI_SERDES:
  436. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  437. hw->media_type = e1000_media_type_internal_serdes;
  438. break;
  439. default:
  440. switch (hw->mac_type) {
  441. case e1000_82542_rev2_0:
  442. case e1000_82542_rev2_1:
  443. hw->media_type = e1000_media_type_fiber;
  444. break;
  445. case e1000_ich8lan:
  446. case e1000_82573:
  447. /* The STATUS_TBIMODE bit is reserved or reused for the this
  448. * device.
  449. */
  450. hw->media_type = e1000_media_type_copper;
  451. break;
  452. default:
  453. status = E1000_READ_REG(hw, STATUS);
  454. if (status & E1000_STATUS_TBIMODE) {
  455. hw->media_type = e1000_media_type_fiber;
  456. /* tbi_compatibility not valid on fiber */
  457. hw->tbi_compatibility_en = FALSE;
  458. } else {
  459. hw->media_type = e1000_media_type_copper;
  460. }
  461. break;
  462. }
  463. }
  464. }
  465. /******************************************************************************
  466. * Reset the transmit and receive units; mask and clear all interrupts.
  467. *
  468. * hw - Struct containing variables accessed by shared code
  469. *****************************************************************************/
  470. int32_t
  471. e1000_reset_hw(struct e1000_hw *hw)
  472. {
  473. uint32_t ctrl;
  474. uint32_t ctrl_ext;
  475. uint32_t icr;
  476. uint32_t manc;
  477. uint32_t led_ctrl;
  478. uint32_t timeout;
  479. uint32_t extcnf_ctrl;
  480. int32_t ret_val;
  481. DEBUGFUNC("e1000_reset_hw");
  482. /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
  483. if (hw->mac_type == e1000_82542_rev2_0) {
  484. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  485. e1000_pci_clear_mwi(hw);
  486. }
  487. if (hw->bus_type == e1000_bus_type_pci_express) {
  488. /* Prevent the PCI-E bus from sticking if there is no TLP connection
  489. * on the last TLP read/write transaction when MAC is reset.
  490. */
  491. if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
  492. DEBUGOUT("PCI-E Master disable polling has failed.\n");
  493. }
  494. }
  495. /* Clear interrupt mask to stop board from generating interrupts */
  496. DEBUGOUT("Masking off all interrupts\n");
  497. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  498. /* Disable the Transmit and Receive units. Then delay to allow
  499. * any pending transactions to complete before we hit the MAC with
  500. * the global reset.
  501. */
  502. E1000_WRITE_REG(hw, RCTL, 0);
  503. E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
  504. E1000_WRITE_FLUSH(hw);
  505. /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
  506. hw->tbi_compatibility_on = FALSE;
  507. /* Delay to allow any outstanding PCI transactions to complete before
  508. * resetting the device
  509. */
  510. msleep(10);
  511. ctrl = E1000_READ_REG(hw, CTRL);
  512. /* Must reset the PHY before resetting the MAC */
  513. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  514. E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
  515. msleep(5);
  516. }
  517. /* Must acquire the MDIO ownership before MAC reset.
  518. * Ownership defaults to firmware after a reset. */
  519. if (hw->mac_type == e1000_82573) {
  520. timeout = 10;
  521. extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
  522. extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
  523. do {
  524. E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
  525. extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
  526. if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
  527. break;
  528. else
  529. extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
  530. msleep(2);
  531. timeout--;
  532. } while (timeout);
  533. }
  534. /* Workaround for ICH8 bit corruption issue in FIFO memory */
  535. if (hw->mac_type == e1000_ich8lan) {
  536. /* Set Tx and Rx buffer allocation to 8k apiece. */
  537. E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
  538. /* Set Packet Buffer Size to 16k. */
  539. E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
  540. }
  541. /* Issue a global reset to the MAC. This will reset the chip's
  542. * transmit, receive, DMA, and link units. It will not effect
  543. * the current PCI configuration. The global reset bit is self-
  544. * clearing, and should clear within a microsecond.
  545. */
  546. DEBUGOUT("Issuing a global reset to MAC\n");
  547. switch (hw->mac_type) {
  548. case e1000_82544:
  549. case e1000_82540:
  550. case e1000_82545:
  551. case e1000_82546:
  552. case e1000_82541:
  553. case e1000_82541_rev_2:
  554. /* These controllers can't ack the 64-bit write when issuing the
  555. * reset, so use IO-mapping as a workaround to issue the reset */
  556. E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
  557. break;
  558. case e1000_82545_rev_3:
  559. case e1000_82546_rev_3:
  560. /* Reset is performed on a shadow of the control register */
  561. E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
  562. break;
  563. case e1000_ich8lan:
  564. if (!hw->phy_reset_disable &&
  565. e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
  566. /* e1000_ich8lan PHY HW reset requires MAC CORE reset
  567. * at the same time to make sure the interface between
  568. * MAC and the external PHY is reset.
  569. */
  570. ctrl |= E1000_CTRL_PHY_RST;
  571. }
  572. e1000_get_software_flag(hw);
  573. E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
  574. msleep(5);
  575. break;
  576. default:
  577. E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
  578. break;
  579. }
  580. /* After MAC reset, force reload of EEPROM to restore power-on settings to
  581. * device. Later controllers reload the EEPROM automatically, so just wait
  582. * for reload to complete.
  583. */
  584. switch (hw->mac_type) {
  585. case e1000_82542_rev2_0:
  586. case e1000_82542_rev2_1:
  587. case e1000_82543:
  588. case e1000_82544:
  589. /* Wait for reset to complete */
  590. udelay(10);
  591. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  592. ctrl_ext |= E1000_CTRL_EXT_EE_RST;
  593. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  594. E1000_WRITE_FLUSH(hw);
  595. /* Wait for EEPROM reload */
  596. msleep(2);
  597. break;
  598. case e1000_82541:
  599. case e1000_82541_rev_2:
  600. case e1000_82547:
  601. case e1000_82547_rev_2:
  602. /* Wait for EEPROM reload */
  603. msleep(20);
  604. break;
  605. case e1000_82573:
  606. if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
  607. udelay(10);
  608. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  609. ctrl_ext |= E1000_CTRL_EXT_EE_RST;
  610. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  611. E1000_WRITE_FLUSH(hw);
  612. }
  613. /* fall through */
  614. default:
  615. /* Auto read done will delay 5ms or poll based on mac type */
  616. ret_val = e1000_get_auto_rd_done(hw);
  617. if (ret_val)
  618. return ret_val;
  619. break;
  620. }
  621. /* Disable HW ARPs on ASF enabled adapters */
  622. if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
  623. manc = E1000_READ_REG(hw, MANC);
  624. manc &= ~(E1000_MANC_ARP_EN);
  625. E1000_WRITE_REG(hw, MANC, manc);
  626. }
  627. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  628. e1000_phy_init_script(hw);
  629. /* Configure activity LED after PHY reset */
  630. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  631. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  632. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  633. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  634. }
  635. /* Clear interrupt mask to stop board from generating interrupts */
  636. DEBUGOUT("Masking off all interrupts\n");
  637. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  638. /* Clear any pending interrupt events. */
  639. icr = E1000_READ_REG(hw, ICR);
  640. /* If MWI was previously enabled, reenable it. */
  641. if (hw->mac_type == e1000_82542_rev2_0) {
  642. if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
  643. e1000_pci_set_mwi(hw);
  644. }
  645. if (hw->mac_type == e1000_ich8lan) {
  646. uint32_t kab = E1000_READ_REG(hw, KABGTXD);
  647. kab |= E1000_KABGTXD_BGSQLBIAS;
  648. E1000_WRITE_REG(hw, KABGTXD, kab);
  649. }
  650. return E1000_SUCCESS;
  651. }
  652. /******************************************************************************
  653. *
  654. * Initialize a number of hardware-dependent bits
  655. *
  656. * hw: Struct containing variables accessed by shared code
  657. *
  658. * This function contains hardware limitation workarounds for PCI-E adapters
  659. *
  660. *****************************************************************************/
  661. static void
  662. e1000_initialize_hardware_bits(struct e1000_hw *hw)
  663. {
  664. if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
  665. /* Settings common to all PCI-express silicon */
  666. uint32_t reg_ctrl, reg_ctrl_ext;
  667. uint32_t reg_tarc0, reg_tarc1;
  668. uint32_t reg_tctl;
  669. uint32_t reg_txdctl, reg_txdctl1;
  670. /* link autonegotiation/sync workarounds */
  671. reg_tarc0 = E1000_READ_REG(hw, TARC0);
  672. reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
  673. /* Enable not-done TX descriptor counting */
  674. reg_txdctl = E1000_READ_REG(hw, TXDCTL);
  675. reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
  676. E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
  677. reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
  678. reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
  679. E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
  680. switch (hw->mac_type) {
  681. case e1000_82571:
  682. case e1000_82572:
  683. /* Clear PHY TX compatible mode bits */
  684. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  685. reg_tarc1 &= ~((1 << 30)|(1 << 29));
  686. /* link autonegotiation/sync workarounds */
  687. reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
  688. /* TX ring control fixes */
  689. reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
  690. /* Multiple read bit is reversed polarity */
  691. reg_tctl = E1000_READ_REG(hw, TCTL);
  692. if (reg_tctl & E1000_TCTL_MULR)
  693. reg_tarc1 &= ~(1 << 28);
  694. else
  695. reg_tarc1 |= (1 << 28);
  696. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  697. break;
  698. case e1000_82573:
  699. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  700. reg_ctrl_ext &= ~(1 << 23);
  701. reg_ctrl_ext |= (1 << 22);
  702. /* TX byte count fix */
  703. reg_ctrl = E1000_READ_REG(hw, CTRL);
  704. reg_ctrl &= ~(1 << 29);
  705. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  706. E1000_WRITE_REG(hw, CTRL, reg_ctrl);
  707. break;
  708. case e1000_80003es2lan:
  709. /* improve small packet performace for fiber/serdes */
  710. if ((hw->media_type == e1000_media_type_fiber) ||
  711. (hw->media_type == e1000_media_type_internal_serdes)) {
  712. reg_tarc0 &= ~(1 << 20);
  713. }
  714. /* Multiple read bit is reversed polarity */
  715. reg_tctl = E1000_READ_REG(hw, TCTL);
  716. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  717. if (reg_tctl & E1000_TCTL_MULR)
  718. reg_tarc1 &= ~(1 << 28);
  719. else
  720. reg_tarc1 |= (1 << 28);
  721. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  722. break;
  723. case e1000_ich8lan:
  724. /* Reduce concurrent DMA requests to 3 from 4 */
  725. if ((hw->revision_id < 3) ||
  726. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  727. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
  728. reg_tarc0 |= ((1 << 29)|(1 << 28));
  729. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  730. reg_ctrl_ext |= (1 << 22);
  731. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  732. /* workaround TX hang with TSO=on */
  733. reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
  734. /* Multiple read bit is reversed polarity */
  735. reg_tctl = E1000_READ_REG(hw, TCTL);
  736. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  737. if (reg_tctl & E1000_TCTL_MULR)
  738. reg_tarc1 &= ~(1 << 28);
  739. else
  740. reg_tarc1 |= (1 << 28);
  741. /* workaround TX hang with TSO=on */
  742. reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
  743. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  744. break;
  745. default:
  746. break;
  747. }
  748. E1000_WRITE_REG(hw, TARC0, reg_tarc0);
  749. }
  750. }
  751. /******************************************************************************
  752. * Performs basic configuration of the adapter.
  753. *
  754. * hw - Struct containing variables accessed by shared code
  755. *
  756. * Assumes that the controller has previously been reset and is in a
  757. * post-reset uninitialized state. Initializes the receive address registers,
  758. * multicast table, and VLAN filter table. Calls routines to setup link
  759. * configuration and flow control settings. Clears all on-chip counters. Leaves
  760. * the transmit and receive units disabled and uninitialized.
  761. *****************************************************************************/
  762. int32_t
  763. e1000_init_hw(struct e1000_hw *hw)
  764. {
  765. uint32_t ctrl;
  766. uint32_t i;
  767. int32_t ret_val;
  768. uint16_t pcix_cmd_word;
  769. uint16_t pcix_stat_hi_word;
  770. uint16_t cmd_mmrbc;
  771. uint16_t stat_mmrbc;
  772. uint32_t mta_size;
  773. uint32_t reg_data;
  774. uint32_t ctrl_ext;
  775. DEBUGFUNC("e1000_init_hw");
  776. /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
  777. if ((hw->mac_type == e1000_ich8lan) &&
  778. ((hw->revision_id < 3) ||
  779. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  780. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
  781. reg_data = E1000_READ_REG(hw, STATUS);
  782. reg_data &= ~0x80000000;
  783. E1000_WRITE_REG(hw, STATUS, reg_data);
  784. }
  785. /* Initialize Identification LED */
  786. ret_val = e1000_id_led_init(hw);
  787. if (ret_val) {
  788. DEBUGOUT("Error Initializing Identification LED\n");
  789. return ret_val;
  790. }
  791. /* Set the media type and TBI compatibility */
  792. e1000_set_media_type(hw);
  793. /* Must be called after e1000_set_media_type because media_type is used */
  794. e1000_initialize_hardware_bits(hw);
  795. /* Disabling VLAN filtering. */
  796. DEBUGOUT("Initializing the IEEE VLAN\n");
  797. /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
  798. if (hw->mac_type != e1000_ich8lan) {
  799. if (hw->mac_type < e1000_82545_rev_3)
  800. E1000_WRITE_REG(hw, VET, 0);
  801. e1000_clear_vfta(hw);
  802. }
  803. /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
  804. if (hw->mac_type == e1000_82542_rev2_0) {
  805. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  806. e1000_pci_clear_mwi(hw);
  807. E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
  808. E1000_WRITE_FLUSH(hw);
  809. msleep(5);
  810. }
  811. /* Setup the receive address. This involves initializing all of the Receive
  812. * Address Registers (RARs 0 - 15).
  813. */
  814. e1000_init_rx_addrs(hw);
  815. /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
  816. if (hw->mac_type == e1000_82542_rev2_0) {
  817. E1000_WRITE_REG(hw, RCTL, 0);
  818. E1000_WRITE_FLUSH(hw);
  819. msleep(1);
  820. if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
  821. e1000_pci_set_mwi(hw);
  822. }
  823. /* Zero out the Multicast HASH table */
  824. DEBUGOUT("Zeroing the MTA\n");
  825. mta_size = E1000_MC_TBL_SIZE;
  826. if (hw->mac_type == e1000_ich8lan)
  827. mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
  828. for (i = 0; i < mta_size; i++) {
  829. E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
  830. /* use write flush to prevent Memory Write Block (MWB) from
  831. * occuring when accessing our register space */
  832. E1000_WRITE_FLUSH(hw);
  833. }
  834. /* Set the PCI priority bit correctly in the CTRL register. This
  835. * determines if the adapter gives priority to receives, or if it
  836. * gives equal priority to transmits and receives. Valid only on
  837. * 82542 and 82543 silicon.
  838. */
  839. if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
  840. ctrl = E1000_READ_REG(hw, CTRL);
  841. E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
  842. }
  843. switch (hw->mac_type) {
  844. case e1000_82545_rev_3:
  845. case e1000_82546_rev_3:
  846. break;
  847. default:
  848. /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
  849. if (hw->bus_type == e1000_bus_type_pcix) {
  850. e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
  851. e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
  852. &pcix_stat_hi_word);
  853. cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
  854. PCIX_COMMAND_MMRBC_SHIFT;
  855. stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
  856. PCIX_STATUS_HI_MMRBC_SHIFT;
  857. if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
  858. stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
  859. if (cmd_mmrbc > stat_mmrbc) {
  860. pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
  861. pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
  862. e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
  863. &pcix_cmd_word);
  864. }
  865. }
  866. break;
  867. }
  868. /* More time needed for PHY to initialize */
  869. if (hw->mac_type == e1000_ich8lan)
  870. msleep(15);
  871. /* Call a subroutine to configure the link and setup flow control. */
  872. ret_val = e1000_setup_link(hw);
  873. /* Set the transmit descriptor write-back policy */
  874. if (hw->mac_type > e1000_82544) {
  875. ctrl = E1000_READ_REG(hw, TXDCTL);
  876. ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
  877. E1000_WRITE_REG(hw, TXDCTL, ctrl);
  878. }
  879. if (hw->mac_type == e1000_82573) {
  880. e1000_enable_tx_pkt_filtering(hw);
  881. }
  882. switch (hw->mac_type) {
  883. default:
  884. break;
  885. case e1000_80003es2lan:
  886. /* Enable retransmit on late collisions */
  887. reg_data = E1000_READ_REG(hw, TCTL);
  888. reg_data |= E1000_TCTL_RTLC;
  889. E1000_WRITE_REG(hw, TCTL, reg_data);
  890. /* Configure Gigabit Carry Extend Padding */
  891. reg_data = E1000_READ_REG(hw, TCTL_EXT);
  892. reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
  893. reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
  894. E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
  895. /* Configure Transmit Inter-Packet Gap */
  896. reg_data = E1000_READ_REG(hw, TIPG);
  897. reg_data &= ~E1000_TIPG_IPGT_MASK;
  898. reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  899. E1000_WRITE_REG(hw, TIPG, reg_data);
  900. reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
  901. reg_data &= ~0x00100000;
  902. E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
  903. /* Fall through */
  904. case e1000_82571:
  905. case e1000_82572:
  906. case e1000_ich8lan:
  907. ctrl = E1000_READ_REG(hw, TXDCTL1);
  908. ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
  909. E1000_WRITE_REG(hw, TXDCTL1, ctrl);
  910. break;
  911. }
  912. if (hw->mac_type == e1000_82573) {
  913. uint32_t gcr = E1000_READ_REG(hw, GCR);
  914. gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
  915. E1000_WRITE_REG(hw, GCR, gcr);
  916. }
  917. /* Clear all of the statistics registers (clear on read). It is
  918. * important that we do this after we have tried to establish link
  919. * because the symbol error count will increment wildly if there
  920. * is no link.
  921. */
  922. e1000_clear_hw_cntrs(hw);
  923. /* ICH8 No-snoop bits are opposite polarity.
  924. * Set to snoop by default after reset. */
  925. if (hw->mac_type == e1000_ich8lan)
  926. e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
  927. if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
  928. hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
  929. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  930. /* Relaxed ordering must be disabled to avoid a parity
  931. * error crash in a PCI slot. */
  932. ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
  933. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  934. }
  935. return ret_val;
  936. }
  937. /******************************************************************************
  938. * Adjust SERDES output amplitude based on EEPROM setting.
  939. *
  940. * hw - Struct containing variables accessed by shared code.
  941. *****************************************************************************/
  942. static int32_t
  943. e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
  944. {
  945. uint16_t eeprom_data;
  946. int32_t ret_val;
  947. DEBUGFUNC("e1000_adjust_serdes_amplitude");
  948. if (hw->media_type != e1000_media_type_internal_serdes)
  949. return E1000_SUCCESS;
  950. switch (hw->mac_type) {
  951. case e1000_82545_rev_3:
  952. case e1000_82546_rev_3:
  953. break;
  954. default:
  955. return E1000_SUCCESS;
  956. }
  957. ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
  958. if (ret_val) {
  959. return ret_val;
  960. }
  961. if (eeprom_data != EEPROM_RESERVED_WORD) {
  962. /* Adjust SERDES output amplitude only. */
  963. eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
  964. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
  965. if (ret_val)
  966. return ret_val;
  967. }
  968. return E1000_SUCCESS;
  969. }
  970. /******************************************************************************
  971. * Configures flow control and link settings.
  972. *
  973. * hw - Struct containing variables accessed by shared code
  974. *
  975. * Determines which flow control settings to use. Calls the apropriate media-
  976. * specific link configuration function. Configures the flow control settings.
  977. * Assuming the adapter has a valid link partner, a valid link should be
  978. * established. Assumes the hardware has previously been reset and the
  979. * transmitter and receiver are not enabled.
  980. *****************************************************************************/
  981. int32_t
  982. e1000_setup_link(struct e1000_hw *hw)
  983. {
  984. uint32_t ctrl_ext;
  985. int32_t ret_val;
  986. uint16_t eeprom_data;
  987. DEBUGFUNC("e1000_setup_link");
  988. /* In the case of the phy reset being blocked, we already have a link.
  989. * We do not have to set it up again. */
  990. if (e1000_check_phy_reset_block(hw))
  991. return E1000_SUCCESS;
  992. /* Read and store word 0x0F of the EEPROM. This word contains bits
  993. * that determine the hardware's default PAUSE (flow control) mode,
  994. * a bit that determines whether the HW defaults to enabling or
  995. * disabling auto-negotiation, and the direction of the
  996. * SW defined pins. If there is no SW over-ride of the flow
  997. * control setting, then the variable hw->fc will
  998. * be initialized based on a value in the EEPROM.
  999. */
  1000. if (hw->fc == E1000_FC_DEFAULT) {
  1001. switch (hw->mac_type) {
  1002. case e1000_ich8lan:
  1003. case e1000_82573:
  1004. hw->fc = E1000_FC_FULL;
  1005. break;
  1006. default:
  1007. ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
  1008. 1, &eeprom_data);
  1009. if (ret_val) {
  1010. DEBUGOUT("EEPROM Read Error\n");
  1011. return -E1000_ERR_EEPROM;
  1012. }
  1013. if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
  1014. hw->fc = E1000_FC_NONE;
  1015. else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
  1016. EEPROM_WORD0F_ASM_DIR)
  1017. hw->fc = E1000_FC_TX_PAUSE;
  1018. else
  1019. hw->fc = E1000_FC_FULL;
  1020. break;
  1021. }
  1022. }
  1023. /* We want to save off the original Flow Control configuration just
  1024. * in case we get disconnected and then reconnected into a different
  1025. * hub or switch with different Flow Control capabilities.
  1026. */
  1027. if (hw->mac_type == e1000_82542_rev2_0)
  1028. hw->fc &= (~E1000_FC_TX_PAUSE);
  1029. if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
  1030. hw->fc &= (~E1000_FC_RX_PAUSE);
  1031. hw->original_fc = hw->fc;
  1032. DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
  1033. /* Take the 4 bits from EEPROM word 0x0F that determine the initial
  1034. * polarity value for the SW controlled pins, and setup the
  1035. * Extended Device Control reg with that info.
  1036. * This is needed because one of the SW controlled pins is used for
  1037. * signal detection. So this should be done before e1000_setup_pcs_link()
  1038. * or e1000_phy_setup() is called.
  1039. */
  1040. if (hw->mac_type == e1000_82543) {
  1041. ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
  1042. 1, &eeprom_data);
  1043. if (ret_val) {
  1044. DEBUGOUT("EEPROM Read Error\n");
  1045. return -E1000_ERR_EEPROM;
  1046. }
  1047. ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
  1048. SWDPIO__EXT_SHIFT);
  1049. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1050. }
  1051. /* Call the necessary subroutine to configure the link. */
  1052. ret_val = (hw->media_type == e1000_media_type_copper) ?
  1053. e1000_setup_copper_link(hw) :
  1054. e1000_setup_fiber_serdes_link(hw);
  1055. /* Initialize the flow control address, type, and PAUSE timer
  1056. * registers to their default values. This is done even if flow
  1057. * control is disabled, because it does not hurt anything to
  1058. * initialize these registers.
  1059. */
  1060. DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
  1061. /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
  1062. if (hw->mac_type != e1000_ich8lan) {
  1063. E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
  1064. E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
  1065. E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
  1066. }
  1067. E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
  1068. /* Set the flow control receive threshold registers. Normally,
  1069. * these registers will be set to a default threshold that may be
  1070. * adjusted later by the driver's runtime code. However, if the
  1071. * ability to transmit pause frames in not enabled, then these
  1072. * registers will be set to 0.
  1073. */
  1074. if (!(hw->fc & E1000_FC_TX_PAUSE)) {
  1075. E1000_WRITE_REG(hw, FCRTL, 0);
  1076. E1000_WRITE_REG(hw, FCRTH, 0);
  1077. } else {
  1078. /* We need to set up the Receive Threshold high and low water marks
  1079. * as well as (optionally) enabling the transmission of XON frames.
  1080. */
  1081. if (hw->fc_send_xon) {
  1082. E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
  1083. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1084. } else {
  1085. E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
  1086. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1087. }
  1088. }
  1089. return ret_val;
  1090. }
  1091. /******************************************************************************
  1092. * Sets up link for a fiber based or serdes based adapter
  1093. *
  1094. * hw - Struct containing variables accessed by shared code
  1095. *
  1096. * Manipulates Physical Coding Sublayer functions in order to configure
  1097. * link. Assumes the hardware has been previously reset and the transmitter
  1098. * and receiver are not enabled.
  1099. *****************************************************************************/
  1100. static int32_t
  1101. e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
  1102. {
  1103. uint32_t ctrl;
  1104. uint32_t status;
  1105. uint32_t txcw = 0;
  1106. uint32_t i;
  1107. uint32_t signal = 0;
  1108. int32_t ret_val;
  1109. DEBUGFUNC("e1000_setup_fiber_serdes_link");
  1110. /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
  1111. * until explicitly turned off or a power cycle is performed. A read to
  1112. * the register does not indicate its status. Therefore, we ensure
  1113. * loopback mode is disabled during initialization.
  1114. */
  1115. if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
  1116. E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
  1117. /* On adapters with a MAC newer than 82544, SWDP 1 will be
  1118. * set when the optics detect a signal. On older adapters, it will be
  1119. * cleared when there is a signal. This applies to fiber media only.
  1120. * If we're on serdes media, adjust the output amplitude to value
  1121. * set in the EEPROM.
  1122. */
  1123. ctrl = E1000_READ_REG(hw, CTRL);
  1124. if (hw->media_type == e1000_media_type_fiber)
  1125. signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
  1126. ret_val = e1000_adjust_serdes_amplitude(hw);
  1127. if (ret_val)
  1128. return ret_val;
  1129. /* Take the link out of reset */
  1130. ctrl &= ~(E1000_CTRL_LRST);
  1131. /* Adjust VCO speed to improve BER performance */
  1132. ret_val = e1000_set_vco_speed(hw);
  1133. if (ret_val)
  1134. return ret_val;
  1135. e1000_config_collision_dist(hw);
  1136. /* Check for a software override of the flow control settings, and setup
  1137. * the device accordingly. If auto-negotiation is enabled, then software
  1138. * will have to set the "PAUSE" bits to the correct value in the Tranmsit
  1139. * Config Word Register (TXCW) and re-start auto-negotiation. However, if
  1140. * auto-negotiation is disabled, then software will have to manually
  1141. * configure the two flow control enable bits in the CTRL register.
  1142. *
  1143. * The possible values of the "fc" parameter are:
  1144. * 0: Flow control is completely disabled
  1145. * 1: Rx flow control is enabled (we can receive pause frames, but
  1146. * not send pause frames).
  1147. * 2: Tx flow control is enabled (we can send pause frames but we do
  1148. * not support receiving pause frames).
  1149. * 3: Both Rx and TX flow control (symmetric) are enabled.
  1150. */
  1151. switch (hw->fc) {
  1152. case E1000_FC_NONE:
  1153. /* Flow control is completely disabled by a software over-ride. */
  1154. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
  1155. break;
  1156. case E1000_FC_RX_PAUSE:
  1157. /* RX Flow control is enabled and TX Flow control is disabled by a
  1158. * software over-ride. Since there really isn't a way to advertise
  1159. * that we are capable of RX Pause ONLY, we will advertise that we
  1160. * support both symmetric and asymmetric RX PAUSE. Later, we will
  1161. * disable the adapter's ability to send PAUSE frames.
  1162. */
  1163. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  1164. break;
  1165. case E1000_FC_TX_PAUSE:
  1166. /* TX Flow control is enabled, and RX Flow control is disabled, by a
  1167. * software over-ride.
  1168. */
  1169. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
  1170. break;
  1171. case E1000_FC_FULL:
  1172. /* Flow control (both RX and TX) is enabled by a software over-ride. */
  1173. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  1174. break;
  1175. default:
  1176. DEBUGOUT("Flow control param set incorrectly\n");
  1177. return -E1000_ERR_CONFIG;
  1178. break;
  1179. }
  1180. /* Since auto-negotiation is enabled, take the link out of reset (the link
  1181. * will be in reset, because we previously reset the chip). This will
  1182. * restart auto-negotiation. If auto-neogtiation is successful then the
  1183. * link-up status bit will be set and the flow control enable bits (RFCE
  1184. * and TFCE) will be set according to their negotiated value.
  1185. */
  1186. DEBUGOUT("Auto-negotiation enabled\n");
  1187. E1000_WRITE_REG(hw, TXCW, txcw);
  1188. E1000_WRITE_REG(hw, CTRL, ctrl);
  1189. E1000_WRITE_FLUSH(hw);
  1190. hw->txcw = txcw;
  1191. msleep(1);
  1192. /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
  1193. * indication in the Device Status Register. Time-out if a link isn't
  1194. * seen in 500 milliseconds seconds (Auto-negotiation should complete in
  1195. * less than 500 milliseconds even if the other end is doing it in SW).
  1196. * For internal serdes, we just assume a signal is present, then poll.
  1197. */
  1198. if (hw->media_type == e1000_media_type_internal_serdes ||
  1199. (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
  1200. DEBUGOUT("Looking for Link\n");
  1201. for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
  1202. msleep(10);
  1203. status = E1000_READ_REG(hw, STATUS);
  1204. if (status & E1000_STATUS_LU) break;
  1205. }
  1206. if (i == (LINK_UP_TIMEOUT / 10)) {
  1207. DEBUGOUT("Never got a valid link from auto-neg!!!\n");
  1208. hw->autoneg_failed = 1;
  1209. /* AutoNeg failed to achieve a link, so we'll call
  1210. * e1000_check_for_link. This routine will force the link up if
  1211. * we detect a signal. This will allow us to communicate with
  1212. * non-autonegotiating link partners.
  1213. */
  1214. ret_val = e1000_check_for_link(hw);
  1215. if (ret_val) {
  1216. DEBUGOUT("Error while checking for link\n");
  1217. return ret_val;
  1218. }
  1219. hw->autoneg_failed = 0;
  1220. } else {
  1221. hw->autoneg_failed = 0;
  1222. DEBUGOUT("Valid Link Found\n");
  1223. }
  1224. } else {
  1225. DEBUGOUT("No Signal Detected\n");
  1226. }
  1227. return E1000_SUCCESS;
  1228. }
  1229. /******************************************************************************
  1230. * Make sure we have a valid PHY and change PHY mode before link setup.
  1231. *
  1232. * hw - Struct containing variables accessed by shared code
  1233. ******************************************************************************/
  1234. static int32_t
  1235. e1000_copper_link_preconfig(struct e1000_hw *hw)
  1236. {
  1237. uint32_t ctrl;
  1238. int32_t ret_val;
  1239. uint16_t phy_data;
  1240. DEBUGFUNC("e1000_copper_link_preconfig");
  1241. ctrl = E1000_READ_REG(hw, CTRL);
  1242. /* With 82543, we need to force speed and duplex on the MAC equal to what
  1243. * the PHY speed and duplex configuration is. In addition, we need to
  1244. * perform a hardware reset on the PHY to take it out of reset.
  1245. */
  1246. if (hw->mac_type > e1000_82543) {
  1247. ctrl |= E1000_CTRL_SLU;
  1248. ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  1249. E1000_WRITE_REG(hw, CTRL, ctrl);
  1250. } else {
  1251. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
  1252. E1000_WRITE_REG(hw, CTRL, ctrl);
  1253. ret_val = e1000_phy_hw_reset(hw);
  1254. if (ret_val)
  1255. return ret_val;
  1256. }
  1257. /* Make sure we have a valid PHY */
  1258. ret_val = e1000_detect_gig_phy(hw);
  1259. if (ret_val) {
  1260. DEBUGOUT("Error, did not detect valid phy.\n");
  1261. return ret_val;
  1262. }
  1263. DEBUGOUT1("Phy ID = %#08lx \n", hw->phy_id);
  1264. /* Set PHY to class A mode (if necessary) */
  1265. ret_val = e1000_set_phy_mode(hw);
  1266. if (ret_val)
  1267. return ret_val;
  1268. if ((hw->mac_type == e1000_82545_rev_3) ||
  1269. (hw->mac_type == e1000_82546_rev_3)) {
  1270. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  1271. phy_data |= 0x00000008;
  1272. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  1273. }
  1274. if (hw->mac_type <= e1000_82543 ||
  1275. hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
  1276. hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
  1277. hw->phy_reset_disable = FALSE;
  1278. return E1000_SUCCESS;
  1279. }
  1280. /********************************************************************
  1281. * Copper link setup for e1000_phy_igp series.
  1282. *
  1283. * hw - Struct containing variables accessed by shared code
  1284. *********************************************************************/
  1285. static int32_t
  1286. e1000_copper_link_igp_setup(struct e1000_hw *hw)
  1287. {
  1288. uint32_t led_ctrl;
  1289. int32_t ret_val;
  1290. uint16_t phy_data;
  1291. DEBUGFUNC("e1000_copper_link_igp_setup");
  1292. if (hw->phy_reset_disable)
  1293. return E1000_SUCCESS;
  1294. ret_val = e1000_phy_reset(hw);
  1295. if (ret_val) {
  1296. DEBUGOUT("Error Resetting the PHY\n");
  1297. return ret_val;
  1298. }
  1299. /* Wait 15ms for MAC to configure PHY from eeprom settings */
  1300. msleep(15);
  1301. if (hw->mac_type != e1000_ich8lan) {
  1302. /* Configure activity LED after PHY reset */
  1303. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  1304. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  1305. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  1306. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  1307. }
  1308. /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
  1309. if (hw->phy_type == e1000_phy_igp) {
  1310. /* disable lplu d3 during driver init */
  1311. ret_val = e1000_set_d3_lplu_state(hw, FALSE);
  1312. if (ret_val) {
  1313. DEBUGOUT("Error Disabling LPLU D3\n");
  1314. return ret_val;
  1315. }
  1316. }
  1317. /* disable lplu d0 during driver init */
  1318. ret_val = e1000_set_d0_lplu_state(hw, FALSE);
  1319. if (ret_val) {
  1320. DEBUGOUT("Error Disabling LPLU D0\n");
  1321. return ret_val;
  1322. }
  1323. /* Configure mdi-mdix settings */
  1324. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
  1325. if (ret_val)
  1326. return ret_val;
  1327. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  1328. hw->dsp_config_state = e1000_dsp_config_disabled;
  1329. /* Force MDI for earlier revs of the IGP PHY */
  1330. phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
  1331. hw->mdix = 1;
  1332. } else {
  1333. hw->dsp_config_state = e1000_dsp_config_enabled;
  1334. phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
  1335. switch (hw->mdix) {
  1336. case 1:
  1337. phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
  1338. break;
  1339. case 2:
  1340. phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
  1341. break;
  1342. case 0:
  1343. default:
  1344. phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
  1345. break;
  1346. }
  1347. }
  1348. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
  1349. if (ret_val)
  1350. return ret_val;
  1351. /* set auto-master slave resolution settings */
  1352. if (hw->autoneg) {
  1353. e1000_ms_type phy_ms_setting = hw->master_slave;
  1354. if (hw->ffe_config_state == e1000_ffe_config_active)
  1355. hw->ffe_config_state = e1000_ffe_config_enabled;
  1356. if (hw->dsp_config_state == e1000_dsp_config_activated)
  1357. hw->dsp_config_state = e1000_dsp_config_enabled;
  1358. /* when autonegotiation advertisment is only 1000Mbps then we
  1359. * should disable SmartSpeed and enable Auto MasterSlave
  1360. * resolution as hardware default. */
  1361. if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
  1362. /* Disable SmartSpeed */
  1363. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  1364. &phy_data);
  1365. if (ret_val)
  1366. return ret_val;
  1367. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  1368. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  1369. phy_data);
  1370. if (ret_val)
  1371. return ret_val;
  1372. /* Set auto Master/Slave resolution process */
  1373. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
  1374. if (ret_val)
  1375. return ret_val;
  1376. phy_data &= ~CR_1000T_MS_ENABLE;
  1377. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
  1378. if (ret_val)
  1379. return ret_val;
  1380. }
  1381. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
  1382. if (ret_val)
  1383. return ret_val;
  1384. /* load defaults for future use */
  1385. hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
  1386. ((phy_data & CR_1000T_MS_VALUE) ?
  1387. e1000_ms_force_master :
  1388. e1000_ms_force_slave) :
  1389. e1000_ms_auto;
  1390. switch (phy_ms_setting) {
  1391. case e1000_ms_force_master:
  1392. phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
  1393. break;
  1394. case e1000_ms_force_slave:
  1395. phy_data |= CR_1000T_MS_ENABLE;
  1396. phy_data &= ~(CR_1000T_MS_VALUE);
  1397. break;
  1398. case e1000_ms_auto:
  1399. phy_data &= ~CR_1000T_MS_ENABLE;
  1400. default:
  1401. break;
  1402. }
  1403. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
  1404. if (ret_val)
  1405. return ret_val;
  1406. }
  1407. return E1000_SUCCESS;
  1408. }
  1409. /********************************************************************
  1410. * Copper link setup for e1000_phy_gg82563 series.
  1411. *
  1412. * hw - Struct containing variables accessed by shared code
  1413. *********************************************************************/
  1414. static int32_t
  1415. e1000_copper_link_ggp_setup(struct e1000_hw *hw)
  1416. {
  1417. int32_t ret_val;
  1418. uint16_t phy_data;
  1419. uint32_t reg_data;
  1420. DEBUGFUNC("e1000_copper_link_ggp_setup");
  1421. if (!hw->phy_reset_disable) {
  1422. /* Enable CRS on TX for half-duplex operation. */
  1423. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
  1424. &phy_data);
  1425. if (ret_val)
  1426. return ret_val;
  1427. phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
  1428. /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
  1429. phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
  1430. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
  1431. phy_data);
  1432. if (ret_val)
  1433. return ret_val;
  1434. /* Options:
  1435. * MDI/MDI-X = 0 (default)
  1436. * 0 - Auto for all speeds
  1437. * 1 - MDI mode
  1438. * 2 - MDI-X mode
  1439. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  1440. */
  1441. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
  1442. if (ret_val)
  1443. return ret_val;
  1444. phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
  1445. switch (hw->mdix) {
  1446. case 1:
  1447. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
  1448. break;
  1449. case 2:
  1450. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
  1451. break;
  1452. case 0:
  1453. default:
  1454. phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
  1455. break;
  1456. }
  1457. /* Options:
  1458. * disable_polarity_correction = 0 (default)
  1459. * Automatic Correction for Reversed Cable Polarity
  1460. * 0 - Disabled
  1461. * 1 - Enabled
  1462. */
  1463. phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
  1464. if (hw->disable_polarity_correction == 1)
  1465. phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
  1466. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
  1467. if (ret_val)
  1468. return ret_val;
  1469. /* SW Reset the PHY so all changes take effect */
  1470. ret_val = e1000_phy_reset(hw);
  1471. if (ret_val) {
  1472. DEBUGOUT("Error Resetting the PHY\n");
  1473. return ret_val;
  1474. }
  1475. } /* phy_reset_disable */
  1476. if (hw->mac_type == e1000_80003es2lan) {
  1477. /* Bypass RX and TX FIFO's */
  1478. ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
  1479. E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
  1480. E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
  1481. if (ret_val)
  1482. return ret_val;
  1483. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
  1484. if (ret_val)
  1485. return ret_val;
  1486. phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
  1487. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
  1488. if (ret_val)
  1489. return ret_val;
  1490. reg_data = E1000_READ_REG(hw, CTRL_EXT);
  1491. reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
  1492. E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
  1493. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
  1494. &phy_data);
  1495. if (ret_val)
  1496. return ret_val;
  1497. /* Do not init these registers when the HW is in IAMT mode, since the
  1498. * firmware will have already initialized them. We only initialize
  1499. * them if the HW is not in IAMT mode.
  1500. */
  1501. if (e1000_check_mng_mode(hw) == FALSE) {
  1502. /* Enable Electrical Idle on the PHY */
  1503. phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
  1504. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
  1505. phy_data);
  1506. if (ret_val)
  1507. return ret_val;
  1508. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
  1509. &phy_data);
  1510. if (ret_val)
  1511. return ret_val;
  1512. phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  1513. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
  1514. phy_data);
  1515. if (ret_val)
  1516. return ret_val;
  1517. }
  1518. /* Workaround: Disable padding in Kumeran interface in the MAC
  1519. * and in the PHY to avoid CRC errors.
  1520. */
  1521. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
  1522. &phy_data);
  1523. if (ret_val)
  1524. return ret_val;
  1525. phy_data |= GG82563_ICR_DIS_PADDING;
  1526. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
  1527. phy_data);
  1528. if (ret_val)
  1529. return ret_val;
  1530. }
  1531. return E1000_SUCCESS;
  1532. }
  1533. /********************************************************************
  1534. * Copper link setup for e1000_phy_m88 series.
  1535. *
  1536. * hw - Struct containing variables accessed by shared code
  1537. *********************************************************************/
  1538. static int32_t
  1539. e1000_copper_link_mgp_setup(struct e1000_hw *hw)
  1540. {
  1541. int32_t ret_val;
  1542. uint16_t phy_data;
  1543. DEBUGFUNC("e1000_copper_link_mgp_setup");
  1544. if (hw->phy_reset_disable)
  1545. return E1000_SUCCESS;
  1546. /* Enable CRS on TX. This must be set for half-duplex operation. */
  1547. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  1548. if (ret_val)
  1549. return ret_val;
  1550. phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  1551. /* Options:
  1552. * MDI/MDI-X = 0 (default)
  1553. * 0 - Auto for all speeds
  1554. * 1 - MDI mode
  1555. * 2 - MDI-X mode
  1556. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  1557. */
  1558. phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  1559. switch (hw->mdix) {
  1560. case 1:
  1561. phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
  1562. break;
  1563. case 2:
  1564. phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
  1565. break;
  1566. case 3:
  1567. phy_data |= M88E1000_PSCR_AUTO_X_1000T;
  1568. break;
  1569. case 0:
  1570. default:
  1571. phy_data |= M88E1000_PSCR_AUTO_X_MODE;
  1572. break;
  1573. }
  1574. /* Options:
  1575. * disable_polarity_correction = 0 (default)
  1576. * Automatic Correction for Reversed Cable Polarity
  1577. * 0 - Disabled
  1578. * 1 - Enabled
  1579. */
  1580. phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
  1581. if (hw->disable_polarity_correction == 1)
  1582. phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
  1583. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  1584. if (ret_val)
  1585. return ret_val;
  1586. if (hw->phy_revision < M88E1011_I_REV_4) {
  1587. /* Force TX_CLK in the Extended PHY Specific Control Register
  1588. * to 25MHz clock.
  1589. */
  1590. ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
  1591. if (ret_val)
  1592. return ret_val;
  1593. phy_data |= M88E1000_EPSCR_TX_CLK_25;
  1594. if ((hw->phy_revision == E1000_REVISION_2) &&
  1595. (hw->phy_id == M88E1111_I_PHY_ID)) {
  1596. /* Vidalia Phy, set the downshift counter to 5x */
  1597. phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
  1598. phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
  1599. ret_val = e1000_write_phy_reg(hw,
  1600. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  1601. if (ret_val)
  1602. return ret_val;
  1603. } else {
  1604. /* Configure Master and Slave downshift values */
  1605. phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
  1606. M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
  1607. phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
  1608. M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
  1609. ret_val = e1000_write_phy_reg(hw,
  1610. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  1611. if (ret_val)
  1612. return ret_val;
  1613. }
  1614. }
  1615. /* SW Reset the PHY so all changes take effect */
  1616. ret_val = e1000_phy_reset(hw);
  1617. if (ret_val) {
  1618. DEBUGOUT("Error Resetting the PHY\n");
  1619. return ret_val;
  1620. }
  1621. return E1000_SUCCESS;
  1622. }
  1623. /********************************************************************
  1624. * Setup auto-negotiation and flow control advertisements,
  1625. * and then perform auto-negotiation.
  1626. *
  1627. * hw - Struct containing variables accessed by shared code
  1628. *********************************************************************/
  1629. static int32_t
  1630. e1000_copper_link_autoneg(struct e1000_hw *hw)
  1631. {
  1632. int32_t ret_val;
  1633. uint16_t phy_data;
  1634. DEBUGFUNC("e1000_copper_link_autoneg");
  1635. /* Perform some bounds checking on the hw->autoneg_advertised
  1636. * parameter. If this variable is zero, then set it to the default.
  1637. */
  1638. hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
  1639. /* If autoneg_advertised is zero, we assume it was not defaulted
  1640. * by the calling code so we set to advertise full capability.
  1641. */
  1642. if (hw->autoneg_advertised == 0)
  1643. hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  1644. /* IFE phy only supports 10/100 */
  1645. if (hw->phy_type == e1000_phy_ife)
  1646. hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
  1647. DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
  1648. ret_val = e1000_phy_setup_autoneg(hw);
  1649. if (ret_val) {
  1650. DEBUGOUT("Error Setting up Auto-Negotiation\n");
  1651. return ret_val;
  1652. }
  1653. DEBUGOUT("Restarting Auto-Neg\n");
  1654. /* Restart auto-negotiation by setting the Auto Neg Enable bit and
  1655. * the Auto Neg Restart bit in the PHY control register.
  1656. */
  1657. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  1658. if (ret_val)
  1659. return ret_val;
  1660. phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
  1661. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  1662. if (ret_val)
  1663. return ret_val;
  1664. /* Does the user want to wait for Auto-Neg to complete here, or
  1665. * check at a later time (for example, callback routine).
  1666. */
  1667. if (hw->wait_autoneg_complete) {
  1668. ret_val = e1000_wait_autoneg(hw);
  1669. if (ret_val) {
  1670. DEBUGOUT("Error while waiting for autoneg to complete\n");
  1671. return ret_val;
  1672. }
  1673. }
  1674. hw->get_link_status = TRUE;
  1675. return E1000_SUCCESS;
  1676. }
  1677. /******************************************************************************
  1678. * Config the MAC and the PHY after link is up.
  1679. * 1) Set up the MAC to the current PHY speed/duplex
  1680. * if we are on 82543. If we
  1681. * are on newer silicon, we only need to configure
  1682. * collision distance in the Transmit Control Register.
  1683. * 2) Set up flow control on the MAC to that established with
  1684. * the link partner.
  1685. * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
  1686. *
  1687. * hw - Struct containing variables accessed by shared code
  1688. ******************************************************************************/
  1689. static int32_t
  1690. e1000_copper_link_postconfig(struct e1000_hw *hw)
  1691. {
  1692. int32_t ret_val;
  1693. DEBUGFUNC("e1000_copper_link_postconfig");
  1694. if (hw->mac_type >= e1000_82544) {
  1695. e1000_config_collision_dist(hw);
  1696. } else {
  1697. ret_val = e1000_config_mac_to_phy(hw);
  1698. if (ret_val) {
  1699. DEBUGOUT("Error configuring MAC to PHY settings\n");
  1700. return ret_val;
  1701. }
  1702. }
  1703. ret_val = e1000_config_fc_after_link_up(hw);
  1704. if (ret_val) {
  1705. DEBUGOUT("Error Configuring Flow Control\n");
  1706. return ret_val;
  1707. }
  1708. /* Config DSP to improve Giga link quality */
  1709. if (hw->phy_type == e1000_phy_igp) {
  1710. ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
  1711. if (ret_val) {
  1712. DEBUGOUT("Error Configuring DSP after link up\n");
  1713. return ret_val;
  1714. }
  1715. }
  1716. return E1000_SUCCESS;
  1717. }
  1718. /******************************************************************************
  1719. * Detects which PHY is present and setup the speed and duplex
  1720. *
  1721. * hw - Struct containing variables accessed by shared code
  1722. ******************************************************************************/
  1723. static int32_t
  1724. e1000_setup_copper_link(struct e1000_hw *hw)
  1725. {
  1726. int32_t ret_val;
  1727. uint16_t i;
  1728. uint16_t phy_data;
  1729. uint16_t reg_data;
  1730. DEBUGFUNC("e1000_setup_copper_link");
  1731. switch (hw->mac_type) {
  1732. case e1000_80003es2lan:
  1733. case e1000_ich8lan:
  1734. /* Set the mac to wait the maximum time between each
  1735. * iteration and increase the max iterations when
  1736. * polling the phy; this fixes erroneous timeouts at 10Mbps. */
  1737. ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
  1738. if (ret_val)
  1739. return ret_val;
  1740. ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
  1741. if (ret_val)
  1742. return ret_val;
  1743. reg_data |= 0x3F;
  1744. ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
  1745. if (ret_val)
  1746. return ret_val;
  1747. default:
  1748. break;
  1749. }
  1750. /* Check if it is a valid PHY and set PHY mode if necessary. */
  1751. ret_val = e1000_copper_link_preconfig(hw);
  1752. if (ret_val)
  1753. return ret_val;
  1754. switch (hw->mac_type) {
  1755. case e1000_80003es2lan:
  1756. /* Kumeran registers are written-only */
  1757. reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
  1758. reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
  1759. ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
  1760. reg_data);
  1761. if (ret_val)
  1762. return ret_val;
  1763. break;
  1764. default:
  1765. break;
  1766. }
  1767. if (hw->phy_type == e1000_phy_igp ||
  1768. hw->phy_type == e1000_phy_igp_3 ||
  1769. hw->phy_type == e1000_phy_igp_2) {
  1770. ret_val = e1000_copper_link_igp_setup(hw);
  1771. if (ret_val)
  1772. return ret_val;
  1773. } else if (hw->phy_type == e1000_phy_m88) {
  1774. ret_val = e1000_copper_link_mgp_setup(hw);
  1775. if (ret_val)
  1776. return ret_val;
  1777. } else if (hw->phy_type == e1000_phy_gg82563) {
  1778. ret_val = e1000_copper_link_ggp_setup(hw);
  1779. if (ret_val)
  1780. return ret_val;
  1781. }
  1782. if (hw->autoneg) {
  1783. /* Setup autoneg and flow control advertisement
  1784. * and perform autonegotiation */
  1785. ret_val = e1000_copper_link_autoneg(hw);
  1786. if (ret_val)
  1787. return ret_val;
  1788. } else {
  1789. /* PHY will be set to 10H, 10F, 100H,or 100F
  1790. * depending on value from forced_speed_duplex. */
  1791. DEBUGOUT("Forcing speed and duplex\n");
  1792. ret_val = e1000_phy_force_speed_duplex(hw);
  1793. if (ret_val) {
  1794. DEBUGOUT("Error Forcing Speed and Duplex\n");
  1795. return ret_val;
  1796. }
  1797. }
  1798. /* Check link status. Wait up to 100 microseconds for link to become
  1799. * valid.
  1800. */
  1801. for (i = 0; i < 10; i++) {
  1802. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  1803. if (ret_val)
  1804. return ret_val;
  1805. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  1806. if (ret_val)
  1807. return ret_val;
  1808. if (phy_data & MII_SR_LINK_STATUS) {
  1809. /* Config the MAC and PHY after link is up */
  1810. ret_val = e1000_copper_link_postconfig(hw);
  1811. if (ret_val)
  1812. return ret_val;
  1813. DEBUGOUT("Valid link established!!!\n");
  1814. return E1000_SUCCESS;
  1815. }
  1816. udelay(10);
  1817. }
  1818. DEBUGOUT("Unable to establish link!!!\n");
  1819. return E1000_SUCCESS;
  1820. }
  1821. /******************************************************************************
  1822. * Configure the MAC-to-PHY interface for 10/100Mbps
  1823. *
  1824. * hw - Struct containing variables accessed by shared code
  1825. ******************************************************************************/
  1826. static int32_t
  1827. e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
  1828. {
  1829. int32_t ret_val = E1000_SUCCESS;
  1830. uint32_t tipg;
  1831. uint16_t reg_data;
  1832. DEBUGFUNC("e1000_configure_kmrn_for_10_100");
  1833. reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
  1834. ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
  1835. reg_data);
  1836. if (ret_val)
  1837. return ret_val;
  1838. /* Configure Transmit Inter-Packet Gap */
  1839. tipg = E1000_READ_REG(hw, TIPG);
  1840. tipg &= ~E1000_TIPG_IPGT_MASK;
  1841. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
  1842. E1000_WRITE_REG(hw, TIPG, tipg);
  1843. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  1844. if (ret_val)
  1845. return ret_val;
  1846. if (duplex == HALF_DUPLEX)
  1847. reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
  1848. else
  1849. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  1850. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  1851. return ret_val;
  1852. }
  1853. static int32_t
  1854. e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
  1855. {
  1856. int32_t ret_val = E1000_SUCCESS;
  1857. uint16_t reg_data;
  1858. uint32_t tipg;
  1859. DEBUGFUNC("e1000_configure_kmrn_for_1000");
  1860. reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
  1861. ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
  1862. reg_data);
  1863. if (ret_val)
  1864. return ret_val;
  1865. /* Configure Transmit Inter-Packet Gap */
  1866. tipg = E1000_READ_REG(hw, TIPG);
  1867. tipg &= ~E1000_TIPG_IPGT_MASK;
  1868. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  1869. E1000_WRITE_REG(hw, TIPG, tipg);
  1870. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  1871. if (ret_val)
  1872. return ret_val;
  1873. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  1874. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  1875. return ret_val;
  1876. }
  1877. /******************************************************************************
  1878. * Configures PHY autoneg and flow control advertisement settings
  1879. *
  1880. * hw - Struct containing variables accessed by shared code
  1881. ******************************************************************************/
  1882. int32_t
  1883. e1000_phy_setup_autoneg(struct e1000_hw *hw)
  1884. {
  1885. int32_t ret_val;
  1886. uint16_t mii_autoneg_adv_reg;
  1887. uint16_t mii_1000t_ctrl_reg;
  1888. DEBUGFUNC("e1000_phy_setup_autoneg");
  1889. /* Read the MII Auto-Neg Advertisement Register (Address 4). */
  1890. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
  1891. if (ret_val)
  1892. return ret_val;
  1893. if (hw->phy_type != e1000_phy_ife) {
  1894. /* Read the MII 1000Base-T Control Register (Address 9). */
  1895. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
  1896. if (ret_val)
  1897. return ret_val;
  1898. } else
  1899. mii_1000t_ctrl_reg=0;
  1900. /* Need to parse both autoneg_advertised and fc and set up
  1901. * the appropriate PHY registers. First we will parse for
  1902. * autoneg_advertised software override. Since we can advertise
  1903. * a plethora of combinations, we need to check each bit
  1904. * individually.
  1905. */
  1906. /* First we clear all the 10/100 mb speed bits in the Auto-Neg
  1907. * Advertisement Register (Address 4) and the 1000 mb speed bits in
  1908. * the 1000Base-T Control Register (Address 9).
  1909. */
  1910. mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
  1911. mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
  1912. DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
  1913. /* Do we want to advertise 10 Mb Half Duplex? */
  1914. if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
  1915. DEBUGOUT("Advertise 10mb Half duplex\n");
  1916. mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
  1917. }
  1918. /* Do we want to advertise 10 Mb Full Duplex? */
  1919. if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
  1920. DEBUGOUT("Advertise 10mb Full duplex\n");
  1921. mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
  1922. }
  1923. /* Do we want to advertise 100 Mb Half Duplex? */
  1924. if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
  1925. DEBUGOUT("Advertise 100mb Half duplex\n");
  1926. mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
  1927. }
  1928. /* Do we want to advertise 100 Mb Full Duplex? */
  1929. if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
  1930. DEBUGOUT("Advertise 100mb Full duplex\n");
  1931. mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
  1932. }
  1933. /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
  1934. if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
  1935. DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
  1936. }
  1937. /* Do we want to advertise 1000 Mb Full Duplex? */
  1938. if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
  1939. DEBUGOUT("Advertise 1000mb Full duplex\n");
  1940. mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
  1941. if (hw->phy_type == e1000_phy_ife) {
  1942. DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
  1943. }
  1944. }
  1945. /* Check for a software override of the flow control settings, and
  1946. * setup the PHY advertisement registers accordingly. If
  1947. * auto-negotiation is enabled, then software will have to set the
  1948. * "PAUSE" bits to the correct value in the Auto-Negotiation
  1949. * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
  1950. *
  1951. * The possible values of the "fc" parameter are:
  1952. * 0: Flow control is completely disabled
  1953. * 1: Rx flow control is enabled (we can receive pause frames
  1954. * but not send pause frames).
  1955. * 2: Tx flow control is enabled (we can send pause frames
  1956. * but we do not support receiving pause frames).
  1957. * 3: Both Rx and TX flow control (symmetric) are enabled.
  1958. * other: No software override. The flow control configuration
  1959. * in the EEPROM is used.
  1960. */
  1961. switch (hw->fc) {
  1962. case E1000_FC_NONE: /* 0 */
  1963. /* Flow control (RX & TX) is completely disabled by a
  1964. * software over-ride.
  1965. */
  1966. mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  1967. break;
  1968. case E1000_FC_RX_PAUSE: /* 1 */
  1969. /* RX Flow control is enabled, and TX Flow control is
  1970. * disabled, by a software over-ride.
  1971. */
  1972. /* Since there really isn't a way to advertise that we are
  1973. * capable of RX Pause ONLY, we will advertise that we
  1974. * support both symmetric and asymmetric RX PAUSE. Later
  1975. * (in e1000_config_fc_after_link_up) we will disable the
  1976. *hw's ability to send PAUSE frames.
  1977. */
  1978. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  1979. break;
  1980. case E1000_FC_TX_PAUSE: /* 2 */
  1981. /* TX Flow control is enabled, and RX Flow control is
  1982. * disabled, by a software over-ride.
  1983. */
  1984. mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
  1985. mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
  1986. break;
  1987. case E1000_FC_FULL: /* 3 */
  1988. /* Flow control (both RX and TX) is enabled by a software
  1989. * over-ride.
  1990. */
  1991. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  1992. break;
  1993. default:
  1994. DEBUGOUT("Flow control param set incorrectly\n");
  1995. return -E1000_ERR_CONFIG;
  1996. }
  1997. ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
  1998. if (ret_val)
  1999. return ret_val;
  2000. DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
  2001. if (hw->phy_type != e1000_phy_ife) {
  2002. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
  2003. if (ret_val)
  2004. return ret_val;
  2005. }
  2006. return E1000_SUCCESS;
  2007. }
  2008. /******************************************************************************
  2009. * Force PHY speed and duplex settings to hw->forced_speed_duplex
  2010. *
  2011. * hw - Struct containing variables accessed by shared code
  2012. ******************************************************************************/
  2013. static int32_t
  2014. e1000_phy_force_speed_duplex(struct e1000_hw *hw)
  2015. {
  2016. uint32_t ctrl;
  2017. int32_t ret_val;
  2018. uint16_t mii_ctrl_reg;
  2019. uint16_t mii_status_reg;
  2020. uint16_t phy_data;
  2021. uint16_t i;
  2022. DEBUGFUNC("e1000_phy_force_speed_duplex");
  2023. /* Turn off Flow control if we are forcing speed and duplex. */
  2024. hw->fc = E1000_FC_NONE;
  2025. DEBUGOUT1("hw->fc = %d\n", hw->fc);
  2026. /* Read the Device Control Register. */
  2027. ctrl = E1000_READ_REG(hw, CTRL);
  2028. /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
  2029. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  2030. ctrl &= ~(DEVICE_SPEED_MASK);
  2031. /* Clear the Auto Speed Detect Enable bit. */
  2032. ctrl &= ~E1000_CTRL_ASDE;
  2033. /* Read the MII Control Register. */
  2034. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
  2035. if (ret_val)
  2036. return ret_val;
  2037. /* We need to disable autoneg in order to force link and duplex. */
  2038. mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
  2039. /* Are we forcing Full or Half Duplex? */
  2040. if (hw->forced_speed_duplex == e1000_100_full ||
  2041. hw->forced_speed_duplex == e1000_10_full) {
  2042. /* We want to force full duplex so we SET the full duplex bits in the
  2043. * Device and MII Control Registers.
  2044. */
  2045. ctrl |= E1000_CTRL_FD;
  2046. mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
  2047. DEBUGOUT("Full Duplex\n");
  2048. } else {
  2049. /* We want to force half duplex so we CLEAR the full duplex bits in
  2050. * the Device and MII Control Registers.
  2051. */
  2052. ctrl &= ~E1000_CTRL_FD;
  2053. mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
  2054. DEBUGOUT("Half Duplex\n");
  2055. }
  2056. /* Are we forcing 100Mbps??? */
  2057. if (hw->forced_speed_duplex == e1000_100_full ||
  2058. hw->forced_speed_duplex == e1000_100_half) {
  2059. /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
  2060. ctrl |= E1000_CTRL_SPD_100;
  2061. mii_ctrl_reg |= MII_CR_SPEED_100;
  2062. mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
  2063. DEBUGOUT("Forcing 100mb ");
  2064. } else {
  2065. /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
  2066. ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
  2067. mii_ctrl_reg |= MII_CR_SPEED_10;
  2068. mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
  2069. DEBUGOUT("Forcing 10mb ");
  2070. }
  2071. e1000_config_collision_dist(hw);
  2072. /* Write the configured values back to the Device Control Reg. */
  2073. E1000_WRITE_REG(hw, CTRL, ctrl);
  2074. if ((hw->phy_type == e1000_phy_m88) ||
  2075. (hw->phy_type == e1000_phy_gg82563)) {
  2076. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  2077. if (ret_val)
  2078. return ret_val;
  2079. /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
  2080. * forced whenever speed are duplex are forced.
  2081. */
  2082. phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  2083. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  2084. if (ret_val)
  2085. return ret_val;
  2086. DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
  2087. /* Need to reset the PHY or these changes will be ignored */
  2088. mii_ctrl_reg |= MII_CR_RESET;
  2089. /* Disable MDI-X support for 10/100 */
  2090. } else if (hw->phy_type == e1000_phy_ife) {
  2091. ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
  2092. if (ret_val)
  2093. return ret_val;
  2094. phy_data &= ~IFE_PMC_AUTO_MDIX;
  2095. phy_data &= ~IFE_PMC_FORCE_MDIX;
  2096. ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
  2097. if (ret_val)
  2098. return ret_val;
  2099. } else {
  2100. /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
  2101. * forced whenever speed or duplex are forced.
  2102. */
  2103. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
  2104. if (ret_val)
  2105. return ret_val;
  2106. phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
  2107. phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
  2108. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
  2109. if (ret_val)
  2110. return ret_val;
  2111. }
  2112. /* Write back the modified PHY MII control register. */
  2113. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
  2114. if (ret_val)
  2115. return ret_val;
  2116. udelay(1);
  2117. /* The wait_autoneg_complete flag may be a little misleading here.
  2118. * Since we are forcing speed and duplex, Auto-Neg is not enabled.
  2119. * But we do want to delay for a period while forcing only so we
  2120. * don't generate false No Link messages. So we will wait here
  2121. * only if the user has set wait_autoneg_complete to 1, which is
  2122. * the default.
  2123. */
  2124. if (hw->wait_autoneg_complete) {
  2125. /* We will wait for autoneg to complete. */
  2126. DEBUGOUT("Waiting for forced speed/duplex link.\n");
  2127. mii_status_reg = 0;
  2128. /* We will wait for autoneg to complete or 4.5 seconds to expire. */
  2129. for (i = PHY_FORCE_TIME; i > 0; i--) {
  2130. /* Read the MII Status Register and wait for Auto-Neg Complete bit
  2131. * to be set.
  2132. */
  2133. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
  2134. if (ret_val)
  2135. return ret_val;
  2136. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
  2137. if (ret_val)
  2138. return ret_val;
  2139. if (mii_status_reg & MII_SR_LINK_STATUS) break;
  2140. msleep(100);
  2141. }
  2142. if ((i == 0) &&
  2143. ((hw->phy_type == e1000_phy_m88) ||
  2144. (hw->phy_type == e1000_phy_gg82563))) {
  2145. /* We didn't get link. Reset the DSP and wait again for link. */
  2146. ret_val = e1000_phy_reset_dsp(hw);
  2147. if (ret_val) {
  2148. DEBUGOUT("Error Resetting PHY DSP\n");
  2149. return ret_val;
  2150. }
  2151. }
  2152. /* This loop will early-out if the link condition has been met. */
  2153. for (i = PHY_FORCE_TIME; i > 0; i--) {
  2154. if (mii_status_reg & MII_SR_LINK_STATUS) break;
  2155. msleep(100);
  2156. /* Read the MII Status Register and wait for Auto-Neg Complete bit
  2157. * to be set.
  2158. */
  2159. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
  2160. if (ret_val)
  2161. return ret_val;
  2162. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
  2163. if (ret_val)
  2164. return ret_val;
  2165. }
  2166. }
  2167. if (hw->phy_type == e1000_phy_m88) {
  2168. /* Because we reset the PHY above, we need to re-force TX_CLK in the
  2169. * Extended PHY Specific Control Register to 25MHz clock. This value
  2170. * defaults back to a 2.5MHz clock when the PHY is reset.
  2171. */
  2172. ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
  2173. if (ret_val)
  2174. return ret_val;
  2175. phy_data |= M88E1000_EPSCR_TX_CLK_25;
  2176. ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  2177. if (ret_val)
  2178. return ret_val;
  2179. /* In addition, because of the s/w reset above, we need to enable CRS on
  2180. * TX. This must be set for both full and half duplex operation.
  2181. */
  2182. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  2183. if (ret_val)
  2184. return ret_val;
  2185. phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  2186. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  2187. if (ret_val)
  2188. return ret_val;
  2189. if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
  2190. (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
  2191. hw->forced_speed_duplex == e1000_10_half)) {
  2192. ret_val = e1000_polarity_reversal_workaround(hw);
  2193. if (ret_val)
  2194. return ret_val;
  2195. }
  2196. } else if (hw->phy_type == e1000_phy_gg82563) {
  2197. /* The TX_CLK of the Extended PHY Specific Control Register defaults
  2198. * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
  2199. * we're not in a forced 10/duplex configuration. */
  2200. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
  2201. if (ret_val)
  2202. return ret_val;
  2203. phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
  2204. if ((hw->forced_speed_duplex == e1000_10_full) ||
  2205. (hw->forced_speed_duplex == e1000_10_half))
  2206. phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
  2207. else
  2208. phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
  2209. /* Also due to the reset, we need to enable CRS on Tx. */
  2210. phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
  2211. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
  2212. if (ret_val)
  2213. return ret_val;
  2214. }
  2215. return E1000_SUCCESS;
  2216. }
  2217. /******************************************************************************
  2218. * Sets the collision distance in the Transmit Control register
  2219. *
  2220. * hw - Struct containing variables accessed by shared code
  2221. *
  2222. * Link should have been established previously. Reads the speed and duplex
  2223. * information from the Device Status register.
  2224. ******************************************************************************/
  2225. void
  2226. e1000_config_collision_dist(struct e1000_hw *hw)
  2227. {
  2228. uint32_t tctl, coll_dist;
  2229. DEBUGFUNC("e1000_config_collision_dist");
  2230. if (hw->mac_type < e1000_82543)
  2231. coll_dist = E1000_COLLISION_DISTANCE_82542;
  2232. else
  2233. coll_dist = E1000_COLLISION_DISTANCE;
  2234. tctl = E1000_READ_REG(hw, TCTL);
  2235. tctl &= ~E1000_TCTL_COLD;
  2236. tctl |= coll_dist << E1000_COLD_SHIFT;
  2237. E1000_WRITE_REG(hw, TCTL, tctl);
  2238. E1000_WRITE_FLUSH(hw);
  2239. }
  2240. /******************************************************************************
  2241. * Sets MAC speed and duplex settings to reflect the those in the PHY
  2242. *
  2243. * hw - Struct containing variables accessed by shared code
  2244. * mii_reg - data to write to the MII control register
  2245. *
  2246. * The contents of the PHY register containing the needed information need to
  2247. * be passed in.
  2248. ******************************************************************************/
  2249. static int32_t
  2250. e1000_config_mac_to_phy(struct e1000_hw *hw)
  2251. {
  2252. uint32_t ctrl;
  2253. int32_t ret_val;
  2254. uint16_t phy_data;
  2255. DEBUGFUNC("e1000_config_mac_to_phy");
  2256. /* 82544 or newer MAC, Auto Speed Detection takes care of
  2257. * MAC speed/duplex configuration.*/
  2258. if (hw->mac_type >= e1000_82544)
  2259. return E1000_SUCCESS;
  2260. /* Read the Device Control Register and set the bits to Force Speed
  2261. * and Duplex.
  2262. */
  2263. ctrl = E1000_READ_REG(hw, CTRL);
  2264. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  2265. ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
  2266. /* Set up duplex in the Device Control and Transmit Control
  2267. * registers depending on negotiated values.
  2268. */
  2269. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
  2270. if (ret_val)
  2271. return ret_val;
  2272. if (phy_data & M88E1000_PSSR_DPLX)
  2273. ctrl |= E1000_CTRL_FD;
  2274. else
  2275. ctrl &= ~E1000_CTRL_FD;
  2276. e1000_config_collision_dist(hw);
  2277. /* Set up speed in the Device Control register depending on
  2278. * negotiated values.
  2279. */
  2280. if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
  2281. ctrl |= E1000_CTRL_SPD_1000;
  2282. else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
  2283. ctrl |= E1000_CTRL_SPD_100;
  2284. /* Write the configured values back to the Device Control Reg. */
  2285. E1000_WRITE_REG(hw, CTRL, ctrl);
  2286. return E1000_SUCCESS;
  2287. }
  2288. /******************************************************************************
  2289. * Forces the MAC's flow control settings.
  2290. *
  2291. * hw - Struct containing variables accessed by shared code
  2292. *
  2293. * Sets the TFCE and RFCE bits in the device control register to reflect
  2294. * the adapter settings. TFCE and RFCE need to be explicitly set by
  2295. * software when a Copper PHY is used because autonegotiation is managed
  2296. * by the PHY rather than the MAC. Software must also configure these
  2297. * bits when link is forced on a fiber connection.
  2298. *****************************************************************************/
  2299. int32_t
  2300. e1000_force_mac_fc(struct e1000_hw *hw)
  2301. {
  2302. uint32_t ctrl;
  2303. DEBUGFUNC("e1000_force_mac_fc");
  2304. /* Get the current configuration of the Device Control Register */
  2305. ctrl = E1000_READ_REG(hw, CTRL);
  2306. /* Because we didn't get link via the internal auto-negotiation
  2307. * mechanism (we either forced link or we got link via PHY
  2308. * auto-neg), we have to manually enable/disable transmit an
  2309. * receive flow control.
  2310. *
  2311. * The "Case" statement below enables/disable flow control
  2312. * according to the "hw->fc" parameter.
  2313. *
  2314. * The possible values of the "fc" parameter are:
  2315. * 0: Flow control is completely disabled
  2316. * 1: Rx flow control is enabled (we can receive pause
  2317. * frames but not send pause frames).
  2318. * 2: Tx flow control is enabled (we can send pause frames
  2319. * frames but we do not receive pause frames).
  2320. * 3: Both Rx and TX flow control (symmetric) is enabled.
  2321. * other: No other values should be possible at this point.
  2322. */
  2323. switch (hw->fc) {
  2324. case E1000_FC_NONE:
  2325. ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
  2326. break;
  2327. case E1000_FC_RX_PAUSE:
  2328. ctrl &= (~E1000_CTRL_TFCE);
  2329. ctrl |= E1000_CTRL_RFCE;
  2330. break;
  2331. case E1000_FC_TX_PAUSE:
  2332. ctrl &= (~E1000_CTRL_RFCE);
  2333. ctrl |= E1000_CTRL_TFCE;
  2334. break;
  2335. case E1000_FC_FULL:
  2336. ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
  2337. break;
  2338. default:
  2339. DEBUGOUT("Flow control param set incorrectly\n");
  2340. return -E1000_ERR_CONFIG;
  2341. }
  2342. /* Disable TX Flow Control for 82542 (rev 2.0) */
  2343. if (hw->mac_type == e1000_82542_rev2_0)
  2344. ctrl &= (~E1000_CTRL_TFCE);
  2345. E1000_WRITE_REG(hw, CTRL, ctrl);
  2346. return E1000_SUCCESS;
  2347. }
  2348. /******************************************************************************
  2349. * Configures flow control settings after link is established
  2350. *
  2351. * hw - Struct containing variables accessed by shared code
  2352. *
  2353. * Should be called immediately after a valid link has been established.
  2354. * Forces MAC flow control settings if link was forced. When in MII/GMII mode
  2355. * and autonegotiation is enabled, the MAC flow control settings will be set
  2356. * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
  2357. * and RFCE bits will be automaticaly set to the negotiated flow control mode.
  2358. *****************************************************************************/
  2359. static int32_t
  2360. e1000_config_fc_after_link_up(struct e1000_hw *hw)
  2361. {
  2362. int32_t ret_val;
  2363. uint16_t mii_status_reg;
  2364. uint16_t mii_nway_adv_reg;
  2365. uint16_t mii_nway_lp_ability_reg;
  2366. uint16_t speed;
  2367. uint16_t duplex;
  2368. DEBUGFUNC("e1000_config_fc_after_link_up");
  2369. /* Check for the case where we have fiber media and auto-neg failed
  2370. * so we had to force link. In this case, we need to force the
  2371. * configuration of the MAC to match the "fc" parameter.
  2372. */
  2373. if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
  2374. ((hw->media_type == e1000_media_type_internal_serdes) &&
  2375. (hw->autoneg_failed)) ||
  2376. ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
  2377. ret_val = e1000_force_mac_fc(hw);
  2378. if (ret_val) {
  2379. DEBUGOUT("Error forcing flow control settings\n");
  2380. return ret_val;
  2381. }
  2382. }
  2383. /* Check for the case where we have copper media and auto-neg is
  2384. * enabled. In this case, we need to check and see if Auto-Neg
  2385. * has completed, and if so, how the PHY and link partner has
  2386. * flow control configured.
  2387. */
  2388. if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
  2389. /* Read the MII Status Register and check to see if AutoNeg
  2390. * has completed. We read this twice because this reg has
  2391. * some "sticky" (latched) bits.
  2392. */
  2393. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
  2394. if (ret_val)
  2395. return ret_val;
  2396. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
  2397. if (ret_val)
  2398. return ret_val;
  2399. if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
  2400. /* The AutoNeg process has completed, so we now need to
  2401. * read both the Auto Negotiation Advertisement Register
  2402. * (Address 4) and the Auto_Negotiation Base Page Ability
  2403. * Register (Address 5) to determine how flow control was
  2404. * negotiated.
  2405. */
  2406. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
  2407. &mii_nway_adv_reg);
  2408. if (ret_val)
  2409. return ret_val;
  2410. ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
  2411. &mii_nway_lp_ability_reg);
  2412. if (ret_val)
  2413. return ret_val;
  2414. /* Two bits in the Auto Negotiation Advertisement Register
  2415. * (Address 4) and two bits in the Auto Negotiation Base
  2416. * Page Ability Register (Address 5) determine flow control
  2417. * for both the PHY and the link partner. The following
  2418. * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
  2419. * 1999, describes these PAUSE resolution bits and how flow
  2420. * control is determined based upon these settings.
  2421. * NOTE: DC = Don't Care
  2422. *
  2423. * LOCAL DEVICE | LINK PARTNER
  2424. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
  2425. *-------|---------|-------|---------|--------------------
  2426. * 0 | 0 | DC | DC | E1000_FC_NONE
  2427. * 0 | 1 | 0 | DC | E1000_FC_NONE
  2428. * 0 | 1 | 1 | 0 | E1000_FC_NONE
  2429. * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
  2430. * 1 | 0 | 0 | DC | E1000_FC_NONE
  2431. * 1 | DC | 1 | DC | E1000_FC_FULL
  2432. * 1 | 1 | 0 | 0 | E1000_FC_NONE
  2433. * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
  2434. *
  2435. */
  2436. /* Are both PAUSE bits set to 1? If so, this implies
  2437. * Symmetric Flow Control is enabled at both ends. The
  2438. * ASM_DIR bits are irrelevant per the spec.
  2439. *
  2440. * For Symmetric Flow Control:
  2441. *
  2442. * LOCAL DEVICE | LINK PARTNER
  2443. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  2444. *-------|---------|-------|---------|--------------------
  2445. * 1 | DC | 1 | DC | E1000_FC_FULL
  2446. *
  2447. */
  2448. if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  2449. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
  2450. /* Now we need to check if the user selected RX ONLY
  2451. * of pause frames. In this case, we had to advertise
  2452. * FULL flow control because we could not advertise RX
  2453. * ONLY. Hence, we must now check to see if we need to
  2454. * turn OFF the TRANSMISSION of PAUSE frames.
  2455. */
  2456. if (hw->original_fc == E1000_FC_FULL) {
  2457. hw->fc = E1000_FC_FULL;
  2458. DEBUGOUT("Flow Control = FULL.\n");
  2459. } else {
  2460. hw->fc = E1000_FC_RX_PAUSE;
  2461. DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
  2462. }
  2463. }
  2464. /* For receiving PAUSE frames ONLY.
  2465. *
  2466. * LOCAL DEVICE | LINK PARTNER
  2467. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  2468. *-------|---------|-------|---------|--------------------
  2469. * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
  2470. *
  2471. */
  2472. else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  2473. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  2474. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  2475. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
  2476. hw->fc = E1000_FC_TX_PAUSE;
  2477. DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
  2478. }
  2479. /* For transmitting PAUSE frames ONLY.
  2480. *
  2481. * LOCAL DEVICE | LINK PARTNER
  2482. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  2483. *-------|---------|-------|---------|--------------------
  2484. * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
  2485. *
  2486. */
  2487. else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  2488. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  2489. !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  2490. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
  2491. hw->fc = E1000_FC_RX_PAUSE;
  2492. DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
  2493. }
  2494. /* Per the IEEE spec, at this point flow control should be
  2495. * disabled. However, we want to consider that we could
  2496. * be connected to a legacy switch that doesn't advertise
  2497. * desired flow control, but can be forced on the link
  2498. * partner. So if we advertised no flow control, that is
  2499. * what we will resolve to. If we advertised some kind of
  2500. * receive capability (Rx Pause Only or Full Flow Control)
  2501. * and the link partner advertised none, we will configure
  2502. * ourselves to enable Rx Flow Control only. We can do
  2503. * this safely for two reasons: If the link partner really
  2504. * didn't want flow control enabled, and we enable Rx, no
  2505. * harm done since we won't be receiving any PAUSE frames
  2506. * anyway. If the intent on the link partner was to have
  2507. * flow control enabled, then by us enabling RX only, we
  2508. * can at least receive pause frames and process them.
  2509. * This is a good idea because in most cases, since we are
  2510. * predominantly a server NIC, more times than not we will
  2511. * be asked to delay transmission of packets than asking
  2512. * our link partner to pause transmission of frames.
  2513. */
  2514. else if ((hw->original_fc == E1000_FC_NONE ||
  2515. hw->original_fc == E1000_FC_TX_PAUSE) ||
  2516. hw->fc_strict_ieee) {
  2517. hw->fc = E1000_FC_NONE;
  2518. DEBUGOUT("Flow Control = NONE.\n");
  2519. } else {
  2520. hw->fc = E1000_FC_RX_PAUSE;
  2521. DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
  2522. }
  2523. /* Now we need to do one last check... If we auto-
  2524. * negotiated to HALF DUPLEX, flow control should not be
  2525. * enabled per IEEE 802.3 spec.
  2526. */
  2527. ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
  2528. if (ret_val) {
  2529. DEBUGOUT("Error getting link speed and duplex\n");
  2530. return ret_val;
  2531. }
  2532. if (duplex == HALF_DUPLEX)
  2533. hw->fc = E1000_FC_NONE;
  2534. /* Now we call a subroutine to actually force the MAC
  2535. * controller to use the correct flow control settings.
  2536. */
  2537. ret_val = e1000_force_mac_fc(hw);
  2538. if (ret_val) {
  2539. DEBUGOUT("Error forcing flow control settings\n");
  2540. return ret_val;
  2541. }
  2542. } else {
  2543. DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
  2544. }
  2545. }
  2546. return E1000_SUCCESS;
  2547. }
  2548. /******************************************************************************
  2549. * Checks to see if the link status of the hardware has changed.
  2550. *
  2551. * hw - Struct containing variables accessed by shared code
  2552. *
  2553. * Called by any function that needs to check the link status of the adapter.
  2554. *****************************************************************************/
  2555. int32_t
  2556. e1000_check_for_link(struct e1000_hw *hw)
  2557. {
  2558. uint32_t rxcw = 0;
  2559. uint32_t ctrl;
  2560. uint32_t status;
  2561. uint32_t rctl;
  2562. uint32_t icr;
  2563. uint32_t signal = 0;
  2564. int32_t ret_val;
  2565. uint16_t phy_data;
  2566. DEBUGFUNC("e1000_check_for_link");
  2567. ctrl = E1000_READ_REG(hw, CTRL);
  2568. status = E1000_READ_REG(hw, STATUS);
  2569. /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
  2570. * set when the optics detect a signal. On older adapters, it will be
  2571. * cleared when there is a signal. This applies to fiber media only.
  2572. */
  2573. if ((hw->media_type == e1000_media_type_fiber) ||
  2574. (hw->media_type == e1000_media_type_internal_serdes)) {
  2575. rxcw = E1000_READ_REG(hw, RXCW);
  2576. if (hw->media_type == e1000_media_type_fiber) {
  2577. signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
  2578. if (status & E1000_STATUS_LU)
  2579. hw->get_link_status = FALSE;
  2580. }
  2581. }
  2582. /* If we have a copper PHY then we only want to go out to the PHY
  2583. * registers to see if Auto-Neg has completed and/or if our link
  2584. * status has changed. The get_link_status flag will be set if we
  2585. * receive a Link Status Change interrupt or we have Rx Sequence
  2586. * Errors.
  2587. */
  2588. if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
  2589. /* First we want to see if the MII Status Register reports
  2590. * link. If so, then we want to get the current speed/duplex
  2591. * of the PHY.
  2592. * Read the register twice since the link bit is sticky.
  2593. */
  2594. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2595. if (ret_val)
  2596. return ret_val;
  2597. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2598. if (ret_val)
  2599. return ret_val;
  2600. if (phy_data & MII_SR_LINK_STATUS) {
  2601. hw->get_link_status = FALSE;
  2602. /* Check if there was DownShift, must be checked immediately after
  2603. * link-up */
  2604. e1000_check_downshift(hw);
  2605. /* If we are on 82544 or 82543 silicon and speed/duplex
  2606. * are forced to 10H or 10F, then we will implement the polarity
  2607. * reversal workaround. We disable interrupts first, and upon
  2608. * returning, place the devices interrupt state to its previous
  2609. * value except for the link status change interrupt which will
  2610. * happen due to the execution of this workaround.
  2611. */
  2612. if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
  2613. (!hw->autoneg) &&
  2614. (hw->forced_speed_duplex == e1000_10_full ||
  2615. hw->forced_speed_duplex == e1000_10_half)) {
  2616. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  2617. ret_val = e1000_polarity_reversal_workaround(hw);
  2618. icr = E1000_READ_REG(hw, ICR);
  2619. E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
  2620. E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
  2621. }
  2622. } else {
  2623. /* No link detected */
  2624. e1000_config_dsp_after_link_change(hw, FALSE);
  2625. return 0;
  2626. }
  2627. /* If we are forcing speed/duplex, then we simply return since
  2628. * we have already determined whether we have link or not.
  2629. */
  2630. if (!hw->autoneg) return -E1000_ERR_CONFIG;
  2631. /* optimize the dsp settings for the igp phy */
  2632. e1000_config_dsp_after_link_change(hw, TRUE);
  2633. /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
  2634. * have Si on board that is 82544 or newer, Auto
  2635. * Speed Detection takes care of MAC speed/duplex
  2636. * configuration. So we only need to configure Collision
  2637. * Distance in the MAC. Otherwise, we need to force
  2638. * speed/duplex on the MAC to the current PHY speed/duplex
  2639. * settings.
  2640. */
  2641. if (hw->mac_type >= e1000_82544)
  2642. e1000_config_collision_dist(hw);
  2643. else {
  2644. ret_val = e1000_config_mac_to_phy(hw);
  2645. if (ret_val) {
  2646. DEBUGOUT("Error configuring MAC to PHY settings\n");
  2647. return ret_val;
  2648. }
  2649. }
  2650. /* Configure Flow Control now that Auto-Neg has completed. First, we
  2651. * need to restore the desired flow control settings because we may
  2652. * have had to re-autoneg with a different link partner.
  2653. */
  2654. ret_val = e1000_config_fc_after_link_up(hw);
  2655. if (ret_val) {
  2656. DEBUGOUT("Error configuring flow control\n");
  2657. return ret_val;
  2658. }
  2659. /* At this point we know that we are on copper and we have
  2660. * auto-negotiated link. These are conditions for checking the link
  2661. * partner capability register. We use the link speed to determine if
  2662. * TBI compatibility needs to be turned on or off. If the link is not
  2663. * at gigabit speed, then TBI compatibility is not needed. If we are
  2664. * at gigabit speed, we turn on TBI compatibility.
  2665. */
  2666. if (hw->tbi_compatibility_en) {
  2667. uint16_t speed, duplex;
  2668. ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
  2669. if (ret_val) {
  2670. DEBUGOUT("Error getting link speed and duplex\n");
  2671. return ret_val;
  2672. }
  2673. if (speed != SPEED_1000) {
  2674. /* If link speed is not set to gigabit speed, we do not need
  2675. * to enable TBI compatibility.
  2676. */
  2677. if (hw->tbi_compatibility_on) {
  2678. /* If we previously were in the mode, turn it off. */
  2679. rctl = E1000_READ_REG(hw, RCTL);
  2680. rctl &= ~E1000_RCTL_SBP;
  2681. E1000_WRITE_REG(hw, RCTL, rctl);
  2682. hw->tbi_compatibility_on = FALSE;
  2683. }
  2684. } else {
  2685. /* If TBI compatibility is was previously off, turn it on. For
  2686. * compatibility with a TBI link partner, we will store bad
  2687. * packets. Some frames have an additional byte on the end and
  2688. * will look like CRC errors to to the hardware.
  2689. */
  2690. if (!hw->tbi_compatibility_on) {
  2691. hw->tbi_compatibility_on = TRUE;
  2692. rctl = E1000_READ_REG(hw, RCTL);
  2693. rctl |= E1000_RCTL_SBP;
  2694. E1000_WRITE_REG(hw, RCTL, rctl);
  2695. }
  2696. }
  2697. }
  2698. }
  2699. /* If we don't have link (auto-negotiation failed or link partner cannot
  2700. * auto-negotiate), the cable is plugged in (we have signal), and our
  2701. * link partner is not trying to auto-negotiate with us (we are receiving
  2702. * idles or data), we need to force link up. We also need to give
  2703. * auto-negotiation time to complete, in case the cable was just plugged
  2704. * in. The autoneg_failed flag does this.
  2705. */
  2706. else if ((((hw->media_type == e1000_media_type_fiber) &&
  2707. ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
  2708. (hw->media_type == e1000_media_type_internal_serdes)) &&
  2709. (!(status & E1000_STATUS_LU)) &&
  2710. (!(rxcw & E1000_RXCW_C))) {
  2711. if (hw->autoneg_failed == 0) {
  2712. hw->autoneg_failed = 1;
  2713. return 0;
  2714. }
  2715. DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
  2716. /* Disable auto-negotiation in the TXCW register */
  2717. E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
  2718. /* Force link-up and also force full-duplex. */
  2719. ctrl = E1000_READ_REG(hw, CTRL);
  2720. ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
  2721. E1000_WRITE_REG(hw, CTRL, ctrl);
  2722. /* Configure Flow Control after forcing link up. */
  2723. ret_val = e1000_config_fc_after_link_up(hw);
  2724. if (ret_val) {
  2725. DEBUGOUT("Error configuring flow control\n");
  2726. return ret_val;
  2727. }
  2728. }
  2729. /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
  2730. * auto-negotiation in the TXCW register and disable forced link in the
  2731. * Device Control register in an attempt to auto-negotiate with our link
  2732. * partner.
  2733. */
  2734. else if (((hw->media_type == e1000_media_type_fiber) ||
  2735. (hw->media_type == e1000_media_type_internal_serdes)) &&
  2736. (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
  2737. DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
  2738. E1000_WRITE_REG(hw, TXCW, hw->txcw);
  2739. E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
  2740. hw->serdes_link_down = FALSE;
  2741. }
  2742. /* If we force link for non-auto-negotiation switch, check link status
  2743. * based on MAC synchronization for internal serdes media type.
  2744. */
  2745. else if ((hw->media_type == e1000_media_type_internal_serdes) &&
  2746. !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
  2747. /* SYNCH bit and IV bit are sticky. */
  2748. udelay(10);
  2749. if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
  2750. if (!(rxcw & E1000_RXCW_IV)) {
  2751. hw->serdes_link_down = FALSE;
  2752. DEBUGOUT("SERDES: Link is up.\n");
  2753. }
  2754. } else {
  2755. hw->serdes_link_down = TRUE;
  2756. DEBUGOUT("SERDES: Link is down.\n");
  2757. }
  2758. }
  2759. if ((hw->media_type == e1000_media_type_internal_serdes) &&
  2760. (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
  2761. hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
  2762. }
  2763. return E1000_SUCCESS;
  2764. }
  2765. /******************************************************************************
  2766. * Detects the current speed and duplex settings of the hardware.
  2767. *
  2768. * hw - Struct containing variables accessed by shared code
  2769. * speed - Speed of the connection
  2770. * duplex - Duplex setting of the connection
  2771. *****************************************************************************/
  2772. int32_t
  2773. e1000_get_speed_and_duplex(struct e1000_hw *hw,
  2774. uint16_t *speed,
  2775. uint16_t *duplex)
  2776. {
  2777. uint32_t status;
  2778. int32_t ret_val;
  2779. uint16_t phy_data;
  2780. DEBUGFUNC("e1000_get_speed_and_duplex");
  2781. if (hw->mac_type >= e1000_82543) {
  2782. status = E1000_READ_REG(hw, STATUS);
  2783. if (status & E1000_STATUS_SPEED_1000) {
  2784. *speed = SPEED_1000;
  2785. DEBUGOUT("1000 Mbs, ");
  2786. } else if (status & E1000_STATUS_SPEED_100) {
  2787. *speed = SPEED_100;
  2788. DEBUGOUT("100 Mbs, ");
  2789. } else {
  2790. *speed = SPEED_10;
  2791. DEBUGOUT("10 Mbs, ");
  2792. }
  2793. if (status & E1000_STATUS_FD) {
  2794. *duplex = FULL_DUPLEX;
  2795. DEBUGOUT("Full Duplex\n");
  2796. } else {
  2797. *duplex = HALF_DUPLEX;
  2798. DEBUGOUT(" Half Duplex\n");
  2799. }
  2800. } else {
  2801. DEBUGOUT("1000 Mbs, Full Duplex\n");
  2802. *speed = SPEED_1000;
  2803. *duplex = FULL_DUPLEX;
  2804. }
  2805. /* IGP01 PHY may advertise full duplex operation after speed downgrade even
  2806. * if it is operating at half duplex. Here we set the duplex settings to
  2807. * match the duplex in the link partner's capabilities.
  2808. */
  2809. if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
  2810. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
  2811. if (ret_val)
  2812. return ret_val;
  2813. if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
  2814. *duplex = HALF_DUPLEX;
  2815. else {
  2816. ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
  2817. if (ret_val)
  2818. return ret_val;
  2819. if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
  2820. (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
  2821. *duplex = HALF_DUPLEX;
  2822. }
  2823. }
  2824. if ((hw->mac_type == e1000_80003es2lan) &&
  2825. (hw->media_type == e1000_media_type_copper)) {
  2826. if (*speed == SPEED_1000)
  2827. ret_val = e1000_configure_kmrn_for_1000(hw);
  2828. else
  2829. ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
  2830. if (ret_val)
  2831. return ret_val;
  2832. }
  2833. if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
  2834. ret_val = e1000_kumeran_lock_loss_workaround(hw);
  2835. if (ret_val)
  2836. return ret_val;
  2837. }
  2838. return E1000_SUCCESS;
  2839. }
  2840. /******************************************************************************
  2841. * Blocks until autoneg completes or times out (~4.5 seconds)
  2842. *
  2843. * hw - Struct containing variables accessed by shared code
  2844. ******************************************************************************/
  2845. static int32_t
  2846. e1000_wait_autoneg(struct e1000_hw *hw)
  2847. {
  2848. int32_t ret_val;
  2849. uint16_t i;
  2850. uint16_t phy_data;
  2851. DEBUGFUNC("e1000_wait_autoneg");
  2852. DEBUGOUT("Waiting for Auto-Neg to complete.\n");
  2853. /* We will wait for autoneg to complete or 4.5 seconds to expire. */
  2854. for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
  2855. /* Read the MII Status Register and wait for Auto-Neg
  2856. * Complete bit to be set.
  2857. */
  2858. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2859. if (ret_val)
  2860. return ret_val;
  2861. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2862. if (ret_val)
  2863. return ret_val;
  2864. if (phy_data & MII_SR_AUTONEG_COMPLETE) {
  2865. return E1000_SUCCESS;
  2866. }
  2867. msleep(100);
  2868. }
  2869. return E1000_SUCCESS;
  2870. }
  2871. /******************************************************************************
  2872. * Raises the Management Data Clock
  2873. *
  2874. * hw - Struct containing variables accessed by shared code
  2875. * ctrl - Device control register's current value
  2876. ******************************************************************************/
  2877. static void
  2878. e1000_raise_mdi_clk(struct e1000_hw *hw,
  2879. uint32_t *ctrl)
  2880. {
  2881. /* Raise the clock input to the Management Data Clock (by setting the MDC
  2882. * bit), and then delay 10 microseconds.
  2883. */
  2884. E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
  2885. E1000_WRITE_FLUSH(hw);
  2886. udelay(10);
  2887. }
  2888. /******************************************************************************
  2889. * Lowers the Management Data Clock
  2890. *
  2891. * hw - Struct containing variables accessed by shared code
  2892. * ctrl - Device control register's current value
  2893. ******************************************************************************/
  2894. static void
  2895. e1000_lower_mdi_clk(struct e1000_hw *hw,
  2896. uint32_t *ctrl)
  2897. {
  2898. /* Lower the clock input to the Management Data Clock (by clearing the MDC
  2899. * bit), and then delay 10 microseconds.
  2900. */
  2901. E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
  2902. E1000_WRITE_FLUSH(hw);
  2903. udelay(10);
  2904. }
  2905. /******************************************************************************
  2906. * Shifts data bits out to the PHY
  2907. *
  2908. * hw - Struct containing variables accessed by shared code
  2909. * data - Data to send out to the PHY
  2910. * count - Number of bits to shift out
  2911. *
  2912. * Bits are shifted out in MSB to LSB order.
  2913. ******************************************************************************/
  2914. static void
  2915. e1000_shift_out_mdi_bits(struct e1000_hw *hw,
  2916. uint32_t data,
  2917. uint16_t count)
  2918. {
  2919. uint32_t ctrl;
  2920. uint32_t mask;
  2921. /* We need to shift "count" number of bits out to the PHY. So, the value
  2922. * in the "data" parameter will be shifted out to the PHY one bit at a
  2923. * time. In order to do this, "data" must be broken down into bits.
  2924. */
  2925. mask = 0x01;
  2926. mask <<= (count - 1);
  2927. ctrl = E1000_READ_REG(hw, CTRL);
  2928. /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
  2929. ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
  2930. while (mask) {
  2931. /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
  2932. * then raising and lowering the Management Data Clock. A "0" is
  2933. * shifted out to the PHY by setting the MDIO bit to "0" and then
  2934. * raising and lowering the clock.
  2935. */
  2936. if (data & mask)
  2937. ctrl |= E1000_CTRL_MDIO;
  2938. else
  2939. ctrl &= ~E1000_CTRL_MDIO;
  2940. E1000_WRITE_REG(hw, CTRL, ctrl);
  2941. E1000_WRITE_FLUSH(hw);
  2942. udelay(10);
  2943. e1000_raise_mdi_clk(hw, &ctrl);
  2944. e1000_lower_mdi_clk(hw, &ctrl);
  2945. mask = mask >> 1;
  2946. }
  2947. }
  2948. /******************************************************************************
  2949. * Shifts data bits in from the PHY
  2950. *
  2951. * hw - Struct containing variables accessed by shared code
  2952. *
  2953. * Bits are shifted in in MSB to LSB order.
  2954. ******************************************************************************/
  2955. static uint16_t
  2956. e1000_shift_in_mdi_bits(struct e1000_hw *hw)
  2957. {
  2958. uint32_t ctrl;
  2959. uint16_t data = 0;
  2960. uint8_t i;
  2961. /* In order to read a register from the PHY, we need to shift in a total
  2962. * of 18 bits from the PHY. The first two bit (turnaround) times are used
  2963. * to avoid contention on the MDIO pin when a read operation is performed.
  2964. * These two bits are ignored by us and thrown away. Bits are "shifted in"
  2965. * by raising the input to the Management Data Clock (setting the MDC bit),
  2966. * and then reading the value of the MDIO bit.
  2967. */
  2968. ctrl = E1000_READ_REG(hw, CTRL);
  2969. /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
  2970. ctrl &= ~E1000_CTRL_MDIO_DIR;
  2971. ctrl &= ~E1000_CTRL_MDIO;
  2972. E1000_WRITE_REG(hw, CTRL, ctrl);
  2973. E1000_WRITE_FLUSH(hw);
  2974. /* Raise and Lower the clock before reading in the data. This accounts for
  2975. * the turnaround bits. The first clock occurred when we clocked out the
  2976. * last bit of the Register Address.
  2977. */
  2978. e1000_raise_mdi_clk(hw, &ctrl);
  2979. e1000_lower_mdi_clk(hw, &ctrl);
  2980. for (data = 0, i = 0; i < 16; i++) {
  2981. data = data << 1;
  2982. e1000_raise_mdi_clk(hw, &ctrl);
  2983. ctrl = E1000_READ_REG(hw, CTRL);
  2984. /* Check to see if we shifted in a "1". */
  2985. if (ctrl & E1000_CTRL_MDIO)
  2986. data |= 1;
  2987. e1000_lower_mdi_clk(hw, &ctrl);
  2988. }
  2989. e1000_raise_mdi_clk(hw, &ctrl);
  2990. e1000_lower_mdi_clk(hw, &ctrl);
  2991. return data;
  2992. }
  2993. static int32_t
  2994. e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
  2995. {
  2996. uint32_t swfw_sync = 0;
  2997. uint32_t swmask = mask;
  2998. uint32_t fwmask = mask << 16;
  2999. int32_t timeout = 200;
  3000. DEBUGFUNC("e1000_swfw_sync_acquire");
  3001. if (hw->swfwhw_semaphore_present)
  3002. return e1000_get_software_flag(hw);
  3003. if (!hw->swfw_sync_present)
  3004. return e1000_get_hw_eeprom_semaphore(hw);
  3005. while (timeout) {
  3006. if (e1000_get_hw_eeprom_semaphore(hw))
  3007. return -E1000_ERR_SWFW_SYNC;
  3008. swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
  3009. if (!(swfw_sync & (fwmask | swmask))) {
  3010. break;
  3011. }
  3012. /* firmware currently using resource (fwmask) */
  3013. /* or other software thread currently using resource (swmask) */
  3014. e1000_put_hw_eeprom_semaphore(hw);
  3015. mdelay(5);
  3016. timeout--;
  3017. }
  3018. if (!timeout) {
  3019. DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
  3020. return -E1000_ERR_SWFW_SYNC;
  3021. }
  3022. swfw_sync |= swmask;
  3023. E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
  3024. e1000_put_hw_eeprom_semaphore(hw);
  3025. return E1000_SUCCESS;
  3026. }
  3027. static void
  3028. e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
  3029. {
  3030. uint32_t swfw_sync;
  3031. uint32_t swmask = mask;
  3032. DEBUGFUNC("e1000_swfw_sync_release");
  3033. if (hw->swfwhw_semaphore_present) {
  3034. e1000_release_software_flag(hw);
  3035. return;
  3036. }
  3037. if (!hw->swfw_sync_present) {
  3038. e1000_put_hw_eeprom_semaphore(hw);
  3039. return;
  3040. }
  3041. /* if (e1000_get_hw_eeprom_semaphore(hw))
  3042. * return -E1000_ERR_SWFW_SYNC; */
  3043. while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
  3044. /* empty */
  3045. swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
  3046. swfw_sync &= ~swmask;
  3047. E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
  3048. e1000_put_hw_eeprom_semaphore(hw);
  3049. }
  3050. /*****************************************************************************
  3051. * Reads the value from a PHY register, if the value is on a specific non zero
  3052. * page, sets the page first.
  3053. * hw - Struct containing variables accessed by shared code
  3054. * reg_addr - address of the PHY register to read
  3055. ******************************************************************************/
  3056. int32_t
  3057. e1000_read_phy_reg(struct e1000_hw *hw,
  3058. uint32_t reg_addr,
  3059. uint16_t *phy_data)
  3060. {
  3061. uint32_t ret_val;
  3062. uint16_t swfw;
  3063. DEBUGFUNC("e1000_read_phy_reg");
  3064. if ((hw->mac_type == e1000_80003es2lan) &&
  3065. (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
  3066. swfw = E1000_SWFW_PHY1_SM;
  3067. } else {
  3068. swfw = E1000_SWFW_PHY0_SM;
  3069. }
  3070. if (e1000_swfw_sync_acquire(hw, swfw))
  3071. return -E1000_ERR_SWFW_SYNC;
  3072. if ((hw->phy_type == e1000_phy_igp ||
  3073. hw->phy_type == e1000_phy_igp_3 ||
  3074. hw->phy_type == e1000_phy_igp_2) &&
  3075. (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
  3076. ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
  3077. (uint16_t)reg_addr);
  3078. if (ret_val) {
  3079. e1000_swfw_sync_release(hw, swfw);
  3080. return ret_val;
  3081. }
  3082. } else if (hw->phy_type == e1000_phy_gg82563) {
  3083. if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
  3084. (hw->mac_type == e1000_80003es2lan)) {
  3085. /* Select Configuration Page */
  3086. if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
  3087. ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
  3088. (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
  3089. } else {
  3090. /* Use Alternative Page Select register to access
  3091. * registers 30 and 31
  3092. */
  3093. ret_val = e1000_write_phy_reg_ex(hw,
  3094. GG82563_PHY_PAGE_SELECT_ALT,
  3095. (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
  3096. }
  3097. if (ret_val) {
  3098. e1000_swfw_sync_release(hw, swfw);
  3099. return ret_val;
  3100. }
  3101. }
  3102. }
  3103. ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
  3104. phy_data);
  3105. e1000_swfw_sync_release(hw, swfw);
  3106. return ret_val;
  3107. }
  3108. static int32_t
  3109. e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
  3110. uint16_t *phy_data)
  3111. {
  3112. uint32_t i;
  3113. uint32_t mdic = 0;
  3114. const uint32_t phy_addr = 1;
  3115. DEBUGFUNC("e1000_read_phy_reg_ex");
  3116. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3117. DEBUGOUT1("PHY Address %ld is out of range\n", reg_addr);
  3118. return -E1000_ERR_PARAM;
  3119. }
  3120. if (hw->mac_type > e1000_82543) {
  3121. /* Set up Op-code, Phy Address, and register address in the MDI
  3122. * Control register. The MAC will take care of interfacing with the
  3123. * PHY to retrieve the desired data.
  3124. */
  3125. mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
  3126. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3127. (E1000_MDIC_OP_READ));
  3128. E1000_WRITE_REG(hw, MDIC, mdic);
  3129. /* Poll the ready bit to see if the MDI read completed */
  3130. for (i = 0; i < 64; i++) {
  3131. udelay(50);
  3132. mdic = E1000_READ_REG(hw, MDIC);
  3133. if (mdic & E1000_MDIC_READY) break;
  3134. }
  3135. if (!(mdic & E1000_MDIC_READY)) {
  3136. DEBUGOUT("MDI Read did not complete\n");
  3137. return -E1000_ERR_PHY;
  3138. }
  3139. if (mdic & E1000_MDIC_ERROR) {
  3140. DEBUGOUT("MDI Error\n");
  3141. return -E1000_ERR_PHY;
  3142. }
  3143. *phy_data = (uint16_t) mdic;
  3144. } else {
  3145. /* We must first send a preamble through the MDIO pin to signal the
  3146. * beginning of an MII instruction. This is done by sending 32
  3147. * consecutive "1" bits.
  3148. */
  3149. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3150. /* Now combine the next few fields that are required for a read
  3151. * operation. We use this method instead of calling the
  3152. * e1000_shift_out_mdi_bits routine five different times. The format of
  3153. * a MII read instruction consists of a shift out of 14 bits and is
  3154. * defined as follows:
  3155. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
  3156. * followed by a shift in of 18 bits. This first two bits shifted in
  3157. * are TurnAround bits used to avoid contention on the MDIO pin when a
  3158. * READ operation is performed. These two bits are thrown away
  3159. * followed by a shift in of 16 bits which contains the desired data.
  3160. */
  3161. mdic = ((reg_addr) | (phy_addr << 5) |
  3162. (PHY_OP_READ << 10) | (PHY_SOF << 12));
  3163. e1000_shift_out_mdi_bits(hw, mdic, 14);
  3164. /* Now that we've shifted out the read command to the MII, we need to
  3165. * "shift in" the 16-bit value (18 total bits) of the requested PHY
  3166. * register address.
  3167. */
  3168. *phy_data = e1000_shift_in_mdi_bits(hw);
  3169. }
  3170. return E1000_SUCCESS;
  3171. }
  3172. /******************************************************************************
  3173. * Writes a value to a PHY register
  3174. *
  3175. * hw - Struct containing variables accessed by shared code
  3176. * reg_addr - address of the PHY register to write
  3177. * data - data to write to the PHY
  3178. ******************************************************************************/
  3179. int32_t
  3180. e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
  3181. uint16_t phy_data)
  3182. {
  3183. uint32_t ret_val;
  3184. uint16_t swfw;
  3185. DEBUGFUNC("e1000_write_phy_reg");
  3186. if ((hw->mac_type == e1000_80003es2lan) &&
  3187. (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
  3188. swfw = E1000_SWFW_PHY1_SM;
  3189. } else {
  3190. swfw = E1000_SWFW_PHY0_SM;
  3191. }
  3192. if (e1000_swfw_sync_acquire(hw, swfw))
  3193. return -E1000_ERR_SWFW_SYNC;
  3194. if ((hw->phy_type == e1000_phy_igp ||
  3195. hw->phy_type == e1000_phy_igp_3 ||
  3196. hw->phy_type == e1000_phy_igp_2) &&
  3197. (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
  3198. ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
  3199. (uint16_t)reg_addr);
  3200. if (ret_val) {
  3201. e1000_swfw_sync_release(hw, swfw);
  3202. return ret_val;
  3203. }
  3204. } else if (hw->phy_type == e1000_phy_gg82563) {
  3205. if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
  3206. (hw->mac_type == e1000_80003es2lan)) {
  3207. /* Select Configuration Page */
  3208. if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
  3209. ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
  3210. (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
  3211. } else {
  3212. /* Use Alternative Page Select register to access
  3213. * registers 30 and 31
  3214. */
  3215. ret_val = e1000_write_phy_reg_ex(hw,
  3216. GG82563_PHY_PAGE_SELECT_ALT,
  3217. (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
  3218. }
  3219. if (ret_val) {
  3220. e1000_swfw_sync_release(hw, swfw);
  3221. return ret_val;
  3222. }
  3223. }
  3224. }
  3225. ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
  3226. phy_data);
  3227. e1000_swfw_sync_release(hw, swfw);
  3228. return ret_val;
  3229. }
  3230. static int32_t
  3231. e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
  3232. uint16_t phy_data)
  3233. {
  3234. uint32_t i;
  3235. uint32_t mdic = 0;
  3236. const uint32_t phy_addr = 1;
  3237. DEBUGFUNC("e1000_write_phy_reg_ex");
  3238. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3239. DEBUGOUT1("PHY Address %ld is out of range\n", reg_addr);
  3240. return -E1000_ERR_PARAM;
  3241. }
  3242. if (hw->mac_type > e1000_82543) {
  3243. /* Set up Op-code, Phy Address, register address, and data intended
  3244. * for the PHY register in the MDI Control register. The MAC will take
  3245. * care of interfacing with the PHY to send the desired data.
  3246. */
  3247. mdic = (((uint32_t) phy_data) |
  3248. (reg_addr << E1000_MDIC_REG_SHIFT) |
  3249. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3250. (E1000_MDIC_OP_WRITE));
  3251. E1000_WRITE_REG(hw, MDIC, mdic);
  3252. /* Poll the ready bit to see if the MDI read completed */
  3253. for (i = 0; i < 641; i++) {
  3254. udelay(5);
  3255. mdic = E1000_READ_REG(hw, MDIC);
  3256. if (mdic & E1000_MDIC_READY) break;
  3257. }
  3258. if (!(mdic & E1000_MDIC_READY)) {
  3259. DEBUGOUT("MDI Write did not complete\n");
  3260. return -E1000_ERR_PHY;
  3261. }
  3262. } else {
  3263. /* We'll need to use the SW defined pins to shift the write command
  3264. * out to the PHY. We first send a preamble to the PHY to signal the
  3265. * beginning of the MII instruction. This is done by sending 32
  3266. * consecutive "1" bits.
  3267. */
  3268. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3269. /* Now combine the remaining required fields that will indicate a
  3270. * write operation. We use this method instead of calling the
  3271. * e1000_shift_out_mdi_bits routine for each field in the command. The
  3272. * format of a MII write instruction is as follows:
  3273. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
  3274. */
  3275. mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
  3276. (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
  3277. mdic <<= 16;
  3278. mdic |= (uint32_t) phy_data;
  3279. e1000_shift_out_mdi_bits(hw, mdic, 32);
  3280. }
  3281. return E1000_SUCCESS;
  3282. }
  3283. static int32_t
  3284. e1000_read_kmrn_reg(struct e1000_hw *hw,
  3285. uint32_t reg_addr,
  3286. uint16_t *data)
  3287. {
  3288. uint32_t reg_val;
  3289. uint16_t swfw;
  3290. DEBUGFUNC("e1000_read_kmrn_reg");
  3291. if ((hw->mac_type == e1000_80003es2lan) &&
  3292. (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
  3293. swfw = E1000_SWFW_PHY1_SM;
  3294. } else {
  3295. swfw = E1000_SWFW_PHY0_SM;
  3296. }
  3297. if (e1000_swfw_sync_acquire(hw, swfw))
  3298. return -E1000_ERR_SWFW_SYNC;
  3299. /* Write register address */
  3300. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
  3301. E1000_KUMCTRLSTA_OFFSET) |
  3302. E1000_KUMCTRLSTA_REN;
  3303. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  3304. udelay(2);
  3305. /* Read the data returned */
  3306. reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
  3307. *data = (uint16_t)reg_val;
  3308. e1000_swfw_sync_release(hw, swfw);
  3309. return E1000_SUCCESS;
  3310. }
  3311. static int32_t
  3312. e1000_write_kmrn_reg(struct e1000_hw *hw,
  3313. uint32_t reg_addr,
  3314. uint16_t data)
  3315. {
  3316. uint32_t reg_val;
  3317. uint16_t swfw;
  3318. DEBUGFUNC("e1000_write_kmrn_reg");
  3319. if ((hw->mac_type == e1000_80003es2lan) &&
  3320. (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
  3321. swfw = E1000_SWFW_PHY1_SM;
  3322. } else {
  3323. swfw = E1000_SWFW_PHY0_SM;
  3324. }
  3325. if (e1000_swfw_sync_acquire(hw, swfw))
  3326. return -E1000_ERR_SWFW_SYNC;
  3327. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
  3328. E1000_KUMCTRLSTA_OFFSET) | data;
  3329. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  3330. udelay(2);
  3331. e1000_swfw_sync_release(hw, swfw);
  3332. return E1000_SUCCESS;
  3333. }
  3334. /******************************************************************************
  3335. * Returns the PHY to the power-on reset state
  3336. *
  3337. * hw - Struct containing variables accessed by shared code
  3338. ******************************************************************************/
  3339. int32_t
  3340. e1000_phy_hw_reset(struct e1000_hw *hw)
  3341. {
  3342. uint32_t ctrl, ctrl_ext;
  3343. uint32_t led_ctrl;
  3344. int32_t ret_val;
  3345. uint16_t swfw;
  3346. DEBUGFUNC("e1000_phy_hw_reset");
  3347. /* In the case of the phy reset being blocked, it's not an error, we
  3348. * simply return success without performing the reset. */
  3349. ret_val = e1000_check_phy_reset_block(hw);
  3350. if (ret_val)
  3351. return E1000_SUCCESS;
  3352. DEBUGOUT("Resetting Phy...\n");
  3353. if (hw->mac_type > e1000_82543) {
  3354. if ((hw->mac_type == e1000_80003es2lan) &&
  3355. (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
  3356. swfw = E1000_SWFW_PHY1_SM;
  3357. } else {
  3358. swfw = E1000_SWFW_PHY0_SM;
  3359. }
  3360. if (e1000_swfw_sync_acquire(hw, swfw)) {
  3361. DEBUGOUT("Unable to acquire swfw sync\n");
  3362. return -E1000_ERR_SWFW_SYNC;
  3363. }
  3364. /* Read the device control register and assert the E1000_CTRL_PHY_RST
  3365. * bit. Then, take it out of reset.
  3366. * For pre-e1000_82571 hardware, we delay for 10ms between the assert
  3367. * and deassert. For e1000_82571 hardware and later, we instead delay
  3368. * for 50us between and 10ms after the deassertion.
  3369. */
  3370. ctrl = E1000_READ_REG(hw, CTRL);
  3371. E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
  3372. E1000_WRITE_FLUSH(hw);
  3373. if (hw->mac_type < e1000_82571)
  3374. msleep(10);
  3375. else
  3376. udelay(100);
  3377. E1000_WRITE_REG(hw, CTRL, ctrl);
  3378. E1000_WRITE_FLUSH(hw);
  3379. if (hw->mac_type >= e1000_82571)
  3380. mdelay(10);
  3381. e1000_swfw_sync_release(hw, swfw);
  3382. } else {
  3383. /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
  3384. * bit to put the PHY into reset. Then, take it out of reset.
  3385. */
  3386. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  3387. ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
  3388. ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
  3389. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  3390. E1000_WRITE_FLUSH(hw);
  3391. msleep(10);
  3392. ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
  3393. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  3394. E1000_WRITE_FLUSH(hw);
  3395. }
  3396. udelay(150);
  3397. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  3398. /* Configure activity LED after PHY reset */
  3399. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  3400. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  3401. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  3402. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  3403. }
  3404. /* Wait for FW to finish PHY configuration. */
  3405. ret_val = e1000_get_phy_cfg_done(hw);
  3406. if (ret_val != E1000_SUCCESS)
  3407. return ret_val;
  3408. e1000_release_software_semaphore(hw);
  3409. if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
  3410. ret_val = e1000_init_lcd_from_nvm(hw);
  3411. return ret_val;
  3412. }
  3413. /******************************************************************************
  3414. * Resets the PHY
  3415. *
  3416. * hw - Struct containing variables accessed by shared code
  3417. *
  3418. * Sets bit 15 of the MII Control register
  3419. ******************************************************************************/
  3420. int32_t
  3421. e1000_phy_reset(struct e1000_hw *hw)
  3422. {
  3423. int32_t ret_val;
  3424. uint16_t phy_data;
  3425. DEBUGFUNC("e1000_phy_reset");
  3426. /* In the case of the phy reset being blocked, it's not an error, we
  3427. * simply return success without performing the reset. */
  3428. ret_val = e1000_check_phy_reset_block(hw);
  3429. if (ret_val)
  3430. return E1000_SUCCESS;
  3431. switch (hw->phy_type) {
  3432. case e1000_phy_igp:
  3433. case e1000_phy_igp_2:
  3434. case e1000_phy_igp_3:
  3435. case e1000_phy_ife:
  3436. ret_val = e1000_phy_hw_reset(hw);
  3437. if (ret_val)
  3438. return ret_val;
  3439. break;
  3440. default:
  3441. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  3442. if (ret_val)
  3443. return ret_val;
  3444. phy_data |= MII_CR_RESET;
  3445. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  3446. if (ret_val)
  3447. return ret_val;
  3448. udelay(1);
  3449. break;
  3450. }
  3451. if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
  3452. e1000_phy_init_script(hw);
  3453. return E1000_SUCCESS;
  3454. }
  3455. /******************************************************************************
  3456. * Work-around for 82566 power-down: on D3 entry-
  3457. * 1) disable gigabit link
  3458. * 2) write VR power-down enable
  3459. * 3) read it back
  3460. * if successful continue, else issue LCD reset and repeat
  3461. *
  3462. * hw - struct containing variables accessed by shared code
  3463. ******************************************************************************/
  3464. void
  3465. e1000_phy_powerdown_workaround(struct e1000_hw *hw)
  3466. {
  3467. int32_t reg;
  3468. uint16_t phy_data;
  3469. int32_t retry = 0;
  3470. DEBUGFUNC("e1000_phy_powerdown_workaround");
  3471. if (hw->phy_type != e1000_phy_igp_3)
  3472. return;
  3473. do {
  3474. /* Disable link */
  3475. reg = E1000_READ_REG(hw, PHY_CTRL);
  3476. E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
  3477. E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
  3478. /* Write VR power-down enable - bits 9:8 should be 10b */
  3479. e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
  3480. phy_data |= (1 << 9);
  3481. phy_data &= ~(1 << 8);
  3482. e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
  3483. /* Read it back and test */
  3484. e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
  3485. if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
  3486. break;
  3487. /* Issue PHY reset and repeat at most one more time */
  3488. reg = E1000_READ_REG(hw, CTRL);
  3489. E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
  3490. retry++;
  3491. } while (retry);
  3492. return;
  3493. }
  3494. /******************************************************************************
  3495. * Work-around for 82566 Kumeran PCS lock loss:
  3496. * On link status change (i.e. PCI reset, speed change) and link is up and
  3497. * speed is gigabit-
  3498. * 0) if workaround is optionally disabled do nothing
  3499. * 1) wait 1ms for Kumeran link to come up
  3500. * 2) check Kumeran Diagnostic register PCS lock loss bit
  3501. * 3) if not set the link is locked (all is good), otherwise...
  3502. * 4) reset the PHY
  3503. * 5) repeat up to 10 times
  3504. * Note: this is only called for IGP3 copper when speed is 1gb.
  3505. *
  3506. * hw - struct containing variables accessed by shared code
  3507. ******************************************************************************/
  3508. static int32_t
  3509. e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
  3510. {
  3511. int32_t ret_val;
  3512. int32_t reg;
  3513. int32_t cnt;
  3514. uint16_t phy_data;
  3515. if (hw->kmrn_lock_loss_workaround_disabled)
  3516. return E1000_SUCCESS;
  3517. /* Make sure link is up before proceeding. If not just return.
  3518. * Attempting this while link is negotiating fouled up link
  3519. * stability */
  3520. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  3521. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  3522. if (phy_data & MII_SR_LINK_STATUS) {
  3523. for (cnt = 0; cnt < 10; cnt++) {
  3524. /* read once to clear */
  3525. ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
  3526. if (ret_val)
  3527. return ret_val;
  3528. /* and again to get new status */
  3529. ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
  3530. if (ret_val)
  3531. return ret_val;
  3532. /* check for PCS lock */
  3533. if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
  3534. return E1000_SUCCESS;
  3535. /* Issue PHY reset */
  3536. e1000_phy_hw_reset(hw);
  3537. mdelay(5);
  3538. }
  3539. /* Disable GigE link negotiation */
  3540. reg = E1000_READ_REG(hw, PHY_CTRL);
  3541. E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
  3542. E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
  3543. /* unable to acquire PCS lock */
  3544. return E1000_ERR_PHY;
  3545. }
  3546. return E1000_SUCCESS;
  3547. }
  3548. /******************************************************************************
  3549. * Probes the expected PHY address for known PHY IDs
  3550. *
  3551. * hw - Struct containing variables accessed by shared code
  3552. ******************************************************************************/
  3553. static int32_t
  3554. e1000_detect_gig_phy(struct e1000_hw *hw)
  3555. {
  3556. int32_t phy_init_status, ret_val;
  3557. uint16_t phy_id_high, phy_id_low;
  3558. boolean_t match = FALSE;
  3559. DEBUGFUNC("e1000_detect_gig_phy");
  3560. if (hw->phy_id != 0)
  3561. return E1000_SUCCESS;
  3562. /* The 82571 firmware may still be configuring the PHY. In this
  3563. * case, we cannot access the PHY until the configuration is done. So
  3564. * we explicitly set the PHY values. */
  3565. if (hw->mac_type == e1000_82571 ||
  3566. hw->mac_type == e1000_82572) {
  3567. hw->phy_id = IGP01E1000_I_PHY_ID;
  3568. hw->phy_type = e1000_phy_igp_2;
  3569. return E1000_SUCCESS;
  3570. }
  3571. /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
  3572. * around that forces PHY page 0 to be set or the reads fail. The rest of
  3573. * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
  3574. * So for ESB-2 we need to have this set so our reads won't fail. If the
  3575. * attached PHY is not a e1000_phy_gg82563, the routines below will figure
  3576. * this out as well. */
  3577. if (hw->mac_type == e1000_80003es2lan)
  3578. hw->phy_type = e1000_phy_gg82563;
  3579. /* Read the PHY ID Registers to identify which PHY is onboard. */
  3580. ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
  3581. if (ret_val)
  3582. return ret_val;
  3583. hw->phy_id = (uint32_t) (phy_id_high << 16);
  3584. udelay(20);
  3585. ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
  3586. if (ret_val)
  3587. return ret_val;
  3588. hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
  3589. hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
  3590. switch (hw->mac_type) {
  3591. case e1000_82543:
  3592. if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
  3593. break;
  3594. case e1000_82544:
  3595. if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
  3596. break;
  3597. case e1000_82540:
  3598. case e1000_82545:
  3599. case e1000_82545_rev_3:
  3600. case e1000_82546:
  3601. case e1000_82546_rev_3:
  3602. if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
  3603. break;
  3604. case e1000_82541:
  3605. case e1000_82541_rev_2:
  3606. case e1000_82547:
  3607. case e1000_82547_rev_2:
  3608. if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
  3609. break;
  3610. case e1000_82573:
  3611. if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
  3612. break;
  3613. case e1000_80003es2lan:
  3614. if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
  3615. break;
  3616. case e1000_ich8lan:
  3617. if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
  3618. if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
  3619. if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
  3620. if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
  3621. break;
  3622. default:
  3623. DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
  3624. return -E1000_ERR_CONFIG;
  3625. }
  3626. phy_init_status = e1000_set_phy_type(hw);
  3627. if ((match) && (phy_init_status == E1000_SUCCESS)) {
  3628. DEBUGOUT1("PHY ID %#08lx detected\n", hw->phy_id);
  3629. return E1000_SUCCESS;
  3630. }
  3631. DEBUGOUT1("Invalid PHY ID %#08lx\n", hw->phy_id);
  3632. return -E1000_ERR_PHY;
  3633. }
  3634. /******************************************************************************
  3635. * Resets the PHY's DSP
  3636. *
  3637. * hw - Struct containing variables accessed by shared code
  3638. ******************************************************************************/
  3639. static int32_t
  3640. e1000_phy_reset_dsp(struct e1000_hw *hw)
  3641. {
  3642. int32_t ret_val;
  3643. DEBUGFUNC("e1000_phy_reset_dsp");
  3644. do {
  3645. if (hw->phy_type != e1000_phy_gg82563) {
  3646. ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
  3647. if (ret_val) break;
  3648. }
  3649. ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
  3650. if (ret_val) break;
  3651. ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
  3652. if (ret_val) break;
  3653. ret_val = E1000_SUCCESS;
  3654. } while (0);
  3655. return ret_val;
  3656. }
  3657. /******************************************************************************
  3658. * Get PHY information from various PHY registers for igp PHY only.
  3659. *
  3660. * hw - Struct containing variables accessed by shared code
  3661. * phy_info - PHY information structure
  3662. ******************************************************************************/
  3663. static int32_t
  3664. e1000_phy_igp_get_info(struct e1000_hw *hw,
  3665. struct e1000_phy_info *phy_info)
  3666. {
  3667. int32_t ret_val;
  3668. uint16_t phy_data, min_length, max_length, average;
  3669. e1000_rev_polarity polarity;
  3670. DEBUGFUNC("e1000_phy_igp_get_info");
  3671. /* The downshift status is checked only once, after link is established,
  3672. * and it stored in the hw->speed_downgraded parameter. */
  3673. phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
  3674. /* IGP01E1000 does not need to support it. */
  3675. phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
  3676. /* IGP01E1000 always correct polarity reversal */
  3677. phy_info->polarity_correction = e1000_polarity_reversal_enabled;
  3678. /* Check polarity status */
  3679. ret_val = e1000_check_polarity(hw, &polarity);
  3680. if (ret_val)
  3681. return ret_val;
  3682. phy_info->cable_polarity = polarity;
  3683. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
  3684. if (ret_val)
  3685. return ret_val;
  3686. phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
  3687. IGP01E1000_PSSR_MDIX_SHIFT);
  3688. if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
  3689. IGP01E1000_PSSR_SPEED_1000MBPS) {
  3690. /* Local/Remote Receiver Information are only valid at 1000 Mbps */
  3691. ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
  3692. if (ret_val)
  3693. return ret_val;
  3694. phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
  3695. SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
  3696. e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
  3697. phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
  3698. SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
  3699. e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
  3700. /* Get cable length */
  3701. ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
  3702. if (ret_val)
  3703. return ret_val;
  3704. /* Translate to old method */
  3705. average = (max_length + min_length) / 2;
  3706. if (average <= e1000_igp_cable_length_50)
  3707. phy_info->cable_length = e1000_cable_length_50;
  3708. else if (average <= e1000_igp_cable_length_80)
  3709. phy_info->cable_length = e1000_cable_length_50_80;
  3710. else if (average <= e1000_igp_cable_length_110)
  3711. phy_info->cable_length = e1000_cable_length_80_110;
  3712. else if (average <= e1000_igp_cable_length_140)
  3713. phy_info->cable_length = e1000_cable_length_110_140;
  3714. else
  3715. phy_info->cable_length = e1000_cable_length_140;
  3716. }
  3717. return E1000_SUCCESS;
  3718. }
  3719. /******************************************************************************
  3720. * Get PHY information from various PHY registers for ife PHY only.
  3721. *
  3722. * hw - Struct containing variables accessed by shared code
  3723. * phy_info - PHY information structure
  3724. ******************************************************************************/
  3725. static int32_t
  3726. e1000_phy_ife_get_info(struct e1000_hw *hw,
  3727. struct e1000_phy_info *phy_info)
  3728. {
  3729. int32_t ret_val;
  3730. uint16_t phy_data;
  3731. e1000_rev_polarity polarity;
  3732. DEBUGFUNC("e1000_phy_ife_get_info");
  3733. phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
  3734. phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
  3735. ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
  3736. if (ret_val)
  3737. return ret_val;
  3738. phy_info->polarity_correction =
  3739. ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
  3740. IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
  3741. e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
  3742. if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
  3743. ret_val = e1000_check_polarity(hw, &polarity);
  3744. if (ret_val)
  3745. return ret_val;
  3746. } else {
  3747. /* Polarity is forced. */
  3748. polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
  3749. IFE_PSC_FORCE_POLARITY_SHIFT) ?
  3750. e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
  3751. }
  3752. phy_info->cable_polarity = polarity;
  3753. ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
  3754. if (ret_val)
  3755. return ret_val;
  3756. phy_info->mdix_mode = (e1000_auto_x_mode)
  3757. ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
  3758. IFE_PMC_MDIX_MODE_SHIFT);
  3759. return E1000_SUCCESS;
  3760. }
  3761. /******************************************************************************
  3762. * Get PHY information from various PHY registers fot m88 PHY only.
  3763. *
  3764. * hw - Struct containing variables accessed by shared code
  3765. * phy_info - PHY information structure
  3766. ******************************************************************************/
  3767. static int32_t
  3768. e1000_phy_m88_get_info(struct e1000_hw *hw,
  3769. struct e1000_phy_info *phy_info)
  3770. {
  3771. int32_t ret_val;
  3772. uint16_t phy_data;
  3773. e1000_rev_polarity polarity;
  3774. DEBUGFUNC("e1000_phy_m88_get_info");
  3775. /* The downshift status is checked only once, after link is established,
  3776. * and it stored in the hw->speed_downgraded parameter. */
  3777. phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
  3778. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  3779. if (ret_val)
  3780. return ret_val;
  3781. phy_info->extended_10bt_distance =
  3782. ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
  3783. M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
  3784. e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
  3785. phy_info->polarity_correction =
  3786. ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
  3787. M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
  3788. e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
  3789. /* Check polarity status */
  3790. ret_val = e1000_check_polarity(hw, &polarity);
  3791. if (ret_val)
  3792. return ret_val;
  3793. phy_info->cable_polarity = polarity;
  3794. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
  3795. if (ret_val)
  3796. return ret_val;
  3797. phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
  3798. M88E1000_PSSR_MDIX_SHIFT);
  3799. if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
  3800. /* Cable Length Estimation and Local/Remote Receiver Information
  3801. * are only valid at 1000 Mbps.
  3802. */
  3803. if (hw->phy_type != e1000_phy_gg82563) {
  3804. phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
  3805. M88E1000_PSSR_CABLE_LENGTH_SHIFT);
  3806. } else {
  3807. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
  3808. &phy_data);
  3809. if (ret_val)
  3810. return ret_val;
  3811. phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
  3812. }
  3813. ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
  3814. if (ret_val)
  3815. return ret_val;
  3816. phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
  3817. SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
  3818. e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
  3819. phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
  3820. SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
  3821. e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
  3822. }
  3823. return E1000_SUCCESS;
  3824. }
  3825. /******************************************************************************
  3826. * Get PHY information from various PHY registers
  3827. *
  3828. * hw - Struct containing variables accessed by shared code
  3829. * phy_info - PHY information structure
  3830. ******************************************************************************/
  3831. int32_t
  3832. e1000_phy_get_info(struct e1000_hw *hw,
  3833. struct e1000_phy_info *phy_info)
  3834. {
  3835. int32_t ret_val;
  3836. uint16_t phy_data;
  3837. DEBUGFUNC("e1000_phy_get_info");
  3838. phy_info->cable_length = e1000_cable_length_undefined;
  3839. phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
  3840. phy_info->cable_polarity = e1000_rev_polarity_undefined;
  3841. phy_info->downshift = e1000_downshift_undefined;
  3842. phy_info->polarity_correction = e1000_polarity_reversal_undefined;
  3843. phy_info->mdix_mode = e1000_auto_x_mode_undefined;
  3844. phy_info->local_rx = e1000_1000t_rx_status_undefined;
  3845. phy_info->remote_rx = e1000_1000t_rx_status_undefined;
  3846. if (hw->media_type != e1000_media_type_copper) {
  3847. DEBUGOUT("PHY info is only valid for copper media\n");
  3848. return -E1000_ERR_CONFIG;
  3849. }
  3850. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  3851. if (ret_val)
  3852. return ret_val;
  3853. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  3854. if (ret_val)
  3855. return ret_val;
  3856. if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
  3857. DEBUGOUT("PHY info is only valid if link is up\n");
  3858. return -E1000_ERR_CONFIG;
  3859. }
  3860. if (hw->phy_type == e1000_phy_igp ||
  3861. hw->phy_type == e1000_phy_igp_3 ||
  3862. hw->phy_type == e1000_phy_igp_2)
  3863. return e1000_phy_igp_get_info(hw, phy_info);
  3864. else if (hw->phy_type == e1000_phy_ife)
  3865. return e1000_phy_ife_get_info(hw, phy_info);
  3866. else
  3867. return e1000_phy_m88_get_info(hw, phy_info);
  3868. }
  3869. int32_t
  3870. e1000_validate_mdi_setting(struct e1000_hw *hw)
  3871. {
  3872. DEBUGFUNC("e1000_validate_mdi_settings");
  3873. if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
  3874. DEBUGOUT("Invalid MDI setting detected\n");
  3875. hw->mdix = 1;
  3876. return -E1000_ERR_CONFIG;
  3877. }
  3878. return E1000_SUCCESS;
  3879. }
  3880. /******************************************************************************
  3881. * Sets up eeprom variables in the hw struct. Must be called after mac_type
  3882. * is configured. Additionally, if this is ICH8, the flash controller GbE
  3883. * registers must be mapped, or this will crash.
  3884. *
  3885. * hw - Struct containing variables accessed by shared code
  3886. *****************************************************************************/
  3887. int32_t
  3888. e1000_init_eeprom_params(struct e1000_hw *hw)
  3889. {
  3890. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  3891. uint32_t eecd = E1000_READ_REG(hw, EECD);
  3892. int32_t ret_val = E1000_SUCCESS;
  3893. uint16_t eeprom_size;
  3894. DEBUGFUNC("e1000_init_eeprom_params");
  3895. switch (hw->mac_type) {
  3896. case e1000_82542_rev2_0:
  3897. case e1000_82542_rev2_1:
  3898. case e1000_82543:
  3899. case e1000_82544:
  3900. eeprom->type = e1000_eeprom_microwire;
  3901. eeprom->word_size = 64;
  3902. eeprom->opcode_bits = 3;
  3903. eeprom->address_bits = 6;
  3904. eeprom->delay_usec = 50;
  3905. eeprom->use_eerd = FALSE;
  3906. eeprom->use_eewr = FALSE;
  3907. break;
  3908. case e1000_82540:
  3909. case e1000_82545:
  3910. case e1000_82545_rev_3:
  3911. case e1000_82546:
  3912. case e1000_82546_rev_3:
  3913. eeprom->type = e1000_eeprom_microwire;
  3914. eeprom->opcode_bits = 3;
  3915. eeprom->delay_usec = 50;
  3916. if (eecd & E1000_EECD_SIZE) {
  3917. eeprom->word_size = 256;
  3918. eeprom->address_bits = 8;
  3919. } else {
  3920. eeprom->word_size = 64;
  3921. eeprom->address_bits = 6;
  3922. }
  3923. eeprom->use_eerd = FALSE;
  3924. eeprom->use_eewr = FALSE;
  3925. break;
  3926. case e1000_82541:
  3927. case e1000_82541_rev_2:
  3928. case e1000_82547:
  3929. case e1000_82547_rev_2:
  3930. if (eecd & E1000_EECD_TYPE) {
  3931. eeprom->type = e1000_eeprom_spi;
  3932. eeprom->opcode_bits = 8;
  3933. eeprom->delay_usec = 1;
  3934. if (eecd & E1000_EECD_ADDR_BITS) {
  3935. eeprom->page_size = 32;
  3936. eeprom->address_bits = 16;
  3937. } else {
  3938. eeprom->page_size = 8;
  3939. eeprom->address_bits = 8;
  3940. }
  3941. } else {
  3942. eeprom->type = e1000_eeprom_microwire;
  3943. eeprom->opcode_bits = 3;
  3944. eeprom->delay_usec = 50;
  3945. if (eecd & E1000_EECD_ADDR_BITS) {
  3946. eeprom->word_size = 256;
  3947. eeprom->address_bits = 8;
  3948. } else {
  3949. eeprom->word_size = 64;
  3950. eeprom->address_bits = 6;
  3951. }
  3952. }
  3953. eeprom->use_eerd = FALSE;
  3954. eeprom->use_eewr = FALSE;
  3955. break;
  3956. case e1000_82571:
  3957. case e1000_82572:
  3958. eeprom->type = e1000_eeprom_spi;
  3959. eeprom->opcode_bits = 8;
  3960. eeprom->delay_usec = 1;
  3961. if (eecd & E1000_EECD_ADDR_BITS) {
  3962. eeprom->page_size = 32;
  3963. eeprom->address_bits = 16;
  3964. } else {
  3965. eeprom->page_size = 8;
  3966. eeprom->address_bits = 8;
  3967. }
  3968. eeprom->use_eerd = FALSE;
  3969. eeprom->use_eewr = FALSE;
  3970. break;
  3971. case e1000_82573:
  3972. eeprom->type = e1000_eeprom_spi;
  3973. eeprom->opcode_bits = 8;
  3974. eeprom->delay_usec = 1;
  3975. if (eecd & E1000_EECD_ADDR_BITS) {
  3976. eeprom->page_size = 32;
  3977. eeprom->address_bits = 16;
  3978. } else {
  3979. eeprom->page_size = 8;
  3980. eeprom->address_bits = 8;
  3981. }
  3982. eeprom->use_eerd = TRUE;
  3983. eeprom->use_eewr = TRUE;
  3984. if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
  3985. eeprom->type = e1000_eeprom_flash;
  3986. eeprom->word_size = 2048;
  3987. /* Ensure that the Autonomous FLASH update bit is cleared due to
  3988. * Flash update issue on parts which use a FLASH for NVM. */
  3989. eecd &= ~E1000_EECD_AUPDEN;
  3990. E1000_WRITE_REG(hw, EECD, eecd);
  3991. }
  3992. break;
  3993. case e1000_80003es2lan:
  3994. eeprom->type = e1000_eeprom_spi;
  3995. eeprom->opcode_bits = 8;
  3996. eeprom->delay_usec = 1;
  3997. if (eecd & E1000_EECD_ADDR_BITS) {
  3998. eeprom->page_size = 32;
  3999. eeprom->address_bits = 16;
  4000. } else {
  4001. eeprom->page_size = 8;
  4002. eeprom->address_bits = 8;
  4003. }
  4004. eeprom->use_eerd = TRUE;
  4005. eeprom->use_eewr = FALSE;
  4006. break;
  4007. case e1000_ich8lan:
  4008. {
  4009. int32_t i = 0;
  4010. uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
  4011. eeprom->type = e1000_eeprom_ich8;
  4012. eeprom->use_eerd = FALSE;
  4013. eeprom->use_eewr = FALSE;
  4014. eeprom->word_size = E1000_SHADOW_RAM_WORDS;
  4015. /* Zero the shadow RAM structure. But don't load it from NVM
  4016. * so as to save time for driver init */
  4017. if (hw->eeprom_shadow_ram != NULL) {
  4018. for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
  4019. hw->eeprom_shadow_ram[i].modified = FALSE;
  4020. hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
  4021. }
  4022. }
  4023. hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
  4024. ICH_FLASH_SECTOR_SIZE;
  4025. hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
  4026. hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
  4027. hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
  4028. hw->flash_bank_size /= 2 * sizeof(uint16_t);
  4029. break;
  4030. }
  4031. default:
  4032. break;
  4033. }
  4034. if (eeprom->type == e1000_eeprom_spi) {
  4035. /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
  4036. * 32KB (incremented by powers of 2).
  4037. */
  4038. if (hw->mac_type <= e1000_82547_rev_2) {
  4039. /* Set to default value for initial eeprom read. */
  4040. eeprom->word_size = 64;
  4041. ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
  4042. if (ret_val)
  4043. return ret_val;
  4044. eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
  4045. /* 256B eeprom size was not supported in earlier hardware, so we
  4046. * bump eeprom_size up one to ensure that "1" (which maps to 256B)
  4047. * is never the result used in the shifting logic below. */
  4048. if (eeprom_size)
  4049. eeprom_size++;
  4050. } else {
  4051. eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
  4052. E1000_EECD_SIZE_EX_SHIFT);
  4053. }
  4054. eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
  4055. }
  4056. return ret_val;
  4057. }
  4058. /******************************************************************************
  4059. * Raises the EEPROM's clock input.
  4060. *
  4061. * hw - Struct containing variables accessed by shared code
  4062. * eecd - EECD's current value
  4063. *****************************************************************************/
  4064. static void
  4065. e1000_raise_ee_clk(struct e1000_hw *hw,
  4066. uint32_t *eecd)
  4067. {
  4068. /* Raise the clock input to the EEPROM (by setting the SK bit), and then
  4069. * wait <delay> microseconds.
  4070. */
  4071. *eecd = *eecd | E1000_EECD_SK;
  4072. E1000_WRITE_REG(hw, EECD, *eecd);
  4073. E1000_WRITE_FLUSH(hw);
  4074. udelay(hw->eeprom.delay_usec);
  4075. }
  4076. /******************************************************************************
  4077. * Lowers the EEPROM's clock input.
  4078. *
  4079. * hw - Struct containing variables accessed by shared code
  4080. * eecd - EECD's current value
  4081. *****************************************************************************/
  4082. static void
  4083. e1000_lower_ee_clk(struct e1000_hw *hw,
  4084. uint32_t *eecd)
  4085. {
  4086. /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
  4087. * wait 50 microseconds.
  4088. */
  4089. *eecd = *eecd & ~E1000_EECD_SK;
  4090. E1000_WRITE_REG(hw, EECD, *eecd);
  4091. E1000_WRITE_FLUSH(hw);
  4092. udelay(hw->eeprom.delay_usec);
  4093. }
  4094. /******************************************************************************
  4095. * Shift data bits out to the EEPROM.
  4096. *
  4097. * hw - Struct containing variables accessed by shared code
  4098. * data - data to send to the EEPROM
  4099. * count - number of bits to shift out
  4100. *****************************************************************************/
  4101. static void
  4102. e1000_shift_out_ee_bits(struct e1000_hw *hw,
  4103. uint16_t data,
  4104. uint16_t count)
  4105. {
  4106. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4107. uint32_t eecd;
  4108. uint32_t mask;
  4109. /* We need to shift "count" bits out to the EEPROM. So, value in the
  4110. * "data" parameter will be shifted out to the EEPROM one bit at a time.
  4111. * In order to do this, "data" must be broken down into bits.
  4112. */
  4113. mask = 0x01 << (count - 1);
  4114. eecd = E1000_READ_REG(hw, EECD);
  4115. if (eeprom->type == e1000_eeprom_microwire) {
  4116. eecd &= ~E1000_EECD_DO;
  4117. } else if (eeprom->type == e1000_eeprom_spi) {
  4118. eecd |= E1000_EECD_DO;
  4119. }
  4120. do {
  4121. /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
  4122. * and then raising and then lowering the clock (the SK bit controls
  4123. * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
  4124. * by setting "DI" to "0" and then raising and then lowering the clock.
  4125. */
  4126. eecd &= ~E1000_EECD_DI;
  4127. if (data & mask)
  4128. eecd |= E1000_EECD_DI;
  4129. E1000_WRITE_REG(hw, EECD, eecd);
  4130. E1000_WRITE_FLUSH(hw);
  4131. udelay(eeprom->delay_usec);
  4132. e1000_raise_ee_clk(hw, &eecd);
  4133. e1000_lower_ee_clk(hw, &eecd);
  4134. mask = mask >> 1;
  4135. } while (mask);
  4136. /* We leave the "DI" bit set to "0" when we leave this routine. */
  4137. eecd &= ~E1000_EECD_DI;
  4138. E1000_WRITE_REG(hw, EECD, eecd);
  4139. }
  4140. /******************************************************************************
  4141. * Shift data bits in from the EEPROM
  4142. *
  4143. * hw - Struct containing variables accessed by shared code
  4144. *****************************************************************************/
  4145. static uint16_t
  4146. e1000_shift_in_ee_bits(struct e1000_hw *hw,
  4147. uint16_t count)
  4148. {
  4149. uint32_t eecd;
  4150. uint32_t i;
  4151. uint16_t data;
  4152. /* In order to read a register from the EEPROM, we need to shift 'count'
  4153. * bits in from the EEPROM. Bits are "shifted in" by raising the clock
  4154. * input to the EEPROM (setting the SK bit), and then reading the value of
  4155. * the "DO" bit. During this "shifting in" process the "DI" bit should
  4156. * always be clear.
  4157. */
  4158. eecd = E1000_READ_REG(hw, EECD);
  4159. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  4160. data = 0;
  4161. for (i = 0; i < count; i++) {
  4162. data = data << 1;
  4163. e1000_raise_ee_clk(hw, &eecd);
  4164. eecd = E1000_READ_REG(hw, EECD);
  4165. eecd &= ~(E1000_EECD_DI);
  4166. if (eecd & E1000_EECD_DO)
  4167. data |= 1;
  4168. e1000_lower_ee_clk(hw, &eecd);
  4169. }
  4170. return data;
  4171. }
  4172. /******************************************************************************
  4173. * Prepares EEPROM for access
  4174. *
  4175. * hw - Struct containing variables accessed by shared code
  4176. *
  4177. * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
  4178. * function should be called before issuing a command to the EEPROM.
  4179. *****************************************************************************/
  4180. static int32_t
  4181. e1000_acquire_eeprom(struct e1000_hw *hw)
  4182. {
  4183. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4184. uint32_t eecd, i=0;
  4185. DEBUGFUNC("e1000_acquire_eeprom");
  4186. if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
  4187. return -E1000_ERR_SWFW_SYNC;
  4188. eecd = E1000_READ_REG(hw, EECD);
  4189. if (hw->mac_type != e1000_82573) {
  4190. /* Request EEPROM Access */
  4191. if (hw->mac_type > e1000_82544) {
  4192. eecd |= E1000_EECD_REQ;
  4193. E1000_WRITE_REG(hw, EECD, eecd);
  4194. eecd = E1000_READ_REG(hw, EECD);
  4195. while ((!(eecd & E1000_EECD_GNT)) &&
  4196. (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
  4197. i++;
  4198. udelay(5);
  4199. eecd = E1000_READ_REG(hw, EECD);
  4200. }
  4201. if (!(eecd & E1000_EECD_GNT)) {
  4202. eecd &= ~E1000_EECD_REQ;
  4203. E1000_WRITE_REG(hw, EECD, eecd);
  4204. DEBUGOUT("Could not acquire EEPROM grant\n");
  4205. e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
  4206. return -E1000_ERR_EEPROM;
  4207. }
  4208. }
  4209. }
  4210. /* Setup EEPROM for Read/Write */
  4211. if (eeprom->type == e1000_eeprom_microwire) {
  4212. /* Clear SK and DI */
  4213. eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
  4214. E1000_WRITE_REG(hw, EECD, eecd);
  4215. /* Set CS */
  4216. eecd |= E1000_EECD_CS;
  4217. E1000_WRITE_REG(hw, EECD, eecd);
  4218. } else if (eeprom->type == e1000_eeprom_spi) {
  4219. /* Clear SK and CS */
  4220. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  4221. E1000_WRITE_REG(hw, EECD, eecd);
  4222. udelay(1);
  4223. }
  4224. return E1000_SUCCESS;
  4225. }
  4226. /******************************************************************************
  4227. * Returns EEPROM to a "standby" state
  4228. *
  4229. * hw - Struct containing variables accessed by shared code
  4230. *****************************************************************************/
  4231. static void
  4232. e1000_standby_eeprom(struct e1000_hw *hw)
  4233. {
  4234. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4235. uint32_t eecd;
  4236. eecd = E1000_READ_REG(hw, EECD);
  4237. if (eeprom->type == e1000_eeprom_microwire) {
  4238. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  4239. E1000_WRITE_REG(hw, EECD, eecd);
  4240. E1000_WRITE_FLUSH(hw);
  4241. udelay(eeprom->delay_usec);
  4242. /* Clock high */
  4243. eecd |= E1000_EECD_SK;
  4244. E1000_WRITE_REG(hw, EECD, eecd);
  4245. E1000_WRITE_FLUSH(hw);
  4246. udelay(eeprom->delay_usec);
  4247. /* Select EEPROM */
  4248. eecd |= E1000_EECD_CS;
  4249. E1000_WRITE_REG(hw, EECD, eecd);
  4250. E1000_WRITE_FLUSH(hw);
  4251. udelay(eeprom->delay_usec);
  4252. /* Clock low */
  4253. eecd &= ~E1000_EECD_SK;
  4254. E1000_WRITE_REG(hw, EECD, eecd);
  4255. E1000_WRITE_FLUSH(hw);
  4256. udelay(eeprom->delay_usec);
  4257. } else if (eeprom->type == e1000_eeprom_spi) {
  4258. /* Toggle CS to flush commands */
  4259. eecd |= E1000_EECD_CS;
  4260. E1000_WRITE_REG(hw, EECD, eecd);
  4261. E1000_WRITE_FLUSH(hw);
  4262. udelay(eeprom->delay_usec);
  4263. eecd &= ~E1000_EECD_CS;
  4264. E1000_WRITE_REG(hw, EECD, eecd);
  4265. E1000_WRITE_FLUSH(hw);
  4266. udelay(eeprom->delay_usec);
  4267. }
  4268. }
  4269. /******************************************************************************
  4270. * Terminates a command by inverting the EEPROM's chip select pin
  4271. *
  4272. * hw - Struct containing variables accessed by shared code
  4273. *****************************************************************************/
  4274. static void
  4275. e1000_release_eeprom(struct e1000_hw *hw)
  4276. {
  4277. uint32_t eecd;
  4278. DEBUGFUNC("e1000_release_eeprom");
  4279. eecd = E1000_READ_REG(hw, EECD);
  4280. if (hw->eeprom.type == e1000_eeprom_spi) {
  4281. eecd |= E1000_EECD_CS; /* Pull CS high */
  4282. eecd &= ~E1000_EECD_SK; /* Lower SCK */
  4283. E1000_WRITE_REG(hw, EECD, eecd);
  4284. udelay(hw->eeprom.delay_usec);
  4285. } else if (hw->eeprom.type == e1000_eeprom_microwire) {
  4286. /* cleanup eeprom */
  4287. /* CS on Microwire is active-high */
  4288. eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
  4289. E1000_WRITE_REG(hw, EECD, eecd);
  4290. /* Rising edge of clock */
  4291. eecd |= E1000_EECD_SK;
  4292. E1000_WRITE_REG(hw, EECD, eecd);
  4293. E1000_WRITE_FLUSH(hw);
  4294. udelay(hw->eeprom.delay_usec);
  4295. /* Falling edge of clock */
  4296. eecd &= ~E1000_EECD_SK;
  4297. E1000_WRITE_REG(hw, EECD, eecd);
  4298. E1000_WRITE_FLUSH(hw);
  4299. udelay(hw->eeprom.delay_usec);
  4300. }
  4301. /* Stop requesting EEPROM access */
  4302. if (hw->mac_type > e1000_82544) {
  4303. eecd &= ~E1000_EECD_REQ;
  4304. E1000_WRITE_REG(hw, EECD, eecd);
  4305. }
  4306. e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
  4307. }
  4308. /******************************************************************************
  4309. * Reads a 16 bit word from the EEPROM.
  4310. *
  4311. * hw - Struct containing variables accessed by shared code
  4312. *****************************************************************************/
  4313. static int32_t
  4314. e1000_spi_eeprom_ready(struct e1000_hw *hw)
  4315. {
  4316. uint16_t retry_count = 0;
  4317. uint8_t spi_stat_reg;
  4318. DEBUGFUNC("e1000_spi_eeprom_ready");
  4319. /* Read "Status Register" repeatedly until the LSB is cleared. The
  4320. * EEPROM will signal that the command has been completed by clearing
  4321. * bit 0 of the internal status register. If it's not cleared within
  4322. * 5 milliseconds, then error out.
  4323. */
  4324. retry_count = 0;
  4325. do {
  4326. e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
  4327. hw->eeprom.opcode_bits);
  4328. spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
  4329. if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
  4330. break;
  4331. udelay(5);
  4332. retry_count += 5;
  4333. e1000_standby_eeprom(hw);
  4334. } while (retry_count < EEPROM_MAX_RETRY_SPI);
  4335. /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
  4336. * only 0-5mSec on 5V devices)
  4337. */
  4338. if (retry_count >= EEPROM_MAX_RETRY_SPI) {
  4339. DEBUGOUT("SPI EEPROM Status error\n");
  4340. return -E1000_ERR_EEPROM;
  4341. }
  4342. return E1000_SUCCESS;
  4343. }
  4344. /******************************************************************************
  4345. * Reads a 16 bit word from the EEPROM.
  4346. *
  4347. * hw - Struct containing variables accessed by shared code
  4348. * offset - offset of word in the EEPROM to read
  4349. * data - word read from the EEPROM
  4350. * words - number of words to read
  4351. *****************************************************************************/
  4352. int32_t
  4353. e1000_read_eeprom(struct e1000_hw *hw,
  4354. uint16_t offset,
  4355. uint16_t words,
  4356. uint16_t *data)
  4357. {
  4358. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4359. uint32_t i = 0;
  4360. DEBUGFUNC("e1000_read_eeprom");
  4361. /* If eeprom is not yet detected, do so now */
  4362. if (eeprom->word_size == 0)
  4363. e1000_init_eeprom_params(hw);
  4364. /* A check for invalid values: offset too large, too many words, and not
  4365. * enough words.
  4366. */
  4367. if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
  4368. (words == 0)) {
  4369. DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
  4370. return -E1000_ERR_EEPROM;
  4371. }
  4372. /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
  4373. * directly. In this case, we need to acquire the EEPROM so that
  4374. * FW or other port software does not interrupt.
  4375. */
  4376. if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
  4377. hw->eeprom.use_eerd == FALSE) {
  4378. /* Prepare the EEPROM for bit-bang reading */
  4379. if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
  4380. return -E1000_ERR_EEPROM;
  4381. }
  4382. /* Eerd register EEPROM access requires no eeprom aquire/release */
  4383. if (eeprom->use_eerd == TRUE)
  4384. return e1000_read_eeprom_eerd(hw, offset, words, data);
  4385. /* ICH EEPROM access is done via the ICH flash controller */
  4386. if (eeprom->type == e1000_eeprom_ich8)
  4387. return e1000_read_eeprom_ich8(hw, offset, words, data);
  4388. /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
  4389. * acquired the EEPROM at this point, so any returns should relase it */
  4390. if (eeprom->type == e1000_eeprom_spi) {
  4391. uint16_t word_in;
  4392. uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
  4393. if (e1000_spi_eeprom_ready(hw)) {
  4394. e1000_release_eeprom(hw);
  4395. return -E1000_ERR_EEPROM;
  4396. }
  4397. e1000_standby_eeprom(hw);
  4398. /* Some SPI eeproms use the 8th address bit embedded in the opcode */
  4399. if ((eeprom->address_bits == 8) && (offset >= 128))
  4400. read_opcode |= EEPROM_A8_OPCODE_SPI;
  4401. /* Send the READ command (opcode + addr) */
  4402. e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
  4403. e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
  4404. /* Read the data. The address of the eeprom internally increments with
  4405. * each byte (spi) being read, saving on the overhead of eeprom setup
  4406. * and tear-down. The address counter will roll over if reading beyond
  4407. * the size of the eeprom, thus allowing the entire memory to be read
  4408. * starting from any offset. */
  4409. for (i = 0; i < words; i++) {
  4410. word_in = e1000_shift_in_ee_bits(hw, 16);
  4411. data[i] = (word_in >> 8) | (word_in << 8);
  4412. }
  4413. } else if (eeprom->type == e1000_eeprom_microwire) {
  4414. for (i = 0; i < words; i++) {
  4415. /* Send the READ command (opcode + addr) */
  4416. e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
  4417. eeprom->opcode_bits);
  4418. e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
  4419. eeprom->address_bits);
  4420. /* Read the data. For microwire, each word requires the overhead
  4421. * of eeprom setup and tear-down. */
  4422. data[i] = e1000_shift_in_ee_bits(hw, 16);
  4423. e1000_standby_eeprom(hw);
  4424. }
  4425. }
  4426. /* End this read operation */
  4427. e1000_release_eeprom(hw);
  4428. return E1000_SUCCESS;
  4429. }
  4430. /******************************************************************************
  4431. * Reads a 16 bit word from the EEPROM using the EERD register.
  4432. *
  4433. * hw - Struct containing variables accessed by shared code
  4434. * offset - offset of word in the EEPROM to read
  4435. * data - word read from the EEPROM
  4436. * words - number of words to read
  4437. *****************************************************************************/
  4438. static int32_t
  4439. e1000_read_eeprom_eerd(struct e1000_hw *hw,
  4440. uint16_t offset,
  4441. uint16_t words,
  4442. uint16_t *data)
  4443. {
  4444. uint32_t i, eerd = 0;
  4445. int32_t error = 0;
  4446. for (i = 0; i < words; i++) {
  4447. eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
  4448. E1000_EEPROM_RW_REG_START;
  4449. E1000_WRITE_REG(hw, EERD, eerd);
  4450. error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
  4451. if (error) {
  4452. break;
  4453. }
  4454. data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
  4455. }
  4456. return error;
  4457. }
  4458. /******************************************************************************
  4459. * Writes a 16 bit word from the EEPROM using the EEWR register.
  4460. *
  4461. * hw - Struct containing variables accessed by shared code
  4462. * offset - offset of word in the EEPROM to read
  4463. * data - word read from the EEPROM
  4464. * words - number of words to read
  4465. *****************************************************************************/
  4466. static int32_t
  4467. e1000_write_eeprom_eewr(struct e1000_hw *hw,
  4468. uint16_t offset,
  4469. uint16_t words,
  4470. uint16_t *data)
  4471. {
  4472. uint32_t register_value = 0;
  4473. uint32_t i = 0;
  4474. int32_t error = 0;
  4475. if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
  4476. return -E1000_ERR_SWFW_SYNC;
  4477. for (i = 0; i < words; i++) {
  4478. register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
  4479. ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
  4480. E1000_EEPROM_RW_REG_START;
  4481. error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
  4482. if (error) {
  4483. break;
  4484. }
  4485. E1000_WRITE_REG(hw, EEWR, register_value);
  4486. error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
  4487. if (error) {
  4488. break;
  4489. }
  4490. }
  4491. e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
  4492. return error;
  4493. }
  4494. /******************************************************************************
  4495. * Polls the status bit (bit 1) of the EERD to determine when the read is done.
  4496. *
  4497. * hw - Struct containing variables accessed by shared code
  4498. *****************************************************************************/
  4499. static int32_t
  4500. e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
  4501. {
  4502. uint32_t attempts = 100000;
  4503. uint32_t i, reg = 0;
  4504. int32_t done = E1000_ERR_EEPROM;
  4505. for (i = 0; i < attempts; i++) {
  4506. if (eerd == E1000_EEPROM_POLL_READ)
  4507. reg = E1000_READ_REG(hw, EERD);
  4508. else
  4509. reg = E1000_READ_REG(hw, EEWR);
  4510. if (reg & E1000_EEPROM_RW_REG_DONE) {
  4511. done = E1000_SUCCESS;
  4512. break;
  4513. }
  4514. udelay(5);
  4515. }
  4516. return done;
  4517. }
  4518. /***************************************************************************
  4519. * Description: Determines if the onboard NVM is FLASH or EEPROM.
  4520. *
  4521. * hw - Struct containing variables accessed by shared code
  4522. ****************************************************************************/
  4523. static boolean_t
  4524. e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
  4525. {
  4526. uint32_t eecd = 0;
  4527. DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
  4528. if (hw->mac_type == e1000_ich8lan)
  4529. return FALSE;
  4530. if (hw->mac_type == e1000_82573) {
  4531. eecd = E1000_READ_REG(hw, EECD);
  4532. /* Isolate bits 15 & 16 */
  4533. eecd = ((eecd >> 15) & 0x03);
  4534. /* If both bits are set, device is Flash type */
  4535. if (eecd == 0x03) {
  4536. return FALSE;
  4537. }
  4538. }
  4539. return TRUE;
  4540. }
  4541. /******************************************************************************
  4542. * Verifies that the EEPROM has a valid checksum
  4543. *
  4544. * hw - Struct containing variables accessed by shared code
  4545. *
  4546. * Reads the first 64 16 bit words of the EEPROM and sums the values read.
  4547. * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
  4548. * valid.
  4549. *****************************************************************************/
  4550. int32_t
  4551. e1000_validate_eeprom_checksum(struct e1000_hw *hw)
  4552. {
  4553. uint16_t checksum = 0;
  4554. uint16_t i, eeprom_data;
  4555. DEBUGFUNC("e1000_validate_eeprom_checksum");
  4556. if ((hw->mac_type == e1000_82573) &&
  4557. (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
  4558. /* Check bit 4 of word 10h. If it is 0, firmware is done updating
  4559. * 10h-12h. Checksum may need to be fixed. */
  4560. e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
  4561. if ((eeprom_data & 0x10) == 0) {
  4562. /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
  4563. * has already been fixed. If the checksum is still wrong and this
  4564. * bit is a 1, we need to return bad checksum. Otherwise, we need
  4565. * to set this bit to a 1 and update the checksum. */
  4566. e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
  4567. if ((eeprom_data & 0x8000) == 0) {
  4568. eeprom_data |= 0x8000;
  4569. e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
  4570. e1000_update_eeprom_checksum(hw);
  4571. }
  4572. }
  4573. }
  4574. if (hw->mac_type == e1000_ich8lan) {
  4575. /* Drivers must allocate the shadow ram structure for the
  4576. * EEPROM checksum to be updated. Otherwise, this bit as well
  4577. * as the checksum must both be set correctly for this
  4578. * validation to pass.
  4579. */
  4580. e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
  4581. if ((eeprom_data & 0x40) == 0) {
  4582. eeprom_data |= 0x40;
  4583. e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
  4584. e1000_update_eeprom_checksum(hw);
  4585. }
  4586. }
  4587. for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
  4588. if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
  4589. DEBUGOUT("EEPROM Read Error\n");
  4590. return -E1000_ERR_EEPROM;
  4591. }
  4592. checksum += eeprom_data;
  4593. }
  4594. if (checksum == (uint16_t) EEPROM_SUM)
  4595. return E1000_SUCCESS;
  4596. else {
  4597. DEBUGOUT("EEPROM Checksum Invalid\n");
  4598. return -E1000_ERR_EEPROM;
  4599. }
  4600. }
  4601. /******************************************************************************
  4602. * Calculates the EEPROM checksum and writes it to the EEPROM
  4603. *
  4604. * hw - Struct containing variables accessed by shared code
  4605. *
  4606. * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
  4607. * Writes the difference to word offset 63 of the EEPROM.
  4608. *****************************************************************************/
  4609. int32_t
  4610. e1000_update_eeprom_checksum(struct e1000_hw *hw)
  4611. {
  4612. uint32_t ctrl_ext;
  4613. uint16_t checksum = 0;
  4614. uint16_t i, eeprom_data;
  4615. DEBUGFUNC("e1000_update_eeprom_checksum");
  4616. for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
  4617. if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
  4618. DEBUGOUT("EEPROM Read Error\n");
  4619. return -E1000_ERR_EEPROM;
  4620. }
  4621. checksum += eeprom_data;
  4622. }
  4623. checksum = (uint16_t) EEPROM_SUM - checksum;
  4624. if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
  4625. DEBUGOUT("EEPROM Write Error\n");
  4626. return -E1000_ERR_EEPROM;
  4627. } else if (hw->eeprom.type == e1000_eeprom_flash) {
  4628. e1000_commit_shadow_ram(hw);
  4629. } else if (hw->eeprom.type == e1000_eeprom_ich8) {
  4630. e1000_commit_shadow_ram(hw);
  4631. /* Reload the EEPROM, or else modifications will not appear
  4632. * until after next adapter reset. */
  4633. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  4634. ctrl_ext |= E1000_CTRL_EXT_EE_RST;
  4635. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4636. msleep(10);
  4637. }
  4638. return E1000_SUCCESS;
  4639. }
  4640. /******************************************************************************
  4641. * Parent function for writing words to the different EEPROM types.
  4642. *
  4643. * hw - Struct containing variables accessed by shared code
  4644. * offset - offset within the EEPROM to be written to
  4645. * words - number of words to write
  4646. * data - 16 bit word to be written to the EEPROM
  4647. *
  4648. * If e1000_update_eeprom_checksum is not called after this function, the
  4649. * EEPROM will most likely contain an invalid checksum.
  4650. *****************************************************************************/
  4651. int32_t
  4652. e1000_write_eeprom(struct e1000_hw *hw,
  4653. uint16_t offset,
  4654. uint16_t words,
  4655. uint16_t *data)
  4656. {
  4657. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4658. int32_t status = 0;
  4659. DEBUGFUNC("e1000_write_eeprom");
  4660. /* If eeprom is not yet detected, do so now */
  4661. if (eeprom->word_size == 0)
  4662. e1000_init_eeprom_params(hw);
  4663. /* A check for invalid values: offset too large, too many words, and not
  4664. * enough words.
  4665. */
  4666. if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
  4667. (words == 0)) {
  4668. DEBUGOUT("\"words\" parameter out of bounds\n");
  4669. return -E1000_ERR_EEPROM;
  4670. }
  4671. /* 82573 writes only through eewr */
  4672. if (eeprom->use_eewr == TRUE)
  4673. return e1000_write_eeprom_eewr(hw, offset, words, data);
  4674. if (eeprom->type == e1000_eeprom_ich8)
  4675. return e1000_write_eeprom_ich8(hw, offset, words, data);
  4676. /* Prepare the EEPROM for writing */
  4677. if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
  4678. return -E1000_ERR_EEPROM;
  4679. if (eeprom->type == e1000_eeprom_microwire) {
  4680. status = e1000_write_eeprom_microwire(hw, offset, words, data);
  4681. } else {
  4682. status = e1000_write_eeprom_spi(hw, offset, words, data);
  4683. msleep(10);
  4684. }
  4685. /* Done with writing */
  4686. e1000_release_eeprom(hw);
  4687. return status;
  4688. }
  4689. /******************************************************************************
  4690. * Writes a 16 bit word to a given offset in an SPI EEPROM.
  4691. *
  4692. * hw - Struct containing variables accessed by shared code
  4693. * offset - offset within the EEPROM to be written to
  4694. * words - number of words to write
  4695. * data - pointer to array of 8 bit words to be written to the EEPROM
  4696. *
  4697. *****************************************************************************/
  4698. static int32_t
  4699. e1000_write_eeprom_spi(struct e1000_hw *hw,
  4700. uint16_t offset,
  4701. uint16_t words,
  4702. uint16_t *data)
  4703. {
  4704. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4705. uint16_t widx = 0;
  4706. DEBUGFUNC("e1000_write_eeprom_spi");
  4707. while (widx < words) {
  4708. uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
  4709. if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
  4710. e1000_standby_eeprom(hw);
  4711. /* Send the WRITE ENABLE command (8 bit opcode ) */
  4712. e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
  4713. eeprom->opcode_bits);
  4714. e1000_standby_eeprom(hw);
  4715. /* Some SPI eeproms use the 8th address bit embedded in the opcode */
  4716. if ((eeprom->address_bits == 8) && (offset >= 128))
  4717. write_opcode |= EEPROM_A8_OPCODE_SPI;
  4718. /* Send the Write command (8-bit opcode + addr) */
  4719. e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
  4720. e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
  4721. eeprom->address_bits);
  4722. /* Send the data */
  4723. /* Loop to allow for up to whole page write (32 bytes) of eeprom */
  4724. while (widx < words) {
  4725. uint16_t word_out = data[widx];
  4726. word_out = (word_out >> 8) | (word_out << 8);
  4727. e1000_shift_out_ee_bits(hw, word_out, 16);
  4728. widx++;
  4729. /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
  4730. * operation, while the smaller eeproms are capable of an 8-byte
  4731. * PAGE WRITE operation. Break the inner loop to pass new address
  4732. */
  4733. if ((((offset + widx)*2) % eeprom->page_size) == 0) {
  4734. e1000_standby_eeprom(hw);
  4735. break;
  4736. }
  4737. }
  4738. }
  4739. return E1000_SUCCESS;
  4740. }
  4741. /******************************************************************************
  4742. * Writes a 16 bit word to a given offset in a Microwire EEPROM.
  4743. *
  4744. * hw - Struct containing variables accessed by shared code
  4745. * offset - offset within the EEPROM to be written to
  4746. * words - number of words to write
  4747. * data - pointer to array of 16 bit words to be written to the EEPROM
  4748. *
  4749. *****************************************************************************/
  4750. static int32_t
  4751. e1000_write_eeprom_microwire(struct e1000_hw *hw,
  4752. uint16_t offset,
  4753. uint16_t words,
  4754. uint16_t *data)
  4755. {
  4756. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4757. uint32_t eecd;
  4758. uint16_t words_written = 0;
  4759. uint16_t i = 0;
  4760. DEBUGFUNC("e1000_write_eeprom_microwire");
  4761. /* Send the write enable command to the EEPROM (3-bit opcode plus
  4762. * 6/8-bit dummy address beginning with 11). It's less work to include
  4763. * the 11 of the dummy address as part of the opcode than it is to shift
  4764. * it over the correct number of bits for the address. This puts the
  4765. * EEPROM into write/erase mode.
  4766. */
  4767. e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
  4768. (uint16_t)(eeprom->opcode_bits + 2));
  4769. e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
  4770. /* Prepare the EEPROM */
  4771. e1000_standby_eeprom(hw);
  4772. while (words_written < words) {
  4773. /* Send the Write command (3-bit opcode + addr) */
  4774. e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
  4775. eeprom->opcode_bits);
  4776. e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
  4777. eeprom->address_bits);
  4778. /* Send the data */
  4779. e1000_shift_out_ee_bits(hw, data[words_written], 16);
  4780. /* Toggle the CS line. This in effect tells the EEPROM to execute
  4781. * the previous command.
  4782. */
  4783. e1000_standby_eeprom(hw);
  4784. /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
  4785. * signal that the command has been completed by raising the DO signal.
  4786. * If DO does not go high in 10 milliseconds, then error out.
  4787. */
  4788. for (i = 0; i < 200; i++) {
  4789. eecd = E1000_READ_REG(hw, EECD);
  4790. if (eecd & E1000_EECD_DO) break;
  4791. udelay(50);
  4792. }
  4793. if (i == 200) {
  4794. DEBUGOUT("EEPROM Write did not complete\n");
  4795. return -E1000_ERR_EEPROM;
  4796. }
  4797. /* Recover from write */
  4798. e1000_standby_eeprom(hw);
  4799. words_written++;
  4800. }
  4801. /* Send the write disable command to the EEPROM (3-bit opcode plus
  4802. * 6/8-bit dummy address beginning with 10). It's less work to include
  4803. * the 10 of the dummy address as part of the opcode than it is to shift
  4804. * it over the correct number of bits for the address. This takes the
  4805. * EEPROM out of write/erase mode.
  4806. */
  4807. e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
  4808. (uint16_t)(eeprom->opcode_bits + 2));
  4809. e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
  4810. return E1000_SUCCESS;
  4811. }
  4812. /******************************************************************************
  4813. * Flushes the cached eeprom to NVM. This is done by saving the modified values
  4814. * in the eeprom cache and the non modified values in the currently active bank
  4815. * to the new bank.
  4816. *
  4817. * hw - Struct containing variables accessed by shared code
  4818. * offset - offset of word in the EEPROM to read
  4819. * data - word read from the EEPROM
  4820. * words - number of words to read
  4821. *****************************************************************************/
  4822. static int32_t
  4823. e1000_commit_shadow_ram(struct e1000_hw *hw)
  4824. {
  4825. uint32_t attempts = 100000;
  4826. uint32_t eecd = 0;
  4827. uint32_t flop = 0;
  4828. uint32_t i = 0;
  4829. int32_t error = E1000_SUCCESS;
  4830. uint32_t old_bank_offset = 0;
  4831. uint32_t new_bank_offset = 0;
  4832. uint8_t low_byte = 0;
  4833. uint8_t high_byte = 0;
  4834. boolean_t sector_write_failed = FALSE;
  4835. if (hw->mac_type == e1000_82573) {
  4836. /* The flop register will be used to determine if flash type is STM */
  4837. flop = E1000_READ_REG(hw, FLOP);
  4838. for (i=0; i < attempts; i++) {
  4839. eecd = E1000_READ_REG(hw, EECD);
  4840. if ((eecd & E1000_EECD_FLUPD) == 0) {
  4841. break;
  4842. }
  4843. udelay(5);
  4844. }
  4845. if (i == attempts) {
  4846. return -E1000_ERR_EEPROM;
  4847. }
  4848. /* If STM opcode located in bits 15:8 of flop, reset firmware */
  4849. if ((flop & 0xFF00) == E1000_STM_OPCODE) {
  4850. E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
  4851. }
  4852. /* Perform the flash update */
  4853. E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
  4854. for (i=0; i < attempts; i++) {
  4855. eecd = E1000_READ_REG(hw, EECD);
  4856. if ((eecd & E1000_EECD_FLUPD) == 0) {
  4857. break;
  4858. }
  4859. udelay(5);
  4860. }
  4861. if (i == attempts) {
  4862. return -E1000_ERR_EEPROM;
  4863. }
  4864. }
  4865. if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
  4866. /* We're writing to the opposite bank so if we're on bank 1,
  4867. * write to bank 0 etc. We also need to erase the segment that
  4868. * is going to be written */
  4869. if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
  4870. new_bank_offset = hw->flash_bank_size * 2;
  4871. old_bank_offset = 0;
  4872. e1000_erase_ich8_4k_segment(hw, 1);
  4873. } else {
  4874. old_bank_offset = hw->flash_bank_size * 2;
  4875. new_bank_offset = 0;
  4876. e1000_erase_ich8_4k_segment(hw, 0);
  4877. }
  4878. sector_write_failed = FALSE;
  4879. /* Loop for every byte in the shadow RAM,
  4880. * which is in units of words. */
  4881. for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
  4882. /* Determine whether to write the value stored
  4883. * in the other NVM bank or a modified value stored
  4884. * in the shadow RAM */
  4885. if (hw->eeprom_shadow_ram[i].modified == TRUE) {
  4886. low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
  4887. udelay(100);
  4888. error = e1000_verify_write_ich8_byte(hw,
  4889. (i << 1) + new_bank_offset, low_byte);
  4890. if (error != E1000_SUCCESS)
  4891. sector_write_failed = TRUE;
  4892. else {
  4893. high_byte =
  4894. (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
  4895. udelay(100);
  4896. }
  4897. } else {
  4898. e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
  4899. &low_byte);
  4900. udelay(100);
  4901. error = e1000_verify_write_ich8_byte(hw,
  4902. (i << 1) + new_bank_offset, low_byte);
  4903. if (error != E1000_SUCCESS)
  4904. sector_write_failed = TRUE;
  4905. else {
  4906. e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
  4907. &high_byte);
  4908. udelay(100);
  4909. }
  4910. }
  4911. /* If the write of the low byte was successful, go ahread and
  4912. * write the high byte while checking to make sure that if it
  4913. * is the signature byte, then it is handled properly */
  4914. if (sector_write_failed == FALSE) {
  4915. /* If the word is 0x13, then make sure the signature bits
  4916. * (15:14) are 11b until the commit has completed.
  4917. * This will allow us to write 10b which indicates the
  4918. * signature is valid. We want to do this after the write
  4919. * has completed so that we don't mark the segment valid
  4920. * while the write is still in progress */
  4921. if (i == E1000_ICH_NVM_SIG_WORD)
  4922. high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
  4923. error = e1000_verify_write_ich8_byte(hw,
  4924. (i << 1) + new_bank_offset + 1, high_byte);
  4925. if (error != E1000_SUCCESS)
  4926. sector_write_failed = TRUE;
  4927. } else {
  4928. /* If the write failed then break from the loop and
  4929. * return an error */
  4930. break;
  4931. }
  4932. }
  4933. /* Don't bother writing the segment valid bits if sector
  4934. * programming failed. */
  4935. if (sector_write_failed == FALSE) {
  4936. /* Finally validate the new segment by setting bit 15:14
  4937. * to 10b in word 0x13 , this can be done without an
  4938. * erase as well since these bits are 11 to start with
  4939. * and we need to change bit 14 to 0b */
  4940. e1000_read_ich8_byte(hw,
  4941. E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
  4942. &high_byte);
  4943. high_byte &= 0xBF;
  4944. error = e1000_verify_write_ich8_byte(hw,
  4945. E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
  4946. /* And invalidate the previously valid segment by setting
  4947. * its signature word (0x13) high_byte to 0b. This can be
  4948. * done without an erase because flash erase sets all bits
  4949. * to 1's. We can write 1's to 0's without an erase */
  4950. if (error == E1000_SUCCESS) {
  4951. error = e1000_verify_write_ich8_byte(hw,
  4952. E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
  4953. }
  4954. /* Clear the now not used entry in the cache */
  4955. for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
  4956. hw->eeprom_shadow_ram[i].modified = FALSE;
  4957. hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
  4958. }
  4959. }
  4960. }
  4961. return error;
  4962. }
  4963. /******************************************************************************
  4964. * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
  4965. * second function of dual function devices
  4966. *
  4967. * hw - Struct containing variables accessed by shared code
  4968. *****************************************************************************/
  4969. int32_t
  4970. e1000_read_mac_addr(struct e1000_hw * hw)
  4971. {
  4972. uint16_t offset;
  4973. uint16_t eeprom_data, i;
  4974. DEBUGFUNC("e1000_read_mac_addr");
  4975. for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  4976. offset = i >> 1;
  4977. if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
  4978. DEBUGOUT("EEPROM Read Error\n");
  4979. return -E1000_ERR_EEPROM;
  4980. }
  4981. hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
  4982. hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
  4983. }
  4984. switch (hw->mac_type) {
  4985. default:
  4986. break;
  4987. case e1000_82546:
  4988. case e1000_82546_rev_3:
  4989. case e1000_82571:
  4990. case e1000_80003es2lan:
  4991. if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
  4992. hw->perm_mac_addr[5] ^= 0x01;
  4993. break;
  4994. }
  4995. for (i = 0; i < NODE_ADDRESS_SIZE; i++)
  4996. hw->mac_addr[i] = hw->perm_mac_addr[i];
  4997. return E1000_SUCCESS;
  4998. }
  4999. /******************************************************************************
  5000. * Initializes receive address filters.
  5001. *
  5002. * hw - Struct containing variables accessed by shared code
  5003. *
  5004. * Places the MAC address in receive address register 0 and clears the rest
  5005. * of the receive addresss registers. Clears the multicast table. Assumes
  5006. * the receiver is in reset when the routine is called.
  5007. *****************************************************************************/
  5008. static void
  5009. e1000_init_rx_addrs(struct e1000_hw *hw)
  5010. {
  5011. uint32_t i;
  5012. uint32_t rar_num;
  5013. DEBUGFUNC("e1000_init_rx_addrs");
  5014. /* Setup the receive address. */
  5015. DEBUGOUT("Programming MAC Address into RAR[0]\n");
  5016. e1000_rar_set(hw, hw->mac_addr, 0);
  5017. rar_num = E1000_RAR_ENTRIES;
  5018. /* Reserve a spot for the Locally Administered Address to work around
  5019. * an 82571 issue in which a reset on one port will reload the MAC on
  5020. * the other port. */
  5021. if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
  5022. rar_num -= 1;
  5023. if (hw->mac_type == e1000_ich8lan)
  5024. rar_num = E1000_RAR_ENTRIES_ICH8LAN;
  5025. /* Zero out the other 15 receive addresses. */
  5026. DEBUGOUT("Clearing RAR[1-15]\n");
  5027. for (i = 1; i < rar_num; i++) {
  5028. E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
  5029. E1000_WRITE_FLUSH(hw);
  5030. E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
  5031. E1000_WRITE_FLUSH(hw);
  5032. }
  5033. }
  5034. /******************************************************************************
  5035. * Hashes an address to determine its location in the multicast table
  5036. *
  5037. * hw - Struct containing variables accessed by shared code
  5038. * mc_addr - the multicast address to hash
  5039. *****************************************************************************/
  5040. uint32_t
  5041. e1000_hash_mc_addr(struct e1000_hw *hw,
  5042. uint8_t *mc_addr)
  5043. {
  5044. uint32_t hash_value = 0;
  5045. /* The portion of the address that is used for the hash table is
  5046. * determined by the mc_filter_type setting.
  5047. */
  5048. switch (hw->mc_filter_type) {
  5049. /* [0] [1] [2] [3] [4] [5]
  5050. * 01 AA 00 12 34 56
  5051. * LSB MSB
  5052. */
  5053. case 0:
  5054. if (hw->mac_type == e1000_ich8lan) {
  5055. /* [47:38] i.e. 0x158 for above example address */
  5056. hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
  5057. } else {
  5058. /* [47:36] i.e. 0x563 for above example address */
  5059. hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
  5060. }
  5061. break;
  5062. case 1:
  5063. if (hw->mac_type == e1000_ich8lan) {
  5064. /* [46:37] i.e. 0x2B1 for above example address */
  5065. hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
  5066. } else {
  5067. /* [46:35] i.e. 0xAC6 for above example address */
  5068. hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
  5069. }
  5070. break;
  5071. case 2:
  5072. if (hw->mac_type == e1000_ich8lan) {
  5073. /*[45:36] i.e. 0x163 for above example address */
  5074. hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
  5075. } else {
  5076. /* [45:34] i.e. 0x5D8 for above example address */
  5077. hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
  5078. }
  5079. break;
  5080. case 3:
  5081. if (hw->mac_type == e1000_ich8lan) {
  5082. /* [43:34] i.e. 0x18D for above example address */
  5083. hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
  5084. } else {
  5085. /* [43:32] i.e. 0x634 for above example address */
  5086. hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
  5087. }
  5088. break;
  5089. }
  5090. hash_value &= 0xFFF;
  5091. if (hw->mac_type == e1000_ich8lan)
  5092. hash_value &= 0x3FF;
  5093. return hash_value;
  5094. }
  5095. /******************************************************************************
  5096. * Sets the bit in the multicast table corresponding to the hash value.
  5097. *
  5098. * hw - Struct containing variables accessed by shared code
  5099. * hash_value - Multicast address hash value
  5100. *****************************************************************************/
  5101. void
  5102. e1000_mta_set(struct e1000_hw *hw,
  5103. uint32_t hash_value)
  5104. {
  5105. uint32_t hash_bit, hash_reg;
  5106. uint32_t mta;
  5107. uint32_t temp;
  5108. /* The MTA is a register array of 128 32-bit registers.
  5109. * It is treated like an array of 4096 bits. We want to set
  5110. * bit BitArray[hash_value]. So we figure out what register
  5111. * the bit is in, read it, OR in the new bit, then write
  5112. * back the new value. The register is determined by the
  5113. * upper 7 bits of the hash value and the bit within that
  5114. * register are determined by the lower 5 bits of the value.
  5115. */
  5116. hash_reg = (hash_value >> 5) & 0x7F;
  5117. if (hw->mac_type == e1000_ich8lan)
  5118. hash_reg &= 0x1F;
  5119. hash_bit = hash_value & 0x1F;
  5120. mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
  5121. mta |= (1 << hash_bit);
  5122. /* If we are on an 82544 and we are trying to write an odd offset
  5123. * in the MTA, save off the previous entry before writing and
  5124. * restore the old value after writing.
  5125. */
  5126. if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
  5127. temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
  5128. E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
  5129. E1000_WRITE_FLUSH(hw);
  5130. E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
  5131. E1000_WRITE_FLUSH(hw);
  5132. } else {
  5133. E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
  5134. E1000_WRITE_FLUSH(hw);
  5135. }
  5136. }
  5137. /******************************************************************************
  5138. * Puts an ethernet address into a receive address register.
  5139. *
  5140. * hw - Struct containing variables accessed by shared code
  5141. * addr - Address to put into receive address register
  5142. * index - Receive address register to write
  5143. *****************************************************************************/
  5144. void
  5145. e1000_rar_set(struct e1000_hw *hw,
  5146. uint8_t *addr,
  5147. uint32_t index)
  5148. {
  5149. uint32_t rar_low, rar_high;
  5150. /* HW expects these in little endian so we reverse the byte order
  5151. * from network order (big endian) to little endian
  5152. */
  5153. rar_low = ((uint32_t) addr[0] |
  5154. ((uint32_t) addr[1] << 8) |
  5155. ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
  5156. rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
  5157. /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
  5158. * unit hang.
  5159. *
  5160. * Description:
  5161. * If there are any Rx frames queued up or otherwise present in the HW
  5162. * before RSS is enabled, and then we enable RSS, the HW Rx unit will
  5163. * hang. To work around this issue, we have to disable receives and
  5164. * flush out all Rx frames before we enable RSS. To do so, we modify we
  5165. * redirect all Rx traffic to manageability and then reset the HW.
  5166. * This flushes away Rx frames, and (since the redirections to
  5167. * manageability persists across resets) keeps new ones from coming in
  5168. * while we work. Then, we clear the Address Valid AV bit for all MAC
  5169. * addresses and undo the re-direction to manageability.
  5170. * Now, frames are coming in again, but the MAC won't accept them, so
  5171. * far so good. We now proceed to initialize RSS (if necessary) and
  5172. * configure the Rx unit. Last, we re-enable the AV bits and continue
  5173. * on our merry way.
  5174. */
  5175. switch (hw->mac_type) {
  5176. case e1000_82571:
  5177. case e1000_82572:
  5178. case e1000_80003es2lan:
  5179. if (hw->leave_av_bit_off == TRUE)
  5180. break;
  5181. default:
  5182. /* Indicate to hardware the Address is Valid. */
  5183. rar_high |= E1000_RAH_AV;
  5184. break;
  5185. }
  5186. E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
  5187. E1000_WRITE_FLUSH(hw);
  5188. E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
  5189. E1000_WRITE_FLUSH(hw);
  5190. }
  5191. /******************************************************************************
  5192. * Writes a value to the specified offset in the VLAN filter table.
  5193. *
  5194. * hw - Struct containing variables accessed by shared code
  5195. * offset - Offset in VLAN filer table to write
  5196. * value - Value to write into VLAN filter table
  5197. *****************************************************************************/
  5198. void
  5199. e1000_write_vfta(struct e1000_hw *hw,
  5200. uint32_t offset,
  5201. uint32_t value)
  5202. {
  5203. uint32_t temp;
  5204. if (hw->mac_type == e1000_ich8lan)
  5205. return;
  5206. if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
  5207. temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
  5208. E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
  5209. E1000_WRITE_FLUSH(hw);
  5210. E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
  5211. E1000_WRITE_FLUSH(hw);
  5212. } else {
  5213. E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
  5214. E1000_WRITE_FLUSH(hw);
  5215. }
  5216. }
  5217. /******************************************************************************
  5218. * Clears the VLAN filer table
  5219. *
  5220. * hw - Struct containing variables accessed by shared code
  5221. *****************************************************************************/
  5222. static void
  5223. e1000_clear_vfta(struct e1000_hw *hw)
  5224. {
  5225. uint32_t offset;
  5226. uint32_t vfta_value = 0;
  5227. uint32_t vfta_offset = 0;
  5228. uint32_t vfta_bit_in_reg = 0;
  5229. if (hw->mac_type == e1000_ich8lan)
  5230. return;
  5231. if (hw->mac_type == e1000_82573) {
  5232. if (hw->mng_cookie.vlan_id != 0) {
  5233. /* The VFTA is a 4096b bit-field, each identifying a single VLAN
  5234. * ID. The following operations determine which 32b entry
  5235. * (i.e. offset) into the array we want to set the VLAN ID
  5236. * (i.e. bit) of the manageability unit. */
  5237. vfta_offset = (hw->mng_cookie.vlan_id >>
  5238. E1000_VFTA_ENTRY_SHIFT) &
  5239. E1000_VFTA_ENTRY_MASK;
  5240. vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
  5241. E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
  5242. }
  5243. }
  5244. for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
  5245. /* If the offset we want to clear is the same offset of the
  5246. * manageability VLAN ID, then clear all bits except that of the
  5247. * manageability unit */
  5248. vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
  5249. E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
  5250. E1000_WRITE_FLUSH(hw);
  5251. }
  5252. }
  5253. static int32_t
  5254. e1000_id_led_init(struct e1000_hw * hw)
  5255. {
  5256. uint32_t ledctl;
  5257. const uint32_t ledctl_mask = 0x000000FF;
  5258. const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
  5259. const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
  5260. uint16_t eeprom_data, i, temp;
  5261. const uint16_t led_mask = 0x0F;
  5262. DEBUGFUNC("e1000_id_led_init");
  5263. if (hw->mac_type < e1000_82540) {
  5264. /* Nothing to do */
  5265. return E1000_SUCCESS;
  5266. }
  5267. ledctl = E1000_READ_REG(hw, LEDCTL);
  5268. hw->ledctl_default = ledctl;
  5269. hw->ledctl_mode1 = hw->ledctl_default;
  5270. hw->ledctl_mode2 = hw->ledctl_default;
  5271. if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
  5272. DEBUGOUT("EEPROM Read Error\n");
  5273. return -E1000_ERR_EEPROM;
  5274. }
  5275. if ((hw->mac_type == e1000_82573) &&
  5276. (eeprom_data == ID_LED_RESERVED_82573))
  5277. eeprom_data = ID_LED_DEFAULT_82573;
  5278. else if ((eeprom_data == ID_LED_RESERVED_0000) ||
  5279. (eeprom_data == ID_LED_RESERVED_FFFF)) {
  5280. if (hw->mac_type == e1000_ich8lan)
  5281. eeprom_data = ID_LED_DEFAULT_ICH8LAN;
  5282. else
  5283. eeprom_data = ID_LED_DEFAULT;
  5284. }
  5285. for (i = 0; i < 4; i++) {
  5286. temp = (eeprom_data >> (i << 2)) & led_mask;
  5287. switch (temp) {
  5288. case ID_LED_ON1_DEF2:
  5289. case ID_LED_ON1_ON2:
  5290. case ID_LED_ON1_OFF2:
  5291. hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
  5292. hw->ledctl_mode1 |= ledctl_on << (i << 3);
  5293. break;
  5294. case ID_LED_OFF1_DEF2:
  5295. case ID_LED_OFF1_ON2:
  5296. case ID_LED_OFF1_OFF2:
  5297. hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
  5298. hw->ledctl_mode1 |= ledctl_off << (i << 3);
  5299. break;
  5300. default:
  5301. /* Do nothing */
  5302. break;
  5303. }
  5304. switch (temp) {
  5305. case ID_LED_DEF1_ON2:
  5306. case ID_LED_ON1_ON2:
  5307. case ID_LED_OFF1_ON2:
  5308. hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
  5309. hw->ledctl_mode2 |= ledctl_on << (i << 3);
  5310. break;
  5311. case ID_LED_DEF1_OFF2:
  5312. case ID_LED_ON1_OFF2:
  5313. case ID_LED_OFF1_OFF2:
  5314. hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
  5315. hw->ledctl_mode2 |= ledctl_off << (i << 3);
  5316. break;
  5317. default:
  5318. /* Do nothing */
  5319. break;
  5320. }
  5321. }
  5322. return E1000_SUCCESS;
  5323. }
  5324. /******************************************************************************
  5325. * Prepares SW controlable LED for use and saves the current state of the LED.
  5326. *
  5327. * hw - Struct containing variables accessed by shared code
  5328. *****************************************************************************/
  5329. int32_t
  5330. e1000_setup_led(struct e1000_hw *hw)
  5331. {
  5332. uint32_t ledctl;
  5333. int32_t ret_val = E1000_SUCCESS;
  5334. DEBUGFUNC("e1000_setup_led");
  5335. switch (hw->mac_type) {
  5336. case e1000_82542_rev2_0:
  5337. case e1000_82542_rev2_1:
  5338. case e1000_82543:
  5339. case e1000_82544:
  5340. /* No setup necessary */
  5341. break;
  5342. case e1000_82541:
  5343. case e1000_82547:
  5344. case e1000_82541_rev_2:
  5345. case e1000_82547_rev_2:
  5346. /* Turn off PHY Smart Power Down (if enabled) */
  5347. ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
  5348. &hw->phy_spd_default);
  5349. if (ret_val)
  5350. return ret_val;
  5351. ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
  5352. (uint16_t)(hw->phy_spd_default &
  5353. ~IGP01E1000_GMII_SPD));
  5354. if (ret_val)
  5355. return ret_val;
  5356. /* Fall Through */
  5357. default:
  5358. if (hw->media_type == e1000_media_type_fiber) {
  5359. ledctl = E1000_READ_REG(hw, LEDCTL);
  5360. /* Save current LEDCTL settings */
  5361. hw->ledctl_default = ledctl;
  5362. /* Turn off LED0 */
  5363. ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
  5364. E1000_LEDCTL_LED0_BLINK |
  5365. E1000_LEDCTL_LED0_MODE_MASK);
  5366. ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
  5367. E1000_LEDCTL_LED0_MODE_SHIFT);
  5368. E1000_WRITE_REG(hw, LEDCTL, ledctl);
  5369. } else if (hw->media_type == e1000_media_type_copper)
  5370. E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
  5371. break;
  5372. }
  5373. return E1000_SUCCESS;
  5374. }
  5375. /******************************************************************************
  5376. * Used on 82571 and later Si that has LED blink bits.
  5377. * Callers must use their own timer and should have already called
  5378. * e1000_id_led_init()
  5379. * Call e1000_cleanup led() to stop blinking
  5380. *
  5381. * hw - Struct containing variables accessed by shared code
  5382. *****************************************************************************/
  5383. int32_t
  5384. e1000_blink_led_start(struct e1000_hw *hw)
  5385. {
  5386. int16_t i;
  5387. uint32_t ledctl_blink = 0;
  5388. DEBUGFUNC("e1000_id_led_blink_on");
  5389. if (hw->mac_type < e1000_82571) {
  5390. /* Nothing to do */
  5391. return E1000_SUCCESS;
  5392. }
  5393. if (hw->media_type == e1000_media_type_fiber) {
  5394. /* always blink LED0 for PCI-E fiber */
  5395. ledctl_blink = E1000_LEDCTL_LED0_BLINK |
  5396. (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
  5397. } else {
  5398. /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
  5399. ledctl_blink = hw->ledctl_mode2;
  5400. for (i=0; i < 4; i++)
  5401. if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
  5402. E1000_LEDCTL_MODE_LED_ON)
  5403. ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
  5404. }
  5405. E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
  5406. return E1000_SUCCESS;
  5407. }
  5408. /******************************************************************************
  5409. * Restores the saved state of the SW controlable LED.
  5410. *
  5411. * hw - Struct containing variables accessed by shared code
  5412. *****************************************************************************/
  5413. int32_t
  5414. e1000_cleanup_led(struct e1000_hw *hw)
  5415. {
  5416. int32_t ret_val = E1000_SUCCESS;
  5417. DEBUGFUNC("e1000_cleanup_led");
  5418. switch (hw->mac_type) {
  5419. case e1000_82542_rev2_0:
  5420. case e1000_82542_rev2_1:
  5421. case e1000_82543:
  5422. case e1000_82544:
  5423. /* No cleanup necessary */
  5424. break;
  5425. case e1000_82541:
  5426. case e1000_82547:
  5427. case e1000_82541_rev_2:
  5428. case e1000_82547_rev_2:
  5429. /* Turn on PHY Smart Power Down (if previously enabled) */
  5430. ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
  5431. hw->phy_spd_default);
  5432. if (ret_val)
  5433. return ret_val;
  5434. /* Fall Through */
  5435. default:
  5436. if (hw->phy_type == e1000_phy_ife) {
  5437. e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
  5438. break;
  5439. }
  5440. /* Restore LEDCTL settings */
  5441. E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
  5442. break;
  5443. }
  5444. return E1000_SUCCESS;
  5445. }
  5446. /******************************************************************************
  5447. * Turns on the software controllable LED
  5448. *
  5449. * hw - Struct containing variables accessed by shared code
  5450. *****************************************************************************/
  5451. int32_t
  5452. e1000_led_on(struct e1000_hw *hw)
  5453. {
  5454. uint32_t ctrl = E1000_READ_REG(hw, CTRL);
  5455. DEBUGFUNC("e1000_led_on");
  5456. switch (hw->mac_type) {
  5457. case e1000_82542_rev2_0:
  5458. case e1000_82542_rev2_1:
  5459. case e1000_82543:
  5460. /* Set SW Defineable Pin 0 to turn on the LED */
  5461. ctrl |= E1000_CTRL_SWDPIN0;
  5462. ctrl |= E1000_CTRL_SWDPIO0;
  5463. break;
  5464. case e1000_82544:
  5465. if (hw->media_type == e1000_media_type_fiber) {
  5466. /* Set SW Defineable Pin 0 to turn on the LED */
  5467. ctrl |= E1000_CTRL_SWDPIN0;
  5468. ctrl |= E1000_CTRL_SWDPIO0;
  5469. } else {
  5470. /* Clear SW Defineable Pin 0 to turn on the LED */
  5471. ctrl &= ~E1000_CTRL_SWDPIN0;
  5472. ctrl |= E1000_CTRL_SWDPIO0;
  5473. }
  5474. break;
  5475. default:
  5476. if (hw->media_type == e1000_media_type_fiber) {
  5477. /* Clear SW Defineable Pin 0 to turn on the LED */
  5478. ctrl &= ~E1000_CTRL_SWDPIN0;
  5479. ctrl |= E1000_CTRL_SWDPIO0;
  5480. } else if (hw->phy_type == e1000_phy_ife) {
  5481. e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
  5482. (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
  5483. } else if (hw->media_type == e1000_media_type_copper) {
  5484. E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
  5485. return E1000_SUCCESS;
  5486. }
  5487. break;
  5488. }
  5489. E1000_WRITE_REG(hw, CTRL, ctrl);
  5490. return E1000_SUCCESS;
  5491. }
  5492. /******************************************************************************
  5493. * Turns off the software controllable LED
  5494. *
  5495. * hw - Struct containing variables accessed by shared code
  5496. *****************************************************************************/
  5497. int32_t
  5498. e1000_led_off(struct e1000_hw *hw)
  5499. {
  5500. uint32_t ctrl = E1000_READ_REG(hw, CTRL);
  5501. DEBUGFUNC("e1000_led_off");
  5502. switch (hw->mac_type) {
  5503. case e1000_82542_rev2_0:
  5504. case e1000_82542_rev2_1:
  5505. case e1000_82543:
  5506. /* Clear SW Defineable Pin 0 to turn off the LED */
  5507. ctrl &= ~E1000_CTRL_SWDPIN0;
  5508. ctrl |= E1000_CTRL_SWDPIO0;
  5509. break;
  5510. case e1000_82544:
  5511. if (hw->media_type == e1000_media_type_fiber) {
  5512. /* Clear SW Defineable Pin 0 to turn off the LED */
  5513. ctrl &= ~E1000_CTRL_SWDPIN0;
  5514. ctrl |= E1000_CTRL_SWDPIO0;
  5515. } else {
  5516. /* Set SW Defineable Pin 0 to turn off the LED */
  5517. ctrl |= E1000_CTRL_SWDPIN0;
  5518. ctrl |= E1000_CTRL_SWDPIO0;
  5519. }
  5520. break;
  5521. default:
  5522. if (hw->media_type == e1000_media_type_fiber) {
  5523. /* Set SW Defineable Pin 0 to turn off the LED */
  5524. ctrl |= E1000_CTRL_SWDPIN0;
  5525. ctrl |= E1000_CTRL_SWDPIO0;
  5526. } else if (hw->phy_type == e1000_phy_ife) {
  5527. e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
  5528. (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
  5529. } else if (hw->media_type == e1000_media_type_copper) {
  5530. E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
  5531. return E1000_SUCCESS;
  5532. }
  5533. break;
  5534. }
  5535. E1000_WRITE_REG(hw, CTRL, ctrl);
  5536. return E1000_SUCCESS;
  5537. }
  5538. /******************************************************************************
  5539. * Clears all hardware statistics counters.
  5540. *
  5541. * hw - Struct containing variables accessed by shared code
  5542. *****************************************************************************/
  5543. static void
  5544. e1000_clear_hw_cntrs(struct e1000_hw *hw)
  5545. {
  5546. volatile uint32_t temp;
  5547. temp = E1000_READ_REG(hw, CRCERRS);
  5548. temp = E1000_READ_REG(hw, SYMERRS);
  5549. temp = E1000_READ_REG(hw, MPC);
  5550. temp = E1000_READ_REG(hw, SCC);
  5551. temp = E1000_READ_REG(hw, ECOL);
  5552. temp = E1000_READ_REG(hw, MCC);
  5553. temp = E1000_READ_REG(hw, LATECOL);
  5554. temp = E1000_READ_REG(hw, COLC);
  5555. temp = E1000_READ_REG(hw, DC);
  5556. temp = E1000_READ_REG(hw, SEC);
  5557. temp = E1000_READ_REG(hw, RLEC);
  5558. temp = E1000_READ_REG(hw, XONRXC);
  5559. temp = E1000_READ_REG(hw, XONTXC);
  5560. temp = E1000_READ_REG(hw, XOFFRXC);
  5561. temp = E1000_READ_REG(hw, XOFFTXC);
  5562. temp = E1000_READ_REG(hw, FCRUC);
  5563. if (hw->mac_type != e1000_ich8lan) {
  5564. temp = E1000_READ_REG(hw, PRC64);
  5565. temp = E1000_READ_REG(hw, PRC127);
  5566. temp = E1000_READ_REG(hw, PRC255);
  5567. temp = E1000_READ_REG(hw, PRC511);
  5568. temp = E1000_READ_REG(hw, PRC1023);
  5569. temp = E1000_READ_REG(hw, PRC1522);
  5570. }
  5571. temp = E1000_READ_REG(hw, GPRC);
  5572. temp = E1000_READ_REG(hw, BPRC);
  5573. temp = E1000_READ_REG(hw, MPRC);
  5574. temp = E1000_READ_REG(hw, GPTC);
  5575. temp = E1000_READ_REG(hw, GORCL);
  5576. temp = E1000_READ_REG(hw, GORCH);
  5577. temp = E1000_READ_REG(hw, GOTCL);
  5578. temp = E1000_READ_REG(hw, GOTCH);
  5579. temp = E1000_READ_REG(hw, RNBC);
  5580. temp = E1000_READ_REG(hw, RUC);
  5581. temp = E1000_READ_REG(hw, RFC);
  5582. temp = E1000_READ_REG(hw, ROC);
  5583. temp = E1000_READ_REG(hw, RJC);
  5584. temp = E1000_READ_REG(hw, TORL);
  5585. temp = E1000_READ_REG(hw, TORH);
  5586. temp = E1000_READ_REG(hw, TOTL);
  5587. temp = E1000_READ_REG(hw, TOTH);
  5588. temp = E1000_READ_REG(hw, TPR);
  5589. temp = E1000_READ_REG(hw, TPT);
  5590. if (hw->mac_type != e1000_ich8lan) {
  5591. temp = E1000_READ_REG(hw, PTC64);
  5592. temp = E1000_READ_REG(hw, PTC127);
  5593. temp = E1000_READ_REG(hw, PTC255);
  5594. temp = E1000_READ_REG(hw, PTC511);
  5595. temp = E1000_READ_REG(hw, PTC1023);
  5596. temp = E1000_READ_REG(hw, PTC1522);
  5597. }
  5598. temp = E1000_READ_REG(hw, MPTC);
  5599. temp = E1000_READ_REG(hw, BPTC);
  5600. if (hw->mac_type < e1000_82543) return;
  5601. temp = E1000_READ_REG(hw, ALGNERRC);
  5602. temp = E1000_READ_REG(hw, RXERRC);
  5603. temp = E1000_READ_REG(hw, TNCRS);
  5604. temp = E1000_READ_REG(hw, CEXTERR);
  5605. temp = E1000_READ_REG(hw, TSCTC);
  5606. temp = E1000_READ_REG(hw, TSCTFC);
  5607. if (hw->mac_type <= e1000_82544) return;
  5608. temp = E1000_READ_REG(hw, MGTPRC);
  5609. temp = E1000_READ_REG(hw, MGTPDC);
  5610. temp = E1000_READ_REG(hw, MGTPTC);
  5611. if (hw->mac_type <= e1000_82547_rev_2) return;
  5612. temp = E1000_READ_REG(hw, IAC);
  5613. temp = E1000_READ_REG(hw, ICRXOC);
  5614. if (hw->mac_type == e1000_ich8lan) return;
  5615. temp = E1000_READ_REG(hw, ICRXPTC);
  5616. temp = E1000_READ_REG(hw, ICRXATC);
  5617. temp = E1000_READ_REG(hw, ICTXPTC);
  5618. temp = E1000_READ_REG(hw, ICTXATC);
  5619. temp = E1000_READ_REG(hw, ICTXQEC);
  5620. temp = E1000_READ_REG(hw, ICTXQMTC);
  5621. temp = E1000_READ_REG(hw, ICRXDMTC);
  5622. }
  5623. /******************************************************************************
  5624. * Resets Adaptive IFS to its default state.
  5625. *
  5626. * hw - Struct containing variables accessed by shared code
  5627. *
  5628. * Call this after e1000_init_hw. You may override the IFS defaults by setting
  5629. * hw->ifs_params_forced to TRUE. However, you must initialize hw->
  5630. * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
  5631. * before calling this function.
  5632. *****************************************************************************/
  5633. void
  5634. e1000_reset_adaptive(struct e1000_hw *hw)
  5635. {
  5636. DEBUGFUNC("e1000_reset_adaptive");
  5637. if (hw->adaptive_ifs) {
  5638. if (!hw->ifs_params_forced) {
  5639. hw->current_ifs_val = 0;
  5640. hw->ifs_min_val = IFS_MIN;
  5641. hw->ifs_max_val = IFS_MAX;
  5642. hw->ifs_step_size = IFS_STEP;
  5643. hw->ifs_ratio = IFS_RATIO;
  5644. }
  5645. hw->in_ifs_mode = FALSE;
  5646. E1000_WRITE_REG(hw, AIT, 0);
  5647. } else {
  5648. DEBUGOUT("Not in Adaptive IFS mode!\n");
  5649. }
  5650. }
  5651. /******************************************************************************
  5652. * Called during the callback/watchdog routine to update IFS value based on
  5653. * the ratio of transmits to collisions.
  5654. *
  5655. * hw - Struct containing variables accessed by shared code
  5656. * tx_packets - Number of transmits since last callback
  5657. * total_collisions - Number of collisions since last callback
  5658. *****************************************************************************/
  5659. void
  5660. e1000_update_adaptive(struct e1000_hw *hw)
  5661. {
  5662. DEBUGFUNC("e1000_update_adaptive");
  5663. if (hw->adaptive_ifs) {
  5664. if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
  5665. if (hw->tx_packet_delta > MIN_NUM_XMITS) {
  5666. hw->in_ifs_mode = TRUE;
  5667. if (hw->current_ifs_val < hw->ifs_max_val) {
  5668. if (hw->current_ifs_val == 0)
  5669. hw->current_ifs_val = hw->ifs_min_val;
  5670. else
  5671. hw->current_ifs_val += hw->ifs_step_size;
  5672. E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
  5673. }
  5674. }
  5675. } else {
  5676. if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
  5677. hw->current_ifs_val = 0;
  5678. hw->in_ifs_mode = FALSE;
  5679. E1000_WRITE_REG(hw, AIT, 0);
  5680. }
  5681. }
  5682. } else {
  5683. DEBUGOUT("Not in Adaptive IFS mode!\n");
  5684. }
  5685. }
  5686. /******************************************************************************
  5687. * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
  5688. *
  5689. * hw - Struct containing variables accessed by shared code
  5690. * frame_len - The length of the frame in question
  5691. * mac_addr - The Ethernet destination address of the frame in question
  5692. *****************************************************************************/
  5693. void
  5694. e1000_tbi_adjust_stats(struct e1000_hw *hw,
  5695. struct e1000_hw_stats *stats,
  5696. uint32_t frame_len,
  5697. uint8_t *mac_addr)
  5698. {
  5699. uint64_t carry_bit;
  5700. /* First adjust the frame length. */
  5701. frame_len--;
  5702. /* We need to adjust the statistics counters, since the hardware
  5703. * counters overcount this packet as a CRC error and undercount
  5704. * the packet as a good packet
  5705. */
  5706. /* This packet should not be counted as a CRC error. */
  5707. stats->crcerrs--;
  5708. /* This packet does count as a Good Packet Received. */
  5709. stats->gprc++;
  5710. /* Adjust the Good Octets received counters */
  5711. carry_bit = 0x80000000 & stats->gorcl;
  5712. stats->gorcl += frame_len;
  5713. /* If the high bit of Gorcl (the low 32 bits of the Good Octets
  5714. * Received Count) was one before the addition,
  5715. * AND it is zero after, then we lost the carry out,
  5716. * need to add one to Gorch (Good Octets Received Count High).
  5717. * This could be simplified if all environments supported
  5718. * 64-bit integers.
  5719. */
  5720. if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
  5721. stats->gorch++;
  5722. /* Is this a broadcast or multicast? Check broadcast first,
  5723. * since the test for a multicast frame will test positive on
  5724. * a broadcast frame.
  5725. */
  5726. if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
  5727. /* Broadcast packet */
  5728. stats->bprc++;
  5729. else if (*mac_addr & 0x01)
  5730. /* Multicast packet */
  5731. stats->mprc++;
  5732. if (frame_len == hw->max_frame_size) {
  5733. /* In this case, the hardware has overcounted the number of
  5734. * oversize frames.
  5735. */
  5736. if (stats->roc > 0)
  5737. stats->roc--;
  5738. }
  5739. /* Adjust the bin counters when the extra byte put the frame in the
  5740. * wrong bin. Remember that the frame_len was adjusted above.
  5741. */
  5742. if (frame_len == 64) {
  5743. stats->prc64++;
  5744. stats->prc127--;
  5745. } else if (frame_len == 127) {
  5746. stats->prc127++;
  5747. stats->prc255--;
  5748. } else if (frame_len == 255) {
  5749. stats->prc255++;
  5750. stats->prc511--;
  5751. } else if (frame_len == 511) {
  5752. stats->prc511++;
  5753. stats->prc1023--;
  5754. } else if (frame_len == 1023) {
  5755. stats->prc1023++;
  5756. stats->prc1522--;
  5757. } else if (frame_len == 1522) {
  5758. stats->prc1522++;
  5759. }
  5760. }
  5761. /******************************************************************************
  5762. * Gets the current PCI bus type, speed, and width of the hardware
  5763. *
  5764. * hw - Struct containing variables accessed by shared code
  5765. *****************************************************************************/
  5766. void
  5767. e1000_get_bus_info(struct e1000_hw *hw)
  5768. {
  5769. int32_t ret_val;
  5770. uint16_t pci_ex_link_status;
  5771. uint32_t status;
  5772. switch (hw->mac_type) {
  5773. case e1000_82542_rev2_0:
  5774. case e1000_82542_rev2_1:
  5775. hw->bus_type = e1000_bus_type_pci;
  5776. hw->bus_speed = e1000_bus_speed_unknown;
  5777. hw->bus_width = e1000_bus_width_unknown;
  5778. break;
  5779. case e1000_82571:
  5780. case e1000_82572:
  5781. case e1000_82573:
  5782. case e1000_80003es2lan:
  5783. hw->bus_type = e1000_bus_type_pci_express;
  5784. hw->bus_speed = e1000_bus_speed_2500;
  5785. ret_val = e1000_read_pcie_cap_reg(hw,
  5786. PCI_EX_LINK_STATUS,
  5787. &pci_ex_link_status);
  5788. if (ret_val)
  5789. hw->bus_width = e1000_bus_width_unknown;
  5790. else
  5791. hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
  5792. PCI_EX_LINK_WIDTH_SHIFT;
  5793. break;
  5794. case e1000_ich8lan:
  5795. hw->bus_type = e1000_bus_type_pci_express;
  5796. hw->bus_speed = e1000_bus_speed_2500;
  5797. hw->bus_width = e1000_bus_width_pciex_1;
  5798. break;
  5799. default:
  5800. status = E1000_READ_REG(hw, STATUS);
  5801. hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
  5802. e1000_bus_type_pcix : e1000_bus_type_pci;
  5803. if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
  5804. hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
  5805. e1000_bus_speed_66 : e1000_bus_speed_120;
  5806. } else if (hw->bus_type == e1000_bus_type_pci) {
  5807. hw->bus_speed = (status & E1000_STATUS_PCI66) ?
  5808. e1000_bus_speed_66 : e1000_bus_speed_33;
  5809. } else {
  5810. switch (status & E1000_STATUS_PCIX_SPEED) {
  5811. case E1000_STATUS_PCIX_SPEED_66:
  5812. hw->bus_speed = e1000_bus_speed_66;
  5813. break;
  5814. case E1000_STATUS_PCIX_SPEED_100:
  5815. hw->bus_speed = e1000_bus_speed_100;
  5816. break;
  5817. case E1000_STATUS_PCIX_SPEED_133:
  5818. hw->bus_speed = e1000_bus_speed_133;
  5819. break;
  5820. default:
  5821. hw->bus_speed = e1000_bus_speed_reserved;
  5822. break;
  5823. }
  5824. }
  5825. hw->bus_width = (status & E1000_STATUS_BUS64) ?
  5826. e1000_bus_width_64 : e1000_bus_width_32;
  5827. break;
  5828. }
  5829. }
  5830. /******************************************************************************
  5831. * Writes a value to one of the devices registers using port I/O (as opposed to
  5832. * memory mapped I/O). Only 82544 and newer devices support port I/O.
  5833. *
  5834. * hw - Struct containing variables accessed by shared code
  5835. * offset - offset to write to
  5836. * value - value to write
  5837. *****************************************************************************/
  5838. static void
  5839. e1000_write_reg_io(struct e1000_hw *hw,
  5840. uint32_t offset,
  5841. uint32_t value)
  5842. {
  5843. unsigned long io_addr = hw->io_base;
  5844. unsigned long io_data = hw->io_base + 4;
  5845. e1000_io_write(hw, io_addr, offset);
  5846. e1000_io_write(hw, io_data, value);
  5847. }
  5848. /******************************************************************************
  5849. * Estimates the cable length.
  5850. *
  5851. * hw - Struct containing variables accessed by shared code
  5852. * min_length - The estimated minimum length
  5853. * max_length - The estimated maximum length
  5854. *
  5855. * returns: - E1000_ERR_XXX
  5856. * E1000_SUCCESS
  5857. *
  5858. * This function always returns a ranged length (minimum & maximum).
  5859. * So for M88 phy's, this function interprets the one value returned from the
  5860. * register to the minimum and maximum range.
  5861. * For IGP phy's, the function calculates the range by the AGC registers.
  5862. *****************************************************************************/
  5863. static int32_t
  5864. e1000_get_cable_length(struct e1000_hw *hw,
  5865. uint16_t *min_length,
  5866. uint16_t *max_length)
  5867. {
  5868. int32_t ret_val;
  5869. uint16_t agc_value = 0;
  5870. uint16_t i, phy_data;
  5871. uint16_t cable_length;
  5872. DEBUGFUNC("e1000_get_cable_length");
  5873. *min_length = *max_length = 0;
  5874. /* Use old method for Phy older than IGP */
  5875. if (hw->phy_type == e1000_phy_m88) {
  5876. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
  5877. &phy_data);
  5878. if (ret_val)
  5879. return ret_val;
  5880. cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
  5881. M88E1000_PSSR_CABLE_LENGTH_SHIFT;
  5882. /* Convert the enum value to ranged values */
  5883. switch (cable_length) {
  5884. case e1000_cable_length_50:
  5885. *min_length = 0;
  5886. *max_length = e1000_igp_cable_length_50;
  5887. break;
  5888. case e1000_cable_length_50_80:
  5889. *min_length = e1000_igp_cable_length_50;
  5890. *max_length = e1000_igp_cable_length_80;
  5891. break;
  5892. case e1000_cable_length_80_110:
  5893. *min_length = e1000_igp_cable_length_80;
  5894. *max_length = e1000_igp_cable_length_110;
  5895. break;
  5896. case e1000_cable_length_110_140:
  5897. *min_length = e1000_igp_cable_length_110;
  5898. *max_length = e1000_igp_cable_length_140;
  5899. break;
  5900. case e1000_cable_length_140:
  5901. *min_length = e1000_igp_cable_length_140;
  5902. *max_length = e1000_igp_cable_length_170;
  5903. break;
  5904. default:
  5905. return -E1000_ERR_PHY;
  5906. break;
  5907. }
  5908. } else if (hw->phy_type == e1000_phy_gg82563) {
  5909. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
  5910. &phy_data);
  5911. if (ret_val)
  5912. return ret_val;
  5913. cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
  5914. switch (cable_length) {
  5915. case e1000_gg_cable_length_60:
  5916. *min_length = 0;
  5917. *max_length = e1000_igp_cable_length_60;
  5918. break;
  5919. case e1000_gg_cable_length_60_115:
  5920. *min_length = e1000_igp_cable_length_60;
  5921. *max_length = e1000_igp_cable_length_115;
  5922. break;
  5923. case e1000_gg_cable_length_115_150:
  5924. *min_length = e1000_igp_cable_length_115;
  5925. *max_length = e1000_igp_cable_length_150;
  5926. break;
  5927. case e1000_gg_cable_length_150:
  5928. *min_length = e1000_igp_cable_length_150;
  5929. *max_length = e1000_igp_cable_length_180;
  5930. break;
  5931. default:
  5932. return -E1000_ERR_PHY;
  5933. break;
  5934. }
  5935. } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
  5936. uint16_t cur_agc_value;
  5937. uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
  5938. uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
  5939. {IGP01E1000_PHY_AGC_A,
  5940. IGP01E1000_PHY_AGC_B,
  5941. IGP01E1000_PHY_AGC_C,
  5942. IGP01E1000_PHY_AGC_D};
  5943. /* Read the AGC registers for all channels */
  5944. for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
  5945. ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
  5946. if (ret_val)
  5947. return ret_val;
  5948. cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
  5949. /* Value bound check. */
  5950. if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
  5951. (cur_agc_value == 0))
  5952. return -E1000_ERR_PHY;
  5953. agc_value += cur_agc_value;
  5954. /* Update minimal AGC value. */
  5955. if (min_agc_value > cur_agc_value)
  5956. min_agc_value = cur_agc_value;
  5957. }
  5958. /* Remove the minimal AGC result for length < 50m */
  5959. if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
  5960. agc_value -= min_agc_value;
  5961. /* Get the average length of the remaining 3 channels */
  5962. agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
  5963. } else {
  5964. /* Get the average length of all the 4 channels. */
  5965. agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
  5966. }
  5967. /* Set the range of the calculated length. */
  5968. *min_length = ((e1000_igp_cable_length_table[agc_value] -
  5969. IGP01E1000_AGC_RANGE) > 0) ?
  5970. (e1000_igp_cable_length_table[agc_value] -
  5971. IGP01E1000_AGC_RANGE) : 0;
  5972. *max_length = e1000_igp_cable_length_table[agc_value] +
  5973. IGP01E1000_AGC_RANGE;
  5974. } else if (hw->phy_type == e1000_phy_igp_2 ||
  5975. hw->phy_type == e1000_phy_igp_3) {
  5976. uint16_t cur_agc_index, max_agc_index = 0;
  5977. uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
  5978. uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
  5979. {IGP02E1000_PHY_AGC_A,
  5980. IGP02E1000_PHY_AGC_B,
  5981. IGP02E1000_PHY_AGC_C,
  5982. IGP02E1000_PHY_AGC_D};
  5983. /* Read the AGC registers for all channels */
  5984. for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
  5985. ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
  5986. if (ret_val)
  5987. return ret_val;
  5988. /* Getting bits 15:9, which represent the combination of course and
  5989. * fine gain values. The result is a number that can be put into
  5990. * the lookup table to obtain the approximate cable length. */
  5991. cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
  5992. IGP02E1000_AGC_LENGTH_MASK;
  5993. /* Array index bound check. */
  5994. if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
  5995. (cur_agc_index == 0))
  5996. return -E1000_ERR_PHY;
  5997. /* Remove min & max AGC values from calculation. */
  5998. if (e1000_igp_2_cable_length_table[min_agc_index] >
  5999. e1000_igp_2_cable_length_table[cur_agc_index])
  6000. min_agc_index = cur_agc_index;
  6001. if (e1000_igp_2_cable_length_table[max_agc_index] <
  6002. e1000_igp_2_cable_length_table[cur_agc_index])
  6003. max_agc_index = cur_agc_index;
  6004. agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
  6005. }
  6006. agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
  6007. e1000_igp_2_cable_length_table[max_agc_index]);
  6008. agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
  6009. /* Calculate cable length with the error range of +/- 10 meters. */
  6010. *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
  6011. (agc_value - IGP02E1000_AGC_RANGE) : 0;
  6012. *max_length = agc_value + IGP02E1000_AGC_RANGE;
  6013. }
  6014. return E1000_SUCCESS;
  6015. }
  6016. /******************************************************************************
  6017. * Check the cable polarity
  6018. *
  6019. * hw - Struct containing variables accessed by shared code
  6020. * polarity - output parameter : 0 - Polarity is not reversed
  6021. * 1 - Polarity is reversed.
  6022. *
  6023. * returns: - E1000_ERR_XXX
  6024. * E1000_SUCCESS
  6025. *
  6026. * For phy's older then IGP, this function simply reads the polarity bit in the
  6027. * Phy Status register. For IGP phy's, this bit is valid only if link speed is
  6028. * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
  6029. * return 0. If the link speed is 1000 Mbps the polarity status is in the
  6030. * IGP01E1000_PHY_PCS_INIT_REG.
  6031. *****************************************************************************/
  6032. static int32_t
  6033. e1000_check_polarity(struct e1000_hw *hw,
  6034. e1000_rev_polarity *polarity)
  6035. {
  6036. int32_t ret_val;
  6037. uint16_t phy_data;
  6038. DEBUGFUNC("e1000_check_polarity");
  6039. if ((hw->phy_type == e1000_phy_m88) ||
  6040. (hw->phy_type == e1000_phy_gg82563)) {
  6041. /* return the Polarity bit in the Status register. */
  6042. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
  6043. &phy_data);
  6044. if (ret_val)
  6045. return ret_val;
  6046. *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
  6047. M88E1000_PSSR_REV_POLARITY_SHIFT) ?
  6048. e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
  6049. } else if (hw->phy_type == e1000_phy_igp ||
  6050. hw->phy_type == e1000_phy_igp_3 ||
  6051. hw->phy_type == e1000_phy_igp_2) {
  6052. /* Read the Status register to check the speed */
  6053. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
  6054. &phy_data);
  6055. if (ret_val)
  6056. return ret_val;
  6057. /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
  6058. * find the polarity status */
  6059. if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
  6060. IGP01E1000_PSSR_SPEED_1000MBPS) {
  6061. /* Read the GIG initialization PCS register (0x00B4) */
  6062. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
  6063. &phy_data);
  6064. if (ret_val)
  6065. return ret_val;
  6066. /* Check the polarity bits */
  6067. *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
  6068. e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
  6069. } else {
  6070. /* For 10 Mbps, read the polarity bit in the status register. (for
  6071. * 100 Mbps this bit is always 0) */
  6072. *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
  6073. e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
  6074. }
  6075. } else if (hw->phy_type == e1000_phy_ife) {
  6076. ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
  6077. &phy_data);
  6078. if (ret_val)
  6079. return ret_val;
  6080. *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
  6081. IFE_PESC_POLARITY_REVERSED_SHIFT) ?
  6082. e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
  6083. }
  6084. return E1000_SUCCESS;
  6085. }
  6086. /******************************************************************************
  6087. * Check if Downshift occured
  6088. *
  6089. * hw - Struct containing variables accessed by shared code
  6090. * downshift - output parameter : 0 - No Downshift ocured.
  6091. * 1 - Downshift ocured.
  6092. *
  6093. * returns: - E1000_ERR_XXX
  6094. * E1000_SUCCESS
  6095. *
  6096. * For phy's older then IGP, this function reads the Downshift bit in the Phy
  6097. * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
  6098. * Link Health register. In IGP this bit is latched high, so the driver must
  6099. * read it immediately after link is established.
  6100. *****************************************************************************/
  6101. static int32_t
  6102. e1000_check_downshift(struct e1000_hw *hw)
  6103. {
  6104. int32_t ret_val;
  6105. uint16_t phy_data;
  6106. DEBUGFUNC("e1000_check_downshift");
  6107. if (hw->phy_type == e1000_phy_igp ||
  6108. hw->phy_type == e1000_phy_igp_3 ||
  6109. hw->phy_type == e1000_phy_igp_2) {
  6110. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
  6111. &phy_data);
  6112. if (ret_val)
  6113. return ret_val;
  6114. hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
  6115. } else if ((hw->phy_type == e1000_phy_m88) ||
  6116. (hw->phy_type == e1000_phy_gg82563)) {
  6117. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
  6118. &phy_data);
  6119. if (ret_val)
  6120. return ret_val;
  6121. hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
  6122. M88E1000_PSSR_DOWNSHIFT_SHIFT;
  6123. } else if (hw->phy_type == e1000_phy_ife) {
  6124. /* e1000_phy_ife supports 10/100 speed only */
  6125. hw->speed_downgraded = FALSE;
  6126. }
  6127. return E1000_SUCCESS;
  6128. }
  6129. /*****************************************************************************
  6130. *
  6131. * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
  6132. * gigabit link is achieved to improve link quality.
  6133. *
  6134. * hw: Struct containing variables accessed by shared code
  6135. *
  6136. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  6137. * E1000_SUCCESS at any other case.
  6138. *
  6139. ****************************************************************************/
  6140. static int32_t
  6141. e1000_config_dsp_after_link_change(struct e1000_hw *hw,
  6142. boolean_t link_up)
  6143. {
  6144. int32_t ret_val;
  6145. uint16_t phy_data, phy_saved_data, speed, duplex, i;
  6146. uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
  6147. {IGP01E1000_PHY_AGC_PARAM_A,
  6148. IGP01E1000_PHY_AGC_PARAM_B,
  6149. IGP01E1000_PHY_AGC_PARAM_C,
  6150. IGP01E1000_PHY_AGC_PARAM_D};
  6151. uint16_t min_length, max_length;
  6152. DEBUGFUNC("e1000_config_dsp_after_link_change");
  6153. if (hw->phy_type != e1000_phy_igp)
  6154. return E1000_SUCCESS;
  6155. if (link_up) {
  6156. ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
  6157. if (ret_val) {
  6158. DEBUGOUT("Error getting link speed and duplex\n");
  6159. return ret_val;
  6160. }
  6161. if (speed == SPEED_1000) {
  6162. ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
  6163. if (ret_val)
  6164. return ret_val;
  6165. if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
  6166. min_length >= e1000_igp_cable_length_50) {
  6167. for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
  6168. ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
  6169. &phy_data);
  6170. if (ret_val)
  6171. return ret_val;
  6172. phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
  6173. ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
  6174. phy_data);
  6175. if (ret_val)
  6176. return ret_val;
  6177. }
  6178. hw->dsp_config_state = e1000_dsp_config_activated;
  6179. }
  6180. if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
  6181. (min_length < e1000_igp_cable_length_50)) {
  6182. uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
  6183. uint32_t idle_errs = 0;
  6184. /* clear previous idle error counts */
  6185. ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
  6186. &phy_data);
  6187. if (ret_val)
  6188. return ret_val;
  6189. for (i = 0; i < ffe_idle_err_timeout; i++) {
  6190. udelay(1000);
  6191. ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
  6192. &phy_data);
  6193. if (ret_val)
  6194. return ret_val;
  6195. idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
  6196. if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
  6197. hw->ffe_config_state = e1000_ffe_config_active;
  6198. ret_val = e1000_write_phy_reg(hw,
  6199. IGP01E1000_PHY_DSP_FFE,
  6200. IGP01E1000_PHY_DSP_FFE_CM_CP);
  6201. if (ret_val)
  6202. return ret_val;
  6203. break;
  6204. }
  6205. if (idle_errs)
  6206. ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
  6207. }
  6208. }
  6209. }
  6210. } else {
  6211. if (hw->dsp_config_state == e1000_dsp_config_activated) {
  6212. /* Save off the current value of register 0x2F5B to be restored at
  6213. * the end of the routines. */
  6214. ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
  6215. if (ret_val)
  6216. return ret_val;
  6217. /* Disable the PHY transmitter */
  6218. ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
  6219. if (ret_val)
  6220. return ret_val;
  6221. mdelay(20);
  6222. ret_val = e1000_write_phy_reg(hw, 0x0000,
  6223. IGP01E1000_IEEE_FORCE_GIGA);
  6224. if (ret_val)
  6225. return ret_val;
  6226. for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
  6227. ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
  6228. if (ret_val)
  6229. return ret_val;
  6230. phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
  6231. phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
  6232. ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
  6233. if (ret_val)
  6234. return ret_val;
  6235. }
  6236. ret_val = e1000_write_phy_reg(hw, 0x0000,
  6237. IGP01E1000_IEEE_RESTART_AUTONEG);
  6238. if (ret_val)
  6239. return ret_val;
  6240. mdelay(20);
  6241. /* Now enable the transmitter */
  6242. ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
  6243. if (ret_val)
  6244. return ret_val;
  6245. hw->dsp_config_state = e1000_dsp_config_enabled;
  6246. }
  6247. if (hw->ffe_config_state == e1000_ffe_config_active) {
  6248. /* Save off the current value of register 0x2F5B to be restored at
  6249. * the end of the routines. */
  6250. ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
  6251. if (ret_val)
  6252. return ret_val;
  6253. /* Disable the PHY transmitter */
  6254. ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
  6255. if (ret_val)
  6256. return ret_val;
  6257. mdelay(20);
  6258. ret_val = e1000_write_phy_reg(hw, 0x0000,
  6259. IGP01E1000_IEEE_FORCE_GIGA);
  6260. if (ret_val)
  6261. return ret_val;
  6262. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
  6263. IGP01E1000_PHY_DSP_FFE_DEFAULT);
  6264. if (ret_val)
  6265. return ret_val;
  6266. ret_val = e1000_write_phy_reg(hw, 0x0000,
  6267. IGP01E1000_IEEE_RESTART_AUTONEG);
  6268. if (ret_val)
  6269. return ret_val;
  6270. mdelay(20);
  6271. /* Now enable the transmitter */
  6272. ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
  6273. if (ret_val)
  6274. return ret_val;
  6275. hw->ffe_config_state = e1000_ffe_config_enabled;
  6276. }
  6277. }
  6278. return E1000_SUCCESS;
  6279. }
  6280. /*****************************************************************************
  6281. * Set PHY to class A mode
  6282. * Assumes the following operations will follow to enable the new class mode.
  6283. * 1. Do a PHY soft reset
  6284. * 2. Restart auto-negotiation or force link.
  6285. *
  6286. * hw - Struct containing variables accessed by shared code
  6287. ****************************************************************************/
  6288. static int32_t
  6289. e1000_set_phy_mode(struct e1000_hw *hw)
  6290. {
  6291. int32_t ret_val;
  6292. uint16_t eeprom_data;
  6293. DEBUGFUNC("e1000_set_phy_mode");
  6294. if ((hw->mac_type == e1000_82545_rev_3) &&
  6295. (hw->media_type == e1000_media_type_copper)) {
  6296. ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
  6297. if (ret_val) {
  6298. return ret_val;
  6299. }
  6300. if ((eeprom_data != EEPROM_RESERVED_WORD) &&
  6301. (eeprom_data & EEPROM_PHY_CLASS_A)) {
  6302. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
  6303. if (ret_val)
  6304. return ret_val;
  6305. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
  6306. if (ret_val)
  6307. return ret_val;
  6308. hw->phy_reset_disable = FALSE;
  6309. }
  6310. }
  6311. return E1000_SUCCESS;
  6312. }
  6313. /*****************************************************************************
  6314. *
  6315. * This function sets the lplu state according to the active flag. When
  6316. * activating lplu this function also disables smart speed and vise versa.
  6317. * lplu will not be activated unless the device autonegotiation advertisment
  6318. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  6319. * hw: Struct containing variables accessed by shared code
  6320. * active - true to enable lplu false to disable lplu.
  6321. *
  6322. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  6323. * E1000_SUCCESS at any other case.
  6324. *
  6325. ****************************************************************************/
  6326. static int32_t
  6327. e1000_set_d3_lplu_state(struct e1000_hw *hw,
  6328. boolean_t active)
  6329. {
  6330. uint32_t phy_ctrl = 0;
  6331. int32_t ret_val;
  6332. uint16_t phy_data;
  6333. DEBUGFUNC("e1000_set_d3_lplu_state");
  6334. if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
  6335. && hw->phy_type != e1000_phy_igp_3)
  6336. return E1000_SUCCESS;
  6337. /* During driver activity LPLU should not be used or it will attain link
  6338. * from the lowest speeds starting from 10Mbps. The capability is used for
  6339. * Dx transitions and states */
  6340. if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
  6341. ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
  6342. if (ret_val)
  6343. return ret_val;
  6344. } else if (hw->mac_type == e1000_ich8lan) {
  6345. /* MAC writes into PHY register based on the state transition
  6346. * and start auto-negotiation. SW driver can overwrite the settings
  6347. * in CSR PHY power control E1000_PHY_CTRL register. */
  6348. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  6349. } else {
  6350. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
  6351. if (ret_val)
  6352. return ret_val;
  6353. }
  6354. if (!active) {
  6355. if (hw->mac_type == e1000_82541_rev_2 ||
  6356. hw->mac_type == e1000_82547_rev_2) {
  6357. phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
  6358. ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
  6359. if (ret_val)
  6360. return ret_val;
  6361. } else {
  6362. if (hw->mac_type == e1000_ich8lan) {
  6363. phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
  6364. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  6365. } else {
  6366. phy_data &= ~IGP02E1000_PM_D3_LPLU;
  6367. ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  6368. phy_data);
  6369. if (ret_val)
  6370. return ret_val;
  6371. }
  6372. }
  6373. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  6374. * Dx states where the power conservation is most important. During
  6375. * driver activity we should enable SmartSpeed, so performance is
  6376. * maintained. */
  6377. if (hw->smart_speed == e1000_smart_speed_on) {
  6378. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  6379. &phy_data);
  6380. if (ret_val)
  6381. return ret_val;
  6382. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  6383. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  6384. phy_data);
  6385. if (ret_val)
  6386. return ret_val;
  6387. } else if (hw->smart_speed == e1000_smart_speed_off) {
  6388. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  6389. &phy_data);
  6390. if (ret_val)
  6391. return ret_val;
  6392. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  6393. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  6394. phy_data);
  6395. if (ret_val)
  6396. return ret_val;
  6397. }
  6398. } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
  6399. (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
  6400. (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
  6401. if (hw->mac_type == e1000_82541_rev_2 ||
  6402. hw->mac_type == e1000_82547_rev_2) {
  6403. phy_data |= IGP01E1000_GMII_FLEX_SPD;
  6404. ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
  6405. if (ret_val)
  6406. return ret_val;
  6407. } else {
  6408. if (hw->mac_type == e1000_ich8lan) {
  6409. phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
  6410. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  6411. } else {
  6412. phy_data |= IGP02E1000_PM_D3_LPLU;
  6413. ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  6414. phy_data);
  6415. if (ret_val)
  6416. return ret_val;
  6417. }
  6418. }
  6419. /* When LPLU is enabled we should disable SmartSpeed */
  6420. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  6421. if (ret_val)
  6422. return ret_val;
  6423. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  6424. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
  6425. if (ret_val)
  6426. return ret_val;
  6427. }
  6428. return E1000_SUCCESS;
  6429. }
  6430. /*****************************************************************************
  6431. *
  6432. * This function sets the lplu d0 state according to the active flag. When
  6433. * activating lplu this function also disables smart speed and vise versa.
  6434. * lplu will not be activated unless the device autonegotiation advertisment
  6435. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  6436. * hw: Struct containing variables accessed by shared code
  6437. * active - true to enable lplu false to disable lplu.
  6438. *
  6439. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  6440. * E1000_SUCCESS at any other case.
  6441. *
  6442. ****************************************************************************/
  6443. static int32_t
  6444. e1000_set_d0_lplu_state(struct e1000_hw *hw,
  6445. boolean_t active)
  6446. {
  6447. uint32_t phy_ctrl = 0;
  6448. int32_t ret_val;
  6449. uint16_t phy_data;
  6450. DEBUGFUNC("e1000_set_d0_lplu_state");
  6451. if (hw->mac_type <= e1000_82547_rev_2)
  6452. return E1000_SUCCESS;
  6453. if (hw->mac_type == e1000_ich8lan) {
  6454. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  6455. } else {
  6456. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
  6457. if (ret_val)
  6458. return ret_val;
  6459. }
  6460. if (!active) {
  6461. if (hw->mac_type == e1000_ich8lan) {
  6462. phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
  6463. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  6464. } else {
  6465. phy_data &= ~IGP02E1000_PM_D0_LPLU;
  6466. ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
  6467. if (ret_val)
  6468. return ret_val;
  6469. }
  6470. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  6471. * Dx states where the power conservation is most important. During
  6472. * driver activity we should enable SmartSpeed, so performance is
  6473. * maintained. */
  6474. if (hw->smart_speed == e1000_smart_speed_on) {
  6475. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  6476. &phy_data);
  6477. if (ret_val)
  6478. return ret_val;
  6479. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  6480. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  6481. phy_data);
  6482. if (ret_val)
  6483. return ret_val;
  6484. } else if (hw->smart_speed == e1000_smart_speed_off) {
  6485. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  6486. &phy_data);
  6487. if (ret_val)
  6488. return ret_val;
  6489. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  6490. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  6491. phy_data);
  6492. if (ret_val)
  6493. return ret_val;
  6494. }
  6495. } else {
  6496. if (hw->mac_type == e1000_ich8lan) {
  6497. phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
  6498. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  6499. } else {
  6500. phy_data |= IGP02E1000_PM_D0_LPLU;
  6501. ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
  6502. if (ret_val)
  6503. return ret_val;
  6504. }
  6505. /* When LPLU is enabled we should disable SmartSpeed */
  6506. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  6507. if (ret_val)
  6508. return ret_val;
  6509. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  6510. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
  6511. if (ret_val)
  6512. return ret_val;
  6513. }
  6514. return E1000_SUCCESS;
  6515. }
  6516. /******************************************************************************
  6517. * Change VCO speed register to improve Bit Error Rate performance of SERDES.
  6518. *
  6519. * hw - Struct containing variables accessed by shared code
  6520. *****************************************************************************/
  6521. static int32_t
  6522. e1000_set_vco_speed(struct e1000_hw *hw)
  6523. {
  6524. int32_t ret_val;
  6525. uint16_t default_page = 0;
  6526. uint16_t phy_data;
  6527. DEBUGFUNC("e1000_set_vco_speed");
  6528. switch (hw->mac_type) {
  6529. case e1000_82545_rev_3:
  6530. case e1000_82546_rev_3:
  6531. break;
  6532. default:
  6533. return E1000_SUCCESS;
  6534. }
  6535. /* Set PHY register 30, page 5, bit 8 to 0 */
  6536. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
  6537. if (ret_val)
  6538. return ret_val;
  6539. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
  6540. if (ret_val)
  6541. return ret_val;
  6542. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
  6543. if (ret_val)
  6544. return ret_val;
  6545. phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
  6546. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
  6547. if (ret_val)
  6548. return ret_val;
  6549. /* Set PHY register 30, page 4, bit 11 to 1 */
  6550. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
  6551. if (ret_val)
  6552. return ret_val;
  6553. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
  6554. if (ret_val)
  6555. return ret_val;
  6556. phy_data |= M88E1000_PHY_VCO_REG_BIT11;
  6557. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
  6558. if (ret_val)
  6559. return ret_val;
  6560. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
  6561. if (ret_val)
  6562. return ret_val;
  6563. return E1000_SUCCESS;
  6564. }
  6565. /*****************************************************************************
  6566. * This function reads the cookie from ARC ram.
  6567. *
  6568. * returns: - E1000_SUCCESS .
  6569. ****************************************************************************/
  6570. static int32_t
  6571. e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
  6572. {
  6573. uint8_t i;
  6574. uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
  6575. uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
  6576. length = (length >> 2);
  6577. offset = (offset >> 2);
  6578. for (i = 0; i < length; i++) {
  6579. *((uint32_t *) buffer + i) =
  6580. E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
  6581. }
  6582. return E1000_SUCCESS;
  6583. }
  6584. /*****************************************************************************
  6585. * This function checks whether the HOST IF is enabled for command operaton
  6586. * and also checks whether the previous command is completed.
  6587. * It busy waits in case of previous command is not completed.
  6588. *
  6589. * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
  6590. * timeout
  6591. * - E1000_SUCCESS for success.
  6592. ****************************************************************************/
  6593. static int32_t
  6594. e1000_mng_enable_host_if(struct e1000_hw * hw)
  6595. {
  6596. uint32_t hicr;
  6597. uint8_t i;
  6598. /* Check that the host interface is enabled. */
  6599. hicr = E1000_READ_REG(hw, HICR);
  6600. if ((hicr & E1000_HICR_EN) == 0) {
  6601. DEBUGOUT("E1000_HOST_EN bit disabled.\n");
  6602. return -E1000_ERR_HOST_INTERFACE_COMMAND;
  6603. }
  6604. /* check the previous command is completed */
  6605. for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
  6606. hicr = E1000_READ_REG(hw, HICR);
  6607. if (!(hicr & E1000_HICR_C))
  6608. break;
  6609. mdelay(1);
  6610. }
  6611. if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
  6612. DEBUGOUT("Previous command timeout failed .\n");
  6613. return -E1000_ERR_HOST_INTERFACE_COMMAND;
  6614. }
  6615. return E1000_SUCCESS;
  6616. }
  6617. /*****************************************************************************
  6618. * This function writes the buffer content at the offset given on the host if.
  6619. * It also does alignment considerations to do the writes in most efficient way.
  6620. * Also fills up the sum of the buffer in *buffer parameter.
  6621. *
  6622. * returns - E1000_SUCCESS for success.
  6623. ****************************************************************************/
  6624. static int32_t
  6625. e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
  6626. uint16_t length, uint16_t offset, uint8_t *sum)
  6627. {
  6628. uint8_t *tmp;
  6629. uint8_t *bufptr = buffer;
  6630. uint32_t data = 0;
  6631. uint16_t remaining, i, j, prev_bytes;
  6632. /* sum = only sum of the data and it is not checksum */
  6633. if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
  6634. return -E1000_ERR_PARAM;
  6635. }
  6636. tmp = (uint8_t *)&data;
  6637. prev_bytes = offset & 0x3;
  6638. offset &= 0xFFFC;
  6639. offset >>= 2;
  6640. if (prev_bytes) {
  6641. data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
  6642. for (j = prev_bytes; j < sizeof(uint32_t); j++) {
  6643. *(tmp + j) = *bufptr++;
  6644. *sum += *(tmp + j);
  6645. }
  6646. E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
  6647. length -= j - prev_bytes;
  6648. offset++;
  6649. }
  6650. remaining = length & 0x3;
  6651. length -= remaining;
  6652. /* Calculate length in DWORDs */
  6653. length >>= 2;
  6654. /* The device driver writes the relevant command block into the
  6655. * ram area. */
  6656. for (i = 0; i < length; i++) {
  6657. for (j = 0; j < sizeof(uint32_t); j++) {
  6658. *(tmp + j) = *bufptr++;
  6659. *sum += *(tmp + j);
  6660. }
  6661. E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
  6662. }
  6663. if (remaining) {
  6664. for (j = 0; j < sizeof(uint32_t); j++) {
  6665. if (j < remaining)
  6666. *(tmp + j) = *bufptr++;
  6667. else
  6668. *(tmp + j) = 0;
  6669. *sum += *(tmp + j);
  6670. }
  6671. E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
  6672. }
  6673. return E1000_SUCCESS;
  6674. }
  6675. /*****************************************************************************
  6676. * This function writes the command header after does the checksum calculation.
  6677. *
  6678. * returns - E1000_SUCCESS for success.
  6679. ****************************************************************************/
  6680. static int32_t
  6681. e1000_mng_write_cmd_header(struct e1000_hw * hw,
  6682. struct e1000_host_mng_command_header * hdr)
  6683. {
  6684. uint16_t i;
  6685. uint8_t sum;
  6686. uint8_t *buffer;
  6687. /* Write the whole command header structure which includes sum of
  6688. * the buffer */
  6689. uint16_t length = sizeof(struct e1000_host_mng_command_header);
  6690. sum = hdr->checksum;
  6691. hdr->checksum = 0;
  6692. buffer = (uint8_t *) hdr;
  6693. i = length;
  6694. while (i--)
  6695. sum += buffer[i];
  6696. hdr->checksum = 0 - sum;
  6697. length >>= 2;
  6698. /* The device driver writes the relevant command block into the ram area. */
  6699. for (i = 0; i < length; i++) {
  6700. E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
  6701. E1000_WRITE_FLUSH(hw);
  6702. }
  6703. return E1000_SUCCESS;
  6704. }
  6705. /*****************************************************************************
  6706. * This function indicates to ARC that a new command is pending which completes
  6707. * one write operation by the driver.
  6708. *
  6709. * returns - E1000_SUCCESS for success.
  6710. ****************************************************************************/
  6711. static int32_t
  6712. e1000_mng_write_commit(struct e1000_hw * hw)
  6713. {
  6714. uint32_t hicr;
  6715. hicr = E1000_READ_REG(hw, HICR);
  6716. /* Setting this bit tells the ARC that a new command is pending. */
  6717. E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
  6718. return E1000_SUCCESS;
  6719. }
  6720. /*****************************************************************************
  6721. * This function checks the mode of the firmware.
  6722. *
  6723. * returns - TRUE when the mode is IAMT or FALSE.
  6724. ****************************************************************************/
  6725. boolean_t
  6726. e1000_check_mng_mode(struct e1000_hw *hw)
  6727. {
  6728. uint32_t fwsm;
  6729. fwsm = E1000_READ_REG(hw, FWSM);
  6730. if (hw->mac_type == e1000_ich8lan) {
  6731. if ((fwsm & E1000_FWSM_MODE_MASK) ==
  6732. (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  6733. return TRUE;
  6734. } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
  6735. (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  6736. return TRUE;
  6737. return FALSE;
  6738. }
  6739. /*****************************************************************************
  6740. * This function writes the dhcp info .
  6741. ****************************************************************************/
  6742. int32_t
  6743. e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
  6744. uint16_t length)
  6745. {
  6746. int32_t ret_val;
  6747. struct e1000_host_mng_command_header hdr;
  6748. hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
  6749. hdr.command_length = length;
  6750. hdr.reserved1 = 0;
  6751. hdr.reserved2 = 0;
  6752. hdr.checksum = 0;
  6753. ret_val = e1000_mng_enable_host_if(hw);
  6754. if (ret_val == E1000_SUCCESS) {
  6755. ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
  6756. &(hdr.checksum));
  6757. if (ret_val == E1000_SUCCESS) {
  6758. ret_val = e1000_mng_write_cmd_header(hw, &hdr);
  6759. if (ret_val == E1000_SUCCESS)
  6760. ret_val = e1000_mng_write_commit(hw);
  6761. }
  6762. }
  6763. return ret_val;
  6764. }
  6765. /*****************************************************************************
  6766. * This function calculates the checksum.
  6767. *
  6768. * returns - checksum of buffer contents.
  6769. ****************************************************************************/
  6770. static uint8_t
  6771. e1000_calculate_mng_checksum(char *buffer, uint32_t length)
  6772. {
  6773. uint8_t sum = 0;
  6774. uint32_t i;
  6775. if (!buffer)
  6776. return 0;
  6777. for (i=0; i < length; i++)
  6778. sum += buffer[i];
  6779. return (uint8_t) (0 - sum);
  6780. }
  6781. /*****************************************************************************
  6782. * This function checks whether tx pkt filtering needs to be enabled or not.
  6783. *
  6784. * returns - TRUE for packet filtering or FALSE.
  6785. ****************************************************************************/
  6786. boolean_t
  6787. e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
  6788. {
  6789. /* called in init as well as watchdog timer functions */
  6790. int32_t ret_val, checksum;
  6791. boolean_t tx_filter = FALSE;
  6792. struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
  6793. uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
  6794. if (e1000_check_mng_mode(hw)) {
  6795. ret_val = e1000_mng_enable_host_if(hw);
  6796. if (ret_val == E1000_SUCCESS) {
  6797. ret_val = e1000_host_if_read_cookie(hw, buffer);
  6798. if (ret_val == E1000_SUCCESS) {
  6799. checksum = hdr->checksum;
  6800. hdr->checksum = 0;
  6801. if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
  6802. checksum == e1000_calculate_mng_checksum((char *)buffer,
  6803. E1000_MNG_DHCP_COOKIE_LENGTH)) {
  6804. if (hdr->status &
  6805. E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
  6806. tx_filter = TRUE;
  6807. } else
  6808. tx_filter = TRUE;
  6809. } else
  6810. tx_filter = TRUE;
  6811. }
  6812. }
  6813. hw->tx_pkt_filtering = tx_filter;
  6814. return tx_filter;
  6815. }
  6816. /******************************************************************************
  6817. * Verifies the hardware needs to allow ARPs to be processed by the host
  6818. *
  6819. * hw - Struct containing variables accessed by shared code
  6820. *
  6821. * returns: - TRUE/FALSE
  6822. *
  6823. *****************************************************************************/
  6824. uint32_t
  6825. e1000_enable_mng_pass_thru(struct e1000_hw *hw)
  6826. {
  6827. uint32_t manc;
  6828. uint32_t fwsm, factps;
  6829. if (hw->asf_firmware_present) {
  6830. manc = E1000_READ_REG(hw, MANC);
  6831. if (!(manc & E1000_MANC_RCV_TCO_EN) ||
  6832. !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
  6833. return FALSE;
  6834. if (e1000_arc_subsystem_valid(hw) == TRUE) {
  6835. fwsm = E1000_READ_REG(hw, FWSM);
  6836. factps = E1000_READ_REG(hw, FACTPS);
  6837. if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
  6838. e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
  6839. return TRUE;
  6840. } else
  6841. if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
  6842. return TRUE;
  6843. }
  6844. return FALSE;
  6845. }
  6846. static int32_t
  6847. e1000_polarity_reversal_workaround(struct e1000_hw *hw)
  6848. {
  6849. int32_t ret_val;
  6850. uint16_t mii_status_reg;
  6851. uint16_t i;
  6852. /* Polarity reversal workaround for forced 10F/10H links. */
  6853. /* Disable the transmitter on the PHY */
  6854. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
  6855. if (ret_val)
  6856. return ret_val;
  6857. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
  6858. if (ret_val)
  6859. return ret_val;
  6860. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
  6861. if (ret_val)
  6862. return ret_val;
  6863. /* This loop will early-out if the NO link condition has been met. */
  6864. for (i = PHY_FORCE_TIME; i > 0; i--) {
  6865. /* Read the MII Status Register and wait for Link Status bit
  6866. * to be clear.
  6867. */
  6868. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
  6869. if (ret_val)
  6870. return ret_val;
  6871. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
  6872. if (ret_val)
  6873. return ret_val;
  6874. if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
  6875. mdelay(100);
  6876. }
  6877. /* Recommended delay time after link has been lost */
  6878. mdelay(1000);
  6879. /* Now we will re-enable th transmitter on the PHY */
  6880. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
  6881. if (ret_val)
  6882. return ret_val;
  6883. mdelay(50);
  6884. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
  6885. if (ret_val)
  6886. return ret_val;
  6887. mdelay(50);
  6888. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
  6889. if (ret_val)
  6890. return ret_val;
  6891. mdelay(50);
  6892. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
  6893. if (ret_val)
  6894. return ret_val;
  6895. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
  6896. if (ret_val)
  6897. return ret_val;
  6898. /* This loop will early-out if the link condition has been met. */
  6899. for (i = PHY_FORCE_TIME; i > 0; i--) {
  6900. /* Read the MII Status Register and wait for Link Status bit
  6901. * to be set.
  6902. */
  6903. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
  6904. if (ret_val)
  6905. return ret_val;
  6906. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
  6907. if (ret_val)
  6908. return ret_val;
  6909. if (mii_status_reg & MII_SR_LINK_STATUS) break;
  6910. mdelay(100);
  6911. }
  6912. return E1000_SUCCESS;
  6913. }
  6914. /***************************************************************************
  6915. *
  6916. * Disables PCI-Express master access.
  6917. *
  6918. * hw: Struct containing variables accessed by shared code
  6919. *
  6920. * returns: - none.
  6921. *
  6922. ***************************************************************************/
  6923. static void
  6924. e1000_set_pci_express_master_disable(struct e1000_hw *hw)
  6925. {
  6926. uint32_t ctrl;
  6927. DEBUGFUNC("e1000_set_pci_express_master_disable");
  6928. if (hw->bus_type != e1000_bus_type_pci_express)
  6929. return;
  6930. ctrl = E1000_READ_REG(hw, CTRL);
  6931. ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
  6932. E1000_WRITE_REG(hw, CTRL, ctrl);
  6933. }
  6934. /*******************************************************************************
  6935. *
  6936. * Disables PCI-Express master access and verifies there are no pending requests
  6937. *
  6938. * hw: Struct containing variables accessed by shared code
  6939. *
  6940. * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
  6941. * caused the master requests to be disabled.
  6942. * E1000_SUCCESS master requests disabled.
  6943. *
  6944. ******************************************************************************/
  6945. int32_t
  6946. e1000_disable_pciex_master(struct e1000_hw *hw)
  6947. {
  6948. int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
  6949. DEBUGFUNC("e1000_disable_pciex_master");
  6950. if (hw->bus_type != e1000_bus_type_pci_express)
  6951. return E1000_SUCCESS;
  6952. e1000_set_pci_express_master_disable(hw);
  6953. while (timeout) {
  6954. if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
  6955. break;
  6956. else
  6957. udelay(100);
  6958. timeout--;
  6959. }
  6960. if (!timeout) {
  6961. DEBUGOUT("Master requests are pending.\n");
  6962. return -E1000_ERR_MASTER_REQUESTS_PENDING;
  6963. }
  6964. return E1000_SUCCESS;
  6965. }
  6966. /*******************************************************************************
  6967. *
  6968. * Check for EEPROM Auto Read bit done.
  6969. *
  6970. * hw: Struct containing variables accessed by shared code
  6971. *
  6972. * returns: - E1000_ERR_RESET if fail to reset MAC
  6973. * E1000_SUCCESS at any other case.
  6974. *
  6975. ******************************************************************************/
  6976. static int32_t
  6977. e1000_get_auto_rd_done(struct e1000_hw *hw)
  6978. {
  6979. int32_t timeout = AUTO_READ_DONE_TIMEOUT;
  6980. DEBUGFUNC("e1000_get_auto_rd_done");
  6981. switch (hw->mac_type) {
  6982. default:
  6983. msleep(5);
  6984. break;
  6985. case e1000_82571:
  6986. case e1000_82572:
  6987. case e1000_82573:
  6988. case e1000_80003es2lan:
  6989. case e1000_ich8lan:
  6990. while (timeout) {
  6991. if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
  6992. break;
  6993. else msleep(1);
  6994. timeout--;
  6995. }
  6996. if (!timeout) {
  6997. DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
  6998. return -E1000_ERR_RESET;
  6999. }
  7000. break;
  7001. }
  7002. /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
  7003. * Need to wait for PHY configuration completion before accessing NVM
  7004. * and PHY. */
  7005. if (hw->mac_type == e1000_82573)
  7006. msleep(25);
  7007. return E1000_SUCCESS;
  7008. }
  7009. /***************************************************************************
  7010. * Checks if the PHY configuration is done
  7011. *
  7012. * hw: Struct containing variables accessed by shared code
  7013. *
  7014. * returns: - E1000_ERR_RESET if fail to reset MAC
  7015. * E1000_SUCCESS at any other case.
  7016. *
  7017. ***************************************************************************/
  7018. static int32_t
  7019. e1000_get_phy_cfg_done(struct e1000_hw *hw)
  7020. {
  7021. int32_t timeout = PHY_CFG_TIMEOUT;
  7022. uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
  7023. DEBUGFUNC("e1000_get_phy_cfg_done");
  7024. switch (hw->mac_type) {
  7025. default:
  7026. mdelay(10);
  7027. break;
  7028. case e1000_80003es2lan:
  7029. /* Separate *_CFG_DONE_* bit for each port */
  7030. if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
  7031. cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
  7032. /* Fall Through */
  7033. case e1000_82571:
  7034. case e1000_82572:
  7035. while (timeout) {
  7036. if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
  7037. break;
  7038. else
  7039. msleep(1);
  7040. timeout--;
  7041. }
  7042. if (!timeout) {
  7043. DEBUGOUT("MNG configuration cycle has not completed.\n");
  7044. return -E1000_ERR_RESET;
  7045. }
  7046. break;
  7047. }
  7048. return E1000_SUCCESS;
  7049. }
  7050. /***************************************************************************
  7051. *
  7052. * Using the combination of SMBI and SWESMBI semaphore bits when resetting
  7053. * adapter or Eeprom access.
  7054. *
  7055. * hw: Struct containing variables accessed by shared code
  7056. *
  7057. * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
  7058. * E1000_SUCCESS at any other case.
  7059. *
  7060. ***************************************************************************/
  7061. static int32_t
  7062. e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
  7063. {
  7064. int32_t timeout;
  7065. uint32_t swsm;
  7066. DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
  7067. if (!hw->eeprom_semaphore_present)
  7068. return E1000_SUCCESS;
  7069. if (hw->mac_type == e1000_80003es2lan) {
  7070. /* Get the SW semaphore. */
  7071. if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
  7072. return -E1000_ERR_EEPROM;
  7073. }
  7074. /* Get the FW semaphore. */
  7075. timeout = hw->eeprom.word_size + 1;
  7076. while (timeout) {
  7077. swsm = E1000_READ_REG(hw, SWSM);
  7078. swsm |= E1000_SWSM_SWESMBI;
  7079. E1000_WRITE_REG(hw, SWSM, swsm);
  7080. /* if we managed to set the bit we got the semaphore. */
  7081. swsm = E1000_READ_REG(hw, SWSM);
  7082. if (swsm & E1000_SWSM_SWESMBI)
  7083. break;
  7084. udelay(50);
  7085. timeout--;
  7086. }
  7087. if (!timeout) {
  7088. /* Release semaphores */
  7089. e1000_put_hw_eeprom_semaphore(hw);
  7090. DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
  7091. return -E1000_ERR_EEPROM;
  7092. }
  7093. return E1000_SUCCESS;
  7094. }
  7095. /***************************************************************************
  7096. * This function clears HW semaphore bits.
  7097. *
  7098. * hw: Struct containing variables accessed by shared code
  7099. *
  7100. * returns: - None.
  7101. *
  7102. ***************************************************************************/
  7103. static void
  7104. e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
  7105. {
  7106. uint32_t swsm;
  7107. DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
  7108. if (!hw->eeprom_semaphore_present)
  7109. return;
  7110. swsm = E1000_READ_REG(hw, SWSM);
  7111. if (hw->mac_type == e1000_80003es2lan) {
  7112. /* Release both semaphores. */
  7113. swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
  7114. } else
  7115. swsm &= ~(E1000_SWSM_SWESMBI);
  7116. E1000_WRITE_REG(hw, SWSM, swsm);
  7117. }
  7118. /***************************************************************************
  7119. *
  7120. * Obtaining software semaphore bit (SMBI) before resetting PHY.
  7121. *
  7122. * hw: Struct containing variables accessed by shared code
  7123. *
  7124. * returns: - E1000_ERR_RESET if fail to obtain semaphore.
  7125. * E1000_SUCCESS at any other case.
  7126. *
  7127. ***************************************************************************/
  7128. static int32_t
  7129. e1000_get_software_semaphore(struct e1000_hw *hw)
  7130. {
  7131. int32_t timeout = hw->eeprom.word_size + 1;
  7132. uint32_t swsm;
  7133. DEBUGFUNC("e1000_get_software_semaphore");
  7134. if (hw->mac_type != e1000_80003es2lan) {
  7135. return E1000_SUCCESS;
  7136. }
  7137. while (timeout) {
  7138. swsm = E1000_READ_REG(hw, SWSM);
  7139. /* If SMBI bit cleared, it is now set and we hold the semaphore */
  7140. if (!(swsm & E1000_SWSM_SMBI))
  7141. break;
  7142. mdelay(1);
  7143. timeout--;
  7144. }
  7145. if (!timeout) {
  7146. DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
  7147. return -E1000_ERR_RESET;
  7148. }
  7149. return E1000_SUCCESS;
  7150. }
  7151. /***************************************************************************
  7152. *
  7153. * Release semaphore bit (SMBI).
  7154. *
  7155. * hw: Struct containing variables accessed by shared code
  7156. *
  7157. ***************************************************************************/
  7158. static void
  7159. e1000_release_software_semaphore(struct e1000_hw *hw)
  7160. {
  7161. uint32_t swsm;
  7162. DEBUGFUNC("e1000_release_software_semaphore");
  7163. if (hw->mac_type != e1000_80003es2lan) {
  7164. return;
  7165. }
  7166. swsm = E1000_READ_REG(hw, SWSM);
  7167. /* Release the SW semaphores.*/
  7168. swsm &= ~E1000_SWSM_SMBI;
  7169. E1000_WRITE_REG(hw, SWSM, swsm);
  7170. }
  7171. /******************************************************************************
  7172. * Checks if PHY reset is blocked due to SOL/IDER session, for example.
  7173. * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
  7174. * the caller to figure out how to deal with it.
  7175. *
  7176. * hw - Struct containing variables accessed by shared code
  7177. *
  7178. * returns: - E1000_BLK_PHY_RESET
  7179. * E1000_SUCCESS
  7180. *
  7181. *****************************************************************************/
  7182. int32_t
  7183. e1000_check_phy_reset_block(struct e1000_hw *hw)
  7184. {
  7185. uint32_t manc = 0;
  7186. uint32_t fwsm = 0;
  7187. if (hw->mac_type == e1000_ich8lan) {
  7188. fwsm = E1000_READ_REG(hw, FWSM);
  7189. return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
  7190. : E1000_BLK_PHY_RESET;
  7191. }
  7192. if (hw->mac_type > e1000_82547_rev_2)
  7193. manc = E1000_READ_REG(hw, MANC);
  7194. return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
  7195. E1000_BLK_PHY_RESET : E1000_SUCCESS;
  7196. }
  7197. static uint8_t
  7198. e1000_arc_subsystem_valid(struct e1000_hw *hw)
  7199. {
  7200. uint32_t fwsm;
  7201. /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
  7202. * may not be provided a DMA clock when no manageability features are
  7203. * enabled. We do not want to perform any reads/writes to these registers
  7204. * if this is the case. We read FWSM to determine the manageability mode.
  7205. */
  7206. switch (hw->mac_type) {
  7207. case e1000_82571:
  7208. case e1000_82572:
  7209. case e1000_82573:
  7210. case e1000_80003es2lan:
  7211. fwsm = E1000_READ_REG(hw, FWSM);
  7212. if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
  7213. return TRUE;
  7214. break;
  7215. case e1000_ich8lan:
  7216. return TRUE;
  7217. default:
  7218. break;
  7219. }
  7220. return FALSE;
  7221. }
  7222. /******************************************************************************
  7223. * Configure PCI-Ex no-snoop
  7224. *
  7225. * hw - Struct containing variables accessed by shared code.
  7226. * no_snoop - Bitmap of no-snoop events.
  7227. *
  7228. * returns: E1000_SUCCESS
  7229. *
  7230. *****************************************************************************/
  7231. static int32_t
  7232. e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
  7233. {
  7234. uint32_t gcr_reg = 0;
  7235. DEBUGFUNC("e1000_set_pci_ex_no_snoop");
  7236. if (hw->bus_type == e1000_bus_type_unknown)
  7237. e1000_get_bus_info(hw);
  7238. if (hw->bus_type != e1000_bus_type_pci_express)
  7239. return E1000_SUCCESS;
  7240. if (no_snoop) {
  7241. gcr_reg = E1000_READ_REG(hw, GCR);
  7242. gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
  7243. gcr_reg |= no_snoop;
  7244. E1000_WRITE_REG(hw, GCR, gcr_reg);
  7245. }
  7246. if (hw->mac_type == e1000_ich8lan) {
  7247. uint32_t ctrl_ext;
  7248. E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
  7249. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  7250. ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
  7251. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  7252. }
  7253. return E1000_SUCCESS;
  7254. }
  7255. /***************************************************************************
  7256. *
  7257. * Get software semaphore FLAG bit (SWFLAG).
  7258. * SWFLAG is used to synchronize the access to all shared resource between
  7259. * SW, FW and HW.
  7260. *
  7261. * hw: Struct containing variables accessed by shared code
  7262. *
  7263. ***************************************************************************/
  7264. static int32_t
  7265. e1000_get_software_flag(struct e1000_hw *hw)
  7266. {
  7267. int32_t timeout = PHY_CFG_TIMEOUT;
  7268. uint32_t extcnf_ctrl;
  7269. DEBUGFUNC("e1000_get_software_flag");
  7270. if (hw->mac_type == e1000_ich8lan) {
  7271. while (timeout) {
  7272. extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
  7273. extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
  7274. E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
  7275. extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
  7276. if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
  7277. break;
  7278. mdelay(1);
  7279. timeout--;
  7280. }
  7281. if (!timeout) {
  7282. DEBUGOUT("FW or HW locks the resource too long.\n");
  7283. return -E1000_ERR_CONFIG;
  7284. }
  7285. }
  7286. return E1000_SUCCESS;
  7287. }
  7288. /***************************************************************************
  7289. *
  7290. * Release software semaphore FLAG bit (SWFLAG).
  7291. * SWFLAG is used to synchronize the access to all shared resource between
  7292. * SW, FW and HW.
  7293. *
  7294. * hw: Struct containing variables accessed by shared code
  7295. *
  7296. ***************************************************************************/
  7297. static void
  7298. e1000_release_software_flag(struct e1000_hw *hw)
  7299. {
  7300. uint32_t extcnf_ctrl;
  7301. DEBUGFUNC("e1000_release_software_flag");
  7302. if (hw->mac_type == e1000_ich8lan) {
  7303. extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
  7304. extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
  7305. E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
  7306. }
  7307. return;
  7308. }
  7309. /******************************************************************************
  7310. * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
  7311. * register.
  7312. *
  7313. * hw - Struct containing variables accessed by shared code
  7314. * offset - offset of word in the EEPROM to read
  7315. * data - word read from the EEPROM
  7316. * words - number of words to read
  7317. *****************************************************************************/
  7318. static int32_t
  7319. e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
  7320. uint16_t *data)
  7321. {
  7322. int32_t error = E1000_SUCCESS;
  7323. uint32_t flash_bank = 0;
  7324. uint32_t act_offset = 0;
  7325. uint32_t bank_offset = 0;
  7326. uint16_t word = 0;
  7327. uint16_t i = 0;
  7328. /* We need to know which is the valid flash bank. In the event
  7329. * that we didn't allocate eeprom_shadow_ram, we may not be
  7330. * managing flash_bank. So it cannot be trusted and needs
  7331. * to be updated with each read.
  7332. */
  7333. /* Value of bit 22 corresponds to the flash bank we're on. */
  7334. flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
  7335. /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
  7336. bank_offset = flash_bank * (hw->flash_bank_size * 2);
  7337. error = e1000_get_software_flag(hw);
  7338. if (error != E1000_SUCCESS)
  7339. return error;
  7340. for (i = 0; i < words; i++) {
  7341. if (hw->eeprom_shadow_ram != NULL &&
  7342. hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
  7343. data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
  7344. } else {
  7345. /* The NVM part needs a byte offset, hence * 2 */
  7346. act_offset = bank_offset + ((offset + i) * 2);
  7347. error = e1000_read_ich8_word(hw, act_offset, &word);
  7348. if (error != E1000_SUCCESS)
  7349. break;
  7350. data[i] = word;
  7351. }
  7352. }
  7353. e1000_release_software_flag(hw);
  7354. return error;
  7355. }
  7356. /******************************************************************************
  7357. * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
  7358. * register. Actually, writes are written to the shadow ram cache in the hw
  7359. * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
  7360. * the NVM, which occurs when the NVM checksum is updated.
  7361. *
  7362. * hw - Struct containing variables accessed by shared code
  7363. * offset - offset of word in the EEPROM to write
  7364. * words - number of words to write
  7365. * data - words to write to the EEPROM
  7366. *****************************************************************************/
  7367. static int32_t
  7368. e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
  7369. uint16_t *data)
  7370. {
  7371. uint32_t i = 0;
  7372. int32_t error = E1000_SUCCESS;
  7373. error = e1000_get_software_flag(hw);
  7374. if (error != E1000_SUCCESS)
  7375. return error;
  7376. /* A driver can write to the NVM only if it has eeprom_shadow_ram
  7377. * allocated. Subsequent reads to the modified words are read from
  7378. * this cached structure as well. Writes will only go into this
  7379. * cached structure unless it's followed by a call to
  7380. * e1000_update_eeprom_checksum() where it will commit the changes
  7381. * and clear the "modified" field.
  7382. */
  7383. if (hw->eeprom_shadow_ram != NULL) {
  7384. for (i = 0; i < words; i++) {
  7385. if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
  7386. hw->eeprom_shadow_ram[offset+i].modified = TRUE;
  7387. hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
  7388. } else {
  7389. error = -E1000_ERR_EEPROM;
  7390. break;
  7391. }
  7392. }
  7393. } else {
  7394. /* Drivers have the option to not allocate eeprom_shadow_ram as long
  7395. * as they don't perform any NVM writes. An attempt in doing so
  7396. * will result in this error.
  7397. */
  7398. error = -E1000_ERR_EEPROM;
  7399. }
  7400. e1000_release_software_flag(hw);
  7401. return error;
  7402. }
  7403. /******************************************************************************
  7404. * This function does initial flash setup so that a new read/write/erase cycle
  7405. * can be started.
  7406. *
  7407. * hw - The pointer to the hw structure
  7408. ****************************************************************************/
  7409. static int32_t
  7410. e1000_ich8_cycle_init(struct e1000_hw *hw)
  7411. {
  7412. union ich8_hws_flash_status hsfsts;
  7413. int32_t error = E1000_ERR_EEPROM;
  7414. int32_t i = 0;
  7415. DEBUGFUNC("e1000_ich8_cycle_init");
  7416. hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
  7417. /* May be check the Flash Des Valid bit in Hw status */
  7418. if (hsfsts.hsf_status.fldesvalid == 0) {
  7419. DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
  7420. return error;
  7421. }
  7422. /* Clear FCERR in Hw status by writing 1 */
  7423. /* Clear DAEL in Hw status by writing a 1 */
  7424. hsfsts.hsf_status.flcerr = 1;
  7425. hsfsts.hsf_status.dael = 1;
  7426. E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
  7427. /* Either we should have a hardware SPI cycle in progress bit to check
  7428. * against, in order to start a new cycle or FDONE bit should be changed
  7429. * in the hardware so that it is 1 after harware reset, which can then be
  7430. * used as an indication whether a cycle is in progress or has been
  7431. * completed .. we should also have some software semaphore mechanism to
  7432. * guard FDONE or the cycle in progress bit so that two threads access to
  7433. * those bits can be sequentiallized or a way so that 2 threads dont
  7434. * start the cycle at the same time */
  7435. if (hsfsts.hsf_status.flcinprog == 0) {
  7436. /* There is no cycle running at present, so we can start a cycle */
  7437. /* Begin by setting Flash Cycle Done. */
  7438. hsfsts.hsf_status.flcdone = 1;
  7439. E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
  7440. error = E1000_SUCCESS;
  7441. } else {
  7442. /* otherwise poll for sometime so the current cycle has a chance
  7443. * to end before giving up. */
  7444. for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
  7445. hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
  7446. if (hsfsts.hsf_status.flcinprog == 0) {
  7447. error = E1000_SUCCESS;
  7448. break;
  7449. }
  7450. udelay(1);
  7451. }
  7452. if (error == E1000_SUCCESS) {
  7453. /* Successful in waiting for previous cycle to timeout,
  7454. * now set the Flash Cycle Done. */
  7455. hsfsts.hsf_status.flcdone = 1;
  7456. E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
  7457. } else {
  7458. DEBUGOUT("Flash controller busy, cannot get access");
  7459. }
  7460. }
  7461. return error;
  7462. }
  7463. /******************************************************************************
  7464. * This function starts a flash cycle and waits for its completion
  7465. *
  7466. * hw - The pointer to the hw structure
  7467. ****************************************************************************/
  7468. static int32_t
  7469. e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
  7470. {
  7471. union ich8_hws_flash_ctrl hsflctl;
  7472. union ich8_hws_flash_status hsfsts;
  7473. int32_t error = E1000_ERR_EEPROM;
  7474. uint32_t i = 0;
  7475. /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
  7476. hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
  7477. hsflctl.hsf_ctrl.flcgo = 1;
  7478. E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
  7479. /* wait till FDONE bit is set to 1 */
  7480. do {
  7481. hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
  7482. if (hsfsts.hsf_status.flcdone == 1)
  7483. break;
  7484. udelay(1);
  7485. i++;
  7486. } while (i < timeout);
  7487. if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
  7488. error = E1000_SUCCESS;
  7489. }
  7490. return error;
  7491. }
  7492. /******************************************************************************
  7493. * Reads a byte or word from the NVM using the ICH8 flash access registers.
  7494. *
  7495. * hw - The pointer to the hw structure
  7496. * index - The index of the byte or word to read.
  7497. * size - Size of data to read, 1=byte 2=word
  7498. * data - Pointer to the word to store the value read.
  7499. *****************************************************************************/
  7500. static int32_t
  7501. e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
  7502. uint32_t size, uint16_t* data)
  7503. {
  7504. union ich8_hws_flash_status hsfsts;
  7505. union ich8_hws_flash_ctrl hsflctl;
  7506. uint32_t flash_linear_address;
  7507. uint32_t flash_data = 0;
  7508. int32_t error = -E1000_ERR_EEPROM;
  7509. int32_t count = 0;
  7510. DEBUGFUNC("e1000_read_ich8_data");
  7511. if (size < 1 || size > 2 || data == 0x0 ||
  7512. index > ICH_FLASH_LINEAR_ADDR_MASK)
  7513. return error;
  7514. flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
  7515. hw->flash_base_addr;
  7516. do {
  7517. udelay(1);
  7518. /* Steps */
  7519. error = e1000_ich8_cycle_init(hw);
  7520. if (error != E1000_SUCCESS)
  7521. break;
  7522. hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
  7523. /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
  7524. hsflctl.hsf_ctrl.fldbcount = size - 1;
  7525. hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
  7526. E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
  7527. /* Write the last 24 bits of index into Flash Linear address field in
  7528. * Flash Address */
  7529. /* TODO: TBD maybe check the index against the size of flash */
  7530. E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
  7531. error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
  7532. /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
  7533. * sequence a few more times, else read in (shift in) the Flash Data0,
  7534. * the order is least significant byte first msb to lsb */
  7535. if (error == E1000_SUCCESS) {
  7536. flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
  7537. if (size == 1) {
  7538. *data = (uint8_t)(flash_data & 0x000000FF);
  7539. } else if (size == 2) {
  7540. *data = (uint16_t)(flash_data & 0x0000FFFF);
  7541. }
  7542. break;
  7543. } else {
  7544. /* If we've gotten here, then things are probably completely hosed,
  7545. * but if the error condition is detected, it won't hurt to give
  7546. * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
  7547. */
  7548. hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
  7549. if (hsfsts.hsf_status.flcerr == 1) {
  7550. /* Repeat for some time before giving up. */
  7551. continue;
  7552. } else if (hsfsts.hsf_status.flcdone == 0) {
  7553. DEBUGOUT("Timeout error - flash cycle did not complete.");
  7554. break;
  7555. }
  7556. }
  7557. } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
  7558. return error;
  7559. }
  7560. /******************************************************************************
  7561. * Writes One /two bytes to the NVM using the ICH8 flash access registers.
  7562. *
  7563. * hw - The pointer to the hw structure
  7564. * index - The index of the byte/word to read.
  7565. * size - Size of data to read, 1=byte 2=word
  7566. * data - The byte(s) to write to the NVM.
  7567. *****************************************************************************/
  7568. static int32_t
  7569. e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
  7570. uint16_t data)
  7571. {
  7572. union ich8_hws_flash_status hsfsts;
  7573. union ich8_hws_flash_ctrl hsflctl;
  7574. uint32_t flash_linear_address;
  7575. uint32_t flash_data = 0;
  7576. int32_t error = -E1000_ERR_EEPROM;
  7577. int32_t count = 0;
  7578. DEBUGFUNC("e1000_write_ich8_data");
  7579. if (size < 1 || size > 2 || data > size * 0xff ||
  7580. index > ICH_FLASH_LINEAR_ADDR_MASK)
  7581. return error;
  7582. flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
  7583. hw->flash_base_addr;
  7584. do {
  7585. udelay(1);
  7586. /* Steps */
  7587. error = e1000_ich8_cycle_init(hw);
  7588. if (error != E1000_SUCCESS)
  7589. break;
  7590. hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
  7591. /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
  7592. hsflctl.hsf_ctrl.fldbcount = size -1;
  7593. hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
  7594. E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
  7595. /* Write the last 24 bits of index into Flash Linear address field in
  7596. * Flash Address */
  7597. E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
  7598. if (size == 1)
  7599. flash_data = (uint32_t)data & 0x00FF;
  7600. else
  7601. flash_data = (uint32_t)data;
  7602. E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
  7603. /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
  7604. * sequence a few more times else done */
  7605. error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
  7606. if (error == E1000_SUCCESS) {
  7607. break;
  7608. } else {
  7609. /* If we're here, then things are most likely completely hosed,
  7610. * but if the error condition is detected, it won't hurt to give
  7611. * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
  7612. */
  7613. hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
  7614. if (hsfsts.hsf_status.flcerr == 1) {
  7615. /* Repeat for some time before giving up. */
  7616. continue;
  7617. } else if (hsfsts.hsf_status.flcdone == 0) {
  7618. DEBUGOUT("Timeout error - flash cycle did not complete.");
  7619. break;
  7620. }
  7621. }
  7622. } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
  7623. return error;
  7624. }
  7625. /******************************************************************************
  7626. * Reads a single byte from the NVM using the ICH8 flash access registers.
  7627. *
  7628. * hw - pointer to e1000_hw structure
  7629. * index - The index of the byte to read.
  7630. * data - Pointer to a byte to store the value read.
  7631. *****************************************************************************/
  7632. static int32_t
  7633. e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
  7634. {
  7635. int32_t status = E1000_SUCCESS;
  7636. uint16_t word = 0;
  7637. status = e1000_read_ich8_data(hw, index, 1, &word);
  7638. if (status == E1000_SUCCESS) {
  7639. *data = (uint8_t)word;
  7640. }
  7641. return status;
  7642. }
  7643. /******************************************************************************
  7644. * Writes a single byte to the NVM using the ICH8 flash access registers.
  7645. * Performs verification by reading back the value and then going through
  7646. * a retry algorithm before giving up.
  7647. *
  7648. * hw - pointer to e1000_hw structure
  7649. * index - The index of the byte to write.
  7650. * byte - The byte to write to the NVM.
  7651. *****************************************************************************/
  7652. static int32_t
  7653. e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
  7654. {
  7655. int32_t error = E1000_SUCCESS;
  7656. int32_t program_retries = 0;
  7657. DEBUGOUT2("Byte := %2.2X Offset := %ld\n", byte, index);
  7658. error = e1000_write_ich8_byte(hw, index, byte);
  7659. if (error != E1000_SUCCESS) {
  7660. for (program_retries = 0; program_retries < 100; program_retries++) {
  7661. DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %ld\n", byte, index);
  7662. error = e1000_write_ich8_byte(hw, index, byte);
  7663. udelay(100);
  7664. if (error == E1000_SUCCESS)
  7665. break;
  7666. }
  7667. }
  7668. if (program_retries == 100)
  7669. error = E1000_ERR_EEPROM;
  7670. return error;
  7671. }
  7672. /******************************************************************************
  7673. * Writes a single byte to the NVM using the ICH8 flash access registers.
  7674. *
  7675. * hw - pointer to e1000_hw structure
  7676. * index - The index of the byte to read.
  7677. * data - The byte to write to the NVM.
  7678. *****************************************************************************/
  7679. static int32_t
  7680. e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
  7681. {
  7682. int32_t status = E1000_SUCCESS;
  7683. uint16_t word = (uint16_t)data;
  7684. status = e1000_write_ich8_data(hw, index, 1, word);
  7685. return status;
  7686. }
  7687. /******************************************************************************
  7688. * Reads a word from the NVM using the ICH8 flash access registers.
  7689. *
  7690. * hw - pointer to e1000_hw structure
  7691. * index - The starting byte index of the word to read.
  7692. * data - Pointer to a word to store the value read.
  7693. *****************************************************************************/
  7694. static int32_t
  7695. e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
  7696. {
  7697. int32_t status = E1000_SUCCESS;
  7698. status = e1000_read_ich8_data(hw, index, 2, data);
  7699. return status;
  7700. }
  7701. /******************************************************************************
  7702. * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
  7703. * based.
  7704. *
  7705. * hw - pointer to e1000_hw structure
  7706. * bank - 0 for first bank, 1 for second bank
  7707. *
  7708. * Note that this function may actually erase as much as 8 or 64 KBytes. The
  7709. * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
  7710. * bank size may be 4, 8 or 64 KBytes
  7711. *****************************************************************************/
  7712. int32_t
  7713. e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
  7714. {
  7715. union ich8_hws_flash_status hsfsts;
  7716. union ich8_hws_flash_ctrl hsflctl;
  7717. uint32_t flash_linear_address;
  7718. int32_t count = 0;
  7719. int32_t error = E1000_ERR_EEPROM;
  7720. int32_t iteration;
  7721. int32_t sub_sector_size = 0;
  7722. int32_t bank_size;
  7723. int32_t j = 0;
  7724. int32_t error_flag = 0;
  7725. hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
  7726. /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
  7727. /* 00: The Hw sector is 256 bytes, hence we need to erase 16
  7728. * consecutive sectors. The start index for the nth Hw sector can be
  7729. * calculated as bank * 4096 + n * 256
  7730. * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
  7731. * The start index for the nth Hw sector can be calculated
  7732. * as bank * 4096
  7733. * 10: The HW sector is 8K bytes
  7734. * 11: The Hw sector size is 64K bytes */
  7735. if (hsfsts.hsf_status.berasesz == 0x0) {
  7736. /* Hw sector size 256 */
  7737. sub_sector_size = ICH_FLASH_SEG_SIZE_256;
  7738. bank_size = ICH_FLASH_SECTOR_SIZE;
  7739. iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
  7740. } else if (hsfsts.hsf_status.berasesz == 0x1) {
  7741. bank_size = ICH_FLASH_SEG_SIZE_4K;
  7742. iteration = 1;
  7743. } else if (hsfsts.hsf_status.berasesz == 0x3) {
  7744. bank_size = ICH_FLASH_SEG_SIZE_64K;
  7745. iteration = 1;
  7746. } else {
  7747. return error;
  7748. }
  7749. for (j = 0; j < iteration ; j++) {
  7750. do {
  7751. count++;
  7752. /* Steps */
  7753. error = e1000_ich8_cycle_init(hw);
  7754. if (error != E1000_SUCCESS) {
  7755. error_flag = 1;
  7756. break;
  7757. }
  7758. /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
  7759. * Control */
  7760. hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
  7761. hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
  7762. E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
  7763. /* Write the last 24 bits of an index within the block into Flash
  7764. * Linear address field in Flash Address. This probably needs to
  7765. * be calculated here based off the on-chip erase sector size and
  7766. * the software bank size (4, 8 or 64 KBytes) */
  7767. flash_linear_address = bank * bank_size + j * sub_sector_size;
  7768. flash_linear_address += hw->flash_base_addr;
  7769. flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
  7770. E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
  7771. error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
  7772. /* Check if FCERR is set to 1. If 1, clear it and try the whole
  7773. * sequence a few more times else Done */
  7774. if (error == E1000_SUCCESS) {
  7775. break;
  7776. } else {
  7777. hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
  7778. if (hsfsts.hsf_status.flcerr == 1) {
  7779. /* repeat for some time before giving up */
  7780. continue;
  7781. } else if (hsfsts.hsf_status.flcdone == 0) {
  7782. error_flag = 1;
  7783. break;
  7784. }
  7785. }
  7786. } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
  7787. if (error_flag == 1)
  7788. break;
  7789. }
  7790. if (error_flag != 1)
  7791. error = E1000_SUCCESS;
  7792. return error;
  7793. }
  7794. static int32_t
  7795. e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
  7796. uint32_t cnf_base_addr, uint32_t cnf_size)
  7797. {
  7798. uint32_t ret_val = E1000_SUCCESS;
  7799. uint16_t word_addr, reg_data, reg_addr;
  7800. uint16_t i;
  7801. /* cnf_base_addr is in DWORD */
  7802. word_addr = (uint16_t)(cnf_base_addr << 1);
  7803. /* cnf_size is returned in size of dwords */
  7804. for (i = 0; i < cnf_size; i++) {
  7805. ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
  7806. if (ret_val)
  7807. return ret_val;
  7808. ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
  7809. if (ret_val)
  7810. return ret_val;
  7811. ret_val = e1000_get_software_flag(hw);
  7812. if (ret_val != E1000_SUCCESS)
  7813. return ret_val;
  7814. ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
  7815. e1000_release_software_flag(hw);
  7816. }
  7817. return ret_val;
  7818. }
  7819. /******************************************************************************
  7820. * This function initializes the PHY from the NVM on ICH8 platforms. This
  7821. * is needed due to an issue where the NVM configuration is not properly
  7822. * autoloaded after power transitions. Therefore, after each PHY reset, we
  7823. * will load the configuration data out of the NVM manually.
  7824. *
  7825. * hw: Struct containing variables accessed by shared code
  7826. *****************************************************************************/
  7827. static int32_t
  7828. e1000_init_lcd_from_nvm(struct e1000_hw *hw)
  7829. {
  7830. uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
  7831. if (hw->phy_type != e1000_phy_igp_3)
  7832. return E1000_SUCCESS;
  7833. /* Check if SW needs configure the PHY */
  7834. reg_data = E1000_READ_REG(hw, FEXTNVM);
  7835. if (!(reg_data & FEXTNVM_SW_CONFIG))
  7836. return E1000_SUCCESS;
  7837. /* Wait for basic configuration completes before proceeding*/
  7838. loop = 0;
  7839. do {
  7840. reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
  7841. udelay(100);
  7842. loop++;
  7843. } while ((!reg_data) && (loop < 50));
  7844. /* Clear the Init Done bit for the next init event */
  7845. reg_data = E1000_READ_REG(hw, STATUS);
  7846. reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
  7847. E1000_WRITE_REG(hw, STATUS, reg_data);
  7848. /* Make sure HW does not configure LCD from PHY extended configuration
  7849. before SW configuration */
  7850. reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
  7851. if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
  7852. reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
  7853. cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
  7854. cnf_size >>= 16;
  7855. if (cnf_size) {
  7856. reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
  7857. cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
  7858. /* cnf_base_addr is in DWORD */
  7859. cnf_base_addr >>= 16;
  7860. /* Configure LCD from extended configuration region. */
  7861. ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
  7862. cnf_size);
  7863. if (ret_val)
  7864. return ret_val;
  7865. }
  7866. }
  7867. return E1000_SUCCESS;
  7868. }
  7869. /*
  7870. * Local variables:
  7871. * c-basic-offset: 8
  7872. * c-indent-level: 8
  7873. * tab-width: 8
  7874. * End:
  7875. */