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realtek.c 33KB

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  1. /*
  2. * Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
  3. *
  4. * (EEPROM code originally implemented for rtl8139.c)
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of the
  9. * License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  19. * 02110-1301, USA.
  20. *
  21. * You can also choose to distribute this program under the terms of
  22. * the Unmodified Binary Distribution Licence (as given in the file
  23. * COPYING.UBDL), provided that you have satisfied its requirements.
  24. */
  25. FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
  26. #include <stdint.h>
  27. #include <string.h>
  28. #include <unistd.h>
  29. #include <errno.h>
  30. #include <byteswap.h>
  31. #include <ipxe/netdevice.h>
  32. #include <ipxe/ethernet.h>
  33. #include <ipxe/if_ether.h>
  34. #include <ipxe/iobuf.h>
  35. #include <ipxe/malloc.h>
  36. #include <ipxe/pci.h>
  37. #include <ipxe/nvs.h>
  38. #include <ipxe/threewire.h>
  39. #include <ipxe/bitbash.h>
  40. #include <ipxe/mii.h>
  41. #include "realtek.h"
  42. /** @file
  43. *
  44. * Realtek 10/100/1000 network card driver
  45. *
  46. * Based on the following datasheets:
  47. *
  48. * http://www.datasheetarchive.com/dl/Datasheets-8/DSA-153536.pdf
  49. * http://www.datasheetarchive.com/indexdl/Datasheet-028/DSA00494723.pdf
  50. */
  51. /******************************************************************************
  52. *
  53. * Debugging
  54. *
  55. ******************************************************************************
  56. */
  57. /**
  58. * Dump all registers (for debugging)
  59. *
  60. * @v rtl Realtek device
  61. */
  62. static __attribute__ (( unused )) void realtek_dump ( struct realtek_nic *rtl ){
  63. uint8_t regs[256];
  64. unsigned int i;
  65. /* Do nothing unless debug output is enabled */
  66. if ( ! DBG_LOG )
  67. return;
  68. /* Dump registers (via byte accesses; may not work for all registers) */
  69. for ( i = 0 ; i < sizeof ( regs ) ; i++ )
  70. regs[i] = readb ( rtl->regs + i );
  71. DBGC ( rtl, "REALTEK %p register dump:\n", rtl );
  72. DBGC_HDA ( rtl, 0, regs, sizeof ( regs ) );
  73. }
  74. /******************************************************************************
  75. *
  76. * EEPROM interface
  77. *
  78. ******************************************************************************
  79. */
  80. /** Pin mapping for SPI bit-bashing interface */
  81. static const uint8_t realtek_eeprom_bits[] = {
  82. [SPI_BIT_SCLK] = RTL_9346CR_EESK,
  83. [SPI_BIT_MOSI] = RTL_9346CR_EEDI,
  84. [SPI_BIT_MISO] = RTL_9346CR_EEDO,
  85. [SPI_BIT_SS(0)] = RTL_9346CR_EECS,
  86. };
  87. /**
  88. * Open bit-bashing interface
  89. *
  90. * @v basher Bit-bashing interface
  91. */
  92. static void realtek_spi_open_bit ( struct bit_basher *basher ) {
  93. struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
  94. spibit.basher );
  95. /* Enable EEPROM access */
  96. writeb ( RTL_9346CR_EEM_EEPROM, rtl->regs + RTL_9346CR );
  97. readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */
  98. }
  99. /**
  100. * Close bit-bashing interface
  101. *
  102. * @v basher Bit-bashing interface
  103. */
  104. static void realtek_spi_close_bit ( struct bit_basher *basher ) {
  105. struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
  106. spibit.basher );
  107. /* Disable EEPROM access */
  108. writeb ( RTL_9346CR_EEM_NORMAL, rtl->regs + RTL_9346CR );
  109. readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */
  110. }
  111. /**
  112. * Read input bit
  113. *
  114. * @v basher Bit-bashing interface
  115. * @v bit_id Bit number
  116. * @ret zero Input is a logic 0
  117. * @ret non-zero Input is a logic 1
  118. */
  119. static int realtek_spi_read_bit ( struct bit_basher *basher,
  120. unsigned int bit_id ) {
  121. struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
  122. spibit.basher );
  123. uint8_t mask = realtek_eeprom_bits[bit_id];
  124. uint8_t reg;
  125. DBG_DISABLE ( DBGLVL_IO );
  126. reg = readb ( rtl->regs + RTL_9346CR );
  127. DBG_ENABLE ( DBGLVL_IO );
  128. return ( reg & mask );
  129. }
  130. /**
  131. * Set/clear output bit
  132. *
  133. * @v basher Bit-bashing interface
  134. * @v bit_id Bit number
  135. * @v data Value to write
  136. */
  137. static void realtek_spi_write_bit ( struct bit_basher *basher,
  138. unsigned int bit_id, unsigned long data ) {
  139. struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
  140. spibit.basher );
  141. uint8_t mask = realtek_eeprom_bits[bit_id];
  142. uint8_t reg;
  143. DBG_DISABLE ( DBGLVL_IO );
  144. reg = readb ( rtl->regs + RTL_9346CR );
  145. reg &= ~mask;
  146. reg |= ( data & mask );
  147. writeb ( reg, rtl->regs + RTL_9346CR );
  148. readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */
  149. DBG_ENABLE ( DBGLVL_IO );
  150. }
  151. /** SPI bit-bashing interface */
  152. static struct bit_basher_operations realtek_basher_ops = {
  153. .open = realtek_spi_open_bit,
  154. .close = realtek_spi_close_bit,
  155. .read = realtek_spi_read_bit,
  156. .write = realtek_spi_write_bit,
  157. };
  158. /**
  159. * Initialise EEPROM
  160. *
  161. * @v netdev Network device
  162. * @ret rc Return status code
  163. */
  164. static int realtek_init_eeprom ( struct net_device *netdev ) {
  165. struct realtek_nic *rtl = netdev->priv;
  166. uint16_t id;
  167. int rc;
  168. /* Initialise SPI bit-bashing interface */
  169. rtl->spibit.basher.op = &realtek_basher_ops;
  170. rtl->spibit.bus.mode = SPI_MODE_THREEWIRE;
  171. init_spi_bit_basher ( &rtl->spibit );
  172. /* Detect EEPROM type and initialise three-wire device */
  173. if ( readl ( rtl->regs + RTL_RCR ) & RTL_RCR_9356SEL ) {
  174. DBGC ( rtl, "REALTEK %p EEPROM is a 93C56\n", rtl );
  175. init_at93c56 ( &rtl->eeprom, 16 );
  176. } else {
  177. DBGC ( rtl, "REALTEK %p EEPROM is a 93C46\n", rtl );
  178. init_at93c46 ( &rtl->eeprom, 16 );
  179. }
  180. rtl->eeprom.bus = &rtl->spibit.bus;
  181. /* Check for EEPROM presence. Some onboard NICs will have no
  182. * EEPROM connected, with the BIOS being responsible for
  183. * programming the initial register values.
  184. */
  185. if ( ( rc = nvs_read ( &rtl->eeprom.nvs, RTL_EEPROM_ID,
  186. &id, sizeof ( id ) ) ) != 0 ) {
  187. DBGC ( rtl, "REALTEK %p could not read EEPROM ID: %s\n",
  188. rtl, strerror ( rc ) );
  189. return rc;
  190. }
  191. if ( id != cpu_to_le16 ( RTL_EEPROM_ID_MAGIC ) ) {
  192. DBGC ( rtl, "REALTEK %p EEPROM ID incorrect (%#04x); assuming "
  193. "no EEPROM\n", rtl, le16_to_cpu ( id ) );
  194. return -ENODEV;
  195. }
  196. /* Initialise space for non-volatile options, if available
  197. *
  198. * We use offset 0x40 (i.e. address 0x20), length 0x40. This
  199. * block is marked as VPD in the Realtek datasheets, so we use
  200. * it only if we detect that the card is not supporting VPD.
  201. */
  202. if ( readb ( rtl->regs + RTL_CONFIG1 ) & RTL_CONFIG1_VPD ) {
  203. DBGC ( rtl, "REALTEK %p EEPROM in use for VPD; cannot use "
  204. "for options\n", rtl );
  205. } else {
  206. nvo_init ( &rtl->nvo, &rtl->eeprom.nvs, RTL_EEPROM_VPD,
  207. RTL_EEPROM_VPD_LEN, NULL, &netdev->refcnt );
  208. }
  209. return 0;
  210. }
  211. /******************************************************************************
  212. *
  213. * MII interface
  214. *
  215. ******************************************************************************
  216. */
  217. /**
  218. * Read from MII register
  219. *
  220. * @v mii MII interface
  221. * @v reg Register address
  222. * @ret value Data read, or negative error
  223. */
  224. static int realtek_mii_read ( struct mii_interface *mii, unsigned int reg ) {
  225. struct realtek_nic *rtl = container_of ( mii, struct realtek_nic, mii );
  226. unsigned int i;
  227. uint32_t value;
  228. /* Fail if PHYAR register is not present */
  229. if ( ! rtl->have_phy_regs )
  230. return -ENOTSUP;
  231. /* Initiate read */
  232. writel ( RTL_PHYAR_VALUE ( 0, reg, 0 ), rtl->regs + RTL_PHYAR );
  233. /* Wait for read to complete */
  234. for ( i = 0 ; i < RTL_MII_MAX_WAIT_US ; i++ ) {
  235. /* If read is not complete, delay 1us and retry */
  236. value = readl ( rtl->regs + RTL_PHYAR );
  237. if ( ! ( value & RTL_PHYAR_FLAG ) ) {
  238. udelay ( 1 );
  239. continue;
  240. }
  241. /* Return register value */
  242. return ( RTL_PHYAR_DATA ( value ) );
  243. }
  244. DBGC ( rtl, "REALTEK %p timed out waiting for MII read\n", rtl );
  245. return -ETIMEDOUT;
  246. }
  247. /**
  248. * Write to MII register
  249. *
  250. * @v mii MII interface
  251. * @v reg Register address
  252. * @v data Data to write
  253. * @ret rc Return status code
  254. */
  255. static int realtek_mii_write ( struct mii_interface *mii, unsigned int reg,
  256. unsigned int data) {
  257. struct realtek_nic *rtl = container_of ( mii, struct realtek_nic, mii );
  258. unsigned int i;
  259. /* Fail if PHYAR register is not present */
  260. if ( ! rtl->have_phy_regs )
  261. return -ENOTSUP;
  262. /* Initiate write */
  263. writel ( RTL_PHYAR_VALUE ( RTL_PHYAR_FLAG, reg, data ),
  264. rtl->regs + RTL_PHYAR );
  265. /* Wait for write to complete */
  266. for ( i = 0 ; i < RTL_MII_MAX_WAIT_US ; i++ ) {
  267. /* If write is not complete, delay 1us and retry */
  268. if ( readl ( rtl->regs + RTL_PHYAR ) & RTL_PHYAR_FLAG ) {
  269. udelay ( 1 );
  270. continue;
  271. }
  272. return 0;
  273. }
  274. DBGC ( rtl, "REALTEK %p timed out waiting for MII write\n", rtl );
  275. return -ETIMEDOUT;
  276. }
  277. /** Realtek MII operations */
  278. static struct mii_operations realtek_mii_operations = {
  279. .read = realtek_mii_read,
  280. .write = realtek_mii_write,
  281. };
  282. /******************************************************************************
  283. *
  284. * Device reset
  285. *
  286. ******************************************************************************
  287. */
  288. /**
  289. * Reset hardware
  290. *
  291. * @v rtl Realtek device
  292. * @ret rc Return status code
  293. */
  294. static int realtek_reset ( struct realtek_nic *rtl ) {
  295. unsigned int i;
  296. /* Issue reset */
  297. writeb ( RTL_CR_RST, rtl->regs + RTL_CR );
  298. /* Wait for reset to complete */
  299. for ( i = 0 ; i < RTL_RESET_MAX_WAIT_MS ; i++ ) {
  300. /* If reset is not complete, delay 1ms and retry */
  301. if ( readb ( rtl->regs + RTL_CR ) & RTL_CR_RST ) {
  302. mdelay ( 1 );
  303. continue;
  304. }
  305. return 0;
  306. }
  307. DBGC ( rtl, "REALTEK %p timed out waiting for reset\n", rtl );
  308. return -ETIMEDOUT;
  309. }
  310. /**
  311. * Configure PHY for Gigabit operation
  312. *
  313. * @v rtl Realtek device
  314. * @ret rc Return status code
  315. */
  316. static int realtek_phy_speed ( struct realtek_nic *rtl ) {
  317. int ctrl1000;
  318. int rc;
  319. /* Read CTRL1000 register */
  320. ctrl1000 = mii_read ( &rtl->mii, MII_CTRL1000 );
  321. if ( ctrl1000 < 0 ) {
  322. rc = ctrl1000;
  323. DBGC ( rtl, "REALTEK %p could not read CTRL1000: %s\n",
  324. rtl, strerror ( rc ) );
  325. return rc;
  326. }
  327. /* Advertise 1000Mbps speeds */
  328. ctrl1000 |= ( ADVERTISE_1000FULL | ADVERTISE_1000HALF );
  329. if ( ( rc = mii_write ( &rtl->mii, MII_CTRL1000, ctrl1000 ) ) != 0 ) {
  330. DBGC ( rtl, "REALTEK %p could not write CTRL1000: %s\n",
  331. rtl, strerror ( rc ) );
  332. return rc;
  333. }
  334. return 0;
  335. }
  336. /**
  337. * Reset PHY
  338. *
  339. * @v rtl Realtek device
  340. * @ret rc Return status code
  341. */
  342. static int realtek_phy_reset ( struct realtek_nic *rtl ) {
  343. int rc;
  344. /* Do nothing if we have no separate PHY register access */
  345. if ( ! rtl->have_phy_regs )
  346. return 0;
  347. /* Perform MII reset */
  348. if ( ( rc = mii_reset ( &rtl->mii ) ) != 0 ) {
  349. DBGC ( rtl, "REALTEK %p could not reset MII: %s\n",
  350. rtl, strerror ( rc ) );
  351. return rc;
  352. }
  353. /* Some cards (e.g. RTL8169SC) do not advertise Gigabit by
  354. * default. Try to enable advertisement of Gigabit speeds.
  355. */
  356. if ( ( rc = realtek_phy_speed ( rtl ) ) != 0 ) {
  357. /* Ignore failures, since the register may not be
  358. * present on non-Gigabit PHYs (e.g. RTL8101).
  359. */
  360. }
  361. /* Restart autonegotiation */
  362. if ( ( rc = mii_restart ( &rtl->mii ) ) != 0 ) {
  363. DBGC ( rtl, "REALTEK %p could not restart MII: %s\n",
  364. rtl, strerror ( rc ) );
  365. return rc;
  366. }
  367. return 0;
  368. }
  369. /******************************************************************************
  370. *
  371. * Link state
  372. *
  373. ******************************************************************************
  374. */
  375. /**
  376. * Check link state
  377. *
  378. * @v netdev Network device
  379. */
  380. static void realtek_check_link ( struct net_device *netdev ) {
  381. struct realtek_nic *rtl = netdev->priv;
  382. uint8_t phystatus;
  383. uint8_t msr;
  384. int link_up;
  385. /* Determine link state */
  386. if ( rtl->have_phy_regs ) {
  387. mii_dump ( &rtl->mii );
  388. phystatus = readb ( rtl->regs + RTL_PHYSTATUS );
  389. link_up = ( phystatus & RTL_PHYSTATUS_LINKSTS );
  390. DBGC ( rtl, "REALTEK %p PHY status is %02x (%s%s%s%s%s%s, "
  391. "Link%s, %sDuplex)\n", rtl, phystatus,
  392. ( ( phystatus & RTL_PHYSTATUS_ENTBI ) ? "TBI" : "GMII" ),
  393. ( ( phystatus & RTL_PHYSTATUS_TXFLOW ) ?
  394. ", TxFlow" : "" ),
  395. ( ( phystatus & RTL_PHYSTATUS_RXFLOW ) ?
  396. ", RxFlow" : "" ),
  397. ( ( phystatus & RTL_PHYSTATUS_1000MF ) ?
  398. ", 1000Mbps" : "" ),
  399. ( ( phystatus & RTL_PHYSTATUS_100M ) ?
  400. ", 100Mbps" : "" ),
  401. ( ( phystatus & RTL_PHYSTATUS_10M ) ?
  402. ", 10Mbps" : "" ),
  403. ( ( phystatus & RTL_PHYSTATUS_LINKSTS ) ?
  404. "Up" : "Down" ),
  405. ( ( phystatus & RTL_PHYSTATUS_FULLDUP ) ?
  406. "Full" : "Half" ) );
  407. } else {
  408. msr = readb ( rtl->regs + RTL_MSR );
  409. link_up = ( ! ( msr & RTL_MSR_LINKB ) );
  410. DBGC ( rtl, "REALTEK %p media status is %02x (Link%s, "
  411. "%dMbps%s%s%s%s%s)\n", rtl, msr,
  412. ( ( msr & RTL_MSR_LINKB ) ? "Down" : "Up" ),
  413. ( ( msr & RTL_MSR_SPEED_10 ) ? 10 : 100 ),
  414. ( ( msr & RTL_MSR_TXFCE ) ? ", TxFlow" : "" ),
  415. ( ( msr & RTL_MSR_RXFCE ) ? ", RxFlow" : "" ),
  416. ( ( msr & RTL_MSR_AUX_STATUS ) ? ", AuxPwr" : "" ),
  417. ( ( msr & RTL_MSR_TXPF ) ? ", TxPause" : "" ),
  418. ( ( msr & RTL_MSR_RXPF ) ? ", RxPause" : "" ) );
  419. }
  420. /* Report link state */
  421. if ( link_up ) {
  422. netdev_link_up ( netdev );
  423. } else {
  424. netdev_link_down ( netdev );
  425. }
  426. }
  427. /******************************************************************************
  428. *
  429. * Network device interface
  430. *
  431. ******************************************************************************
  432. */
  433. /**
  434. * Create receive buffer (legacy mode)
  435. *
  436. * @v rtl Realtek device
  437. * @ret rc Return status code
  438. */
  439. static int realtek_create_buffer ( struct realtek_nic *rtl ) {
  440. size_t len = ( RTL_RXBUF_LEN + RTL_RXBUF_PAD );
  441. physaddr_t address;
  442. int rc;
  443. /* Do nothing unless in legacy mode */
  444. if ( ! rtl->legacy )
  445. return 0;
  446. /* Allocate buffer */
  447. rtl->rx_buffer = malloc_dma ( len, RTL_RXBUF_ALIGN );
  448. if ( ! rtl->rx_buffer ) {
  449. rc = -ENOMEM;
  450. goto err_alloc;
  451. }
  452. address = virt_to_bus ( rtl->rx_buffer );
  453. /* Check that card can support address */
  454. if ( address & ~0xffffffffULL ) {
  455. DBGC ( rtl, "REALTEK %p cannot support 64-bit RX buffer "
  456. "address\n", rtl );
  457. rc = -ENOTSUP;
  458. goto err_64bit;
  459. }
  460. /* Program buffer address */
  461. writel ( address, rtl->regs + RTL_RBSTART );
  462. DBGC ( rtl, "REALTEK %p receive buffer is at [%08llx,%08llx,%08llx)\n",
  463. rtl, ( ( unsigned long long ) address ),
  464. ( ( unsigned long long ) address + RTL_RXBUF_LEN ),
  465. ( ( unsigned long long ) address + len ) );
  466. return 0;
  467. err_64bit:
  468. free_dma ( rtl->rx_buffer, len );
  469. rtl->rx_buffer = NULL;
  470. err_alloc:
  471. return rc;
  472. }
  473. /**
  474. * Destroy receive buffer (legacy mode)
  475. *
  476. * @v rtl Realtek device
  477. */
  478. static void realtek_destroy_buffer ( struct realtek_nic *rtl ) {
  479. size_t len = ( RTL_RXBUF_LEN + RTL_RXBUF_PAD );
  480. /* Do nothing unless in legacy mode */
  481. if ( ! rtl->legacy )
  482. return;
  483. /* Clear buffer address */
  484. writel ( 0, rtl->regs + RTL_RBSTART );
  485. /* Free buffer */
  486. free_dma ( rtl->rx_buffer, len );
  487. rtl->rx_buffer = NULL;
  488. rtl->rx_offset = 0;
  489. }
  490. /**
  491. * Create descriptor ring
  492. *
  493. * @v rtl Realtek device
  494. * @v ring Descriptor ring
  495. * @ret rc Return status code
  496. */
  497. static int realtek_create_ring ( struct realtek_nic *rtl,
  498. struct realtek_ring *ring ) {
  499. physaddr_t address;
  500. /* Do nothing in legacy mode */
  501. if ( rtl->legacy )
  502. return 0;
  503. /* Allocate descriptor ring */
  504. ring->desc = malloc_dma ( ring->len, RTL_RING_ALIGN );
  505. if ( ! ring->desc )
  506. return -ENOMEM;
  507. /* Initialise descriptor ring */
  508. memset ( ring->desc, 0, ring->len );
  509. /* Program ring address */
  510. address = virt_to_bus ( ring->desc );
  511. writel ( ( ( ( uint64_t ) address ) >> 32 ),
  512. rtl->regs + ring->reg + 4 );
  513. writel ( ( address & 0xffffffffUL ), rtl->regs + ring->reg );
  514. DBGC ( rtl, "REALTEK %p ring %02x is at [%08llx,%08llx)\n",
  515. rtl, ring->reg, ( ( unsigned long long ) address ),
  516. ( ( unsigned long long ) address + ring->len ) );
  517. return 0;
  518. }
  519. /**
  520. * Destroy descriptor ring
  521. *
  522. * @v rtl Realtek device
  523. * @v ring Descriptor ring
  524. */
  525. static void realtek_destroy_ring ( struct realtek_nic *rtl,
  526. struct realtek_ring *ring ) {
  527. /* Reset producer and consumer counters */
  528. ring->prod = 0;
  529. ring->cons = 0;
  530. /* Do nothing more if in legacy mode */
  531. if ( rtl->legacy )
  532. return;
  533. /* Clear ring address */
  534. writel ( 0, rtl->regs + ring->reg );
  535. writel ( 0, rtl->regs + ring->reg + 4 );
  536. /* Free descriptor ring */
  537. free_dma ( ring->desc, ring->len );
  538. ring->desc = NULL;
  539. }
  540. /**
  541. * Refill receive descriptor ring
  542. *
  543. * @v rtl Realtek device
  544. */
  545. static void realtek_refill_rx ( struct realtek_nic *rtl ) {
  546. struct realtek_descriptor *rx;
  547. struct io_buffer *iobuf;
  548. unsigned int rx_idx;
  549. physaddr_t address;
  550. int is_last;
  551. /* Do nothing in legacy mode */
  552. if ( rtl->legacy )
  553. return;
  554. while ( ( rtl->rx.prod - rtl->rx.cons ) < RTL_NUM_RX_DESC ) {
  555. /* Allocate I/O buffer */
  556. iobuf = alloc_iob ( RTL_RX_MAX_LEN );
  557. if ( ! iobuf ) {
  558. /* Wait for next refill */
  559. return;
  560. }
  561. /* Get next receive descriptor */
  562. rx_idx = ( rtl->rx.prod++ % RTL_NUM_RX_DESC );
  563. is_last = ( rx_idx == ( RTL_NUM_RX_DESC - 1 ) );
  564. rx = &rtl->rx.desc[rx_idx];
  565. /* Populate receive descriptor */
  566. address = virt_to_bus ( iobuf->data );
  567. rx->address = cpu_to_le64 ( address );
  568. rx->length = cpu_to_le16 ( RTL_RX_MAX_LEN );
  569. wmb();
  570. rx->flags = ( cpu_to_le16 ( RTL_DESC_OWN ) |
  571. ( is_last ? cpu_to_le16 ( RTL_DESC_EOR ) : 0 ) );
  572. wmb();
  573. /* Record I/O buffer */
  574. assert ( rtl->rx_iobuf[rx_idx] == NULL );
  575. rtl->rx_iobuf[rx_idx] = iobuf;
  576. DBGC2 ( rtl, "REALTEK %p RX %d is [%llx,%llx)\n", rtl, rx_idx,
  577. ( ( unsigned long long ) address ),
  578. ( ( unsigned long long ) address + RTL_RX_MAX_LEN ) );
  579. }
  580. }
  581. /**
  582. * Open network device
  583. *
  584. * @v netdev Network device
  585. * @ret rc Return status code
  586. */
  587. static int realtek_open ( struct net_device *netdev ) {
  588. struct realtek_nic *rtl = netdev->priv;
  589. uint32_t tcr;
  590. uint32_t rcr;
  591. int rc;
  592. /* Create transmit descriptor ring */
  593. if ( ( rc = realtek_create_ring ( rtl, &rtl->tx ) ) != 0 )
  594. goto err_create_tx;
  595. /* Create receive descriptor ring */
  596. if ( ( rc = realtek_create_ring ( rtl, &rtl->rx ) ) != 0 )
  597. goto err_create_rx;
  598. /* Create receive buffer */
  599. if ( ( rc = realtek_create_buffer ( rtl ) ) != 0 )
  600. goto err_create_buffer;
  601. /* Accept all packets */
  602. writel ( 0xffffffffUL, rtl->regs + RTL_MAR0 );
  603. writel ( 0xffffffffUL, rtl->regs + RTL_MAR4 );
  604. /* Enable transmitter and receiver. RTL8139 requires that
  605. * this happens before writing to RCR.
  606. */
  607. writeb ( ( RTL_CR_TE | RTL_CR_RE ), rtl->regs + RTL_CR );
  608. /* Configure transmitter */
  609. tcr = readl ( rtl->regs + RTL_TCR );
  610. tcr &= ~RTL_TCR_MXDMA_MASK;
  611. tcr |= RTL_TCR_MXDMA_DEFAULT;
  612. writel ( tcr, rtl->regs + RTL_TCR );
  613. /* Configure receiver */
  614. rcr = readl ( rtl->regs + RTL_RCR );
  615. rcr &= ~( RTL_RCR_STOP_WORKING | RTL_RCR_RXFTH_MASK |
  616. RTL_RCR_RBLEN_MASK | RTL_RCR_MXDMA_MASK );
  617. rcr |= ( RTL_RCR_RXFTH_DEFAULT | RTL_RCR_RBLEN_DEFAULT |
  618. RTL_RCR_MXDMA_DEFAULT | RTL_RCR_WRAP | RTL_RCR_AB |
  619. RTL_RCR_AM | RTL_RCR_APM | RTL_RCR_AAP );
  620. writel ( rcr, rtl->regs + RTL_RCR );
  621. /* Fill receive ring */
  622. realtek_refill_rx ( rtl );
  623. /* Update link state */
  624. realtek_check_link ( netdev );
  625. return 0;
  626. realtek_destroy_buffer ( rtl );
  627. err_create_buffer:
  628. realtek_destroy_ring ( rtl, &rtl->rx );
  629. err_create_rx:
  630. realtek_destroy_ring ( rtl, &rtl->tx );
  631. err_create_tx:
  632. return rc;
  633. }
  634. /**
  635. * Close network device
  636. *
  637. * @v netdev Network device
  638. */
  639. static void realtek_close ( struct net_device *netdev ) {
  640. struct realtek_nic *rtl = netdev->priv;
  641. unsigned int i;
  642. /* Disable receiver and transmitter */
  643. writeb ( 0, rtl->regs + RTL_CR );
  644. /* Destroy receive buffer */
  645. realtek_destroy_buffer ( rtl );
  646. /* Destroy receive descriptor ring */
  647. realtek_destroy_ring ( rtl, &rtl->rx );
  648. /* Discard any unused receive buffers */
  649. for ( i = 0 ; i < RTL_NUM_RX_DESC ; i++ ) {
  650. if ( rtl->rx_iobuf[i] )
  651. free_iob ( rtl->rx_iobuf[i] );
  652. rtl->rx_iobuf[i] = NULL;
  653. }
  654. /* Destroy transmit descriptor ring */
  655. realtek_destroy_ring ( rtl, &rtl->tx );
  656. }
  657. /**
  658. * Transmit packet
  659. *
  660. * @v netdev Network device
  661. * @v iobuf I/O buffer
  662. * @ret rc Return status code
  663. */
  664. static int realtek_transmit ( struct net_device *netdev,
  665. struct io_buffer *iobuf ) {
  666. struct realtek_nic *rtl = netdev->priv;
  667. struct realtek_descriptor *tx;
  668. unsigned int tx_idx;
  669. physaddr_t address;
  670. int is_last;
  671. /* Get next transmit descriptor */
  672. if ( ( rtl->tx.prod - rtl->tx.cons ) >= RTL_NUM_TX_DESC ) {
  673. netdev_tx_defer ( netdev, iobuf );
  674. return 0;
  675. }
  676. tx_idx = ( rtl->tx.prod++ % RTL_NUM_TX_DESC );
  677. /* Transmit packet */
  678. if ( rtl->legacy ) {
  679. /* Pad and align packet */
  680. iob_pad ( iobuf, ETH_ZLEN );
  681. address = virt_to_bus ( iobuf->data );
  682. /* Check that card can support address */
  683. if ( address & ~0xffffffffULL ) {
  684. DBGC ( rtl, "REALTEK %p cannot support 64-bit TX "
  685. "buffer address\n", rtl );
  686. return -ENOTSUP;
  687. }
  688. /* Add to transmit ring */
  689. writel ( address, rtl->regs + RTL_TSAD ( tx_idx ) );
  690. writel ( ( RTL_TSD_ERTXTH_DEFAULT | iob_len ( iobuf ) ),
  691. rtl->regs + RTL_TSD ( tx_idx ) );
  692. } else {
  693. /* Populate transmit descriptor */
  694. address = virt_to_bus ( iobuf->data );
  695. is_last = ( tx_idx == ( RTL_NUM_TX_DESC - 1 ) );
  696. tx = &rtl->tx.desc[tx_idx];
  697. tx->address = cpu_to_le64 ( address );
  698. tx->length = cpu_to_le16 ( iob_len ( iobuf ) );
  699. wmb();
  700. tx->flags = ( cpu_to_le16 ( RTL_DESC_OWN | RTL_DESC_FS |
  701. RTL_DESC_LS ) |
  702. ( is_last ? cpu_to_le16 ( RTL_DESC_EOR ) : 0 ) );
  703. wmb();
  704. /* Notify card that there are packets ready to transmit */
  705. writeb ( RTL_TPPOLL_NPQ, rtl->regs + rtl->tppoll );
  706. }
  707. DBGC2 ( rtl, "REALTEK %p TX %d is [%llx,%llx)\n", rtl, tx_idx,
  708. ( ( unsigned long long ) virt_to_bus ( iobuf->data ) ),
  709. ( ( ( unsigned long long ) virt_to_bus ( iobuf->data ) ) +
  710. iob_len ( iobuf ) ) );
  711. return 0;
  712. }
  713. /**
  714. * Poll for completed packets
  715. *
  716. * @v netdev Network device
  717. */
  718. static void realtek_poll_tx ( struct net_device *netdev ) {
  719. struct realtek_nic *rtl = netdev->priv;
  720. struct realtek_descriptor *tx;
  721. unsigned int tx_idx;
  722. /* Check for completed packets */
  723. while ( rtl->tx.cons != rtl->tx.prod ) {
  724. /* Get next transmit descriptor */
  725. tx_idx = ( rtl->tx.cons % RTL_NUM_TX_DESC );
  726. /* Stop if descriptor is still in use */
  727. if ( rtl->legacy ) {
  728. /* Check ownership bit in transmit status register */
  729. if ( ! ( readl ( rtl->regs + RTL_TSD ( tx_idx ) ) &
  730. RTL_TSD_OWN ) )
  731. return;
  732. } else {
  733. /* Check ownership bit in descriptor */
  734. tx = &rtl->tx.desc[tx_idx];
  735. if ( tx->flags & cpu_to_le16 ( RTL_DESC_OWN ) )
  736. return;
  737. }
  738. DBGC2 ( rtl, "REALTEK %p TX %d complete\n", rtl, tx_idx );
  739. /* Complete TX descriptor */
  740. rtl->tx.cons++;
  741. netdev_tx_complete_next ( netdev );
  742. }
  743. }
  744. /**
  745. * Poll for received packets (legacy mode)
  746. *
  747. * @v netdev Network device
  748. */
  749. static void realtek_legacy_poll_rx ( struct net_device *netdev ) {
  750. struct realtek_nic *rtl = netdev->priv;
  751. struct realtek_legacy_header *rx;
  752. struct io_buffer *iobuf;
  753. size_t len;
  754. /* Check for received packets */
  755. while ( ! ( readb ( rtl->regs + RTL_CR ) & RTL_CR_BUFE ) ) {
  756. /* Extract packet from receive buffer */
  757. rx = ( rtl->rx_buffer + rtl->rx_offset );
  758. len = le16_to_cpu ( rx->length );
  759. if ( rx->status & cpu_to_le16 ( RTL_STAT_ROK ) ) {
  760. DBGC2 ( rtl, "REALTEK %p RX offset %x+%zx\n",
  761. rtl, rtl->rx_offset, len );
  762. /* Allocate I/O buffer */
  763. iobuf = alloc_iob ( len );
  764. if ( ! iobuf ) {
  765. netdev_rx_err ( netdev, NULL, -ENOMEM );
  766. /* Leave packet for next poll */
  767. break;
  768. }
  769. /* Copy data to I/O buffer */
  770. memcpy ( iob_put ( iobuf, len ), rx->data, len );
  771. iob_unput ( iobuf, 4 /* strip CRC */ );
  772. /* Hand off to network stack */
  773. netdev_rx ( netdev, iobuf );
  774. } else {
  775. DBGC ( rtl, "REALTEK %p RX offset %x+%zx error %04x\n",
  776. rtl, rtl->rx_offset, len,
  777. le16_to_cpu ( rx->status ) );
  778. netdev_rx_err ( netdev, NULL, -EIO );
  779. }
  780. /* Update buffer offset */
  781. rtl->rx_offset = ( rtl->rx_offset + sizeof ( *rx ) + len );
  782. rtl->rx_offset = ( ( rtl->rx_offset + 3 ) & ~3 );
  783. rtl->rx_offset = ( rtl->rx_offset % RTL_RXBUF_LEN );
  784. writew ( ( rtl->rx_offset - 16 ), rtl->regs + RTL_CAPR );
  785. /* Give chip time to react before rechecking RTL_CR */
  786. readw ( rtl->regs + RTL_CAPR );
  787. }
  788. }
  789. /**
  790. * Poll for received packets
  791. *
  792. * @v netdev Network device
  793. */
  794. static void realtek_poll_rx ( struct net_device *netdev ) {
  795. struct realtek_nic *rtl = netdev->priv;
  796. struct realtek_descriptor *rx;
  797. struct io_buffer *iobuf;
  798. unsigned int rx_idx;
  799. size_t len;
  800. /* Poll receive buffer if in legacy mode */
  801. if ( rtl->legacy ) {
  802. realtek_legacy_poll_rx ( netdev );
  803. return;
  804. }
  805. /* Check for received packets */
  806. while ( rtl->rx.cons != rtl->rx.prod ) {
  807. /* Get next receive descriptor */
  808. rx_idx = ( rtl->rx.cons % RTL_NUM_RX_DESC );
  809. rx = &rtl->rx.desc[rx_idx];
  810. /* Stop if descriptor is still in use */
  811. if ( rx->flags & cpu_to_le16 ( RTL_DESC_OWN ) )
  812. return;
  813. /* Populate I/O buffer */
  814. iobuf = rtl->rx_iobuf[rx_idx];
  815. rtl->rx_iobuf[rx_idx] = NULL;
  816. len = ( le16_to_cpu ( rx->length ) & RTL_DESC_SIZE_MASK );
  817. iob_put ( iobuf, ( len - 4 /* strip CRC */ ) );
  818. /* Hand off to network stack */
  819. if ( rx->flags & cpu_to_le16 ( RTL_DESC_RES ) ) {
  820. DBGC ( rtl, "REALTEK %p RX %d error (length %zd, "
  821. "flags %04x)\n", rtl, rx_idx, len,
  822. le16_to_cpu ( rx->flags ) );
  823. netdev_rx_err ( netdev, iobuf, -EIO );
  824. } else {
  825. DBGC2 ( rtl, "REALTEK %p RX %d complete (length "
  826. "%zd)\n", rtl, rx_idx, len );
  827. netdev_rx ( netdev, iobuf );
  828. }
  829. rtl->rx.cons++;
  830. }
  831. }
  832. /**
  833. * Poll for completed and received packets
  834. *
  835. * @v netdev Network device
  836. */
  837. static void realtek_poll ( struct net_device *netdev ) {
  838. struct realtek_nic *rtl = netdev->priv;
  839. uint16_t isr;
  840. /* Check for and acknowledge interrupts */
  841. isr = readw ( rtl->regs + RTL_ISR );
  842. if ( ! isr )
  843. return;
  844. writew ( isr, rtl->regs + RTL_ISR );
  845. /* Poll for TX completions, if applicable */
  846. if ( isr & ( RTL_IRQ_TER | RTL_IRQ_TOK ) )
  847. realtek_poll_tx ( netdev );
  848. /* Poll for RX completionsm, if applicable */
  849. if ( isr & ( RTL_IRQ_RER | RTL_IRQ_ROK ) )
  850. realtek_poll_rx ( netdev );
  851. /* Check link state, if applicable */
  852. if ( isr & RTL_IRQ_PUN_LINKCHG )
  853. realtek_check_link ( netdev );
  854. /* Refill RX ring */
  855. realtek_refill_rx ( rtl );
  856. }
  857. /**
  858. * Enable or disable interrupts
  859. *
  860. * @v netdev Network device
  861. * @v enable Interrupts should be enabled
  862. */
  863. static void realtek_irq ( struct net_device *netdev, int enable ) {
  864. struct realtek_nic *rtl = netdev->priv;
  865. uint16_t imr;
  866. /* Set interrupt mask */
  867. imr = ( enable ? ( RTL_IRQ_PUN_LINKCHG | RTL_IRQ_TER | RTL_IRQ_TOK |
  868. RTL_IRQ_RER | RTL_IRQ_ROK ) : 0 );
  869. writew ( imr, rtl->regs + RTL_IMR );
  870. }
  871. /** Realtek network device operations */
  872. static struct net_device_operations realtek_operations = {
  873. .open = realtek_open,
  874. .close = realtek_close,
  875. .transmit = realtek_transmit,
  876. .poll = realtek_poll,
  877. .irq = realtek_irq,
  878. };
  879. /******************************************************************************
  880. *
  881. * PCI interface
  882. *
  883. ******************************************************************************
  884. */
  885. /**
  886. * Detect device type
  887. *
  888. * @v rtl Realtek device
  889. */
  890. static void realtek_detect ( struct realtek_nic *rtl ) {
  891. uint16_t rms;
  892. uint16_t check_rms;
  893. uint16_t cpcr;
  894. uint16_t check_cpcr;
  895. /* The RX Packet Maximum Size register is present only on
  896. * 8169. Try to set to our intended MTU.
  897. */
  898. rms = RTL_RX_MAX_LEN;
  899. writew ( rms, rtl->regs + RTL_RMS );
  900. check_rms = readw ( rtl->regs + RTL_RMS );
  901. /* The C+ Command register is present only on 8169 and 8139C+.
  902. * Try to enable C+ mode and PCI Dual Address Cycle (for
  903. * 64-bit systems), if supported.
  904. *
  905. * Note that enabling DAC seems to cause bizarre behaviour
  906. * (lockups, garbage data on the wire) on some systems, even
  907. * if only 32-bit addresses are used.
  908. */
  909. cpcr = readw ( rtl->regs + RTL_CPCR );
  910. cpcr |= ( RTL_CPCR_MULRW | RTL_CPCR_CPRX | RTL_CPCR_CPTX );
  911. if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) )
  912. cpcr |= RTL_CPCR_DAC;
  913. writew ( cpcr, rtl->regs + RTL_CPCR );
  914. check_cpcr = readw ( rtl->regs + RTL_CPCR );
  915. /* Detect device type */
  916. if ( check_rms == rms ) {
  917. DBGC ( rtl, "REALTEK %p appears to be an RTL8169\n", rtl );
  918. rtl->have_phy_regs = 1;
  919. rtl->tppoll = RTL_TPPOLL_8169;
  920. } else {
  921. if ( ( check_cpcr == cpcr ) && ( cpcr != 0xffff ) ) {
  922. DBGC ( rtl, "REALTEK %p appears to be an RTL8139C+\n",
  923. rtl );
  924. rtl->tppoll = RTL_TPPOLL_8139CP;
  925. } else {
  926. DBGC ( rtl, "REALTEK %p appears to be an RTL8139\n",
  927. rtl );
  928. rtl->legacy = 1;
  929. }
  930. }
  931. }
  932. /**
  933. * Probe PCI device
  934. *
  935. * @v pci PCI device
  936. * @ret rc Return status code
  937. */
  938. static int realtek_probe ( struct pci_device *pci ) {
  939. struct net_device *netdev;
  940. struct realtek_nic *rtl;
  941. unsigned int i;
  942. int rc;
  943. /* Allocate and initialise net device */
  944. netdev = alloc_etherdev ( sizeof ( *rtl ) );
  945. if ( ! netdev ) {
  946. rc = -ENOMEM;
  947. goto err_alloc;
  948. }
  949. netdev_init ( netdev, &realtek_operations );
  950. rtl = netdev->priv;
  951. pci_set_drvdata ( pci, netdev );
  952. netdev->dev = &pci->dev;
  953. memset ( rtl, 0, sizeof ( *rtl ) );
  954. realtek_init_ring ( &rtl->tx, RTL_NUM_TX_DESC, RTL_TNPDS );
  955. realtek_init_ring ( &rtl->rx, RTL_NUM_RX_DESC, RTL_RDSAR );
  956. /* Fix up PCI device */
  957. adjust_pci_device ( pci );
  958. /* Map registers */
  959. rtl->regs = ioremap ( pci->membase, RTL_BAR_SIZE );
  960. if ( ! rtl->regs ) {
  961. rc = -ENODEV;
  962. goto err_ioremap;
  963. }
  964. /* Reset the NIC */
  965. if ( ( rc = realtek_reset ( rtl ) ) != 0 )
  966. goto err_reset;
  967. /* Detect device type */
  968. realtek_detect ( rtl );
  969. /* Initialise EEPROM */
  970. if ( ( rc = realtek_init_eeprom ( netdev ) ) == 0 ) {
  971. /* Read MAC address from EEPROM */
  972. if ( ( rc = nvs_read ( &rtl->eeprom.nvs, RTL_EEPROM_MAC,
  973. netdev->hw_addr, ETH_ALEN ) ) != 0 ) {
  974. DBGC ( rtl, "REALTEK %p could not read MAC address: "
  975. "%s\n", rtl, strerror ( rc ) );
  976. goto err_nvs_read;
  977. }
  978. } else {
  979. /* EEPROM not present. Fall back to reading the
  980. * current ID register value, which will hopefully
  981. * have been programmed by the platform firmware.
  982. */
  983. for ( i = 0 ; i < ETH_ALEN ; i++ )
  984. netdev->hw_addr[i] = readb ( rtl->regs + RTL_IDR0 + i );
  985. }
  986. /* Initialise and reset MII interface */
  987. mii_init ( &rtl->mii, &realtek_mii_operations );
  988. if ( ( rc = realtek_phy_reset ( rtl ) ) != 0 )
  989. goto err_phy_reset;
  990. /* Register network device */
  991. if ( ( rc = register_netdev ( netdev ) ) != 0 )
  992. goto err_register_netdev;
  993. /* Set initial link state */
  994. realtek_check_link ( netdev );
  995. /* Register non-volatile options, if applicable */
  996. if ( rtl->nvo.nvs ) {
  997. if ( ( rc = register_nvo ( &rtl->nvo,
  998. netdev_settings ( netdev ) ) ) != 0)
  999. goto err_register_nvo;
  1000. }
  1001. return 0;
  1002. err_register_nvo:
  1003. unregister_netdev ( netdev );
  1004. err_register_netdev:
  1005. err_phy_reset:
  1006. err_nvs_read:
  1007. realtek_reset ( rtl );
  1008. err_reset:
  1009. iounmap ( rtl->regs );
  1010. err_ioremap:
  1011. netdev_nullify ( netdev );
  1012. netdev_put ( netdev );
  1013. err_alloc:
  1014. return rc;
  1015. }
  1016. /**
  1017. * Remove PCI device
  1018. *
  1019. * @v pci PCI device
  1020. */
  1021. static void realtek_remove ( struct pci_device *pci ) {
  1022. struct net_device *netdev = pci_get_drvdata ( pci );
  1023. struct realtek_nic *rtl = netdev->priv;
  1024. /* Unregister non-volatile options, if applicable */
  1025. if ( rtl->nvo.nvs )
  1026. unregister_nvo ( &rtl->nvo );
  1027. /* Unregister network device */
  1028. unregister_netdev ( netdev );
  1029. /* Reset card */
  1030. realtek_reset ( rtl );
  1031. /* Free network device */
  1032. iounmap ( rtl->regs );
  1033. netdev_nullify ( netdev );
  1034. netdev_put ( netdev );
  1035. }
  1036. /** Realtek PCI device IDs */
  1037. static struct pci_device_id realtek_nics[] = {
  1038. PCI_ROM ( 0x0001, 0x8168, "clone8169", "Cloned 8169", 0 ),
  1039. PCI_ROM ( 0x018a, 0x0106, "fpc0106tx", "LevelOne FPC-0106TX", 0 ),
  1040. PCI_ROM ( 0x021b, 0x8139, "hne300", "Compaq HNE-300", 0 ),
  1041. PCI_ROM ( 0x02ac, 0x1012, "s1012", "SpeedStream 1012", 0 ),
  1042. PCI_ROM ( 0x0357, 0x000a, "ttpmon", "TTTech TTP-Monitoring", 0 ),
  1043. PCI_ROM ( 0x10ec, 0x8129, "rtl8129", "RTL-8129", 0 ),
  1044. PCI_ROM ( 0x10ec, 0x8136, "rtl8136", "RTL8101E/RTL8102E", 0 ),
  1045. PCI_ROM ( 0x10ec, 0x8138, "rtl8138", "RT8139 (B/C)", 0 ),
  1046. PCI_ROM ( 0x10ec, 0x8139, "rtl8139", "RTL-8139/8139C/8139C+", 0 ),
  1047. PCI_ROM ( 0x10ec, 0x8167, "rtl8167", "RTL-8110SC/8169SC", 0 ),
  1048. PCI_ROM ( 0x10ec, 0x8168, "rtl8168", "RTL8111/8168B", 0 ),
  1049. PCI_ROM ( 0x10ec, 0x8169, "rtl8169", "RTL-8169", 0 ),
  1050. PCI_ROM ( 0x1113, 0x1211, "smc1211", "SMC2-1211TX", 0 ),
  1051. PCI_ROM ( 0x1186, 0x1300, "dfe538", "DFE530TX+/DFE538TX", 0 ),
  1052. PCI_ROM ( 0x1186, 0x1340, "dfe690", "DFE-690TXD", 0 ),
  1053. PCI_ROM ( 0x1186, 0x4300, "dge528t", "DGE-528T", 0 ),
  1054. PCI_ROM ( 0x11db, 0x1234, "sega8139", "Sega Enterprises 8139", 0 ),
  1055. PCI_ROM ( 0x1259, 0xa117, "allied8139", "Allied Telesyn 8139", 0 ),
  1056. PCI_ROM ( 0x1259, 0xa11e, "allied81xx", "Allied Telesyn 81xx", 0 ),
  1057. PCI_ROM ( 0x1259, 0xc107, "allied8169", "Allied Telesyn 8169", 0 ),
  1058. PCI_ROM ( 0x126c, 0x1211, "northen8139","Northern Telecom 8139", 0 ),
  1059. PCI_ROM ( 0x13d1, 0xab06, "fe2000vx", "Abocom FE2000VX", 0 ),
  1060. PCI_ROM ( 0x1432, 0x9130, "edi8139", "Edimax 8139", 0 ),
  1061. PCI_ROM ( 0x14ea, 0xab06, "fnw3603tx", "Planex FNW-3603-TX", 0 ),
  1062. PCI_ROM ( 0x14ea, 0xab07, "fnw3800tx", "Planex FNW-3800-TX", 0 ),
  1063. PCI_ROM ( 0x1500, 0x1360, "delta8139", "Delta Electronics 8139", 0 ),
  1064. PCI_ROM ( 0x16ec, 0x0116, "usr997902", "USR997902", 0 ),
  1065. PCI_ROM ( 0x1737, 0x1032, "linksys8169","Linksys 8169", 0 ),
  1066. PCI_ROM ( 0x1743, 0x8139, "rolf100", "Peppercorn ROL/F-100", 0 ),
  1067. PCI_ROM ( 0x4033, 0x1360, "addron8139", "Addtron 8139", 0 ),
  1068. PCI_ROM ( 0xffff, 0x8139, "clonse8139", "Cloned 8139", 0 ),
  1069. };
  1070. /** Realtek PCI driver */
  1071. struct pci_driver realtek_driver __pci_driver = {
  1072. .ids = realtek_nics,
  1073. .id_count = ( sizeof ( realtek_nics ) / sizeof ( realtek_nics[0] ) ),
  1074. .probe = realtek_probe,
  1075. .remove = realtek_remove,
  1076. };