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  1. /*
  2. * Copyright (c) 2010 Andrei Faur <da3drus@gmail.com>
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of the
  7. * License, or any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12. * General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  17. * 02110-1301, USA.
  18. *
  19. */
  20. FILE_LICENCE ( GPL2_OR_LATER );
  21. #ifndef _PCNET32_H_
  22. #define _PCNET32_H_
  23. #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  24. /*
  25. * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  26. * Set default values to 16 Tx buffers and 32 Rx buffers.
  27. */
  28. #define PCNET32_LOG_TX_BUFFERS 4
  29. #define PCNET32_LOG_RX_BUFFERS 5
  30. /* Maximum number of descriptor rings is 512 */
  31. #define PCNET32_LOG_MAX_TX_BUFFERS 9
  32. #define PCNET32_LOG_MAX_RX_BUFFERS 9
  33. #define TX_RING_SIZE ( 1 << ( PCNET32_LOG_TX_BUFFERS ) )
  34. #define TX_MAX_RING_SIZE ( 1 << ( PCNET32_LOG_MAX_TX_BUFFERS ) )
  35. #define RX_RING_SIZE ( 1 << ( PCNET32_LOG_RX_BUFFERS ) )
  36. #define RX_MAX_RING_SIZE ( 1 << ( PCNET32_LOG_MAX_RX_BUFFERS ) )
  37. #define RX_RING_BYTES ( RX_RING_SIZE * sizeof(struct pcnet32_rx_desc ) )
  38. #define TX_RING_BYTES ( TX_RING_SIZE * sizeof(struct pcnet32_tx_desc ) )
  39. #define PKT_BUF_SIZE 1536
  40. #define RX_RING_ALIGN 16
  41. #define TX_RING_ALIGN 16
  42. #define INIT_BLOCK_ALIGN 32
  43. #define PCNET32_WIO_RDP 0x10
  44. #define PCNET32_WIO_RAP 0x12
  45. #define PCNET32_WIO_RESET 0x14
  46. #define PCNET32_WIO_BDP 0x16
  47. #define PCNET32_DWIO_RDP 0x10
  48. #define PCNET32_DWIO_RAP 0x14
  49. #define PCNET32_DWIO_RESET 0x18
  50. #define PCNET32_DWIO_BDP 0x1C
  51. #define PCNET32_PORT_AUI 0x00
  52. #define PCNET32_PORT_10BT 0x01
  53. #define PCNET32_PORT_GPSI 0x02
  54. #define PCNET32_PORT_MII 0x03
  55. #define PCNET32_PORT_PORTSEL 0x03
  56. #define PCNET32_PORT_ASEL 0x04
  57. #define PCNET32_PORT_100 0x40
  58. #define PCNET32_PORT_FD 0x80
  59. #define PCNET32_SWSTYLE_LANCE 0x00
  60. #define PCNET32_SWSTYLE_ILACC 0x01
  61. #define PCNET32_SWSTYLE_PCNET32 0x02
  62. #define PCNET32_MAX_PHYS 32
  63. #ifndef PCI_VENDOR_ID_AT
  64. #define PCI_VENDOR_ID_AT 0x1259
  65. #endif
  66. #ifndef PCI_SUBDEVICE_ID_AT_2700FX
  67. #define PCI_SUBDEVICE_ID_AT_2700FX 0x2701
  68. #endif
  69. #ifndef PCI_SUBDEVICE_ID_AT_2701FX
  70. #define PCI_SUBDEVICE_ID_AT_2701FX 0x2703
  71. #endif
  72. struct pcnet32_rx_desc {
  73. u32 base;
  74. s16 buf_length;
  75. s16 status;
  76. u32 msg_length;
  77. u32 reserved;
  78. };
  79. struct pcnet32_tx_desc {
  80. u32 base;
  81. s16 length;
  82. s16 status;
  83. u32 misc;
  84. u32 reserved;
  85. };
  86. struct pcnet32_init_block {
  87. u16 mode;
  88. u16 tlen_rlen;
  89. u8 phys_addr[6];
  90. u16 reserved;
  91. u32 filter[2];
  92. u32 rx_ring;
  93. u32 tx_ring;
  94. };
  95. struct pcnet32_access {
  96. u16 ( *read_csr ) ( unsigned long, int );
  97. void ( *write_csr ) ( unsigned long, int, u16 );
  98. u16 ( *read_bcr ) ( unsigned long, int );
  99. void ( *write_bcr ) ( unsigned long, int, u16 );
  100. u16 ( *read_rap ) ( unsigned long );
  101. void ( *write_rap ) ( unsigned long, u16 );
  102. void ( *reset ) ( unsigned long );
  103. };
  104. struct pcnet32_private {
  105. struct pcnet32_init_block init_block __attribute__((aligned(32)));
  106. struct pci_device *pci_dev;
  107. struct net_device *netdev;
  108. struct io_buffer *rx_iobuf[RX_RING_SIZE];
  109. struct io_buffer *tx_iobuf[TX_RING_SIZE];
  110. struct pcnet32_rx_desc *rx_base;
  111. struct pcnet32_tx_desc *tx_base;
  112. uint32_t rx_curr;
  113. uint32_t tx_curr;
  114. uint32_t tx_tail;
  115. uint32_t tx_fill_ctr;
  116. struct pcnet32_access *a;
  117. int options;
  118. unsigned int mii:1,
  119. full_duplex:1;
  120. unsigned short chip_version;
  121. char irq_enabled;
  122. };
  123. enum pcnet32_desc_status_bit {
  124. DescOwn = (1 << 15),
  125. StartOfPacket = (1 << 9),
  126. EndOfPacket = (1 << 8)
  127. };
  128. enum pcnet32_register_content {
  129. /* CSR0 bits - Controller status register */
  130. RxInt = (1 << 10),
  131. TxInt = (1 << 9),
  132. InitDone = (1 << 8),
  133. IntFlag = (1 << 7),
  134. IntEnable = (1 << 6),
  135. TxDemand = (1 << 3),
  136. Stop = (1 << 2),
  137. Strt = (1 << 1),
  138. Init = (1 << 0),
  139. /* CSR3 bits - Controller status register */
  140. BablMask = (1 << 14),
  141. MissFrameMask = (1 << 12),
  142. MemErrMask = (1 << 11),
  143. RxIntMask = (1 << 10),
  144. TxIntMask = (1 << 9),
  145. InitDoneMask = (1 << 8)
  146. };
  147. #endif /* _PCNET32_H_ */