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ns8390.h 7.9KB

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  1. /**************************************************************************
  2. ETHERBOOT - BOOTP/TFTP Bootstrap Program
  3. Author: Martin Renters
  4. Date: Jun/94
  5. **************************************************************************/
  6. FILE_LICENCE ( BSD2 );
  7. #define VENDOR_NONE 0
  8. #define VENDOR_WD 1
  9. #define VENDOR_NOVELL 2
  10. #define VENDOR_3COM 3
  11. #define FLAG_PIO 0x01
  12. #define FLAG_16BIT 0x02
  13. #define FLAG_790 0x04
  14. #define MEM_8192 32
  15. #define MEM_16384 64
  16. #define MEM_32768 128
  17. #define ISA_MAX_ADDR 0x400
  18. /**************************************************************************
  19. Western Digital/SMC Board Definitions
  20. **************************************************************************/
  21. #define WD_LOW_BASE 0x200
  22. #define WD_HIGH_BASE 0x3e0
  23. #ifndef WD_DEFAULT_MEM
  24. #define WD_DEFAULT_MEM 0xD0000
  25. #endif
  26. #define WD_NIC_ADDR 0x10
  27. /**************************************************************************
  28. Western Digital/SMC ASIC Addresses
  29. **************************************************************************/
  30. #define WD_MSR 0x00
  31. #define WD_ICR 0x01
  32. #define WD_IAR 0x02
  33. #define WD_BIO 0x03
  34. #define WD_IRR 0x04
  35. #define WD_LAAR 0x05
  36. #define WD_IJR 0x06
  37. #define WD_GP2 0x07
  38. #define WD_LAR 0x08
  39. #define WD_BID 0x0E
  40. #define WD_ICR_16BIT 0x01
  41. #define WD_MSR_MENB 0x40
  42. #define WD_LAAR_L16EN 0x40
  43. #define WD_LAAR_M16EN 0x80
  44. #define WD_SOFTCONFIG 0x20
  45. /**************************************************************************
  46. Western Digital/SMC Board Types
  47. **************************************************************************/
  48. #define TYPE_WD8003S 0x02
  49. #define TYPE_WD8003E 0x03
  50. #define TYPE_WD8013EBT 0x05
  51. #define TYPE_WD8003W 0x24
  52. #define TYPE_WD8003EB 0x25
  53. #define TYPE_WD8013W 0x26
  54. #define TYPE_WD8013EP 0x27
  55. #define TYPE_WD8013WC 0x28
  56. #define TYPE_WD8013EPC 0x29
  57. #define TYPE_SMC8216T 0x2a
  58. #define TYPE_SMC8216C 0x2b
  59. #define TYPE_SMC8416T 0x00 /* Bogus entries: the 8416 generates the */
  60. #define TYPE_SMC8416C 0x00 /* the same codes as the 8216. */
  61. #define TYPE_SMC8013EBP 0x2c
  62. /**************************************************************************
  63. 3com 3c503 definitions
  64. **************************************************************************/
  65. #ifndef _3COM_BASE
  66. #define _3COM_BASE 0x300
  67. #endif
  68. #define _3COM_TX_PAGE_OFFSET_8BIT 0x20
  69. #define _3COM_TX_PAGE_OFFSET_16BIT 0x0
  70. #define _3COM_RX_PAGE_OFFSET_16BIT 0x20
  71. #define _3COM_ASIC_OFFSET 0x400
  72. #define _3COM_NIC_OFFSET 0x0
  73. #define _3COM_PSTR 0
  74. #define _3COM_PSPR 1
  75. #define _3COM_BCFR 3
  76. #define _3COM_BCFR_2E0 0x01
  77. #define _3COM_BCFR_2A0 0x02
  78. #define _3COM_BCFR_280 0x04
  79. #define _3COM_BCFR_250 0x08
  80. #define _3COM_BCFR_350 0x10
  81. #define _3COM_BCFR_330 0x20
  82. #define _3COM_BCFR_310 0x40
  83. #define _3COM_BCFR_300 0x80
  84. #define _3COM_PCFR 4
  85. #define _3COM_PCFR_PIO 0
  86. #define _3COM_PCFR_C8000 0x10
  87. #define _3COM_PCFR_CC000 0x20
  88. #define _3COM_PCFR_D8000 0x40
  89. #define _3COM_PCFR_DC000 0x80
  90. #define _3COM_CR 6
  91. #define _3COM_CR_RST 0x01 /* Reset GA and NIC */
  92. #define _3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
  93. #define _3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
  94. #define _3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
  95. #define _3COM_CR_SHARE 0x10 /* select interrupt sharing option */
  96. #define _3COM_CR_DBSEL 0x20 /* Double buffer select */
  97. #define _3COM_CR_DDIR 0x40 /* DMA direction select */
  98. #define _3COM_CR_START 0x80 /* Start DMA controller */
  99. #define _3COM_GACFR 5
  100. #define _3COM_GACFR_MBS0 0x01
  101. #define _3COM_GACFR_MBS1 0x02
  102. #define _3COM_GACFR_MBS2 0x04
  103. #define _3COM_GACFR_RSEL 0x08 /* enable shared memory */
  104. #define _3COM_GACFR_TEST 0x10 /* for GA testing */
  105. #define _3COM_GACFR_OWS 0x20 /* select 0WS access to GA */
  106. #define _3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */
  107. #define _3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */
  108. #define _3COM_STREG 7
  109. #define _3COM_STREG_REV 0x07 /* GA revision */
  110. #define _3COM_STREG_DIP 0x08 /* DMA in progress */
  111. #define _3COM_STREG_DTC 0x10 /* DMA terminal count */
  112. #define _3COM_STREG_OFLW 0x20 /* Overflow */
  113. #define _3COM_STREG_UFLW 0x40 /* Underflow */
  114. #define _3COM_STREG_DPRDY 0x80 /* Data port ready */
  115. #define _3COM_IDCFR 8
  116. #define _3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */
  117. #define _3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */
  118. #define _3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */
  119. #define _3COM_IDCFR_UNUSED 0x08 /* not used */
  120. #define _3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
  121. #define _3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
  122. #define _3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
  123. #define _3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
  124. #define _3COM_IRQ2 2
  125. #define _3COM_IRQ3 3
  126. #define _3COM_IRQ4 4
  127. #define _3COM_IRQ5 5
  128. #define _3COM_DAMSB 9
  129. #define _3COM_DALSB 0x0a
  130. #define _3COM_VPTR2 0x0b
  131. #define _3COM_VPTR1 0x0c
  132. #define _3COM_VPTR0 0x0d
  133. #define _3COM_RFMSB 0x0e
  134. #define _3COM_RFLSB 0x0f
  135. /**************************************************************************
  136. NE1000/2000 definitions
  137. **************************************************************************/
  138. #define NE_ASIC_OFFSET 0x10
  139. #define NE_RESET 0x0F /* Used to reset card */
  140. #define NE_DATA 0x00 /* Used to read/write NIC mem */
  141. #define COMPEX_RL2000_TRIES 200
  142. /**************************************************************************
  143. 8390 Register Definitions
  144. **************************************************************************/
  145. #define D8390_P0_COMMAND 0x00
  146. #define D8390_P0_PSTART 0x01
  147. #define D8390_P0_PSTOP 0x02
  148. #define D8390_P0_BOUND 0x03
  149. #define D8390_P0_TSR 0x04
  150. #define D8390_P0_TPSR 0x04
  151. #define D8390_P0_TBCR0 0x05
  152. #define D8390_P0_TBCR1 0x06
  153. #define D8390_P0_ISR 0x07
  154. #define D8390_P0_RSAR0 0x08
  155. #define D8390_P0_RSAR1 0x09
  156. #define D8390_P0_RBCR0 0x0A
  157. #define D8390_P0_RBCR1 0x0B
  158. #define D8390_P0_RSR 0x0C
  159. #define D8390_P0_RCR 0x0C
  160. #define D8390_P0_TCR 0x0D
  161. #define D8390_P0_DCR 0x0E
  162. #define D8390_P0_IMR 0x0F
  163. #define D8390_P1_COMMAND 0x00
  164. #define D8390_P1_PAR0 0x01
  165. #define D8390_P1_PAR1 0x02
  166. #define D8390_P1_PAR2 0x03
  167. #define D8390_P1_PAR3 0x04
  168. #define D8390_P1_PAR4 0x05
  169. #define D8390_P1_PAR5 0x06
  170. #define D8390_P1_CURR 0x07
  171. #define D8390_P1_MAR0 0x08
  172. #define D8390_COMMAND_PS0 0x0 /* Page 0 select */
  173. #define D8390_COMMAND_PS1 0x40 /* Page 1 select */
  174. #define D8390_COMMAND_PS2 0x80 /* Page 2 select */
  175. #define D8390_COMMAND_RD2 0x20 /* Remote DMA control */
  176. #define D8390_COMMAND_RD1 0x10
  177. #define D8390_COMMAND_RD0 0x08
  178. #define D8390_COMMAND_TXP 0x04 /* transmit packet */
  179. #define D8390_COMMAND_STA 0x02 /* start */
  180. #define D8390_COMMAND_STP 0x01 /* stop */
  181. #define D8390_RCR_MON 0x20 /* monitor mode */
  182. #define D8390_DCR_FT1 0x40
  183. #define D8390_DCR_LS 0x08 /* Loopback select */
  184. #define D8390_DCR_WTS 0x01 /* Word transfer select */
  185. #define D8390_ISR_PRX 0x01 /* successful recv */
  186. #define D8390_ISR_PTX 0x02 /* successful xmit */
  187. #define D8390_ISR_RXE 0x04 /* receive error */
  188. #define D8390_ISR_TXE 0x08 /* transmit error */
  189. #define D8390_ISR_OVW 0x10 /* Overflow */
  190. #define D8390_ISR_CNT 0x20 /* Counter overflow */
  191. #define D8390_ISR_RDC 0x40 /* Remote DMA complete */
  192. #define D8390_ISR_RST 0x80 /* reset */
  193. #define D8390_RSTAT_PRX 0x01 /* successful recv */
  194. #define D8390_RSTAT_CRC 0x02 /* CRC error */
  195. #define D8390_RSTAT_FAE 0x04 /* Frame alignment error */
  196. #define D8390_RSTAT_OVER 0x08 /* FIFO overrun */
  197. #define D8390_TXBUF_SIZE 6
  198. #define D8390_RXBUF_END 32
  199. #define D8390_PAGE_SIZE 256
  200. struct ringbuffer {
  201. unsigned char status;
  202. unsigned char next;
  203. unsigned short len;
  204. };
  205. /*
  206. * Local variables:
  207. * c-basic-offset: 8
  208. * End:
  209. */