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intel.h 7.3KB

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  1. #ifndef _INTEL_H
  2. #define _INTEL_H
  3. /** @file
  4. *
  5. * Intel 10/100/1000 network card driver
  6. *
  7. */
  8. FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
  9. #include <stdint.h>
  10. #include <ipxe/if_ether.h>
  11. #include <ipxe/nvs.h>
  12. /** Intel BAR size */
  13. #define INTEL_BAR_SIZE ( 128 * 1024 )
  14. /** A packet descriptor */
  15. struct intel_descriptor {
  16. /** Buffer address */
  17. uint64_t address;
  18. /** Length */
  19. uint16_t length;
  20. /** Reserved */
  21. uint8_t reserved_a;
  22. /** Command */
  23. uint8_t command;
  24. /** Status */
  25. uint8_t status;
  26. /** Errors */
  27. uint8_t errors;
  28. /** Reserved */
  29. uint16_t reserved_b;
  30. } __attribute__ (( packed ));
  31. /** Packet descriptor command bits */
  32. enum intel_descriptor_command {
  33. /** Report status */
  34. INTEL_DESC_CMD_RS = 0x08,
  35. /** Insert frame checksum (CRC) */
  36. INTEL_DESC_CMD_IFCS = 0x02,
  37. /** End of packet */
  38. INTEL_DESC_CMD_EOP = 0x01,
  39. };
  40. /** Packet descriptor status bits */
  41. enum intel_descriptor_status {
  42. /** Descriptor done */
  43. INTEL_DESC_STATUS_DD = 0x01,
  44. };
  45. /** Device Control Register */
  46. #define INTEL_CTRL 0x00000UL
  47. #define INTEL_CTRL_LRST 0x00000008UL /**< Link reset */
  48. #define INTEL_CTRL_ASDE 0x00000020UL /**< Auto-speed detection */
  49. #define INTEL_CTRL_SLU 0x00000040UL /**< Set link up */
  50. #define INTEL_CTRL_FRCSPD 0x00000800UL /**< Force speed */
  51. #define INTEL_CTRL_FRCDPLX 0x00001000UL /**< Force duplex */
  52. #define INTEL_CTRL_RST 0x04000000UL /**< Device reset */
  53. #define INTEL_CTRL_PHY_RST 0x80000000UL /**< PHY reset */
  54. /** Time to delay for device reset, in milliseconds */
  55. #define INTEL_RESET_DELAY_MS 20
  56. /** Device Status Register */
  57. #define INTEL_STATUS 0x00008UL
  58. #define INTEL_STATUS_LU 0x00000002UL /**< Link up */
  59. /** EEPROM Read Register */
  60. #define INTEL_EERD 0x00014UL
  61. #define INTEL_EERD_START 0x00000001UL /**< Start read */
  62. #define INTEL_EERD_DONE_SMALL 0x00000010UL /**< Read done (small EERD) */
  63. #define INTEL_EERD_DONE_LARGE 0x00000002UL /**< Read done (large EERD) */
  64. #define INTEL_EERD_ADDR_SHIFT_SMALL 8 /**< Address shift (small) */
  65. #define INTEL_EERD_ADDR_SHIFT_LARGE 2 /**< Address shift (large) */
  66. #define INTEL_EERD_DATA(value) ( (value) >> 16 ) /**< Read data */
  67. /** Maximum time to wait for EEPROM read, in milliseconds */
  68. #define INTEL_EEPROM_MAX_WAIT_MS 100
  69. /** EEPROM word length */
  70. #define INTEL_EEPROM_WORD_LEN_LOG2 1
  71. /** Minimum EEPROM size, in words */
  72. #define INTEL_EEPROM_MIN_SIZE_WORDS 64
  73. /** Offset of MAC address within EEPROM */
  74. #define INTEL_EEPROM_MAC 0x00
  75. /** Interrupt Cause Read Register */
  76. #define INTEL_ICR 0x000c0UL
  77. #define INTEL_IRQ_TXDW 0x00000001UL /**< Transmit descriptor done */
  78. #define INTEL_IRQ_LSC 0x00000004UL /**< Link status change */
  79. #define INTEL_IRQ_RXT0 0x00000080UL /**< Receive timer */
  80. #define INTEL_IRQ_RXO 0x00000400UL /**< Receive overrun */
  81. /** Interrupt Mask Set/Read Register */
  82. #define INTEL_IMS 0x000d0UL
  83. /** Interrupt Mask Clear Register */
  84. #define INTEL_IMC 0x000d8UL
  85. /** Receive Control Register */
  86. #define INTEL_RCTL 0x00100UL
  87. #define INTEL_RCTL_EN 0x00000002UL /**< Receive enable */
  88. #define INTEL_RCTL_UPE 0x00000008UL /**< Unicast promiscuous mode */
  89. #define INTEL_RCTL_MPE 0x00000010UL /**< Multicast promiscuous */
  90. #define INTEL_RCTL_BAM 0x00008000UL /**< Broadcast accept mode */
  91. #define INTEL_RCTL_BSIZE_BSEX(bsex,bsize) \
  92. ( ( (bsize) << 16 ) | ( (bsex) << 25 ) ) /**< Buffer size */
  93. #define INTEL_RCTL_BSIZE_2048 INTEL_RCTL_BSIZE_BSEX ( 0, 0 )
  94. #define INTEL_RCTL_BSIZE_BSEX_MASK INTEL_RCTL_BSIZE_BSEX ( 1, 3 )
  95. #define INTEL_RCTL_SECRC 0x04000000UL /**< Strip CRC */
  96. /** Transmit Control Register */
  97. #define INTEL_TCTL 0x00400UL
  98. #define INTEL_TCTL_EN 0x00000002UL /**< Transmit enable */
  99. #define INTEL_TCTL_PSP 0x00000008UL /**< Pad short packets */
  100. #define INTEL_TCTL_CT(x) ( (x) << 4 ) /**< Collision threshold */
  101. #define INTEL_TCTL_CT_DEFAULT INTEL_TCTL_CT ( 0x0f )
  102. #define INTEL_TCTL_CT_MASK INTEL_TCTL_CT ( 0xff )
  103. #define INTEL_TCTL_COLD(x) ( (x) << 12 ) /**< Collision distance */
  104. #define INTEL_TCTL_COLD_DEFAULT INTEL_TCTL_COLD ( 0x040 )
  105. #define INTEL_TCTL_COLD_MASK INTEL_TCTL_COLD ( 0x3ff )
  106. /** Packet Buffer Allocation */
  107. #define INTEL_PBA 0x01000UL
  108. /** Packet Buffer Size */
  109. #define INTEL_PBS 0x01008UL
  110. /** Receive Descriptor register block */
  111. #define INTEL_RD 0x02800UL
  112. /** Number of receive descriptors
  113. *
  114. * Minimum value is 8, since the descriptor ring length must be a
  115. * multiple of 128.
  116. */
  117. #define INTEL_NUM_RX_DESC 16
  118. /** Receive descriptor ring fill level */
  119. #define INTEL_RX_FILL 8
  120. /** Receive buffer length */
  121. #define INTEL_RX_MAX_LEN 2048
  122. /** Transmit Descriptor register block */
  123. #define INTEL_TD 0x03800UL
  124. /** Number of transmit descriptors
  125. *
  126. * Descriptor ring length must be a multiple of 16. ICH8/9/10
  127. * requires a minimum of 16 TX descriptors.
  128. */
  129. #define INTEL_NUM_TX_DESC 16
  130. /** Transmit descriptor ring maximum fill level */
  131. #define INTEL_TX_FILL ( INTEL_NUM_TX_DESC - 1 )
  132. /** Receive/Transmit Descriptor Base Address Low (offset) */
  133. #define INTEL_xDBAL 0x00
  134. /** Receive/Transmit Descriptor Base Address High (offset) */
  135. #define INTEL_xDBAH 0x04
  136. /** Receive/Transmit Descriptor Length (offset) */
  137. #define INTEL_xDLEN 0x08
  138. /** Receive/Transmit Descriptor Head (offset) */
  139. #define INTEL_xDH 0x10
  140. /** Receive/Transmit Descriptor Tail (offset) */
  141. #define INTEL_xDT 0x18
  142. /** Receive/Transmit Descriptor Control (offset) */
  143. #define INTEL_xDCTL 0x28
  144. #define INTEL_xDCTL_ENABLE 0x02000000UL /**< Queue enable */
  145. /** Receive Address Low */
  146. #define INTEL_RAL0 0x05400UL
  147. /** Receive Address High */
  148. #define INTEL_RAH0 0x05404UL
  149. #define INTEL_RAH0_AV 0x80000000UL /**< Address valid */
  150. /** Receive address */
  151. union intel_receive_address {
  152. struct {
  153. uint32_t low;
  154. uint32_t high;
  155. } __attribute__ (( packed )) reg;
  156. uint8_t raw[ETH_ALEN];
  157. };
  158. /** An Intel descriptor ring */
  159. struct intel_ring {
  160. /** Descriptors */
  161. struct intel_descriptor *desc;
  162. /** Producer index */
  163. unsigned int prod;
  164. /** Consumer index */
  165. unsigned int cons;
  166. /** Register block */
  167. unsigned int reg;
  168. /** Length (in bytes) */
  169. size_t len;
  170. };
  171. /**
  172. * Initialise descriptor ring
  173. *
  174. * @v ring Descriptor ring
  175. * @v count Number of descriptors
  176. * @v reg Descriptor register block
  177. */
  178. static inline __attribute__ (( always_inline)) void
  179. intel_init_ring ( struct intel_ring *ring, unsigned int count,
  180. unsigned int reg ) {
  181. ring->len = ( count * sizeof ( ring->desc[0] ) );
  182. ring->reg = reg;
  183. }
  184. /** An Intel network card */
  185. struct intel_nic {
  186. /** Registers */
  187. void *regs;
  188. /** Port number (for multi-port devices) */
  189. unsigned int port;
  190. /** Flags */
  191. unsigned int flags;
  192. /** EEPROM */
  193. struct nvs_device eeprom;
  194. /** EEPROM done flag */
  195. uint32_t eerd_done;
  196. /** EEPROM address shift */
  197. unsigned int eerd_addr_shift;
  198. /** Transmit descriptor ring */
  199. struct intel_ring tx;
  200. /** Receive descriptor ring */
  201. struct intel_ring rx;
  202. /** Receive I/O buffers */
  203. struct io_buffer *rx_iobuf[INTEL_NUM_RX_DESC];
  204. };
  205. /** Driver flags */
  206. enum intel_flags {
  207. /** PBS/PBA errata workaround required */
  208. INTEL_PBS_ERRATA = 0x0001,
  209. };
  210. extern int intel_create_ring ( struct intel_nic *intel,
  211. struct intel_ring *ring );
  212. extern void intel_destroy_ring ( struct intel_nic *intel,
  213. struct intel_ring *ring );
  214. extern void intel_refill_rx ( struct intel_nic *intel );
  215. extern void intel_empty_rx ( struct intel_nic *intel );
  216. extern int intel_transmit ( struct net_device *netdev,
  217. struct io_buffer *iobuf );
  218. extern void intel_poll_tx ( struct net_device *netdev );
  219. extern void intel_poll_rx ( struct net_device *netdev );
  220. #endif /* _INTEL_H */