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intel.c 30KB

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  1. /*
  2. * Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of the
  7. * License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12. * General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  17. * 02110-1301, USA.
  18. *
  19. * You can also choose to distribute this program under the terms of
  20. * the Unmodified Binary Distribution Licence (as given in the file
  21. * COPYING.UBDL), provided that you have satisfied its requirements.
  22. */
  23. FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
  24. #include <stdint.h>
  25. #include <string.h>
  26. #include <unistd.h>
  27. #include <errno.h>
  28. #include <byteswap.h>
  29. #include <ipxe/netdevice.h>
  30. #include <ipxe/ethernet.h>
  31. #include <ipxe/if_ether.h>
  32. #include <ipxe/iobuf.h>
  33. #include <ipxe/malloc.h>
  34. #include <ipxe/pci.h>
  35. #include <ipxe/profile.h>
  36. #include "intel.h"
  37. /** @file
  38. *
  39. * Intel 10/100/1000 network card driver
  40. *
  41. */
  42. /** VM transmit profiler */
  43. static struct profiler intel_vm_tx_profiler __profiler =
  44. { .name = "intel.vm_tx" };
  45. /** VM receive refill profiler */
  46. static struct profiler intel_vm_refill_profiler __profiler =
  47. { .name = "intel.vm_refill" };
  48. /** VM poll profiler */
  49. static struct profiler intel_vm_poll_profiler __profiler =
  50. { .name = "intel.vm_poll" };
  51. /******************************************************************************
  52. *
  53. * EEPROM interface
  54. *
  55. ******************************************************************************
  56. */
  57. /**
  58. * Read data from EEPROM
  59. *
  60. * @v nvs NVS device
  61. * @v address Address from which to read
  62. * @v data Data buffer
  63. * @v len Length of data buffer
  64. * @ret rc Return status code
  65. */
  66. static int intel_read_eeprom ( struct nvs_device *nvs, unsigned int address,
  67. void *data, size_t len ) {
  68. struct intel_nic *intel =
  69. container_of ( nvs, struct intel_nic, eeprom );
  70. unsigned int i;
  71. uint32_t value;
  72. uint16_t *data_word = data;
  73. /* Sanity check. We advertise a blocksize of one word, so
  74. * should only ever receive single-word requests.
  75. */
  76. assert ( len == sizeof ( *data_word ) );
  77. /* Initiate read */
  78. writel ( ( INTEL_EERD_START | ( address << intel->eerd_addr_shift ) ),
  79. intel->regs + INTEL_EERD );
  80. /* Wait for read to complete */
  81. for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
  82. /* If read is not complete, delay 1ms and retry */
  83. value = readl ( intel->regs + INTEL_EERD );
  84. if ( ! ( value & intel->eerd_done ) ) {
  85. mdelay ( 1 );
  86. continue;
  87. }
  88. /* Extract data */
  89. *data_word = cpu_to_le16 ( INTEL_EERD_DATA ( value ) );
  90. return 0;
  91. }
  92. DBGC ( intel, "INTEL %p timed out waiting for EEPROM read\n", intel );
  93. return -ETIMEDOUT;
  94. }
  95. /**
  96. * Write data to EEPROM
  97. *
  98. * @v nvs NVS device
  99. * @v address Address to which to write
  100. * @v data Data buffer
  101. * @v len Length of data buffer
  102. * @ret rc Return status code
  103. */
  104. static int intel_write_eeprom ( struct nvs_device *nvs,
  105. unsigned int address __unused,
  106. const void *data __unused,
  107. size_t len __unused ) {
  108. struct intel_nic *intel =
  109. container_of ( nvs, struct intel_nic, eeprom );
  110. DBGC ( intel, "INTEL %p EEPROM write not supported\n", intel );
  111. return -ENOTSUP;
  112. }
  113. /**
  114. * Initialise EEPROM
  115. *
  116. * @v intel Intel device
  117. * @ret rc Return status code
  118. */
  119. static int intel_init_eeprom ( struct intel_nic *intel ) {
  120. unsigned int i;
  121. uint32_t value;
  122. /* The NIC automatically detects the type of attached EEPROM.
  123. * The EERD register provides access to only a single word at
  124. * a time, so we pretend to have a single-word block size.
  125. *
  126. * The EEPROM size may be larger than the minimum size, but
  127. * this doesn't matter to us since we access only the first
  128. * few words.
  129. */
  130. intel->eeprom.word_len_log2 = INTEL_EEPROM_WORD_LEN_LOG2;
  131. intel->eeprom.size = INTEL_EEPROM_MIN_SIZE_WORDS;
  132. intel->eeprom.block_size = 1;
  133. intel->eeprom.read = intel_read_eeprom;
  134. intel->eeprom.write = intel_write_eeprom;
  135. /* The layout of the EERD register was changed at some point
  136. * to accommodate larger EEPROMs. Read from address zero (for
  137. * which the request layouts are compatible) to determine
  138. * which type of register we have.
  139. */
  140. writel ( INTEL_EERD_START, intel->regs + INTEL_EERD );
  141. for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
  142. value = readl ( intel->regs + INTEL_EERD );
  143. if ( value & INTEL_EERD_DONE_LARGE ) {
  144. DBGC ( intel, "INTEL %p has large-format EERD\n",
  145. intel );
  146. intel->eerd_done = INTEL_EERD_DONE_LARGE;
  147. intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_LARGE;
  148. return 0;
  149. }
  150. if ( value & INTEL_EERD_DONE_SMALL ) {
  151. DBGC ( intel, "INTEL %p has small-format EERD\n",
  152. intel );
  153. intel->eerd_done = INTEL_EERD_DONE_SMALL;
  154. intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_SMALL;
  155. return 0;
  156. }
  157. mdelay ( 1 );
  158. }
  159. DBGC ( intel, "INTEL %p timed out waiting for initial EEPROM read "
  160. "(value %08x)\n", intel, value );
  161. return -ETIMEDOUT;
  162. }
  163. /******************************************************************************
  164. *
  165. * MAC address
  166. *
  167. ******************************************************************************
  168. */
  169. /**
  170. * Fetch initial MAC address from EEPROM
  171. *
  172. * @v intel Intel device
  173. * @v hw_addr Hardware address to fill in
  174. * @ret rc Return status code
  175. */
  176. static int intel_fetch_mac_eeprom ( struct intel_nic *intel,
  177. uint8_t *hw_addr ) {
  178. int rc;
  179. /* Initialise EEPROM */
  180. if ( ( rc = intel_init_eeprom ( intel ) ) != 0 )
  181. return rc;
  182. /* Read base MAC address from EEPROM */
  183. if ( ( rc = nvs_read ( &intel->eeprom, INTEL_EEPROM_MAC,
  184. hw_addr, ETH_ALEN ) ) != 0 ) {
  185. DBGC ( intel, "INTEL %p could not read EEPROM base MAC "
  186. "address: %s\n", intel, strerror ( rc ) );
  187. return rc;
  188. }
  189. /* Adjust MAC address for multi-port devices */
  190. hw_addr[ETH_ALEN-1] ^= intel->port;
  191. DBGC ( intel, "INTEL %p has EEPROM MAC address %s (port %d)\n",
  192. intel, eth_ntoa ( hw_addr ), intel->port );
  193. return 0;
  194. }
  195. /**
  196. * Fetch initial MAC address
  197. *
  198. * @v intel Intel device
  199. * @v hw_addr Hardware address to fill in
  200. * @ret rc Return status code
  201. */
  202. static int intel_fetch_mac ( struct intel_nic *intel, uint8_t *hw_addr ) {
  203. union intel_receive_address mac;
  204. int rc;
  205. /* Read current address from RAL0/RAH0 */
  206. mac.reg.low = cpu_to_le32 ( readl ( intel->regs + INTEL_RAL0 ) );
  207. mac.reg.high = cpu_to_le32 ( readl ( intel->regs + INTEL_RAH0 ) );
  208. DBGC ( intel, "INTEL %p has autoloaded MAC address %s\n",
  209. intel, eth_ntoa ( mac.raw ) );
  210. /* Use current address if valid */
  211. if ( is_valid_ether_addr ( mac.raw ) ) {
  212. memcpy ( hw_addr, mac.raw, ETH_ALEN );
  213. return 0;
  214. }
  215. /* Otherwise, try to read address from EEPROM */
  216. if ( ( rc = intel_fetch_mac_eeprom ( intel, hw_addr ) ) == 0 )
  217. return 0;
  218. DBGC ( intel, "INTEL %p has no MAC address to use\n", intel );
  219. return -ENOENT;
  220. }
  221. /******************************************************************************
  222. *
  223. * Diagnostics
  224. *
  225. ******************************************************************************
  226. */
  227. /**
  228. * Dump diagnostic information
  229. *
  230. * @v intel Intel device
  231. */
  232. static void __attribute__ (( unused )) intel_diag ( struct intel_nic *intel ) {
  233. DBGC ( intel, "INTEL %p TX %04x(%02x)/%04x(%02x) "
  234. "RX %04x(%02x)/%04x(%02x)\n", intel,
  235. ( intel->tx.cons & 0xffff ),
  236. readl ( intel->regs + intel->tx.reg + INTEL_xDH ),
  237. ( intel->tx.prod & 0xffff ),
  238. readl ( intel->regs + intel->tx.reg + INTEL_xDT ),
  239. ( intel->rx.cons & 0xffff ),
  240. readl ( intel->regs + intel->rx.reg + INTEL_xDH ),
  241. ( intel->rx.prod & 0xffff ),
  242. readl ( intel->regs + intel->rx.reg + INTEL_xDT ) );
  243. }
  244. /******************************************************************************
  245. *
  246. * Device reset
  247. *
  248. ******************************************************************************
  249. */
  250. /**
  251. * Reset hardware
  252. *
  253. * @v intel Intel device
  254. * @ret rc Return status code
  255. */
  256. static int intel_reset ( struct intel_nic *intel ) {
  257. uint32_t pbs;
  258. uint32_t pba;
  259. uint32_t ctrl;
  260. uint32_t status;
  261. /* Force RX and TX packet buffer allocation, to work around an
  262. * errata in ICH devices.
  263. */
  264. if ( intel->flags & INTEL_PBS_ERRATA ) {
  265. DBGC ( intel, "INTEL %p WARNING: applying ICH PBS/PBA errata\n",
  266. intel );
  267. pbs = readl ( intel->regs + INTEL_PBS );
  268. pba = readl ( intel->regs + INTEL_PBA );
  269. writel ( 0x08, intel->regs + INTEL_PBA );
  270. writel ( 0x10, intel->regs + INTEL_PBS );
  271. DBGC ( intel, "INTEL %p PBS %#08x->%#08x PBA %#08x->%#08x\n",
  272. intel, pbs, readl ( intel->regs + INTEL_PBS ),
  273. pba, readl ( intel->regs + INTEL_PBA ) );
  274. }
  275. /* Always reset MAC. Required to reset the TX and RX rings. */
  276. ctrl = readl ( intel->regs + INTEL_CTRL );
  277. writel ( ( ctrl | INTEL_CTRL_RST ), intel->regs + INTEL_CTRL );
  278. mdelay ( INTEL_RESET_DELAY_MS );
  279. /* Set a sensible default configuration */
  280. ctrl |= ( INTEL_CTRL_SLU | INTEL_CTRL_ASDE );
  281. ctrl &= ~( INTEL_CTRL_LRST | INTEL_CTRL_FRCSPD | INTEL_CTRL_FRCDPLX );
  282. writel ( ctrl, intel->regs + INTEL_CTRL );
  283. mdelay ( INTEL_RESET_DELAY_MS );
  284. /* If link is already up, do not attempt to reset the PHY. On
  285. * some models (notably ICH), performing a PHY reset seems to
  286. * drop the link speed to 10Mbps.
  287. */
  288. status = readl ( intel->regs + INTEL_STATUS );
  289. if ( status & INTEL_STATUS_LU ) {
  290. DBGC ( intel, "INTEL %p MAC reset (ctrl %08x)\n",
  291. intel, ctrl );
  292. return 0;
  293. }
  294. /* Reset PHY and MAC simultaneously */
  295. writel ( ( ctrl | INTEL_CTRL_RST | INTEL_CTRL_PHY_RST ),
  296. intel->regs + INTEL_CTRL );
  297. mdelay ( INTEL_RESET_DELAY_MS );
  298. /* PHY reset is not self-clearing on all models */
  299. writel ( ctrl, intel->regs + INTEL_CTRL );
  300. mdelay ( INTEL_RESET_DELAY_MS );
  301. DBGC ( intel, "INTEL %p MAC+PHY reset (ctrl %08x)\n", intel, ctrl );
  302. return 0;
  303. }
  304. /******************************************************************************
  305. *
  306. * Link state
  307. *
  308. ******************************************************************************
  309. */
  310. /**
  311. * Check link state
  312. *
  313. * @v netdev Network device
  314. */
  315. static void intel_check_link ( struct net_device *netdev ) {
  316. struct intel_nic *intel = netdev->priv;
  317. uint32_t status;
  318. /* Read link status */
  319. status = readl ( intel->regs + INTEL_STATUS );
  320. DBGC ( intel, "INTEL %p link status is %08x\n", intel, status );
  321. /* Update network device */
  322. if ( status & INTEL_STATUS_LU ) {
  323. netdev_link_up ( netdev );
  324. } else {
  325. netdev_link_down ( netdev );
  326. }
  327. }
  328. /******************************************************************************
  329. *
  330. * Network device interface
  331. *
  332. ******************************************************************************
  333. */
  334. /**
  335. * Create descriptor ring
  336. *
  337. * @v intel Intel device
  338. * @v ring Descriptor ring
  339. * @ret rc Return status code
  340. */
  341. int intel_create_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
  342. physaddr_t address;
  343. uint32_t dctl;
  344. /* Allocate descriptor ring. Align ring on its own size to
  345. * prevent any possible page-crossing errors due to hardware
  346. * errata.
  347. */
  348. ring->desc = malloc_dma ( ring->len, ring->len );
  349. if ( ! ring->desc )
  350. return -ENOMEM;
  351. /* Initialise descriptor ring */
  352. memset ( ring->desc, 0, ring->len );
  353. /* Program ring address */
  354. address = virt_to_bus ( ring->desc );
  355. writel ( ( address & 0xffffffffUL ),
  356. ( intel->regs + ring->reg + INTEL_xDBAL ) );
  357. if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
  358. writel ( ( ( ( uint64_t ) address ) >> 32 ),
  359. ( intel->regs + ring->reg + INTEL_xDBAH ) );
  360. } else {
  361. writel ( 0, intel->regs + ring->reg + INTEL_xDBAH );
  362. }
  363. /* Program ring length */
  364. writel ( ring->len, ( intel->regs + ring->reg + INTEL_xDLEN ) );
  365. /* Reset head and tail pointers */
  366. writel ( 0, ( intel->regs + ring->reg + INTEL_xDH ) );
  367. writel ( 0, ( intel->regs + ring->reg + INTEL_xDT ) );
  368. /* Enable ring */
  369. dctl = readl ( intel->regs + ring->reg + INTEL_xDCTL );
  370. dctl |= INTEL_xDCTL_ENABLE;
  371. writel ( dctl, intel->regs + ring->reg + INTEL_xDCTL );
  372. DBGC ( intel, "INTEL %p ring %05x is at [%08llx,%08llx)\n",
  373. intel, ring->reg, ( ( unsigned long long ) address ),
  374. ( ( unsigned long long ) address + ring->len ) );
  375. return 0;
  376. }
  377. /**
  378. * Destroy descriptor ring
  379. *
  380. * @v intel Intel device
  381. * @v ring Descriptor ring
  382. */
  383. void intel_destroy_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
  384. /* Clear ring length */
  385. writel ( 0, ( intel->regs + ring->reg + INTEL_xDLEN ) );
  386. /* Clear ring address */
  387. writel ( 0, ( intel->regs + ring->reg + INTEL_xDBAL ) );
  388. writel ( 0, ( intel->regs + ring->reg + INTEL_xDBAH ) );
  389. /* Free descriptor ring */
  390. free_dma ( ring->desc, ring->len );
  391. ring->desc = NULL;
  392. ring->prod = 0;
  393. ring->cons = 0;
  394. }
  395. /**
  396. * Refill receive descriptor ring
  397. *
  398. * @v intel Intel device
  399. */
  400. void intel_refill_rx ( struct intel_nic *intel ) {
  401. struct intel_descriptor *rx;
  402. struct io_buffer *iobuf;
  403. unsigned int rx_idx;
  404. unsigned int rx_tail;
  405. physaddr_t address;
  406. unsigned int refilled = 0;
  407. /* Refill ring */
  408. while ( ( intel->rx.prod - intel->rx.cons ) < INTEL_RX_FILL ) {
  409. /* Allocate I/O buffer */
  410. iobuf = alloc_iob ( INTEL_RX_MAX_LEN );
  411. if ( ! iobuf ) {
  412. /* Wait for next refill */
  413. break;
  414. }
  415. /* Get next receive descriptor */
  416. rx_idx = ( intel->rx.prod++ % INTEL_NUM_RX_DESC );
  417. rx = &intel->rx.desc[rx_idx];
  418. /* Populate receive descriptor */
  419. address = virt_to_bus ( iobuf->data );
  420. rx->address = cpu_to_le64 ( address );
  421. rx->length = 0;
  422. rx->status = 0;
  423. rx->errors = 0;
  424. /* Record I/O buffer */
  425. assert ( intel->rx_iobuf[rx_idx] == NULL );
  426. intel->rx_iobuf[rx_idx] = iobuf;
  427. DBGC2 ( intel, "INTEL %p RX %d is [%llx,%llx)\n", intel, rx_idx,
  428. ( ( unsigned long long ) address ),
  429. ( ( unsigned long long ) address + INTEL_RX_MAX_LEN ) );
  430. refilled++;
  431. }
  432. /* Push descriptors to card, if applicable */
  433. if ( refilled ) {
  434. wmb();
  435. rx_tail = ( intel->rx.prod % INTEL_NUM_RX_DESC );
  436. profile_start ( &intel_vm_refill_profiler );
  437. writel ( rx_tail, intel->regs + intel->rx.reg + INTEL_xDT );
  438. profile_stop ( &intel_vm_refill_profiler );
  439. profile_exclude ( &intel_vm_refill_profiler );
  440. }
  441. }
  442. /**
  443. * Discard unused receive I/O buffers
  444. *
  445. * @v intel Intel device
  446. */
  447. void intel_empty_rx ( struct intel_nic *intel ) {
  448. unsigned int i;
  449. for ( i = 0 ; i < INTEL_NUM_RX_DESC ; i++ ) {
  450. if ( intel->rx_iobuf[i] )
  451. free_iob ( intel->rx_iobuf[i] );
  452. intel->rx_iobuf[i] = NULL;
  453. }
  454. }
  455. /**
  456. * Open network device
  457. *
  458. * @v netdev Network device
  459. * @ret rc Return status code
  460. */
  461. static int intel_open ( struct net_device *netdev ) {
  462. struct intel_nic *intel = netdev->priv;
  463. union intel_receive_address mac;
  464. uint32_t tctl;
  465. uint32_t rctl;
  466. int rc;
  467. /* Create transmit descriptor ring */
  468. if ( ( rc = intel_create_ring ( intel, &intel->tx ) ) != 0 )
  469. goto err_create_tx;
  470. /* Create receive descriptor ring */
  471. if ( ( rc = intel_create_ring ( intel, &intel->rx ) ) != 0 )
  472. goto err_create_rx;
  473. /* Program MAC address */
  474. memset ( &mac, 0, sizeof ( mac ) );
  475. memcpy ( mac.raw, netdev->ll_addr, sizeof ( mac.raw ) );
  476. writel ( le32_to_cpu ( mac.reg.low ), intel->regs + INTEL_RAL0 );
  477. writel ( ( le32_to_cpu ( mac.reg.high ) | INTEL_RAH0_AV ),
  478. intel->regs + INTEL_RAH0 );
  479. /* Enable transmitter */
  480. tctl = readl ( intel->regs + INTEL_TCTL );
  481. tctl &= ~( INTEL_TCTL_CT_MASK | INTEL_TCTL_COLD_MASK );
  482. tctl |= ( INTEL_TCTL_EN | INTEL_TCTL_PSP | INTEL_TCTL_CT_DEFAULT |
  483. INTEL_TCTL_COLD_DEFAULT );
  484. writel ( tctl, intel->regs + INTEL_TCTL );
  485. /* Enable receiver */
  486. rctl = readl ( intel->regs + INTEL_RCTL );
  487. rctl &= ~( INTEL_RCTL_BSIZE_BSEX_MASK );
  488. rctl |= ( INTEL_RCTL_EN | INTEL_RCTL_UPE | INTEL_RCTL_MPE |
  489. INTEL_RCTL_BAM | INTEL_RCTL_BSIZE_2048 | INTEL_RCTL_SECRC );
  490. writel ( rctl, intel->regs + INTEL_RCTL );
  491. /* Fill receive ring */
  492. intel_refill_rx ( intel );
  493. /* Update link state */
  494. intel_check_link ( netdev );
  495. return 0;
  496. intel_destroy_ring ( intel, &intel->rx );
  497. err_create_rx:
  498. intel_destroy_ring ( intel, &intel->tx );
  499. err_create_tx:
  500. return rc;
  501. }
  502. /**
  503. * Close network device
  504. *
  505. * @v netdev Network device
  506. */
  507. static void intel_close ( struct net_device *netdev ) {
  508. struct intel_nic *intel = netdev->priv;
  509. /* Disable receiver */
  510. writel ( 0, intel->regs + INTEL_RCTL );
  511. /* Disable transmitter */
  512. writel ( 0, intel->regs + INTEL_TCTL );
  513. /* Destroy receive descriptor ring */
  514. intel_destroy_ring ( intel, &intel->rx );
  515. /* Discard any unused receive buffers */
  516. intel_empty_rx ( intel );
  517. /* Destroy transmit descriptor ring */
  518. intel_destroy_ring ( intel, &intel->tx );
  519. /* Reset the NIC, to flush the transmit and receive FIFOs */
  520. intel_reset ( intel );
  521. }
  522. /**
  523. * Transmit packet
  524. *
  525. * @v netdev Network device
  526. * @v iobuf I/O buffer
  527. * @ret rc Return status code
  528. */
  529. int intel_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
  530. struct intel_nic *intel = netdev->priv;
  531. struct intel_descriptor *tx;
  532. unsigned int tx_idx;
  533. unsigned int tx_tail;
  534. physaddr_t address;
  535. /* Get next transmit descriptor */
  536. if ( ( intel->tx.prod - intel->tx.cons ) >= INTEL_TX_FILL ) {
  537. DBGC ( intel, "INTEL %p out of transmit descriptors\n", intel );
  538. return -ENOBUFS;
  539. }
  540. tx_idx = ( intel->tx.prod++ % INTEL_NUM_TX_DESC );
  541. tx_tail = ( intel->tx.prod % INTEL_NUM_TX_DESC );
  542. tx = &intel->tx.desc[tx_idx];
  543. /* Populate transmit descriptor */
  544. address = virt_to_bus ( iobuf->data );
  545. tx->address = cpu_to_le64 ( address );
  546. tx->length = cpu_to_le16 ( iob_len ( iobuf ) );
  547. tx->command = ( INTEL_DESC_CMD_RS | INTEL_DESC_CMD_IFCS |
  548. INTEL_DESC_CMD_EOP );
  549. tx->status = 0;
  550. wmb();
  551. /* Notify card that there are packets ready to transmit */
  552. profile_start ( &intel_vm_tx_profiler );
  553. writel ( tx_tail, intel->regs + intel->tx.reg + INTEL_xDT );
  554. profile_stop ( &intel_vm_tx_profiler );
  555. profile_exclude ( &intel_vm_tx_profiler );
  556. DBGC2 ( intel, "INTEL %p TX %d is [%llx,%llx)\n", intel, tx_idx,
  557. ( ( unsigned long long ) address ),
  558. ( ( unsigned long long ) address + iob_len ( iobuf ) ) );
  559. return 0;
  560. }
  561. /**
  562. * Poll for completed packets
  563. *
  564. * @v netdev Network device
  565. */
  566. void intel_poll_tx ( struct net_device *netdev ) {
  567. struct intel_nic *intel = netdev->priv;
  568. struct intel_descriptor *tx;
  569. unsigned int tx_idx;
  570. /* Check for completed packets */
  571. while ( intel->tx.cons != intel->tx.prod ) {
  572. /* Get next transmit descriptor */
  573. tx_idx = ( intel->tx.cons % INTEL_NUM_TX_DESC );
  574. tx = &intel->tx.desc[tx_idx];
  575. /* Stop if descriptor is still in use */
  576. if ( ! ( tx->status & INTEL_DESC_STATUS_DD ) )
  577. return;
  578. DBGC2 ( intel, "INTEL %p TX %d complete\n", intel, tx_idx );
  579. /* Complete TX descriptor */
  580. netdev_tx_complete_next ( netdev );
  581. intel->tx.cons++;
  582. }
  583. }
  584. /**
  585. * Poll for received packets
  586. *
  587. * @v netdev Network device
  588. */
  589. void intel_poll_rx ( struct net_device *netdev ) {
  590. struct intel_nic *intel = netdev->priv;
  591. struct intel_descriptor *rx;
  592. struct io_buffer *iobuf;
  593. unsigned int rx_idx;
  594. size_t len;
  595. /* Check for received packets */
  596. while ( intel->rx.cons != intel->rx.prod ) {
  597. /* Get next receive descriptor */
  598. rx_idx = ( intel->rx.cons % INTEL_NUM_RX_DESC );
  599. rx = &intel->rx.desc[rx_idx];
  600. /* Stop if descriptor is still in use */
  601. if ( ! ( rx->status & INTEL_DESC_STATUS_DD ) )
  602. return;
  603. /* Populate I/O buffer */
  604. iobuf = intel->rx_iobuf[rx_idx];
  605. intel->rx_iobuf[rx_idx] = NULL;
  606. len = le16_to_cpu ( rx->length );
  607. iob_put ( iobuf, len );
  608. /* Hand off to network stack */
  609. if ( rx->errors ) {
  610. DBGC ( intel, "INTEL %p RX %d error (length %zd, "
  611. "errors %02x)\n",
  612. intel, rx_idx, len, rx->errors );
  613. netdev_rx_err ( netdev, iobuf, -EIO );
  614. } else {
  615. DBGC2 ( intel, "INTEL %p RX %d complete (length %zd)\n",
  616. intel, rx_idx, len );
  617. netdev_rx ( netdev, iobuf );
  618. }
  619. intel->rx.cons++;
  620. }
  621. }
  622. /**
  623. * Poll for completed and received packets
  624. *
  625. * @v netdev Network device
  626. */
  627. static void intel_poll ( struct net_device *netdev ) {
  628. struct intel_nic *intel = netdev->priv;
  629. uint32_t icr;
  630. /* Check for and acknowledge interrupts */
  631. profile_start ( &intel_vm_poll_profiler );
  632. icr = readl ( intel->regs + INTEL_ICR );
  633. profile_stop ( &intel_vm_poll_profiler );
  634. profile_exclude ( &intel_vm_poll_profiler );
  635. if ( ! icr )
  636. return;
  637. /* Poll for TX completions, if applicable */
  638. if ( icr & INTEL_IRQ_TXDW )
  639. intel_poll_tx ( netdev );
  640. /* Poll for RX completions, if applicable */
  641. if ( icr & ( INTEL_IRQ_RXT0 | INTEL_IRQ_RXO ) )
  642. intel_poll_rx ( netdev );
  643. /* Report receive overruns */
  644. if ( icr & INTEL_IRQ_RXO )
  645. netdev_rx_err ( netdev, NULL, -ENOBUFS );
  646. /* Check link state, if applicable */
  647. if ( icr & INTEL_IRQ_LSC )
  648. intel_check_link ( netdev );
  649. /* Refill RX ring */
  650. intel_refill_rx ( intel );
  651. }
  652. /**
  653. * Enable or disable interrupts
  654. *
  655. * @v netdev Network device
  656. * @v enable Interrupts should be enabled
  657. */
  658. static void intel_irq ( struct net_device *netdev, int enable ) {
  659. struct intel_nic *intel = netdev->priv;
  660. uint32_t mask;
  661. mask = ( INTEL_IRQ_TXDW | INTEL_IRQ_LSC | INTEL_IRQ_RXT0 );
  662. if ( enable ) {
  663. writel ( mask, intel->regs + INTEL_IMS );
  664. } else {
  665. writel ( mask, intel->regs + INTEL_IMC );
  666. }
  667. }
  668. /** Intel network device operations */
  669. static struct net_device_operations intel_operations = {
  670. .open = intel_open,
  671. .close = intel_close,
  672. .transmit = intel_transmit,
  673. .poll = intel_poll,
  674. .irq = intel_irq,
  675. };
  676. /******************************************************************************
  677. *
  678. * PCI interface
  679. *
  680. ******************************************************************************
  681. */
  682. /**
  683. * Probe PCI device
  684. *
  685. * @v pci PCI device
  686. * @ret rc Return status code
  687. */
  688. static int intel_probe ( struct pci_device *pci ) {
  689. struct net_device *netdev;
  690. struct intel_nic *intel;
  691. int rc;
  692. /* Allocate and initialise net device */
  693. netdev = alloc_etherdev ( sizeof ( *intel ) );
  694. if ( ! netdev ) {
  695. rc = -ENOMEM;
  696. goto err_alloc;
  697. }
  698. netdev_init ( netdev, &intel_operations );
  699. intel = netdev->priv;
  700. pci_set_drvdata ( pci, netdev );
  701. netdev->dev = &pci->dev;
  702. memset ( intel, 0, sizeof ( *intel ) );
  703. intel->port = PCI_FUNC ( pci->busdevfn );
  704. intel->flags = pci->id->driver_data;
  705. intel_init_ring ( &intel->tx, INTEL_NUM_TX_DESC, INTEL_TD );
  706. intel_init_ring ( &intel->rx, INTEL_NUM_RX_DESC, INTEL_RD );
  707. /* Fix up PCI device */
  708. adjust_pci_device ( pci );
  709. /* Map registers */
  710. intel->regs = ioremap ( pci->membase, INTEL_BAR_SIZE );
  711. if ( ! intel->regs ) {
  712. rc = -ENODEV;
  713. goto err_ioremap;
  714. }
  715. /* Reset the NIC */
  716. if ( ( rc = intel_reset ( intel ) ) != 0 )
  717. goto err_reset;
  718. /* Fetch MAC address */
  719. if ( ( rc = intel_fetch_mac ( intel, netdev->hw_addr ) ) != 0 )
  720. goto err_fetch_mac;
  721. /* Register network device */
  722. if ( ( rc = register_netdev ( netdev ) ) != 0 )
  723. goto err_register_netdev;
  724. /* Set initial link state */
  725. intel_check_link ( netdev );
  726. return 0;
  727. unregister_netdev ( netdev );
  728. err_register_netdev:
  729. err_fetch_mac:
  730. intel_reset ( intel );
  731. err_reset:
  732. iounmap ( intel->regs );
  733. err_ioremap:
  734. netdev_nullify ( netdev );
  735. netdev_put ( netdev );
  736. err_alloc:
  737. return rc;
  738. }
  739. /**
  740. * Remove PCI device
  741. *
  742. * @v pci PCI device
  743. */
  744. static void intel_remove ( struct pci_device *pci ) {
  745. struct net_device *netdev = pci_get_drvdata ( pci );
  746. struct intel_nic *intel = netdev->priv;
  747. /* Unregister network device */
  748. unregister_netdev ( netdev );
  749. /* Reset the NIC */
  750. intel_reset ( intel );
  751. /* Free network device */
  752. iounmap ( intel->regs );
  753. netdev_nullify ( netdev );
  754. netdev_put ( netdev );
  755. }
  756. /** Intel PCI device IDs */
  757. static struct pci_device_id intel_nics[] = {
  758. PCI_ROM ( 0x8086, 0x0438, "dh8900cc", "DH8900CC", 0 ),
  759. PCI_ROM ( 0x8086, 0x043a, "dh8900cc-f", "DH8900CC Fiber", 0 ),
  760. PCI_ROM ( 0x8086, 0x043c, "dh8900cc-b", "DH8900CC Backplane", 0 ),
  761. PCI_ROM ( 0x8086, 0x0440, "dh8900cc-s", "DH8900CC SFP", 0 ),
  762. PCI_ROM ( 0x8086, 0x1000, "82542-f", "82542 (Fiber)", 0 ),
  763. PCI_ROM ( 0x8086, 0x1001, "82543gc-f", "82543GC (Fiber)", 0 ),
  764. PCI_ROM ( 0x8086, 0x1004, "82543gc", "82543GC (Copper)", 0 ),
  765. PCI_ROM ( 0x8086, 0x1008, "82544ei", "82544EI (Copper)", 0 ),
  766. PCI_ROM ( 0x8086, 0x1009, "82544ei-f", "82544EI (Fiber)", 0 ),
  767. PCI_ROM ( 0x8086, 0x100c, "82544gc", "82544GC (Copper)", 0 ),
  768. PCI_ROM ( 0x8086, 0x100d, "82544gc-l", "82544GC (LOM)", 0 ),
  769. PCI_ROM ( 0x8086, 0x100e, "82540em", "82540EM", 0 ),
  770. PCI_ROM ( 0x8086, 0x100f, "82545em", "82545EM (Copper)", 0 ),
  771. PCI_ROM ( 0x8086, 0x1010, "82546eb", "82546EB (Copper)", 0 ),
  772. PCI_ROM ( 0x8086, 0x1011, "82545em-f", "82545EM (Fiber)", 0 ),
  773. PCI_ROM ( 0x8086, 0x1012, "82546eb-f", "82546EB (Fiber)", 0 ),
  774. PCI_ROM ( 0x8086, 0x1013, "82541ei", "82541EI", 0 ),
  775. PCI_ROM ( 0x8086, 0x1014, "82541er", "82541ER", 0 ),
  776. PCI_ROM ( 0x8086, 0x1015, "82540em-l", "82540EM (LOM)", 0 ),
  777. PCI_ROM ( 0x8086, 0x1016, "82540ep-m", "82540EP (Mobile)", 0 ),
  778. PCI_ROM ( 0x8086, 0x1017, "82540ep", "82540EP", 0 ),
  779. PCI_ROM ( 0x8086, 0x1018, "82541ei", "82541EI", 0 ),
  780. PCI_ROM ( 0x8086, 0x1019, "82547ei", "82547EI", 0 ),
  781. PCI_ROM ( 0x8086, 0x101a, "82547ei-m", "82547EI (Mobile)", 0 ),
  782. PCI_ROM ( 0x8086, 0x101d, "82546eb", "82546EB", 0 ),
  783. PCI_ROM ( 0x8086, 0x101e, "82540ep-m", "82540EP (Mobile)", 0 ),
  784. PCI_ROM ( 0x8086, 0x1026, "82545gm", "82545GM", 0 ),
  785. PCI_ROM ( 0x8086, 0x1027, "82545gm-1", "82545GM", 0 ),
  786. PCI_ROM ( 0x8086, 0x1028, "82545gm-2", "82545GM", 0 ),
  787. PCI_ROM ( 0x8086, 0x1049, "82566mm", "82566MM", INTEL_PBS_ERRATA ),
  788. PCI_ROM ( 0x8086, 0x104a, "82566dm", "82566DM", INTEL_PBS_ERRATA ),
  789. PCI_ROM ( 0x8086, 0x104b, "82566dc", "82566DC", INTEL_PBS_ERRATA ),
  790. PCI_ROM ( 0x8086, 0x104c, "82562v", "82562V", INTEL_PBS_ERRATA ),
  791. PCI_ROM ( 0x8086, 0x104d, "82566mc", "82566MC", INTEL_PBS_ERRATA ),
  792. PCI_ROM ( 0x8086, 0x105e, "82571eb", "82571EB", 0 ),
  793. PCI_ROM ( 0x8086, 0x105f, "82571eb-1", "82571EB", 0 ),
  794. PCI_ROM ( 0x8086, 0x1060, "82571eb-2", "82571EB", 0 ),
  795. PCI_ROM ( 0x8086, 0x1075, "82547gi", "82547GI", 0 ),
  796. PCI_ROM ( 0x8086, 0x1076, "82541gi", "82541GI", 0 ),
  797. PCI_ROM ( 0x8086, 0x1077, "82541gi-1", "82541GI", 0 ),
  798. PCI_ROM ( 0x8086, 0x1078, "82541er", "82541ER", 0 ),
  799. PCI_ROM ( 0x8086, 0x1079, "82546gb", "82546GB", 0 ),
  800. PCI_ROM ( 0x8086, 0x107a, "82546gb-1", "82546GB", 0 ),
  801. PCI_ROM ( 0x8086, 0x107b, "82546gb-2", "82546GB", 0 ),
  802. PCI_ROM ( 0x8086, 0x107c, "82541pi", "82541PI", 0 ),
  803. PCI_ROM ( 0x8086, 0x107d, "82572ei", "82572EI (Copper)", 0 ),
  804. PCI_ROM ( 0x8086, 0x107e, "82572ei-f", "82572EI (Fiber)", 0 ),
  805. PCI_ROM ( 0x8086, 0x107f, "82572ei", "82572EI", 0 ),
  806. PCI_ROM ( 0x8086, 0x108a, "82546gb-3", "82546GB", 0 ),
  807. PCI_ROM ( 0x8086, 0x108b, "82573v", "82573V (Copper)", 0 ),
  808. PCI_ROM ( 0x8086, 0x108c, "82573e", "82573E (Copper)", 0 ),
  809. PCI_ROM ( 0x8086, 0x1096, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
  810. PCI_ROM ( 0x8086, 0x1098, "80003es2lan-s", "80003ES2LAN (Serdes)", 0 ),
  811. PCI_ROM ( 0x8086, 0x1099, "82546gb-4", "82546GB (Copper)", 0 ),
  812. PCI_ROM ( 0x8086, 0x109a, "82573l", "82573L", 0 ),
  813. PCI_ROM ( 0x8086, 0x10a4, "82571eb", "82571EB", 0 ),
  814. PCI_ROM ( 0x8086, 0x10a5, "82571eb", "82571EB (Fiber)", 0 ),
  815. PCI_ROM ( 0x8086, 0x10a7, "82575eb", "82575EB", 0 ),
  816. PCI_ROM ( 0x8086, 0x10a9, "82575eb", "82575EB Backplane", 0 ),
  817. PCI_ROM ( 0x8086, 0x10b5, "82546gb", "82546GB (Copper)", 0 ),
  818. PCI_ROM ( 0x8086, 0x10b9, "82572ei", "82572EI (Copper)", 0 ),
  819. PCI_ROM ( 0x8086, 0x10ba, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
  820. PCI_ROM ( 0x8086, 0x10bb, "80003es2lan", "80003ES2LAN (Serdes)", 0 ),
  821. PCI_ROM ( 0x8086, 0x10bc, "82571eb", "82571EB (Copper)", 0 ),
  822. PCI_ROM ( 0x8086, 0x10bd, "82566dm-2", "82566DM-2", 0 ),
  823. PCI_ROM ( 0x8086, 0x10bf, "82567lf", "82567LF", 0 ),
  824. PCI_ROM ( 0x8086, 0x10c0, "82562v-2", "82562V-2", 0 ),
  825. PCI_ROM ( 0x8086, 0x10c2, "82562g-2", "82562G-2", 0 ),
  826. PCI_ROM ( 0x8086, 0x10c3, "82562gt-2", "82562GT-2", 0 ),
  827. PCI_ROM ( 0x8086, 0x10c4, "82562gt", "82562GT", INTEL_PBS_ERRATA ),
  828. PCI_ROM ( 0x8086, 0x10c5, "82562g", "82562G", INTEL_PBS_ERRATA ),
  829. PCI_ROM ( 0x8086, 0x10c9, "82576", "82576", 0 ),
  830. PCI_ROM ( 0x8086, 0x10cb, "82567v", "82567V", 0 ),
  831. PCI_ROM ( 0x8086, 0x10cc, "82567lm-2", "82567LM-2", 0 ),
  832. PCI_ROM ( 0x8086, 0x10cd, "82567lf-2", "82567LF-2", 0 ),
  833. PCI_ROM ( 0x8086, 0x10ce, "82567v-2", "82567V-2", 0 ),
  834. PCI_ROM ( 0x8086, 0x10d3, "82574l", "82574L", 0 ),
  835. PCI_ROM ( 0x8086, 0x10d5, "82571pt", "82571PT PT Quad", 0 ),
  836. PCI_ROM ( 0x8086, 0x10d6, "82575gb", "82575GB", 0 ),
  837. PCI_ROM ( 0x8086, 0x10d9, "82571eb-d", "82571EB Dual Mezzanine", 0 ),
  838. PCI_ROM ( 0x8086, 0x10da, "82571eb-q", "82571EB Quad Mezzanine", 0 ),
  839. PCI_ROM ( 0x8086, 0x10de, "82567lm-3", "82567LM-3", 0 ),
  840. PCI_ROM ( 0x8086, 0x10df, "82567lf-3", "82567LF-3", 0 ),
  841. PCI_ROM ( 0x8086, 0x10e5, "82567lm-4", "82567LM-4", 0 ),
  842. PCI_ROM ( 0x8086, 0x10e6, "82576", "82576", 0 ),
  843. PCI_ROM ( 0x8086, 0x10e7, "82576-2", "82576", 0 ),
  844. PCI_ROM ( 0x8086, 0x10e8, "82576-3", "82576", 0 ),
  845. PCI_ROM ( 0x8086, 0x10ea, "82577lm", "82577LM", 0 ),
  846. PCI_ROM ( 0x8086, 0x10eb, "82577lc", "82577LC", 0 ),
  847. PCI_ROM ( 0x8086, 0x10ef, "82578dm", "82578DM", 0 ),
  848. PCI_ROM ( 0x8086, 0x10f0, "82578dc", "82578DC", 0 ),
  849. PCI_ROM ( 0x8086, 0x10f5, "82567lm", "82567LM", 0 ),
  850. PCI_ROM ( 0x8086, 0x10f6, "82574l", "82574L", 0 ),
  851. PCI_ROM ( 0x8086, 0x1501, "82567v-3", "82567V-3", INTEL_PBS_ERRATA ),
  852. PCI_ROM ( 0x8086, 0x1502, "82579lm", "82579LM", 0 ),
  853. PCI_ROM ( 0x8086, 0x1503, "82579v", "82579V", 0 ),
  854. PCI_ROM ( 0x8086, 0x150a, "82576ns", "82576NS", 0 ),
  855. PCI_ROM ( 0x8086, 0x150c, "82583v", "82583V", 0 ),
  856. PCI_ROM ( 0x8086, 0x150d, "82576-4", "82576 Backplane", 0 ),
  857. PCI_ROM ( 0x8086, 0x150e, "82580", "82580", 0 ),
  858. PCI_ROM ( 0x8086, 0x150f, "82580-f", "82580 Fiber", 0 ),
  859. PCI_ROM ( 0x8086, 0x1510, "82580-b", "82580 Backplane", 0 ),
  860. PCI_ROM ( 0x8086, 0x1511, "82580-s", "82580 SFP", 0 ),
  861. PCI_ROM ( 0x8086, 0x1516, "82580-2", "82580", 0 ),
  862. PCI_ROM ( 0x8086, 0x1518, "82576ns", "82576NS SerDes", 0 ),
  863. PCI_ROM ( 0x8086, 0x1521, "i350", "I350", 0 ),
  864. PCI_ROM ( 0x8086, 0x1522, "i350-f", "I350 Fiber", 0 ),
  865. PCI_ROM ( 0x8086, 0x1523, "i350-b", "I350 Backplane", 0 ),
  866. PCI_ROM ( 0x8086, 0x1524, "i350-2", "I350", 0 ),
  867. PCI_ROM ( 0x8086, 0x1525, "82567v-4", "82567V-4", 0 ),
  868. PCI_ROM ( 0x8086, 0x1526, "82576-5", "82576", 0 ),
  869. PCI_ROM ( 0x8086, 0x1527, "82580-f2", "82580 Fiber", 0 ),
  870. PCI_ROM ( 0x8086, 0x1533, "i210", "I210", 0 ),
  871. PCI_ROM ( 0x8086, 0x153a, "i217lm", "I217-LM", 0 ),
  872. PCI_ROM ( 0x8086, 0x153b, "i217v", "I217-V", 0 ),
  873. PCI_ROM ( 0x8086, 0x294c, "82566dc-2", "82566DC-2", 0 ),
  874. PCI_ROM ( 0x8086, 0x2e6e, "cemedia", "CE Media Processor", 0 ),
  875. };
  876. /** Intel PCI driver */
  877. struct pci_driver intel_driver __pci_driver = {
  878. .ids = intel_nics,
  879. .id_count = ( sizeof ( intel_nics ) / sizeof ( intel_nics[0] ) ),
  880. .probe = intel_probe,
  881. .remove = intel_remove,
  882. };