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  1. #ifdef ALLMULTI
  2. #error multicast support is not yet implemented
  3. #endif
  4. /*
  5. DAVICOM DM9009/DM9102/DM9102A Etherboot Driver V1.00
  6. This driver was ported from Marty Connor's Tulip Etherboot driver.
  7. Thanks Marty Connor (mdc@etherboot.org)
  8. This davicom etherboot driver supports DM9009/DM9102/DM9102A/
  9. DM9102A+DM9801/DM9102A+DM9802 NICs.
  10. This software may be used and distributed according to the terms
  11. of the GNU Public License, incorporated herein by reference.
  12. */
  13. FILE_LICENCE ( GPL_ANY );
  14. /*********************************************************************/
  15. /* Revision History */
  16. /*********************************************************************/
  17. /*
  18. 19 OCT 2000 Sten 1.00
  19. Different half and full duplex mode
  20. Do the different programming for DM9801/DM9802
  21. 12 OCT 2000 Sten 0.90
  22. This driver was ported from tulip driver and it
  23. has the following difference.
  24. Changed symbol tulip/TULIP to davicom/DAVICOM
  25. Deleted some code that did not use in this driver.
  26. Used chain-strcture to replace ring structure
  27. for both TX/RX descriptor.
  28. Allocated two tx descriptor.
  29. According current media mode to set operating
  30. register(CR6)
  31. */
  32. /*********************************************************************/
  33. /* Declarations */
  34. /*********************************************************************/
  35. #include "etherboot.h"
  36. #include "nic.h"
  37. #include <ipxe/pci.h>
  38. #include <ipxe/ethernet.h>
  39. #define TX_TIME_OUT 2*TICKS_PER_SEC
  40. /* Register offsets for davicom device */
  41. enum davicom_offsets {
  42. CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
  43. CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58,
  44. CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0
  45. };
  46. /* EEPROM Address width definitions */
  47. #define EEPROM_ADDRLEN 6
  48. #define EEPROM_SIZE 32 /* 1 << EEPROM_ADDRLEN */
  49. /* Used to be 128, but we only need to read enough to get the MAC
  50. address at bytes 20..25 */
  51. /* Data Read from the EEPROM */
  52. static unsigned char ee_data[EEPROM_SIZE];
  53. /* The EEPROM commands include the alway-set leading bit. */
  54. #define EE_WRITE_CMD (5 << addr_len)
  55. #define EE_READ_CMD (6 << addr_len)
  56. #define EE_ERASE_CMD (7 << addr_len)
  57. /* EEPROM_Ctrl bits. */
  58. #define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */
  59. #define EE_CS 0x01 /* EEPROM chip select. */
  60. #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
  61. #define EE_WRITE_0 0x01
  62. #define EE_WRITE_1 0x05
  63. #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
  64. #define EE_ENB (0x4800 | EE_CS)
  65. /* Sten 10/11 for phyxcer */
  66. #define PHY_DATA_0 0x0
  67. #define PHY_DATA_1 0x20000
  68. #define MDCLKH 0x10000
  69. /* Delay between EEPROM clock transitions. Even at 33Mhz current PCI
  70. implementations don't overrun the EEPROM clock. We add a bus
  71. turn-around to insure that this remains true. */
  72. #define eeprom_delay() inl(ee_addr)
  73. /* helpful macro if on a big_endian machine for changing byte order.
  74. not strictly needed on Intel
  75. Already defined in Etherboot includes
  76. #define le16_to_cpu(val) (val)
  77. */
  78. /* transmit and receive descriptor format */
  79. struct txdesc {
  80. volatile unsigned long status; /* owner, status */
  81. unsigned long buf1sz:11, /* size of buffer 1 */
  82. buf2sz:11, /* size of buffer 2 */
  83. control:10; /* control bits */
  84. const unsigned char *buf1addr; /* buffer 1 address */
  85. const unsigned char *buf2addr; /* buffer 2 address */
  86. };
  87. struct rxdesc {
  88. volatile unsigned long status; /* owner, status */
  89. unsigned long buf1sz:11, /* size of buffer 1 */
  90. buf2sz:11, /* size of buffer 2 */
  91. control:10; /* control bits */
  92. unsigned char *buf1addr; /* buffer 1 address */
  93. unsigned char *buf2addr; /* buffer 2 address */
  94. };
  95. /* Size of transmit and receive buffers */
  96. #define BUFLEN 1536
  97. /*********************************************************************/
  98. /* Global Storage */
  99. /*********************************************************************/
  100. static struct nic_operations davicom_operations;
  101. /* PCI Bus parameters */
  102. static unsigned short vendor, dev_id;
  103. static unsigned long ioaddr;
  104. /* Note: transmit and receive buffers must be longword aligned and
  105. longword divisable */
  106. /* transmit descriptor and buffer */
  107. #define NTXD 2
  108. #define NRXD 4
  109. struct {
  110. struct txdesc txd[NTXD] __attribute__ ((aligned(4)));
  111. unsigned char txb[BUFLEN] __attribute__ ((aligned(4)));
  112. struct rxdesc rxd[NRXD] __attribute__ ((aligned(4)));
  113. unsigned char rxb[NRXD * BUFLEN] __attribute__ ((aligned(4)));
  114. } davicom_bufs __shared;
  115. #define txd davicom_bufs.txd
  116. #define txb davicom_bufs.txb
  117. #define rxd davicom_bufs.rxd
  118. #define rxb davicom_bufs.rxb
  119. static int rxd_tail;
  120. static int TxPtr;
  121. /*********************************************************************/
  122. /* Function Prototypes */
  123. /*********************************************************************/
  124. static void whereami(const char *str);
  125. static int read_eeprom(unsigned long ioaddr, int location, int addr_len);
  126. static int davicom_probe(struct nic *nic,struct pci_device *pci);
  127. static void davicom_init_chain(struct nic *nic); /* Sten 10/9 */
  128. static void davicom_reset(struct nic *nic);
  129. static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
  130. unsigned int s, const char *p);
  131. static int davicom_poll(struct nic *nic, int retrieve);
  132. static void davicom_disable(struct nic *nic);
  133. static void davicom_wait(unsigned int nticks);
  134. static int phy_read(int);
  135. static void phy_write(int, u16);
  136. static void phy_write_1bit(u32, u32);
  137. static int phy_read_1bit(u32);
  138. static void davicom_media_chk(struct nic *);
  139. /*********************************************************************/
  140. /* Utility Routines */
  141. /*********************************************************************/
  142. static inline void whereami(const char *str)
  143. {
  144. DBGP("%s\n", str);
  145. /* sleep(2); */
  146. }
  147. static void davicom_wait(unsigned int nticks)
  148. {
  149. unsigned int to = currticks() + nticks;
  150. while (currticks() < to)
  151. /* wait */ ;
  152. }
  153. /*********************************************************************/
  154. /* For DAVICOM phyxcer register by MII interface */
  155. /*********************************************************************/
  156. /*
  157. Read a word data from phy register
  158. */
  159. static int phy_read(int location)
  160. {
  161. int i, phy_addr=1;
  162. u16 phy_data;
  163. u32 io_dcr9;
  164. whereami("phy_read\n");
  165. io_dcr9 = ioaddr + CSR9;
  166. /* Send 33 synchronization clock to Phy controller */
  167. for (i=0; i<34; i++)
  168. phy_write_1bit(io_dcr9, PHY_DATA_1);
  169. /* Send start command(01) to Phy */
  170. phy_write_1bit(io_dcr9, PHY_DATA_0);
  171. phy_write_1bit(io_dcr9, PHY_DATA_1);
  172. /* Send read command(10) to Phy */
  173. phy_write_1bit(io_dcr9, PHY_DATA_1);
  174. phy_write_1bit(io_dcr9, PHY_DATA_0);
  175. /* Send Phy address */
  176. for (i=0x10; i>0; i=i>>1)
  177. phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
  178. /* Send register address */
  179. for (i=0x10; i>0; i=i>>1)
  180. phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
  181. /* Skip transition state */
  182. phy_read_1bit(io_dcr9);
  183. /* read 16bit data */
  184. for (phy_data=0, i=0; i<16; i++) {
  185. phy_data<<=1;
  186. phy_data|=phy_read_1bit(io_dcr9);
  187. }
  188. return phy_data;
  189. }
  190. /*
  191. Write a word to Phy register
  192. */
  193. static void phy_write(int location, u16 phy_data)
  194. {
  195. u16 i, phy_addr=1;
  196. u32 io_dcr9;
  197. whereami("phy_write\n");
  198. io_dcr9 = ioaddr + CSR9;
  199. /* Send 33 synchronization clock to Phy controller */
  200. for (i=0; i<34; i++)
  201. phy_write_1bit(io_dcr9, PHY_DATA_1);
  202. /* Send start command(01) to Phy */
  203. phy_write_1bit(io_dcr9, PHY_DATA_0);
  204. phy_write_1bit(io_dcr9, PHY_DATA_1);
  205. /* Send write command(01) to Phy */
  206. phy_write_1bit(io_dcr9, PHY_DATA_0);
  207. phy_write_1bit(io_dcr9, PHY_DATA_1);
  208. /* Send Phy address */
  209. for (i=0x10; i>0; i=i>>1)
  210. phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
  211. /* Send register address */
  212. for (i=0x10; i>0; i=i>>1)
  213. phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
  214. /* written trasnition */
  215. phy_write_1bit(io_dcr9, PHY_DATA_1);
  216. phy_write_1bit(io_dcr9, PHY_DATA_0);
  217. /* Write a word data to PHY controller */
  218. for (i=0x8000; i>0; i>>=1)
  219. phy_write_1bit(io_dcr9, phy_data&i ? PHY_DATA_1: PHY_DATA_0);
  220. }
  221. /*
  222. Write one bit data to Phy Controller
  223. */
  224. static void phy_write_1bit(u32 ee_addr, u32 phy_data)
  225. {
  226. whereami("phy_write_1bit\n");
  227. outl(phy_data, ee_addr); /* MII Clock Low */
  228. eeprom_delay();
  229. outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */
  230. eeprom_delay();
  231. outl(phy_data, ee_addr); /* MII Clock Low */
  232. eeprom_delay();
  233. }
  234. /*
  235. Read one bit phy data from PHY controller
  236. */
  237. static int phy_read_1bit(u32 ee_addr)
  238. {
  239. int phy_data;
  240. whereami("phy_read_1bit\n");
  241. outl(0x50000, ee_addr);
  242. eeprom_delay();
  243. phy_data=(inl(ee_addr)>>19) & 0x1;
  244. outl(0x40000, ee_addr);
  245. eeprom_delay();
  246. return phy_data;
  247. }
  248. /*
  249. DM9801/DM9802 present check and program
  250. */
  251. static void HPNA_process(void)
  252. {
  253. if ( (phy_read(3) & 0xfff0) == 0xb900 ) {
  254. if ( phy_read(31) == 0x4404 ) {
  255. /* DM9801 present */
  256. if (phy_read(3) == 0xb901)
  257. phy_write(16, 0x5); /* DM9801 E4 */
  258. else
  259. phy_write(16, 0x1005); /* DM9801 E3 and others */
  260. phy_write(25, ((phy_read(24) + 3) & 0xff) | 0xf000);
  261. } else {
  262. /* DM9802 present */
  263. phy_write(16, 0x5);
  264. phy_write(25, (phy_read(25) & 0xff00) + 2);
  265. }
  266. }
  267. }
  268. /*
  269. Sense media mode and set CR6
  270. */
  271. static void davicom_media_chk(struct nic * nic __unused)
  272. {
  273. unsigned long to, csr6;
  274. csr6 = 0x00200000; /* SF */
  275. outl(csr6, ioaddr + CSR6);
  276. #define PCI_VENDOR_ID_DAVICOM 0x1282
  277. #define PCI_DEVICE_ID_DM9009 0x9009
  278. if (vendor == PCI_VENDOR_ID_DAVICOM && dev_id == PCI_DEVICE_ID_DM9009) {
  279. /* Set to 10BaseT mode for DM9009 */
  280. phy_write(0, 0);
  281. } else {
  282. /* For DM9102/DM9102A */
  283. to = currticks() + 2 * TICKS_PER_SEC;
  284. while ( ((phy_read(1) & 0x24)!=0x24) && (currticks() < to))
  285. /* wait */ ;
  286. if ( (phy_read(1) & 0x24) == 0x24 ) {
  287. if (phy_read(17) & 0xa000)
  288. csr6 |= 0x00000200; /* Full Duplex mode */
  289. } else
  290. csr6 |= 0x00040000; /* Select DM9801/DM9802 when Ethernet link failed */
  291. }
  292. /* set the chip's operating mode */
  293. outl(csr6, ioaddr + CSR6);
  294. /* DM9801/DM9802 present check & program */
  295. if (csr6 & 0x40000)
  296. HPNA_process();
  297. }
  298. /*********************************************************************/
  299. /* EEPROM Reading Code */
  300. /*********************************************************************/
  301. /* EEPROM routines adapted from the Linux Tulip Code */
  302. /* Reading a serial EEPROM is a "bit" grungy, but we work our way
  303. through:->.
  304. */
  305. static int read_eeprom(unsigned long ioaddr, int location, int addr_len)
  306. {
  307. int i;
  308. unsigned short retval = 0;
  309. long ee_addr = ioaddr + CSR9;
  310. int read_cmd = location | EE_READ_CMD;
  311. whereami("read_eeprom\n");
  312. outl(EE_ENB & ~EE_CS, ee_addr);
  313. outl(EE_ENB, ee_addr);
  314. /* Shift the read command bits out. */
  315. for (i = 4 + addr_len; i >= 0; i--) {
  316. short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  317. outl(EE_ENB | dataval, ee_addr);
  318. eeprom_delay();
  319. outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
  320. eeprom_delay();
  321. }
  322. outl(EE_ENB, ee_addr);
  323. for (i = 16; i > 0; i--) {
  324. outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
  325. eeprom_delay();
  326. retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
  327. outl(EE_ENB, ee_addr);
  328. eeprom_delay();
  329. }
  330. /* Terminate the EEPROM access. */
  331. outl(EE_ENB & ~EE_CS, ee_addr);
  332. return retval;
  333. }
  334. /*********************************************************************/
  335. /* davicom_init_chain - setup the tx and rx descriptors */
  336. /* Sten 10/9 */
  337. /*********************************************************************/
  338. static void davicom_init_chain(struct nic *nic)
  339. {
  340. int i;
  341. /* setup the transmit descriptor */
  342. /* Sten: Set 2 TX descriptor but use one TX buffer because
  343. it transmit a packet and wait complete every time. */
  344. for (i=0; i<NTXD; i++) {
  345. txd[i].buf1addr = (void *)virt_to_bus(&txb[0]); /* Used same TX buffer */
  346. txd[i].buf2addr = (void *)virt_to_bus(&txd[i+1]); /* Point to Next TX desc */
  347. txd[i].buf1sz = 0;
  348. txd[i].buf2sz = 0;
  349. txd[i].control = 0x184; /* Begin/End/Chain */
  350. txd[i].status = 0x00000000; /* give ownership to Host */
  351. }
  352. /* construct perfect filter frame with mac address as first match
  353. and broadcast address for all others */
  354. for (i=0; i<192; i++) txb[i] = 0xFF;
  355. txb[0] = nic->node_addr[0];
  356. txb[1] = nic->node_addr[1];
  357. txb[4] = nic->node_addr[2];
  358. txb[5] = nic->node_addr[3];
  359. txb[8] = nic->node_addr[4];
  360. txb[9] = nic->node_addr[5];
  361. /* setup receive descriptor */
  362. for (i=0; i<NRXD; i++) {
  363. rxd[i].buf1addr = (void *)virt_to_bus(&rxb[i * BUFLEN]);
  364. rxd[i].buf2addr = (void *)virt_to_bus(&rxd[i+1]); /* Point to Next RX desc */
  365. rxd[i].buf1sz = BUFLEN;
  366. rxd[i].buf2sz = 0; /* not used */
  367. rxd[i].control = 0x4; /* Chain Structure */
  368. rxd[i].status = 0x80000000; /* give ownership to device */
  369. }
  370. /* Chain the last descriptor to first */
  371. txd[NTXD - 1].buf2addr = (void *)virt_to_bus(&txd[0]);
  372. rxd[NRXD - 1].buf2addr = (void *)virt_to_bus(&rxd[0]);
  373. TxPtr = 0;
  374. rxd_tail = 0;
  375. }
  376. /*********************************************************************/
  377. /* davicom_reset - Reset adapter */
  378. /*********************************************************************/
  379. static void davicom_reset(struct nic *nic)
  380. {
  381. unsigned long to;
  382. whereami("davicom_reset\n");
  383. /* Stop Tx and RX */
  384. outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
  385. /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
  386. outl(0x00000001, ioaddr + CSR0);
  387. davicom_wait(TICKS_PER_SEC);
  388. /* TX/RX descriptor burst */
  389. outl(0x0C00000, ioaddr + CSR0); /* Sten 10/9 */
  390. /* set up transmit and receive descriptors */
  391. davicom_init_chain(nic); /* Sten 10/9 */
  392. /* Point to receive descriptor */
  393. outl(virt_to_bus(&rxd[0]), ioaddr + CSR3);
  394. outl(virt_to_bus(&txd[0]), ioaddr + CSR4); /* Sten 10/9 */
  395. /* According phyxcer media mode to set CR6,
  396. DM9102/A phyxcer can auto-detect media mode */
  397. davicom_media_chk(nic);
  398. /* Prepare Setup Frame Sten 10/9 */
  399. txd[TxPtr].buf1sz = 192;
  400. txd[TxPtr].control = 0x024; /* SF/CE */
  401. txd[TxPtr].status = 0x80000000; /* Give ownership to device */
  402. /* Start Tx */
  403. outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6);
  404. /* immediate transmit demand */
  405. outl(0, ioaddr + CSR1);
  406. to = currticks() + TX_TIME_OUT;
  407. while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) /* Sten 10/9 */
  408. /* wait */ ;
  409. if (currticks() >= to) {
  410. DBG ("TX Setup Timeout!\n");
  411. }
  412. /* Point to next TX descriptor */
  413. TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */
  414. DBG("txd.status = %lX\n", txd[TxPtr].status);
  415. DBG("ticks = %ld\n", currticks() - (to - TX_TIME_OUT));
  416. DBG_MORE();
  417. /* enable RX */
  418. outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6);
  419. /* immediate poll demand */
  420. outl(0, ioaddr + CSR2);
  421. }
  422. /*********************************************************************/
  423. /* eth_transmit - Transmit a frame */
  424. /*********************************************************************/
  425. static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
  426. unsigned int s, const char *p)
  427. {
  428. unsigned long to;
  429. whereami("davicom_transmit\n");
  430. /* Stop Tx */
  431. /* outl(inl(ioaddr + CSR6) & ~0x00002000, ioaddr + CSR6); */
  432. /* setup ethernet header */
  433. memcpy(&txb[0], d, ETH_ALEN); /* DA 6byte */
  434. memcpy(&txb[ETH_ALEN], nic->node_addr, ETH_ALEN); /* SA 6byte*/
  435. txb[ETH_ALEN*2] = (t >> 8) & 0xFF; /* Frame type: 2byte */
  436. txb[ETH_ALEN*2+1] = t & 0xFF;
  437. memcpy(&txb[ETH_HLEN], p, s); /* Frame data */
  438. /* setup the transmit descriptor */
  439. txd[TxPtr].buf1sz = ETH_HLEN+s;
  440. txd[TxPtr].control = 0x00000184; /* LS+FS+CE */
  441. txd[TxPtr].status = 0x80000000; /* give ownership to device */
  442. /* immediate transmit demand */
  443. outl(0, ioaddr + CSR1);
  444. to = currticks() + TX_TIME_OUT;
  445. while ((txd[TxPtr].status & 0x80000000) && (currticks() < to))
  446. /* wait */ ;
  447. if (currticks() >= to) {
  448. DBG ("TX Timeout!\n");
  449. }
  450. /* Point to next TX descriptor */
  451. TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */
  452. }
  453. /*********************************************************************/
  454. /* eth_poll - Wait for a frame */
  455. /*********************************************************************/
  456. static int davicom_poll(struct nic *nic, int retrieve)
  457. {
  458. whereami("davicom_poll\n");
  459. if (rxd[rxd_tail].status & 0x80000000)
  460. return 0;
  461. if ( ! retrieve ) return 1;
  462. whereami("davicom_poll got one\n");
  463. nic->packetlen = (rxd[rxd_tail].status & 0x3FFF0000) >> 16;
  464. if( rxd[rxd_tail].status & 0x00008000){
  465. rxd[rxd_tail].status = 0x80000000;
  466. rxd_tail++;
  467. if (rxd_tail == NRXD) rxd_tail = 0;
  468. return 0;
  469. }
  470. /* copy packet to working buffer */
  471. /* XXX - this copy could be avoided with a little more work
  472. but for now we are content with it because the optimised
  473. memcpy is quite fast */
  474. memcpy(nic->packet, rxb + rxd_tail * BUFLEN, nic->packetlen);
  475. /* return the descriptor and buffer to receive ring */
  476. rxd[rxd_tail].status = 0x80000000;
  477. rxd_tail++;
  478. if (rxd_tail == NRXD) rxd_tail = 0;
  479. return 1;
  480. }
  481. /*********************************************************************/
  482. /* eth_disable - Disable the interface */
  483. /*********************************************************************/
  484. static void davicom_disable ( struct nic *nic ) {
  485. whereami("davicom_disable\n");
  486. davicom_reset(nic);
  487. /* disable interrupts */
  488. outl(0x00000000, ioaddr + CSR7);
  489. /* Stop the chip's Tx and Rx processes. */
  490. outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
  491. /* Clear the missed-packet counter. */
  492. inl(ioaddr + CSR8);
  493. }
  494. /*********************************************************************/
  495. /* eth_irq - enable, disable and force interrupts */
  496. /*********************************************************************/
  497. static void davicom_irq(struct nic *nic __unused, irq_action_t action __unused)
  498. {
  499. switch ( action ) {
  500. case DISABLE :
  501. break;
  502. case ENABLE :
  503. break;
  504. case FORCE :
  505. break;
  506. }
  507. }
  508. /*********************************************************************/
  509. /* eth_probe - Look for an adapter */
  510. /*********************************************************************/
  511. static int davicom_probe ( struct nic *nic, struct pci_device *pci ) {
  512. unsigned int i;
  513. whereami("davicom_probe\n");
  514. if (pci->ioaddr == 0)
  515. return 0;
  516. vendor = pci->vendor;
  517. dev_id = pci->device;
  518. ioaddr = pci->ioaddr;
  519. nic->ioaddr = pci->ioaddr;
  520. nic->irqno = 0;
  521. /* wakeup chip */
  522. pci_write_config_dword(pci, 0x40, 0x00000000);
  523. /* Stop the chip's Tx and Rx processes. */
  524. outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
  525. /* Clear the missed-packet counter. */
  526. inl(ioaddr + CSR8);
  527. /* Get MAC Address */
  528. /* read EEPROM data */
  529. for (i = 0; i < sizeof(ee_data)/2; i++)
  530. ((unsigned short *)ee_data)[i] =
  531. le16_to_cpu(read_eeprom(ioaddr, i, EEPROM_ADDRLEN));
  532. /* extract MAC address from EEPROM buffer */
  533. for (i=0; i<ETH_ALEN; i++)
  534. nic->node_addr[i] = ee_data[20+i];
  535. DBG ( "Davicom %s at IOADDR %4.4lx\n", eth_ntoa ( nic->node_addr ), ioaddr );
  536. /* initialize device */
  537. davicom_reset(nic);
  538. nic->nic_op = &davicom_operations;
  539. return 1;
  540. }
  541. static struct nic_operations davicom_operations = {
  542. .connect = dummy_connect,
  543. .poll = davicom_poll,
  544. .transmit = davicom_transmit,
  545. .irq = davicom_irq,
  546. };
  547. static struct pci_device_id davicom_nics[] = {
  548. PCI_ROM(0x1282, 0x9100, "davicom9100", "Davicom 9100", 0),
  549. PCI_ROM(0x1282, 0x9102, "davicom9102", "Davicom 9102", 0),
  550. PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009", 0),
  551. PCI_ROM(0x1282, 0x9132, "davicom9132", "Davicom 9132", 0), /* Needs probably some fixing */
  552. };
  553. PCI_DRIVER ( davicom_driver, davicom_nics, PCI_NO_CLASS );
  554. DRIVER ( "DAVICOM", nic_driver, pci_driver, davicom_driver,
  555. davicom_probe, davicom_disable );
  556. /*
  557. * Local variables:
  558. * c-basic-offset: 8
  559. * c-indent-level: 8
  560. * tab-width: 8
  561. * End:
  562. */