Vous ne pouvez pas sélectionner plus de 25 sujets Les noms de sujets doivent commencer par une lettre ou un nombre, peuvent contenir des tirets ('-') et peuvent comporter jusqu'à 35 caractères.

bnx2.h 190KB

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  1. /* bnx2.h: Broadcom NX2 network driver.
  2. *
  3. * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Written by: Michael Chan (mchan@broadcom.com)
  10. */
  11. FILE_LICENCE ( GPL_ANY );
  12. #ifndef BNX2_H
  13. #define BNX2_H
  14. #define L1_CACHE_BYTES 128 /* Rough approximaition of the cache line size */
  15. #define L1_CACHE_ALIGN(X) (((X) + L1_CACHE_BYTES-1)&~(L1_CACHE_BYTES -1))
  16. typedef unsigned long dma_addr_t;
  17. /* From pci.h */
  18. typedef int pci_power_t;
  19. #define PCI_D0 ((pci_power_t) 0)
  20. #define PCI_D1 ((pci_power_t) 1)
  21. #define PCI_D2 ((pci_power_t) 2)
  22. #define PCI_D3hot ((pci_power_t) 3)
  23. #define PCI_D3cold ((pci_power_t) 4)
  24. #define PCI_UNKNOWN ((pci_power_t) 5)
  25. #define PCI_POWER_ERROR ((pci_power_t) -1)
  26. /* From pci_regs.h */
  27. #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
  28. #define PCI_X_CMD 2 /* Modes & Features */
  29. #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
  30. /* From mii.h */
  31. /* Indicates what features are advertised by the interface. */
  32. #define ADVERTISED_10baseT_Half (1 << 0)
  33. #define ADVERTISED_10baseT_Full (1 << 1)
  34. #define ADVERTISED_100baseT_Half (1 << 2)
  35. #define ADVERTISED_100baseT_Full (1 << 3)
  36. #define ADVERTISED_1000baseT_Half (1 << 4)
  37. #define ADVERTISED_1000baseT_Full (1 << 5)
  38. #define ADVERTISED_Autoneg (1 << 6)
  39. #define ADVERTISED_TP (1 << 7)
  40. #define ADVERTISED_AUI (1 << 8)
  41. #define ADVERTISED_MII (1 << 9)
  42. #define ADVERTISED_FIBRE (1 << 10)
  43. #define ADVERTISED_BNC (1 << 11)
  44. /* The following are all involved in forcing a particular link
  45. * mode for the device for setting things. When getting the
  46. * devices settings, these indicate the current mode and whether
  47. * it was foced up into this mode or autonegotiated.
  48. */
  49. /* Duplex, half or full. */
  50. #define DUPLEX_HALF 0x00
  51. #define DUPLEX_FULL 0x01
  52. #define DUPLEX_INVALID 0x02
  53. /* Which connector port. */
  54. #define PORT_TP 0x00
  55. #define PORT_AUI 0x01
  56. #define PORT_MII 0x02
  57. #define PORT_FIBRE 0x03
  58. #define PORT_BNC 0x04
  59. /* Which tranceiver to use. */
  60. #define XCVR_INTERNAL 0x00
  61. #define XCVR_EXTERNAL 0x01
  62. #define XCVR_DUMMY1 0x02
  63. #define XCVR_DUMMY2 0x03
  64. #define XCVR_DUMMY3 0x04
  65. /* Enable or disable autonegotiation. If this is set to enable,
  66. * the forced link modes above are completely ignored.
  67. */
  68. #define AUTONEG_DISABLE 0x00
  69. #define AUTONEG_ENABLE 0x01
  70. /* Wake-On-Lan options. */
  71. #define WAKE_PHY (1 << 0)
  72. #define WAKE_UCAST (1 << 1)
  73. #define WAKE_MCAST (1 << 2)
  74. #define WAKE_BCAST (1 << 3)
  75. #define WAKE_ARP (1 << 4)
  76. #define WAKE_MAGIC (1 << 5)
  77. #define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */
  78. /* The following are all involved in forcing a particular link
  79. * * mode for the device for setting things. When getting the
  80. * * devices settings, these indicate the current mode and whether
  81. * * it was foced up into this mode or autonegotiated.
  82. * */
  83. /* The forced speed, 10Mb, 100Mb, gigabit. */
  84. #define SPEED_10 10
  85. #define SPEED_100 100
  86. #define SPEED_1000 1000
  87. #define SPEED_2500 2500
  88. #define SPEED_INVALID 0 /* XXX was 3 */
  89. /* Duplex, half or full. */
  90. #define DUPLEX_HALF 0x00
  91. #define DUPLEX_FULL 0x01
  92. #define DUPLEX_INVALID 0x02
  93. /* Which connector port. */
  94. #define PORT_TP 0x00
  95. #define PORT_AUI 0x01
  96. #define PORT_MII 0x02
  97. #define PORT_FIBRE 0x03
  98. #define PORT_BNC 0x04
  99. /* Which tranceiver to use. */
  100. #define XCVR_INTERNAL 0x00
  101. #define XCVR_EXTERNAL 0x01
  102. #define XCVR_DUMMY1 0x02
  103. #define XCVR_DUMMY2 0x03
  104. #define XCVR_DUMMY3 0x04
  105. /* Enable or disable autonegotiation. If this is set to enable,
  106. * * the forced link modes above are completely ignored.
  107. * */
  108. #define AUTONEG_DISABLE 0x00
  109. #define AUTONEG_ENABLE 0x01
  110. /* Wake-On-Lan options. */
  111. #define WAKE_PHY (1 << 0)
  112. #define WAKE_UCAST (1 << 1)
  113. #define WAKE_MCAST (1 << 2)
  114. #define WAKE_BCAST (1 << 3)
  115. #define WAKE_ARP (1 << 4)
  116. #define WAKE_MAGIC (1 << 5)
  117. #define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */
  118. /* Hardware data structures and register definitions automatically
  119. * generated from RTL code. Do not modify.
  120. */
  121. /*
  122. * tx_bd definition
  123. */
  124. struct tx_bd {
  125. u32 tx_bd_haddr_hi;
  126. u32 tx_bd_haddr_lo;
  127. u32 tx_bd_mss_nbytes;
  128. u32 tx_bd_vlan_tag_flags;
  129. #define TX_BD_FLAGS_CONN_FAULT (1<<0)
  130. #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1)
  131. #define TX_BD_FLAGS_IP_CKSUM (1<<2)
  132. #define TX_BD_FLAGS_VLAN_TAG (1<<3)
  133. #define TX_BD_FLAGS_COAL_NOW (1<<4)
  134. #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5)
  135. #define TX_BD_FLAGS_END (1<<6)
  136. #define TX_BD_FLAGS_START (1<<7)
  137. #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
  138. #define TX_BD_FLAGS_SW_FLAGS (1<<13)
  139. #define TX_BD_FLAGS_SW_SNAP (1<<14)
  140. #define TX_BD_FLAGS_SW_LSO (1<<15)
  141. };
  142. /*
  143. * rx_bd definition
  144. */
  145. struct rx_bd {
  146. u32 rx_bd_haddr_hi;
  147. u32 rx_bd_haddr_lo;
  148. u32 rx_bd_len;
  149. u32 rx_bd_flags;
  150. #define RX_BD_FLAGS_NOPUSH (1<<0)
  151. #define RX_BD_FLAGS_DUMMY (1<<1)
  152. #define RX_BD_FLAGS_END (1<<2)
  153. #define RX_BD_FLAGS_START (1<<3)
  154. };
  155. /*
  156. * status_block definition
  157. */
  158. struct status_block {
  159. u32 status_attn_bits;
  160. #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
  161. #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
  162. #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
  163. #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
  164. #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
  165. #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
  166. #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
  167. #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
  168. #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
  169. #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
  170. #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
  171. #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
  172. #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
  173. #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
  174. #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
  175. #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
  176. #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
  177. #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
  178. #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
  179. #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
  180. #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
  181. #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
  182. #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
  183. #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
  184. #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
  185. #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
  186. #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
  187. #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
  188. #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
  189. u32 status_attn_bits_ack;
  190. #if __BYTE_ORDER == __BIG_ENDIAN
  191. u16 status_tx_quick_consumer_index0;
  192. u16 status_tx_quick_consumer_index1;
  193. u16 status_tx_quick_consumer_index2;
  194. u16 status_tx_quick_consumer_index3;
  195. u16 status_rx_quick_consumer_index0;
  196. u16 status_rx_quick_consumer_index1;
  197. u16 status_rx_quick_consumer_index2;
  198. u16 status_rx_quick_consumer_index3;
  199. u16 status_rx_quick_consumer_index4;
  200. u16 status_rx_quick_consumer_index5;
  201. u16 status_rx_quick_consumer_index6;
  202. u16 status_rx_quick_consumer_index7;
  203. u16 status_rx_quick_consumer_index8;
  204. u16 status_rx_quick_consumer_index9;
  205. u16 status_rx_quick_consumer_index10;
  206. u16 status_rx_quick_consumer_index11;
  207. u16 status_rx_quick_consumer_index12;
  208. u16 status_rx_quick_consumer_index13;
  209. u16 status_rx_quick_consumer_index14;
  210. u16 status_rx_quick_consumer_index15;
  211. u16 status_completion_producer_index;
  212. u16 status_cmd_consumer_index;
  213. u16 status_idx;
  214. u16 status_unused;
  215. #elif __BYTE_ORDER == __LITTLE_ENDIAN
  216. u16 status_tx_quick_consumer_index1;
  217. u16 status_tx_quick_consumer_index0;
  218. u16 status_tx_quick_consumer_index3;
  219. u16 status_tx_quick_consumer_index2;
  220. u16 status_rx_quick_consumer_index1;
  221. u16 status_rx_quick_consumer_index0;
  222. u16 status_rx_quick_consumer_index3;
  223. u16 status_rx_quick_consumer_index2;
  224. u16 status_rx_quick_consumer_index5;
  225. u16 status_rx_quick_consumer_index4;
  226. u16 status_rx_quick_consumer_index7;
  227. u16 status_rx_quick_consumer_index6;
  228. u16 status_rx_quick_consumer_index9;
  229. u16 status_rx_quick_consumer_index8;
  230. u16 status_rx_quick_consumer_index11;
  231. u16 status_rx_quick_consumer_index10;
  232. u16 status_rx_quick_consumer_index13;
  233. u16 status_rx_quick_consumer_index12;
  234. u16 status_rx_quick_consumer_index15;
  235. u16 status_rx_quick_consumer_index14;
  236. u16 status_cmd_consumer_index;
  237. u16 status_completion_producer_index;
  238. u16 status_unused;
  239. u16 status_idx;
  240. #endif
  241. };
  242. /*
  243. * statistics_block definition
  244. */
  245. struct statistics_block {
  246. u32 stat_IfHCInOctets_hi;
  247. u32 stat_IfHCInOctets_lo;
  248. u32 stat_IfHCInBadOctets_hi;
  249. u32 stat_IfHCInBadOctets_lo;
  250. u32 stat_IfHCOutOctets_hi;
  251. u32 stat_IfHCOutOctets_lo;
  252. u32 stat_IfHCOutBadOctets_hi;
  253. u32 stat_IfHCOutBadOctets_lo;
  254. u32 stat_IfHCInUcastPkts_hi;
  255. u32 stat_IfHCInUcastPkts_lo;
  256. u32 stat_IfHCInMulticastPkts_hi;
  257. u32 stat_IfHCInMulticastPkts_lo;
  258. u32 stat_IfHCInBroadcastPkts_hi;
  259. u32 stat_IfHCInBroadcastPkts_lo;
  260. u32 stat_IfHCOutUcastPkts_hi;
  261. u32 stat_IfHCOutUcastPkts_lo;
  262. u32 stat_IfHCOutMulticastPkts_hi;
  263. u32 stat_IfHCOutMulticastPkts_lo;
  264. u32 stat_IfHCOutBroadcastPkts_hi;
  265. u32 stat_IfHCOutBroadcastPkts_lo;
  266. u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
  267. u32 stat_Dot3StatsCarrierSenseErrors;
  268. u32 stat_Dot3StatsFCSErrors;
  269. u32 stat_Dot3StatsAlignmentErrors;
  270. u32 stat_Dot3StatsSingleCollisionFrames;
  271. u32 stat_Dot3StatsMultipleCollisionFrames;
  272. u32 stat_Dot3StatsDeferredTransmissions;
  273. u32 stat_Dot3StatsExcessiveCollisions;
  274. u32 stat_Dot3StatsLateCollisions;
  275. u32 stat_EtherStatsCollisions;
  276. u32 stat_EtherStatsFragments;
  277. u32 stat_EtherStatsJabbers;
  278. u32 stat_EtherStatsUndersizePkts;
  279. u32 stat_EtherStatsOverrsizePkts;
  280. u32 stat_EtherStatsPktsRx64Octets;
  281. u32 stat_EtherStatsPktsRx65Octetsto127Octets;
  282. u32 stat_EtherStatsPktsRx128Octetsto255Octets;
  283. u32 stat_EtherStatsPktsRx256Octetsto511Octets;
  284. u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
  285. u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
  286. u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
  287. u32 stat_EtherStatsPktsTx64Octets;
  288. u32 stat_EtherStatsPktsTx65Octetsto127Octets;
  289. u32 stat_EtherStatsPktsTx128Octetsto255Octets;
  290. u32 stat_EtherStatsPktsTx256Octetsto511Octets;
  291. u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
  292. u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
  293. u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
  294. u32 stat_XonPauseFramesReceived;
  295. u32 stat_XoffPauseFramesReceived;
  296. u32 stat_OutXonSent;
  297. u32 stat_OutXoffSent;
  298. u32 stat_FlowControlDone;
  299. u32 stat_MacControlFramesReceived;
  300. u32 stat_XoffStateEntered;
  301. u32 stat_IfInFramesL2FilterDiscards;
  302. u32 stat_IfInRuleCheckerDiscards;
  303. u32 stat_IfInFTQDiscards;
  304. u32 stat_IfInMBUFDiscards;
  305. u32 stat_IfInRuleCheckerP4Hit;
  306. u32 stat_CatchupInRuleCheckerDiscards;
  307. u32 stat_CatchupInFTQDiscards;
  308. u32 stat_CatchupInMBUFDiscards;
  309. u32 stat_CatchupInRuleCheckerP4Hit;
  310. u32 stat_GenStat00;
  311. u32 stat_GenStat01;
  312. u32 stat_GenStat02;
  313. u32 stat_GenStat03;
  314. u32 stat_GenStat04;
  315. u32 stat_GenStat05;
  316. u32 stat_GenStat06;
  317. u32 stat_GenStat07;
  318. u32 stat_GenStat08;
  319. u32 stat_GenStat09;
  320. u32 stat_GenStat10;
  321. u32 stat_GenStat11;
  322. u32 stat_GenStat12;
  323. u32 stat_GenStat13;
  324. u32 stat_GenStat14;
  325. u32 stat_GenStat15;
  326. };
  327. /*
  328. * l2_fhdr definition
  329. */
  330. struct l2_fhdr {
  331. u32 l2_fhdr_status;
  332. #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
  333. #define L2_FHDR_STATUS_RULE_P2 (1<<3)
  334. #define L2_FHDR_STATUS_RULE_P3 (1<<4)
  335. #define L2_FHDR_STATUS_RULE_P4 (1<<5)
  336. #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
  337. #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
  338. #define L2_FHDR_STATUS_RSS_HASH (1<<8)
  339. #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
  340. #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
  341. #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
  342. #define L2_FHDR_ERRORS_BAD_CRC (1<<17)
  343. #define L2_FHDR_ERRORS_PHY_DECODE (1<<18)
  344. #define L2_FHDR_ERRORS_ALIGNMENT (1<<19)
  345. #define L2_FHDR_ERRORS_TOO_SHORT (1<<20)
  346. #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21)
  347. #define L2_FHDR_ERRORS_TCP_XSUM (1<<28)
  348. #define L2_FHDR_ERRORS_UDP_XSUM (1<<31)
  349. u32 l2_fhdr_hash;
  350. #if __BYTE_ORDER == __BIG_ENDIAN
  351. u16 l2_fhdr_pkt_len;
  352. u16 l2_fhdr_vlan_tag;
  353. u16 l2_fhdr_ip_xsum;
  354. u16 l2_fhdr_tcp_udp_xsum;
  355. #elif __BYTE_ORDER == __LITTLE_ENDIAN
  356. u16 l2_fhdr_vlan_tag;
  357. u16 l2_fhdr_pkt_len;
  358. u16 l2_fhdr_tcp_udp_xsum;
  359. u16 l2_fhdr_ip_xsum;
  360. #endif
  361. };
  362. /*
  363. * l2_context definition
  364. */
  365. #define BNX2_L2CTX_TYPE 0x00000000
  366. #define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
  367. #define BNX2_L2CTX_TYPE_TYPE (0xf<<28)
  368. #define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28)
  369. #define BNX2_L2CTX_TYPE_TYPE_L2 (1<<28)
  370. #define BNX2_L2CTX_TX_HOST_BIDX 0x00000088
  371. #define BNX2_L2CTX_EST_NBD 0x00000088
  372. #define BNX2_L2CTX_CMD_TYPE 0x00000088
  373. #define BNX2_L2CTX_CMD_TYPE_TYPE (0xf<<24)
  374. #define BNX2_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
  375. #define BNX2_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
  376. #define BNX2_L2CTX_TX_HOST_BSEQ 0x00000090
  377. #define BNX2_L2CTX_TSCH_BSEQ 0x00000094
  378. #define BNX2_L2CTX_TBDR_BSEQ 0x00000098
  379. #define BNX2_L2CTX_TBDR_BOFF 0x0000009c
  380. #define BNX2_L2CTX_TBDR_BIDX 0x0000009c
  381. #define BNX2_L2CTX_TBDR_BHADDR_HI 0x000000a0
  382. #define BNX2_L2CTX_TBDR_BHADDR_LO 0x000000a4
  383. #define BNX2_L2CTX_TXP_BOFF 0x000000a8
  384. #define BNX2_L2CTX_TXP_BIDX 0x000000a8
  385. #define BNX2_L2CTX_TXP_BSEQ 0x000000ac
  386. /*
  387. * l2_bd_chain_context definition
  388. */
  389. #define BNX2_L2CTX_BD_PRE_READ 0x00000000
  390. #define BNX2_L2CTX_CTX_SIZE 0x00000000
  391. #define BNX2_L2CTX_CTX_TYPE 0x00000000
  392. #define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
  393. #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
  394. #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
  395. #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
  396. #define BNX2_L2CTX_HOST_BDIDX 0x00000004
  397. #define BNX2_L2CTX_HOST_BSEQ 0x00000008
  398. #define BNX2_L2CTX_NX_BSEQ 0x0000000c
  399. #define BNX2_L2CTX_NX_BDHADDR_HI 0x00000010
  400. #define BNX2_L2CTX_NX_BDHADDR_LO 0x00000014
  401. #define BNX2_L2CTX_NX_BDIDX 0x00000018
  402. /*
  403. * pci_config_l definition
  404. * offset: 0000
  405. */
  406. #define BNX2_PCICFG_MISC_CONFIG 0x00000068
  407. #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
  408. #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
  409. #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
  410. #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
  411. #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
  412. #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
  413. #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
  414. #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
  415. #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
  416. #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
  417. #define BNX2_PCICFG_MISC_STATUS 0x0000006c
  418. #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
  419. #define BNX2_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
  420. #define BNX2_PCICFG_MISC_STATUS_M66EN (1L<<2)
  421. #define BNX2_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
  422. #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4)
  423. #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
  424. #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
  425. #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
  426. #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
  427. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
  428. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
  429. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
  430. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
  431. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
  432. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
  433. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
  434. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
  435. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
  436. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
  437. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
  438. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
  439. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
  440. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
  441. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
  442. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
  443. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
  444. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
  445. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
  446. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
  447. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
  448. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
  449. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
  450. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
  451. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
  452. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
  453. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
  454. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
  455. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
  456. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
  457. #define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078
  458. #define BNX2_PCICFG_REG_WINDOW 0x00000080
  459. #define BNX2_PCICFG_INT_ACK_CMD 0x00000084
  460. #define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
  461. #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
  462. #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
  463. #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
  464. #define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088
  465. #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
  466. #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
  467. #define BNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
  468. /*
  469. * pci_reg definition
  470. * offset: 0x400
  471. */
  472. #define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400
  473. #define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8)
  474. #define BNX2_PCI_CONFIG_1 0x00000404
  475. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
  476. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
  477. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
  478. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
  479. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
  480. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
  481. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
  482. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
  483. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
  484. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11)
  485. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
  486. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
  487. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
  488. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
  489. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
  490. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
  491. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
  492. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
  493. #define BNX2_PCI_CONFIG_2 0x00000408
  494. #define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
  495. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
  496. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
  497. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
  498. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
  499. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
  500. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
  501. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
  502. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
  503. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
  504. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
  505. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
  506. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
  507. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
  508. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
  509. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
  510. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
  511. #define BNX2_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
  512. #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
  513. #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
  514. #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
  515. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
  516. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
  517. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
  518. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
  519. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
  520. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
  521. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
  522. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
  523. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
  524. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
  525. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
  526. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
  527. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
  528. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
  529. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
  530. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
  531. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
  532. #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16)
  533. #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21)
  534. #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
  535. #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
  536. #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
  537. #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
  538. #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
  539. #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
  540. #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
  541. #define BNX2_PCI_CONFIG_3 0x0000040c
  542. #define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
  543. #define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24)
  544. #define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25)
  545. #define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26)
  546. #define BNX2_PCI_CONFIG_3_PM_STATE (0x3L<<27)
  547. #define BNX2_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
  548. #define BNX2_PCI_CONFIG_3_PCI_POWER (1L<<31)
  549. #define BNX2_PCI_PM_DATA_A 0x00000410
  550. #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0)
  551. #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8)
  552. #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16)
  553. #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24)
  554. #define BNX2_PCI_PM_DATA_B 0x00000414
  555. #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0)
  556. #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8)
  557. #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16)
  558. #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24)
  559. #define BNX2_PCI_SWAP_DIAG0 0x00000418
  560. #define BNX2_PCI_SWAP_DIAG1 0x0000041c
  561. #define BNX2_PCI_EXP_ROM_ADDR 0x00000420
  562. #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2)
  563. #define BNX2_PCI_EXP_ROM_ADDR_REQ (1L<<31)
  564. #define BNX2_PCI_EXP_ROM_DATA 0x00000424
  565. #define BNX2_PCI_VPD_INTF 0x00000428
  566. #define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0)
  567. #define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c
  568. #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2)
  569. #define BNX2_PCI_VPD_ADDR_FLAG_WR (1<<15)
  570. #define BNX2_PCI_VPD_DATA 0x00000430
  571. #define BNX2_PCI_ID_VAL1 0x00000434
  572. #define BNX2_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0)
  573. #define BNX2_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16)
  574. #define BNX2_PCI_ID_VAL2 0x00000438
  575. #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0)
  576. #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16)
  577. #define BNX2_PCI_ID_VAL3 0x0000043c
  578. #define BNX2_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0)
  579. #define BNX2_PCI_ID_VAL3_REVISION_ID (0xffL<<24)
  580. #define BNX2_PCI_ID_VAL4 0x00000440
  581. #define BNX2_PCI_ID_VAL4_CAP_ENA (0xfL<<0)
  582. #define BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
  583. #define BNX2_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
  584. #define BNX2_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
  585. #define BNX2_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
  586. #define BNX2_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
  587. #define BNX2_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
  588. #define BNX2_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
  589. #define BNX2_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
  590. #define BNX2_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
  591. #define BNX2_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
  592. #define BNX2_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
  593. #define BNX2_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
  594. #define BNX2_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
  595. #define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
  596. #define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
  597. #define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
  598. #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
  599. #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
  600. #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
  601. #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
  602. #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
  603. #define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
  604. #define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12)
  605. #define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
  606. #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
  607. #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
  608. #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21)
  609. #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23)
  610. #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26)
  611. #define BNX2_PCI_ID_VAL5 0x00000444
  612. #define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
  613. #define BNX2_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
  614. #define BNX2_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
  615. #define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
  616. #define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
  617. #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
  618. #define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448
  619. #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
  620. #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
  621. #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16)
  622. #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24)
  623. #define BNX2_PCI_ID_VAL6 0x0000044c
  624. #define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
  625. #define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
  626. #define BNX2_PCI_ID_VAL6_BIST (0xffL<<16)
  627. #define BNX2_PCI_MSI_DATA 0x00000450
  628. #define BNX2_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0)
  629. #define BNX2_PCI_MSI_ADDR_H 0x00000454
  630. #define BNX2_PCI_MSI_ADDR_L 0x00000458
  631. /*
  632. * misc_reg definition
  633. * offset: 0x800
  634. */
  635. #define BNX2_MISC_COMMAND 0x00000800
  636. #define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0)
  637. #define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1)
  638. #define BNX2_MISC_COMMAND_CORE_RESET (1L<<4)
  639. #define BNX2_MISC_COMMAND_HARD_RESET (1L<<5)
  640. #define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8)
  641. #define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
  642. #define BNX2_MISC_CFG 0x00000804
  643. #define BNX2_MISC_CFG_PCI_GRC_TMOUT (1L<<0)
  644. #define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1)
  645. #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
  646. #define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
  647. #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
  648. #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
  649. #define BNX2_MISC_CFG_BIST_EN (1L<<3)
  650. #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
  651. #define BNX2_MISC_CFG_BYPASS_BSCAN (1L<<5)
  652. #define BNX2_MISC_CFG_BYPASS_EJTAG (1L<<6)
  653. #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
  654. #define BNX2_MISC_CFG_LEDMODE (0x3L<<8)
  655. #define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8)
  656. #define BNX2_MISC_CFG_LEDMODE_GPHY1 (1L<<8)
  657. #define BNX2_MISC_CFG_LEDMODE_GPHY2 (2L<<8)
  658. #define BNX2_MISC_ID 0x00000808
  659. #define BNX2_MISC_ID_BOND_ID (0xfL<<0)
  660. #define BNX2_MISC_ID_CHIP_METAL (0xffL<<4)
  661. #define BNX2_MISC_ID_CHIP_REV (0xfL<<12)
  662. #define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16)
  663. #define BNX2_MISC_ENABLE_STATUS_BITS 0x0000080c
  664. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
  665. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
  666. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
  667. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
  668. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
  669. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
  670. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
  671. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
  672. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
  673. #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
  674. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
  675. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
  676. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
  677. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
  678. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
  679. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
  680. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
  681. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
  682. #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
  683. #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
  684. #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
  685. #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
  686. #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
  687. #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
  688. #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
  689. #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
  690. #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
  691. #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
  692. #define BNX2_MISC_ENABLE_SET_BITS 0x00000810
  693. #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
  694. #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
  695. #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
  696. #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
  697. #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
  698. #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
  699. #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
  700. #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
  701. #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
  702. #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
  703. #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
  704. #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
  705. #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
  706. #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
  707. #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
  708. #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
  709. #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
  710. #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
  711. #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
  712. #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
  713. #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
  714. #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
  715. #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
  716. #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
  717. #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
  718. #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
  719. #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
  720. #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
  721. #define BNX2_MISC_ENABLE_CLR_BITS 0x00000814
  722. #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
  723. #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
  724. #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
  725. #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
  726. #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
  727. #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
  728. #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
  729. #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
  730. #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
  731. #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
  732. #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
  733. #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
  734. #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
  735. #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
  736. #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
  737. #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
  738. #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
  739. #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
  740. #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
  741. #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
  742. #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
  743. #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
  744. #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
  745. #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
  746. #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
  747. #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
  748. #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
  749. #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
  750. #define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818
  751. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
  752. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
  753. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
  754. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
  755. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
  756. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
  757. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
  758. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
  759. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
  760. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
  761. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
  762. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
  763. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
  764. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
  765. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
  766. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
  767. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
  768. #define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
  769. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
  770. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
  771. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
  772. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
  773. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
  774. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
  775. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
  776. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
  777. #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
  778. #define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
  779. #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
  780. #define BNX2_MISC_GPIO 0x0000081c
  781. #define BNX2_MISC_GPIO_VALUE (0xffL<<0)
  782. #define BNX2_MISC_GPIO_SET (0xffL<<8)
  783. #define BNX2_MISC_GPIO_CLR (0xffL<<16)
  784. #define BNX2_MISC_GPIO_FLOAT (0xffL<<24)
  785. #define BNX2_MISC_GPIO_INT 0x00000820
  786. #define BNX2_MISC_GPIO_INT_INT_STATE (0xfL<<0)
  787. #define BNX2_MISC_GPIO_INT_OLD_VALUE (0xfL<<8)
  788. #define BNX2_MISC_GPIO_INT_OLD_SET (0xfL<<16)
  789. #define BNX2_MISC_GPIO_INT_OLD_CLR (0xfL<<24)
  790. #define BNX2_MISC_CONFIG_LFSR 0x00000824
  791. #define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
  792. #define BNX2_MISC_LFSR_MASK_BITS 0x00000828
  793. #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
  794. #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
  795. #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
  796. #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
  797. #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
  798. #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
  799. #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
  800. #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
  801. #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
  802. #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
  803. #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
  804. #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
  805. #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
  806. #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
  807. #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
  808. #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
  809. #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
  810. #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
  811. #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
  812. #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
  813. #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
  814. #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
  815. #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
  816. #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
  817. #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
  818. #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
  819. #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
  820. #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
  821. #define BNX2_MISC_ARB_REQ0 0x0000082c
  822. #define BNX2_MISC_ARB_REQ1 0x00000830
  823. #define BNX2_MISC_ARB_REQ2 0x00000834
  824. #define BNX2_MISC_ARB_REQ3 0x00000838
  825. #define BNX2_MISC_ARB_REQ4 0x0000083c
  826. #define BNX2_MISC_ARB_FREE0 0x00000840
  827. #define BNX2_MISC_ARB_FREE1 0x00000844
  828. #define BNX2_MISC_ARB_FREE2 0x00000848
  829. #define BNX2_MISC_ARB_FREE3 0x0000084c
  830. #define BNX2_MISC_ARB_FREE4 0x00000850
  831. #define BNX2_MISC_ARB_REQ_STATUS0 0x00000854
  832. #define BNX2_MISC_ARB_REQ_STATUS1 0x00000858
  833. #define BNX2_MISC_ARB_REQ_STATUS2 0x0000085c
  834. #define BNX2_MISC_ARB_REQ_STATUS3 0x00000860
  835. #define BNX2_MISC_ARB_REQ_STATUS4 0x00000864
  836. #define BNX2_MISC_ARB_GNT0 0x00000868
  837. #define BNX2_MISC_ARB_GNT0_0 (0x7L<<0)
  838. #define BNX2_MISC_ARB_GNT0_1 (0x7L<<4)
  839. #define BNX2_MISC_ARB_GNT0_2 (0x7L<<8)
  840. #define BNX2_MISC_ARB_GNT0_3 (0x7L<<12)
  841. #define BNX2_MISC_ARB_GNT0_4 (0x7L<<16)
  842. #define BNX2_MISC_ARB_GNT0_5 (0x7L<<20)
  843. #define BNX2_MISC_ARB_GNT0_6 (0x7L<<24)
  844. #define BNX2_MISC_ARB_GNT0_7 (0x7L<<28)
  845. #define BNX2_MISC_ARB_GNT1 0x0000086c
  846. #define BNX2_MISC_ARB_GNT1_8 (0x7L<<0)
  847. #define BNX2_MISC_ARB_GNT1_9 (0x7L<<4)
  848. #define BNX2_MISC_ARB_GNT1_10 (0x7L<<8)
  849. #define BNX2_MISC_ARB_GNT1_11 (0x7L<<12)
  850. #define BNX2_MISC_ARB_GNT1_12 (0x7L<<16)
  851. #define BNX2_MISC_ARB_GNT1_13 (0x7L<<20)
  852. #define BNX2_MISC_ARB_GNT1_14 (0x7L<<24)
  853. #define BNX2_MISC_ARB_GNT1_15 (0x7L<<28)
  854. #define BNX2_MISC_ARB_GNT2 0x00000870
  855. #define BNX2_MISC_ARB_GNT2_16 (0x7L<<0)
  856. #define BNX2_MISC_ARB_GNT2_17 (0x7L<<4)
  857. #define BNX2_MISC_ARB_GNT2_18 (0x7L<<8)
  858. #define BNX2_MISC_ARB_GNT2_19 (0x7L<<12)
  859. #define BNX2_MISC_ARB_GNT2_20 (0x7L<<16)
  860. #define BNX2_MISC_ARB_GNT2_21 (0x7L<<20)
  861. #define BNX2_MISC_ARB_GNT2_22 (0x7L<<24)
  862. #define BNX2_MISC_ARB_GNT2_23 (0x7L<<28)
  863. #define BNX2_MISC_ARB_GNT3 0x00000874
  864. #define BNX2_MISC_ARB_GNT3_24 (0x7L<<0)
  865. #define BNX2_MISC_ARB_GNT3_25 (0x7L<<4)
  866. #define BNX2_MISC_ARB_GNT3_26 (0x7L<<8)
  867. #define BNX2_MISC_ARB_GNT3_27 (0x7L<<12)
  868. #define BNX2_MISC_ARB_GNT3_28 (0x7L<<16)
  869. #define BNX2_MISC_ARB_GNT3_29 (0x7L<<20)
  870. #define BNX2_MISC_ARB_GNT3_30 (0x7L<<24)
  871. #define BNX2_MISC_ARB_GNT3_31 (0x7L<<28)
  872. #define BNX2_MISC_PRBS_CONTROL 0x00000878
  873. #define BNX2_MISC_PRBS_CONTROL_EN (1L<<0)
  874. #define BNX2_MISC_PRBS_CONTROL_RSTB (1L<<1)
  875. #define BNX2_MISC_PRBS_CONTROL_INV (1L<<2)
  876. #define BNX2_MISC_PRBS_CONTROL_ERR_CLR (1L<<3)
  877. #define BNX2_MISC_PRBS_CONTROL_ORDER (0x3L<<4)
  878. #define BNX2_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4)
  879. #define BNX2_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4)
  880. #define BNX2_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4)
  881. #define BNX2_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4)
  882. #define BNX2_MISC_PRBS_STATUS 0x0000087c
  883. #define BNX2_MISC_PRBS_STATUS_LOCK (1L<<0)
  884. #define BNX2_MISC_PRBS_STATUS_STKY (1L<<1)
  885. #define BNX2_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2)
  886. #define BNX2_MISC_PRBS_STATUS_STATE (0xfL<<16)
  887. #define BNX2_MISC_SM_ASF_CONTROL 0x00000880
  888. #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
  889. #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
  890. #define BNX2_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
  891. #define BNX2_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
  892. #define BNX2_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
  893. #define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
  894. #define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
  895. #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
  896. #define BNX2_MISC_SM_ASF_CONTROL_RES (0xfL<<8)
  897. #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
  898. #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
  899. #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
  900. #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
  901. #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16)
  902. #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24)
  903. #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
  904. #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
  905. #define BNX2_MISC_SMB_IN 0x00000884
  906. #define BNX2_MISC_SMB_IN_DAT_IN (0xffL<<0)
  907. #define BNX2_MISC_SMB_IN_RDY (1L<<8)
  908. #define BNX2_MISC_SMB_IN_DONE (1L<<9)
  909. #define BNX2_MISC_SMB_IN_FIRSTBYTE (1L<<10)
  910. #define BNX2_MISC_SMB_IN_STATUS (0x7L<<11)
  911. #define BNX2_MISC_SMB_IN_STATUS_OK (0x0L<<11)
  912. #define BNX2_MISC_SMB_IN_STATUS_PEC (0x1L<<11)
  913. #define BNX2_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11)
  914. #define BNX2_MISC_SMB_IN_STATUS_STOP (0x3L<<11)
  915. #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11)
  916. #define BNX2_MISC_SMB_OUT 0x00000888
  917. #define BNX2_MISC_SMB_OUT_DAT_OUT (0xffL<<0)
  918. #define BNX2_MISC_SMB_OUT_RDY (1L<<8)
  919. #define BNX2_MISC_SMB_OUT_START (1L<<9)
  920. #define BNX2_MISC_SMB_OUT_LAST (1L<<10)
  921. #define BNX2_MISC_SMB_OUT_ACC_TYPE (1L<<11)
  922. #define BNX2_MISC_SMB_OUT_ENB_PEC (1L<<12)
  923. #define BNX2_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
  924. #define BNX2_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
  925. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
  926. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
  927. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
  928. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
  929. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
  930. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
  931. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
  932. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
  933. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
  934. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20)
  935. #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
  936. #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
  937. #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
  938. #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
  939. #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
  940. #define BNX2_MISC_SMB_WATCHDOG 0x0000088c
  941. #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)
  942. #define BNX2_MISC_SMB_HEARTBEAT 0x00000890
  943. #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0)
  944. #define BNX2_MISC_SMB_POLL_ASF 0x00000894
  945. #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0)
  946. #define BNX2_MISC_SMB_POLL_LEGACY 0x00000898
  947. #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
  948. #define BNX2_MISC_SMB_RETRAN 0x0000089c
  949. #define BNX2_MISC_SMB_RETRAN_RETRAN (0xffL<<0)
  950. #define BNX2_MISC_SMB_TIMESTAMP 0x000008a0
  951. #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
  952. #define BNX2_MISC_PERR_ENA0 0x000008a4
  953. #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
  954. #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
  955. #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
  956. #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
  957. #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
  958. #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
  959. #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
  960. #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
  961. #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
  962. #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
  963. #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
  964. #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
  965. #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
  966. #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
  967. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
  968. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
  969. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
  970. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
  971. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
  972. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
  973. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
  974. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
  975. #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
  976. #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
  977. #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
  978. #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
  979. #define BNX2_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
  980. #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
  981. #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
  982. #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
  983. #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
  984. #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
  985. #define BNX2_MISC_PERR_ENA1 0x000008a8
  986. #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
  987. #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
  988. #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
  989. #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
  990. #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
  991. #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
  992. #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
  993. #define BNX2_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
  994. #define BNX2_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
  995. #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
  996. #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
  997. #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
  998. #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
  999. #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
  1000. #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
  1001. #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
  1002. #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
  1003. #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
  1004. #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
  1005. #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
  1006. #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
  1007. #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
  1008. #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
  1009. #define BNX2_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
  1010. #define BNX2_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
  1011. #define BNX2_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
  1012. #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
  1013. #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
  1014. #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
  1015. #define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
  1016. #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
  1017. #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
  1018. #define BNX2_MISC_PERR_ENA2 0x000008ac
  1019. #define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
  1020. #define BNX2_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
  1021. #define BNX2_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
  1022. #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
  1023. #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
  1024. #define BNX2_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
  1025. #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
  1026. #define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
  1027. #define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
  1028. #define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0
  1029. #define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
  1030. #define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
  1031. #define BNX2_MISC_VREG_CONTROL 0x000008b4
  1032. #define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0)
  1033. #define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4)
  1034. #define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8
  1035. #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
  1036. #define BNX2_MISC_UNUSED0 0x000008bc
  1037. /*
  1038. * nvm_reg definition
  1039. * offset: 0x6400
  1040. */
  1041. #define BNX2_NVM_COMMAND 0x00006400
  1042. #define BNX2_NVM_COMMAND_RST (1L<<0)
  1043. #define BNX2_NVM_COMMAND_DONE (1L<<3)
  1044. #define BNX2_NVM_COMMAND_DOIT (1L<<4)
  1045. #define BNX2_NVM_COMMAND_WR (1L<<5)
  1046. #define BNX2_NVM_COMMAND_ERASE (1L<<6)
  1047. #define BNX2_NVM_COMMAND_FIRST (1L<<7)
  1048. #define BNX2_NVM_COMMAND_LAST (1L<<8)
  1049. #define BNX2_NVM_COMMAND_WREN (1L<<16)
  1050. #define BNX2_NVM_COMMAND_WRDI (1L<<17)
  1051. #define BNX2_NVM_COMMAND_EWSR (1L<<18)
  1052. #define BNX2_NVM_COMMAND_WRSR (1L<<19)
  1053. #define BNX2_NVM_STATUS 0x00006404
  1054. #define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
  1055. #define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
  1056. #define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
  1057. #define BNX2_NVM_WRITE 0x00006408
  1058. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
  1059. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
  1060. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
  1061. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
  1062. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
  1063. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
  1064. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
  1065. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
  1066. #define BNX2_NVM_ADDR 0x0000640c
  1067. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
  1068. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
  1069. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
  1070. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
  1071. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
  1072. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
  1073. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
  1074. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
  1075. #define BNX2_NVM_READ 0x00006410
  1076. #define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
  1077. #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
  1078. #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
  1079. #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
  1080. #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
  1081. #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
  1082. #define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
  1083. #define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
  1084. #define BNX2_NVM_CFG1 0x00006414
  1085. #define BNX2_NVM_CFG1_FLASH_MODE (1L<<0)
  1086. #define BNX2_NVM_CFG1_BUFFER_MODE (1L<<1)
  1087. #define BNX2_NVM_CFG1_PASS_MODE (1L<<2)
  1088. #define BNX2_NVM_CFG1_BITBANG_MODE (1L<<3)
  1089. #define BNX2_NVM_CFG1_STATUS_BIT (0x7L<<4)
  1090. #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
  1091. #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
  1092. #define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
  1093. #define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
  1094. #define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24)
  1095. #define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25)
  1096. #define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
  1097. #define BNX2_NVM_CFG2 0x00006418
  1098. #define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0)
  1099. #define BNX2_NVM_CFG2_DUMMY (0xffL<<8)
  1100. #define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16)
  1101. #define BNX2_NVM_CFG3 0x0000641c
  1102. #define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
  1103. #define BNX2_NVM_CFG3_WRITE_CMD (0xffL<<8)
  1104. #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
  1105. #define BNX2_NVM_CFG3_READ_CMD (0xffL<<24)
  1106. #define BNX2_NVM_SW_ARB 0x00006420
  1107. #define BNX2_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
  1108. #define BNX2_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
  1109. #define BNX2_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
  1110. #define BNX2_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
  1111. #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
  1112. #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
  1113. #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
  1114. #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
  1115. #define BNX2_NVM_SW_ARB_ARB_ARB0 (1L<<8)
  1116. #define BNX2_NVM_SW_ARB_ARB_ARB1 (1L<<9)
  1117. #define BNX2_NVM_SW_ARB_ARB_ARB2 (1L<<10)
  1118. #define BNX2_NVM_SW_ARB_ARB_ARB3 (1L<<11)
  1119. #define BNX2_NVM_SW_ARB_REQ0 (1L<<12)
  1120. #define BNX2_NVM_SW_ARB_REQ1 (1L<<13)
  1121. #define BNX2_NVM_SW_ARB_REQ2 (1L<<14)
  1122. #define BNX2_NVM_SW_ARB_REQ3 (1L<<15)
  1123. #define BNX2_NVM_ACCESS_ENABLE 0x00006424
  1124. #define BNX2_NVM_ACCESS_ENABLE_EN (1L<<0)
  1125. #define BNX2_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
  1126. #define BNX2_NVM_WRITE1 0x00006428
  1127. #define BNX2_NVM_WRITE1_WREN_CMD (0xffL<<0)
  1128. #define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8)
  1129. #define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16)
  1130. /*
  1131. * dma_reg definition
  1132. * offset: 0xc00
  1133. */
  1134. #define BNX2_DMA_COMMAND 0x00000c00
  1135. #define BNX2_DMA_COMMAND_ENABLE (1L<<0)
  1136. #define BNX2_DMA_STATUS 0x00000c04
  1137. #define BNX2_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
  1138. #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
  1139. #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
  1140. #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
  1141. #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
  1142. #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
  1143. #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
  1144. #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
  1145. #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
  1146. #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
  1147. #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
  1148. #define BNX2_DMA_CONFIG 0x00000c08
  1149. #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
  1150. #define BNX2_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
  1151. #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
  1152. #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
  1153. #define BNX2_DMA_CONFIG_ONE_DMA (1L<<6)
  1154. #define BNX2_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
  1155. #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
  1156. #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
  1157. #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
  1158. #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12)
  1159. #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16)
  1160. #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20)
  1161. #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
  1162. #define BNX2_DMA_CONFIG_BIG_SIZE (0xfL<<24)
  1163. #define BNX2_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24)
  1164. #define BNX2_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24)
  1165. #define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
  1166. #define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
  1167. #define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
  1168. #define BNX2_DMA_BLACKOUT 0x00000c0c
  1169. #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
  1170. #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
  1171. #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
  1172. #define BNX2_DMA_RCHAN_STAT 0x00000c30
  1173. #define BNX2_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0)
  1174. #define BNX2_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3)
  1175. #define BNX2_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4)
  1176. #define BNX2_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7)
  1177. #define BNX2_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8)
  1178. #define BNX2_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11)
  1179. #define BNX2_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12)
  1180. #define BNX2_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15)
  1181. #define BNX2_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16)
  1182. #define BNX2_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19)
  1183. #define BNX2_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20)
  1184. #define BNX2_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23)
  1185. #define BNX2_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24)
  1186. #define BNX2_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27)
  1187. #define BNX2_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28)
  1188. #define BNX2_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31)
  1189. #define BNX2_DMA_WCHAN_STAT 0x00000c34
  1190. #define BNX2_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0)
  1191. #define BNX2_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3)
  1192. #define BNX2_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4)
  1193. #define BNX2_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7)
  1194. #define BNX2_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8)
  1195. #define BNX2_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11)
  1196. #define BNX2_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12)
  1197. #define BNX2_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15)
  1198. #define BNX2_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16)
  1199. #define BNX2_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19)
  1200. #define BNX2_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20)
  1201. #define BNX2_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23)
  1202. #define BNX2_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24)
  1203. #define BNX2_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27)
  1204. #define BNX2_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28)
  1205. #define BNX2_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31)
  1206. #define BNX2_DMA_RCHAN_ASSIGNMENT 0x00000c38
  1207. #define BNX2_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0)
  1208. #define BNX2_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4)
  1209. #define BNX2_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8)
  1210. #define BNX2_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12)
  1211. #define BNX2_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16)
  1212. #define BNX2_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20)
  1213. #define BNX2_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24)
  1214. #define BNX2_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28)
  1215. #define BNX2_DMA_WCHAN_ASSIGNMENT 0x00000c3c
  1216. #define BNX2_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0)
  1217. #define BNX2_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4)
  1218. #define BNX2_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8)
  1219. #define BNX2_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12)
  1220. #define BNX2_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16)
  1221. #define BNX2_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20)
  1222. #define BNX2_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24)
  1223. #define BNX2_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28)
  1224. #define BNX2_DMA_RCHAN_STAT_00 0x00000c40
  1225. #define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
  1226. #define BNX2_DMA_RCHAN_STAT_01 0x00000c44
  1227. #define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
  1228. #define BNX2_DMA_RCHAN_STAT_02 0x00000c48
  1229. #define BNX2_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0)
  1230. #define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16)
  1231. #define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17)
  1232. #define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18)
  1233. #define BNX2_DMA_RCHAN_STAT_10 0x00000c4c
  1234. #define BNX2_DMA_RCHAN_STAT_11 0x00000c50
  1235. #define BNX2_DMA_RCHAN_STAT_12 0x00000c54
  1236. #define BNX2_DMA_RCHAN_STAT_20 0x00000c58
  1237. #define BNX2_DMA_RCHAN_STAT_21 0x00000c5c
  1238. #define BNX2_DMA_RCHAN_STAT_22 0x00000c60
  1239. #define BNX2_DMA_RCHAN_STAT_30 0x00000c64
  1240. #define BNX2_DMA_RCHAN_STAT_31 0x00000c68
  1241. #define BNX2_DMA_RCHAN_STAT_32 0x00000c6c
  1242. #define BNX2_DMA_RCHAN_STAT_40 0x00000c70
  1243. #define BNX2_DMA_RCHAN_STAT_41 0x00000c74
  1244. #define BNX2_DMA_RCHAN_STAT_42 0x00000c78
  1245. #define BNX2_DMA_RCHAN_STAT_50 0x00000c7c
  1246. #define BNX2_DMA_RCHAN_STAT_51 0x00000c80
  1247. #define BNX2_DMA_RCHAN_STAT_52 0x00000c84
  1248. #define BNX2_DMA_RCHAN_STAT_60 0x00000c88
  1249. #define BNX2_DMA_RCHAN_STAT_61 0x00000c8c
  1250. #define BNX2_DMA_RCHAN_STAT_62 0x00000c90
  1251. #define BNX2_DMA_RCHAN_STAT_70 0x00000c94
  1252. #define BNX2_DMA_RCHAN_STAT_71 0x00000c98
  1253. #define BNX2_DMA_RCHAN_STAT_72 0x00000c9c
  1254. #define BNX2_DMA_WCHAN_STAT_00 0x00000ca0
  1255. #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
  1256. #define BNX2_DMA_WCHAN_STAT_01 0x00000ca4
  1257. #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
  1258. #define BNX2_DMA_WCHAN_STAT_02 0x00000ca8
  1259. #define BNX2_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0)
  1260. #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
  1261. #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
  1262. #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
  1263. #define BNX2_DMA_WCHAN_STAT_10 0x00000cac
  1264. #define BNX2_DMA_WCHAN_STAT_11 0x00000cb0
  1265. #define BNX2_DMA_WCHAN_STAT_12 0x00000cb4
  1266. #define BNX2_DMA_WCHAN_STAT_20 0x00000cb8
  1267. #define BNX2_DMA_WCHAN_STAT_21 0x00000cbc
  1268. #define BNX2_DMA_WCHAN_STAT_22 0x00000cc0
  1269. #define BNX2_DMA_WCHAN_STAT_30 0x00000cc4
  1270. #define BNX2_DMA_WCHAN_STAT_31 0x00000cc8
  1271. #define BNX2_DMA_WCHAN_STAT_32 0x00000ccc
  1272. #define BNX2_DMA_WCHAN_STAT_40 0x00000cd0
  1273. #define BNX2_DMA_WCHAN_STAT_41 0x00000cd4
  1274. #define BNX2_DMA_WCHAN_STAT_42 0x00000cd8
  1275. #define BNX2_DMA_WCHAN_STAT_50 0x00000cdc
  1276. #define BNX2_DMA_WCHAN_STAT_51 0x00000ce0
  1277. #define BNX2_DMA_WCHAN_STAT_52 0x00000ce4
  1278. #define BNX2_DMA_WCHAN_STAT_60 0x00000ce8
  1279. #define BNX2_DMA_WCHAN_STAT_61 0x00000cec
  1280. #define BNX2_DMA_WCHAN_STAT_62 0x00000cf0
  1281. #define BNX2_DMA_WCHAN_STAT_70 0x00000cf4
  1282. #define BNX2_DMA_WCHAN_STAT_71 0x00000cf8
  1283. #define BNX2_DMA_WCHAN_STAT_72 0x00000cfc
  1284. #define BNX2_DMA_ARB_STAT_00 0x00000d00
  1285. #define BNX2_DMA_ARB_STAT_00_MASTER (0xffffL<<0)
  1286. #define BNX2_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16)
  1287. #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24)
  1288. #define BNX2_DMA_ARB_STAT_01 0x00000d04
  1289. #define BNX2_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0)
  1290. #define BNX2_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4)
  1291. #define BNX2_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8)
  1292. #define BNX2_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12)
  1293. #define BNX2_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16)
  1294. #define BNX2_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20)
  1295. #define BNX2_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24)
  1296. #define BNX2_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28)
  1297. #define BNX2_DMA_FUSE_CTRL0_CMD 0x00000f00
  1298. #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
  1299. #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
  1300. #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
  1301. #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
  1302. #define BNX2_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8)
  1303. #define BNX2_DMA_FUSE_CTRL0_DATA 0x00000f04
  1304. #define BNX2_DMA_FUSE_CTRL1_CMD 0x00000f08
  1305. #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
  1306. #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
  1307. #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
  1308. #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
  1309. #define BNX2_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8)
  1310. #define BNX2_DMA_FUSE_CTRL1_DATA 0x00000f0c
  1311. #define BNX2_DMA_FUSE_CTRL2_CMD 0x00000f10
  1312. #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
  1313. #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
  1314. #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
  1315. #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
  1316. #define BNX2_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8)
  1317. #define BNX2_DMA_FUSE_CTRL2_DATA 0x00000f14
  1318. /*
  1319. * context_reg definition
  1320. * offset: 0x1000
  1321. */
  1322. #define BNX2_CTX_COMMAND 0x00001000
  1323. #define BNX2_CTX_COMMAND_ENABLED (1L<<0)
  1324. #define BNX2_CTX_STATUS 0x00001004
  1325. #define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0)
  1326. #define BNX2_CTX_STATUS_READ_STAT (1L<<16)
  1327. #define BNX2_CTX_STATUS_WRITE_STAT (1L<<17)
  1328. #define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18)
  1329. #define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
  1330. #define BNX2_CTX_VIRT_ADDR 0x00001008
  1331. #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
  1332. #define BNX2_CTX_PAGE_TBL 0x0000100c
  1333. #define BNX2_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
  1334. #define BNX2_CTX_DATA_ADR 0x00001010
  1335. #define BNX2_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
  1336. #define BNX2_CTX_DATA 0x00001014
  1337. #define BNX2_CTX_LOCK 0x00001018
  1338. #define BNX2_CTX_LOCK_TYPE (0x7L<<0)
  1339. #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
  1340. #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
  1341. #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
  1342. #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
  1343. #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
  1344. #define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7)
  1345. #define BNX2_CTX_LOCK_GRANTED (1L<<26)
  1346. #define BNX2_CTX_LOCK_MODE (0x7L<<27)
  1347. #define BNX2_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
  1348. #define BNX2_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
  1349. #define BNX2_CTX_LOCK_MODE_SURE (0x2L<<27)
  1350. #define BNX2_CTX_LOCK_STATUS (1L<<30)
  1351. #define BNX2_CTX_LOCK_REQ (1L<<31)
  1352. #define BNX2_CTX_ACCESS_STATUS 0x00001040
  1353. #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
  1354. #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
  1355. #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
  1356. #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
  1357. #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
  1358. #define BNX2_CTX_DBG_LOCK_STATUS 0x00001044
  1359. #define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
  1360. #define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
  1361. #define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080
  1362. #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
  1363. #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
  1364. #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
  1365. #define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084
  1366. #define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088
  1367. #define BNX2_CTX_CHNL_LOCK_STATUS_3 0x0000108c
  1368. #define BNX2_CTX_CHNL_LOCK_STATUS_4 0x00001090
  1369. #define BNX2_CTX_CHNL_LOCK_STATUS_5 0x00001094
  1370. #define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098
  1371. #define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c
  1372. #define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0
  1373. /*
  1374. * emac_reg definition
  1375. * offset: 0x1400
  1376. */
  1377. #define BNX2_EMAC_MODE 0x00001400
  1378. #define BNX2_EMAC_MODE_RESET (1L<<0)
  1379. #define BNX2_EMAC_MODE_HALF_DUPLEX (1L<<1)
  1380. #define BNX2_EMAC_MODE_PORT (0x3L<<2)
  1381. #define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
  1382. #define BNX2_EMAC_MODE_PORT_MII (1L<<2)
  1383. #define BNX2_EMAC_MODE_PORT_GMII (2L<<2)
  1384. #define BNX2_EMAC_MODE_PORT_MII_10 (3L<<2)
  1385. #define BNX2_EMAC_MODE_MAC_LOOP (1L<<4)
  1386. #define BNX2_EMAC_MODE_25G (1L<<5)
  1387. #define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
  1388. #define BNX2_EMAC_MODE_TX_BURST (1L<<8)
  1389. #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
  1390. #define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10)
  1391. #define BNX2_EMAC_MODE_FORCE_LINK (1L<<11)
  1392. #define BNX2_EMAC_MODE_MPKT (1L<<18)
  1393. #define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19)
  1394. #define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20)
  1395. #define BNX2_EMAC_STATUS 0x00001404
  1396. #define BNX2_EMAC_STATUS_LINK (1L<<11)
  1397. #define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12)
  1398. #define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22)
  1399. #define BNX2_EMAC_STATUS_MI_INT (1L<<23)
  1400. #define BNX2_EMAC_STATUS_AP_ERROR (1L<<24)
  1401. #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
  1402. #define BNX2_EMAC_ATTENTION_ENA 0x00001408
  1403. #define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11)
  1404. #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
  1405. #define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
  1406. #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
  1407. #define BNX2_EMAC_LED 0x0000140c
  1408. #define BNX2_EMAC_LED_OVERRIDE (1L<<0)
  1409. #define BNX2_EMAC_LED_1000MB_OVERRIDE (1L<<1)
  1410. #define BNX2_EMAC_LED_100MB_OVERRIDE (1L<<2)
  1411. #define BNX2_EMAC_LED_10MB_OVERRIDE (1L<<3)
  1412. #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
  1413. #define BNX2_EMAC_LED_BLNK_TRAFFIC (1L<<5)
  1414. #define BNX2_EMAC_LED_TRAFFIC (1L<<6)
  1415. #define BNX2_EMAC_LED_1000MB (1L<<7)
  1416. #define BNX2_EMAC_LED_100MB (1L<<8)
  1417. #define BNX2_EMAC_LED_10MB (1L<<9)
  1418. #define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10)
  1419. #define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19)
  1420. #define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31)
  1421. #define BNX2_EMAC_MAC_MATCH0 0x00001410
  1422. #define BNX2_EMAC_MAC_MATCH1 0x00001414
  1423. #define BNX2_EMAC_MAC_MATCH2 0x00001418
  1424. #define BNX2_EMAC_MAC_MATCH3 0x0000141c
  1425. #define BNX2_EMAC_MAC_MATCH4 0x00001420
  1426. #define BNX2_EMAC_MAC_MATCH5 0x00001424
  1427. #define BNX2_EMAC_MAC_MATCH6 0x00001428
  1428. #define BNX2_EMAC_MAC_MATCH7 0x0000142c
  1429. #define BNX2_EMAC_MAC_MATCH8 0x00001430
  1430. #define BNX2_EMAC_MAC_MATCH9 0x00001434
  1431. #define BNX2_EMAC_MAC_MATCH10 0x00001438
  1432. #define BNX2_EMAC_MAC_MATCH11 0x0000143c
  1433. #define BNX2_EMAC_MAC_MATCH12 0x00001440
  1434. #define BNX2_EMAC_MAC_MATCH13 0x00001444
  1435. #define BNX2_EMAC_MAC_MATCH14 0x00001448
  1436. #define BNX2_EMAC_MAC_MATCH15 0x0000144c
  1437. #define BNX2_EMAC_MAC_MATCH16 0x00001450
  1438. #define BNX2_EMAC_MAC_MATCH17 0x00001454
  1439. #define BNX2_EMAC_MAC_MATCH18 0x00001458
  1440. #define BNX2_EMAC_MAC_MATCH19 0x0000145c
  1441. #define BNX2_EMAC_MAC_MATCH20 0x00001460
  1442. #define BNX2_EMAC_MAC_MATCH21 0x00001464
  1443. #define BNX2_EMAC_MAC_MATCH22 0x00001468
  1444. #define BNX2_EMAC_MAC_MATCH23 0x0000146c
  1445. #define BNX2_EMAC_MAC_MATCH24 0x00001470
  1446. #define BNX2_EMAC_MAC_MATCH25 0x00001474
  1447. #define BNX2_EMAC_MAC_MATCH26 0x00001478
  1448. #define BNX2_EMAC_MAC_MATCH27 0x0000147c
  1449. #define BNX2_EMAC_MAC_MATCH28 0x00001480
  1450. #define BNX2_EMAC_MAC_MATCH29 0x00001484
  1451. #define BNX2_EMAC_MAC_MATCH30 0x00001488
  1452. #define BNX2_EMAC_MAC_MATCH31 0x0000148c
  1453. #define BNX2_EMAC_BACKOFF_SEED 0x00001498
  1454. #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
  1455. #define BNX2_EMAC_RX_MTU_SIZE 0x0000149c
  1456. #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
  1457. #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
  1458. #define BNX2_EMAC_SERDES_CNTL 0x000014a4
  1459. #define BNX2_EMAC_SERDES_CNTL_RXR (0x7L<<0)
  1460. #define BNX2_EMAC_SERDES_CNTL_RXG (0x3L<<3)
  1461. #define BNX2_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
  1462. #define BNX2_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7)
  1463. #define BNX2_EMAC_SERDES_CNTL_BGMAX (1L<<10)
  1464. #define BNX2_EMAC_SERDES_CNTL_BGMIN (1L<<11)
  1465. #define BNX2_EMAC_SERDES_CNTL_TXMODE (1L<<12)
  1466. #define BNX2_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
  1467. #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
  1468. #define BNX2_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
  1469. #define BNX2_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
  1470. #define BNX2_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
  1471. #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
  1472. #define BNX2_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
  1473. #define BNX2_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20)
  1474. #define BNX2_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22)
  1475. #define BNX2_EMAC_SERDES_STATUS 0x000014a8
  1476. #define BNX2_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0)
  1477. #define BNX2_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
  1478. #define BNX2_EMAC_MDIO_COMM 0x000014ac
  1479. #define BNX2_EMAC_MDIO_COMM_DATA (0xffffL<<0)
  1480. #define BNX2_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
  1481. #define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
  1482. #define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
  1483. #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
  1484. #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
  1485. #define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
  1486. #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
  1487. #define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28)
  1488. #define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29)
  1489. #define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30)
  1490. #define BNX2_EMAC_MDIO_STATUS 0x000014b0
  1491. #define BNX2_EMAC_MDIO_STATUS_LINK (1L<<0)
  1492. #define BNX2_EMAC_MDIO_STATUS_10MB (1L<<1)
  1493. #define BNX2_EMAC_MDIO_MODE 0x000014b4
  1494. #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
  1495. #define BNX2_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
  1496. #define BNX2_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
  1497. #define BNX2_EMAC_MDIO_MODE_MDIO (1L<<9)
  1498. #define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
  1499. #define BNX2_EMAC_MDIO_MODE_MDC (1L<<11)
  1500. #define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12)
  1501. #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
  1502. #define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8
  1503. #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
  1504. #define BNX2_EMAC_TX_MODE 0x000014bc
  1505. #define BNX2_EMAC_TX_MODE_RESET (1L<<0)
  1506. #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
  1507. #define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4)
  1508. #define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
  1509. #define BNX2_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
  1510. #define BNX2_EMAC_TX_MODE_LINK_AWARE (1L<<7)
  1511. #define BNX2_EMAC_TX_STATUS 0x000014c0
  1512. #define BNX2_EMAC_TX_STATUS_XOFFED (1L<<0)
  1513. #define BNX2_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
  1514. #define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2)
  1515. #define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3)
  1516. #define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4)
  1517. #define BNX2_EMAC_TX_LENGTHS 0x000014c4
  1518. #define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
  1519. #define BNX2_EMAC_TX_LENGTHS_IPG (0xfL<<8)
  1520. #define BNX2_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
  1521. #define BNX2_EMAC_RX_MODE 0x000014c8
  1522. #define BNX2_EMAC_RX_MODE_RESET (1L<<0)
  1523. #define BNX2_EMAC_RX_MODE_FLOW_EN (1L<<2)
  1524. #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
  1525. #define BNX2_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
  1526. #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
  1527. #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
  1528. #define BNX2_EMAC_RX_MODE_LLC_CHK (1L<<7)
  1529. #define BNX2_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
  1530. #define BNX2_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
  1531. #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
  1532. #define BNX2_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
  1533. #define BNX2_EMAC_RX_MODE_SORT_MODE (1L<<12)
  1534. #define BNX2_EMAC_RX_STATUS 0x000014cc
  1535. #define BNX2_EMAC_RX_STATUS_FFED (1L<<0)
  1536. #define BNX2_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
  1537. #define BNX2_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
  1538. #define BNX2_EMAC_MULTICAST_HASH0 0x000014d0
  1539. #define BNX2_EMAC_MULTICAST_HASH1 0x000014d4
  1540. #define BNX2_EMAC_MULTICAST_HASH2 0x000014d8
  1541. #define BNX2_EMAC_MULTICAST_HASH3 0x000014dc
  1542. #define BNX2_EMAC_MULTICAST_HASH4 0x000014e0
  1543. #define BNX2_EMAC_MULTICAST_HASH5 0x000014e4
  1544. #define BNX2_EMAC_MULTICAST_HASH6 0x000014e8
  1545. #define BNX2_EMAC_MULTICAST_HASH7 0x000014ec
  1546. #define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
  1547. #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
  1548. #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
  1549. #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c
  1550. #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510
  1551. #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514
  1552. #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518
  1553. #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c
  1554. #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520
  1555. #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
  1556. #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528
  1557. #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c
  1558. #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530
  1559. #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
  1560. #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538
  1561. #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c
  1562. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
  1563. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
  1564. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548
  1565. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
  1566. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
  1567. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
  1568. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558
  1569. #define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c
  1570. #define BNX2_EMAC_RXMAC_DEBUG1 0x00001560
  1571. #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
  1572. #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
  1573. #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
  1574. #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
  1575. #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
  1576. #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
  1577. #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
  1578. #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
  1579. #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
  1580. #define BNX2_EMAC_RXMAC_DEBUG2 0x00001564
  1581. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
  1582. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0)
  1583. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0)
  1584. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0)
  1585. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0)
  1586. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0)
  1587. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0)
  1588. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0)
  1589. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0)
  1590. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
  1591. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3)
  1592. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3)
  1593. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3)
  1594. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3)
  1595. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3)
  1596. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3)
  1597. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3)
  1598. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3)
  1599. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3)
  1600. #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
  1601. #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
  1602. #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
  1603. #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
  1604. #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
  1605. #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
  1606. #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
  1607. #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
  1608. #define BNX2_EMAC_RXMAC_DEBUG3 0x00001568
  1609. #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
  1610. #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
  1611. #define BNX2_EMAC_RXMAC_DEBUG4 0x0000156c
  1612. #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
  1613. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
  1614. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16)
  1615. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
  1616. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
  1617. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
  1618. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
  1619. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
  1620. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
  1621. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
  1622. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
  1623. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
  1624. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16)
  1625. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16)
  1626. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16)
  1627. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16)
  1628. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16)
  1629. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16)
  1630. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16)
  1631. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16)
  1632. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16)
  1633. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16)
  1634. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16)
  1635. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16)
  1636. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16)
  1637. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16)
  1638. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16)
  1639. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16)
  1640. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16)
  1641. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16)
  1642. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16)
  1643. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
  1644. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16)
  1645. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16)
  1646. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16)
  1647. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16)
  1648. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16)
  1649. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16)
  1650. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16)
  1651. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16)
  1652. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16)
  1653. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16)
  1654. #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
  1655. #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
  1656. #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
  1657. #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
  1658. #define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26)
  1659. #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
  1660. #define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28)
  1661. #define BNX2_EMAC_RXMAC_DEBUG5 0x00001570
  1662. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
  1663. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
  1664. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
  1665. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
  1666. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
  1667. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
  1668. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
  1669. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
  1670. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
  1671. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4)
  1672. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4)
  1673. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4)
  1674. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4)
  1675. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4)
  1676. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4)
  1677. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4)
  1678. #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
  1679. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
  1680. #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
  1681. #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
  1682. #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
  1683. #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
  1684. #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
  1685. #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
  1686. #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
  1687. #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
  1688. #define BNX2_EMAC_RX_STAT_AC0 0x00001580
  1689. #define BNX2_EMAC_RX_STAT_AC1 0x00001584
  1690. #define BNX2_EMAC_RX_STAT_AC2 0x00001588
  1691. #define BNX2_EMAC_RX_STAT_AC3 0x0000158c
  1692. #define BNX2_EMAC_RX_STAT_AC4 0x00001590
  1693. #define BNX2_EMAC_RX_STAT_AC5 0x00001594
  1694. #define BNX2_EMAC_RX_STAT_AC6 0x00001598
  1695. #define BNX2_EMAC_RX_STAT_AC7 0x0000159c
  1696. #define BNX2_EMAC_RX_STAT_AC8 0x000015a0
  1697. #define BNX2_EMAC_RX_STAT_AC9 0x000015a4
  1698. #define BNX2_EMAC_RX_STAT_AC10 0x000015a8
  1699. #define BNX2_EMAC_RX_STAT_AC11 0x000015ac
  1700. #define BNX2_EMAC_RX_STAT_AC12 0x000015b0
  1701. #define BNX2_EMAC_RX_STAT_AC13 0x000015b4
  1702. #define BNX2_EMAC_RX_STAT_AC14 0x000015b8
  1703. #define BNX2_EMAC_RX_STAT_AC15 0x000015bc
  1704. #define BNX2_EMAC_RX_STAT_AC16 0x000015c0
  1705. #define BNX2_EMAC_RX_STAT_AC17 0x000015c4
  1706. #define BNX2_EMAC_RX_STAT_AC18 0x000015c8
  1707. #define BNX2_EMAC_RX_STAT_AC19 0x000015cc
  1708. #define BNX2_EMAC_RX_STAT_AC20 0x000015d0
  1709. #define BNX2_EMAC_RX_STAT_AC21 0x000015d4
  1710. #define BNX2_EMAC_RX_STAT_AC22 0x000015d8
  1711. #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
  1712. #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
  1713. #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
  1714. #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
  1715. #define BNX2_EMAC_TX_STAT_OUTXONSENT 0x0000160c
  1716. #define BNX2_EMAC_TX_STAT_OUTXOFFSENT 0x00001610
  1717. #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614
  1718. #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
  1719. #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c
  1720. #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
  1721. #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
  1722. #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628
  1723. #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c
  1724. #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630
  1725. #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634
  1726. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
  1727. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
  1728. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640
  1729. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
  1730. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
  1731. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
  1732. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650
  1733. #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
  1734. #define BNX2_EMAC_TXMAC_DEBUG0 0x00001658
  1735. #define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c
  1736. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
  1737. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0)
  1738. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0)
  1739. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0)
  1740. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0)
  1741. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0)
  1742. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0)
  1743. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0)
  1744. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0)
  1745. #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
  1746. #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
  1747. #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
  1748. #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
  1749. #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
  1750. #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
  1751. #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
  1752. #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
  1753. #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
  1754. #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
  1755. #define BNX2_EMAC_TXMAC_DEBUG2 0x00001660
  1756. #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
  1757. #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
  1758. #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
  1759. #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
  1760. #define BNX2_EMAC_TXMAC_DEBUG3 0x00001664
  1761. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
  1762. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0)
  1763. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0)
  1764. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0)
  1765. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0)
  1766. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0)
  1767. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0)
  1768. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0)
  1769. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0)
  1770. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0)
  1771. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0)
  1772. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0)
  1773. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0)
  1774. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0)
  1775. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0)
  1776. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0)
  1777. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
  1778. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4)
  1779. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4)
  1780. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4)
  1781. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4)
  1782. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4)
  1783. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4)
  1784. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4)
  1785. #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
  1786. #define BNX2_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
  1787. #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
  1788. #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
  1789. #define BNX2_EMAC_TXMAC_DEBUG4 0x00001668
  1790. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
  1791. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
  1792. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
  1793. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
  1794. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
  1795. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
  1796. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
  1797. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
  1798. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
  1799. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
  1800. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
  1801. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
  1802. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
  1803. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
  1804. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
  1805. #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
  1806. #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
  1807. #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
  1808. #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
  1809. #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
  1810. #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
  1811. #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
  1812. #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
  1813. #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
  1814. #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
  1815. #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
  1816. #define BNX2_EMAC_TXMAC_DEBUG4_GO (1L<<31)
  1817. #define BNX2_EMAC_TX_STAT_AC0 0x00001680
  1818. #define BNX2_EMAC_TX_STAT_AC1 0x00001684
  1819. #define BNX2_EMAC_TX_STAT_AC2 0x00001688
  1820. #define BNX2_EMAC_TX_STAT_AC3 0x0000168c
  1821. #define BNX2_EMAC_TX_STAT_AC4 0x00001690
  1822. #define BNX2_EMAC_TX_STAT_AC5 0x00001694
  1823. #define BNX2_EMAC_TX_STAT_AC6 0x00001698
  1824. #define BNX2_EMAC_TX_STAT_AC7 0x0000169c
  1825. #define BNX2_EMAC_TX_STAT_AC8 0x000016a0
  1826. #define BNX2_EMAC_TX_STAT_AC9 0x000016a4
  1827. #define BNX2_EMAC_TX_STAT_AC10 0x000016a8
  1828. #define BNX2_EMAC_TX_STAT_AC11 0x000016ac
  1829. #define BNX2_EMAC_TX_STAT_AC12 0x000016b0
  1830. #define BNX2_EMAC_TX_STAT_AC13 0x000016b4
  1831. #define BNX2_EMAC_TX_STAT_AC14 0x000016b8
  1832. #define BNX2_EMAC_TX_STAT_AC15 0x000016bc
  1833. #define BNX2_EMAC_TX_STAT_AC16 0x000016c0
  1834. #define BNX2_EMAC_TX_STAT_AC17 0x000016c4
  1835. #define BNX2_EMAC_TX_STAT_AC18 0x000016c8
  1836. #define BNX2_EMAC_TX_STAT_AC19 0x000016cc
  1837. #define BNX2_EMAC_TX_STAT_AC20 0x000016d0
  1838. #define BNX2_EMAC_TX_STAT_AC21 0x000016d4
  1839. #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
  1840. /*
  1841. * rpm_reg definition
  1842. * offset: 0x1800
  1843. */
  1844. #define BNX2_RPM_COMMAND 0x00001800
  1845. #define BNX2_RPM_COMMAND_ENABLED (1L<<0)
  1846. #define BNX2_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
  1847. #define BNX2_RPM_STATUS 0x00001804
  1848. #define BNX2_RPM_STATUS_MBUF_WAIT (1L<<0)
  1849. #define BNX2_RPM_STATUS_FREE_WAIT (1L<<1)
  1850. #define BNX2_RPM_CONFIG 0x00001808
  1851. #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
  1852. #define BNX2_RPM_CONFIG_ACPI_ENA (1L<<1)
  1853. #define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2)
  1854. #define BNX2_RPM_CONFIG_MP_KEEP (1L<<3)
  1855. #define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
  1856. #define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31)
  1857. #define BNX2_RPM_VLAN_MATCH0 0x00001810
  1858. #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
  1859. #define BNX2_RPM_VLAN_MATCH1 0x00001814
  1860. #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
  1861. #define BNX2_RPM_VLAN_MATCH2 0x00001818
  1862. #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
  1863. #define BNX2_RPM_VLAN_MATCH3 0x0000181c
  1864. #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
  1865. #define BNX2_RPM_SORT_USER0 0x00001820
  1866. #define BNX2_RPM_SORT_USER0_PM_EN (0xffffL<<0)
  1867. #define BNX2_RPM_SORT_USER0_BC_EN (1L<<16)
  1868. #define BNX2_RPM_SORT_USER0_MC_EN (1L<<17)
  1869. #define BNX2_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
  1870. #define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19)
  1871. #define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
  1872. #define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24)
  1873. #define BNX2_RPM_SORT_USER0_ENA (1L<<31)
  1874. #define BNX2_RPM_SORT_USER1 0x00001824
  1875. #define BNX2_RPM_SORT_USER1_PM_EN (0xffffL<<0)
  1876. #define BNX2_RPM_SORT_USER1_BC_EN (1L<<16)
  1877. #define BNX2_RPM_SORT_USER1_MC_EN (1L<<17)
  1878. #define BNX2_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
  1879. #define BNX2_RPM_SORT_USER1_PROM_EN (1L<<19)
  1880. #define BNX2_RPM_SORT_USER1_VLAN_EN (0xfL<<20)
  1881. #define BNX2_RPM_SORT_USER1_PROM_VLAN (1L<<24)
  1882. #define BNX2_RPM_SORT_USER1_ENA (1L<<31)
  1883. #define BNX2_RPM_SORT_USER2 0x00001828
  1884. #define BNX2_RPM_SORT_USER2_PM_EN (0xffffL<<0)
  1885. #define BNX2_RPM_SORT_USER2_BC_EN (1L<<16)
  1886. #define BNX2_RPM_SORT_USER2_MC_EN (1L<<17)
  1887. #define BNX2_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
  1888. #define BNX2_RPM_SORT_USER2_PROM_EN (1L<<19)
  1889. #define BNX2_RPM_SORT_USER2_VLAN_EN (0xfL<<20)
  1890. #define BNX2_RPM_SORT_USER2_PROM_VLAN (1L<<24)
  1891. #define BNX2_RPM_SORT_USER2_ENA (1L<<31)
  1892. #define BNX2_RPM_SORT_USER3 0x0000182c
  1893. #define BNX2_RPM_SORT_USER3_PM_EN (0xffffL<<0)
  1894. #define BNX2_RPM_SORT_USER3_BC_EN (1L<<16)
  1895. #define BNX2_RPM_SORT_USER3_MC_EN (1L<<17)
  1896. #define BNX2_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
  1897. #define BNX2_RPM_SORT_USER3_PROM_EN (1L<<19)
  1898. #define BNX2_RPM_SORT_USER3_VLAN_EN (0xfL<<20)
  1899. #define BNX2_RPM_SORT_USER3_PROM_VLAN (1L<<24)
  1900. #define BNX2_RPM_SORT_USER3_ENA (1L<<31)
  1901. #define BNX2_RPM_STAT_L2_FILTER_DISCARDS 0x00001840
  1902. #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844
  1903. #define BNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848
  1904. #define BNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c
  1905. #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
  1906. #define BNX2_RPM_STAT_AC0 0x00001880
  1907. #define BNX2_RPM_STAT_AC1 0x00001884
  1908. #define BNX2_RPM_STAT_AC2 0x00001888
  1909. #define BNX2_RPM_STAT_AC3 0x0000188c
  1910. #define BNX2_RPM_STAT_AC4 0x00001890
  1911. #define BNX2_RPM_RC_CNTL_0 0x00001900
  1912. #define BNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
  1913. #define BNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8)
  1914. #define BNX2_RPM_RC_CNTL_0_PRIORITY (1L<<11)
  1915. #define BNX2_RPM_RC_CNTL_0_P4 (1L<<12)
  1916. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13)
  1917. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
  1918. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
  1919. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
  1920. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
  1921. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
  1922. #define BNX2_RPM_RC_CNTL_0_COMP (0x3L<<16)
  1923. #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
  1924. #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
  1925. #define BNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
  1926. #define BNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
  1927. #define BNX2_RPM_RC_CNTL_0_SBIT (1L<<19)
  1928. #define BNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
  1929. #define BNX2_RPM_RC_CNTL_0_MAP (1L<<24)
  1930. #define BNX2_RPM_RC_CNTL_0_DISCARD (1L<<25)
  1931. #define BNX2_RPM_RC_CNTL_0_MASK (1L<<26)
  1932. #define BNX2_RPM_RC_CNTL_0_P1 (1L<<27)
  1933. #define BNX2_RPM_RC_CNTL_0_P2 (1L<<28)
  1934. #define BNX2_RPM_RC_CNTL_0_P3 (1L<<29)
  1935. #define BNX2_RPM_RC_CNTL_0_NBIT (1L<<30)
  1936. #define BNX2_RPM_RC_VALUE_MASK_0 0x00001904
  1937. #define BNX2_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0)
  1938. #define BNX2_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16)
  1939. #define BNX2_RPM_RC_CNTL_1 0x00001908
  1940. #define BNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0)
  1941. #define BNX2_RPM_RC_CNTL_1_B (0xfffL<<19)
  1942. #define BNX2_RPM_RC_VALUE_MASK_1 0x0000190c
  1943. #define BNX2_RPM_RC_CNTL_2 0x00001910
  1944. #define BNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0)
  1945. #define BNX2_RPM_RC_CNTL_2_B (0xfffL<<19)
  1946. #define BNX2_RPM_RC_VALUE_MASK_2 0x00001914
  1947. #define BNX2_RPM_RC_CNTL_3 0x00001918
  1948. #define BNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0)
  1949. #define BNX2_RPM_RC_CNTL_3_B (0xfffL<<19)
  1950. #define BNX2_RPM_RC_VALUE_MASK_3 0x0000191c
  1951. #define BNX2_RPM_RC_CNTL_4 0x00001920
  1952. #define BNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0)
  1953. #define BNX2_RPM_RC_CNTL_4_B (0xfffL<<19)
  1954. #define BNX2_RPM_RC_VALUE_MASK_4 0x00001924
  1955. #define BNX2_RPM_RC_CNTL_5 0x00001928
  1956. #define BNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0)
  1957. #define BNX2_RPM_RC_CNTL_5_B (0xfffL<<19)
  1958. #define BNX2_RPM_RC_VALUE_MASK_5 0x0000192c
  1959. #define BNX2_RPM_RC_CNTL_6 0x00001930
  1960. #define BNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0)
  1961. #define BNX2_RPM_RC_CNTL_6_B (0xfffL<<19)
  1962. #define BNX2_RPM_RC_VALUE_MASK_6 0x00001934
  1963. #define BNX2_RPM_RC_CNTL_7 0x00001938
  1964. #define BNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0)
  1965. #define BNX2_RPM_RC_CNTL_7_B (0xfffL<<19)
  1966. #define BNX2_RPM_RC_VALUE_MASK_7 0x0000193c
  1967. #define BNX2_RPM_RC_CNTL_8 0x00001940
  1968. #define BNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0)
  1969. #define BNX2_RPM_RC_CNTL_8_B (0xfffL<<19)
  1970. #define BNX2_RPM_RC_VALUE_MASK_8 0x00001944
  1971. #define BNX2_RPM_RC_CNTL_9 0x00001948
  1972. #define BNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0)
  1973. #define BNX2_RPM_RC_CNTL_9_B (0xfffL<<19)
  1974. #define BNX2_RPM_RC_VALUE_MASK_9 0x0000194c
  1975. #define BNX2_RPM_RC_CNTL_10 0x00001950
  1976. #define BNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0)
  1977. #define BNX2_RPM_RC_CNTL_10_B (0xfffL<<19)
  1978. #define BNX2_RPM_RC_VALUE_MASK_10 0x00001954
  1979. #define BNX2_RPM_RC_CNTL_11 0x00001958
  1980. #define BNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0)
  1981. #define BNX2_RPM_RC_CNTL_11_B (0xfffL<<19)
  1982. #define BNX2_RPM_RC_VALUE_MASK_11 0x0000195c
  1983. #define BNX2_RPM_RC_CNTL_12 0x00001960
  1984. #define BNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0)
  1985. #define BNX2_RPM_RC_CNTL_12_B (0xfffL<<19)
  1986. #define BNX2_RPM_RC_VALUE_MASK_12 0x00001964
  1987. #define BNX2_RPM_RC_CNTL_13 0x00001968
  1988. #define BNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0)
  1989. #define BNX2_RPM_RC_CNTL_13_B (0xfffL<<19)
  1990. #define BNX2_RPM_RC_VALUE_MASK_13 0x0000196c
  1991. #define BNX2_RPM_RC_CNTL_14 0x00001970
  1992. #define BNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0)
  1993. #define BNX2_RPM_RC_CNTL_14_B (0xfffL<<19)
  1994. #define BNX2_RPM_RC_VALUE_MASK_14 0x00001974
  1995. #define BNX2_RPM_RC_CNTL_15 0x00001978
  1996. #define BNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0)
  1997. #define BNX2_RPM_RC_CNTL_15_B (0xfffL<<19)
  1998. #define BNX2_RPM_RC_VALUE_MASK_15 0x0000197c
  1999. #define BNX2_RPM_RC_CONFIG 0x00001980
  2000. #define BNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
  2001. #define BNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
  2002. #define BNX2_RPM_DEBUG0 0x00001984
  2003. #define BNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
  2004. #define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
  2005. #define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
  2006. #define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
  2007. #define BNX2_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
  2008. #define BNX2_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
  2009. #define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
  2010. #define BNX2_RPM_DEBUG0_LLC_SNAP (1L<<22)
  2011. #define BNX2_RPM_DEBUG0_FM_STARTED (1L<<23)
  2012. #define BNX2_RPM_DEBUG0_DONE (1L<<24)
  2013. #define BNX2_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
  2014. #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
  2015. #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
  2016. #define BNX2_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
  2017. #define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
  2018. #define BNX2_RPM_DEBUG1 0x00001988
  2019. #define BNX2_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0)
  2020. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
  2021. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
  2022. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
  2023. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
  2024. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
  2025. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
  2026. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
  2027. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
  2028. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
  2029. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
  2030. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
  2031. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
  2032. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
  2033. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0)
  2034. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0)
  2035. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0)
  2036. #define BNX2_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16)
  2037. #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
  2038. #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
  2039. #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
  2040. #define BNX2_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
  2041. #define BNX2_RPM_DEBUG2 0x0000198c
  2042. #define BNX2_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0)
  2043. #define BNX2_RPM_DEBUG2_IP_BCNT (0xffL<<16)
  2044. #define BNX2_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
  2045. #define BNX2_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
  2046. #define BNX2_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
  2047. #define BNX2_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
  2048. #define BNX2_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
  2049. #define BNX2_RPM_DEBUG2_FM_DISCARD (1L<<29)
  2050. #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
  2051. #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
  2052. #define BNX2_RPM_DEBUG3 0x00001990
  2053. #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0)
  2054. #define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
  2055. #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
  2056. #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
  2057. #define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
  2058. #define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
  2059. #define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
  2060. #define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
  2061. #define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16)
  2062. #define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
  2063. #define BNX2_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
  2064. #define BNX2_RPM_DEBUG3_DROP_NXT (1L<<23)
  2065. #define BNX2_RPM_DEBUG3_FTQ_FSM (0x3L<<24)
  2066. #define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24)
  2067. #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24)
  2068. #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24)
  2069. #define BNX2_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26)
  2070. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26)
  2071. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26)
  2072. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26)
  2073. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26)
  2074. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26)
  2075. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26)
  2076. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26)
  2077. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26)
  2078. #define BNX2_RPM_DEBUG3_MBFREE_FSM (1L<<29)
  2079. #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
  2080. #define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
  2081. #define BNX2_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
  2082. #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30)
  2083. #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30)
  2084. #define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
  2085. #define BNX2_RPM_DEBUG4 0x00001994
  2086. #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0)
  2087. #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25)
  2088. #define BNX2_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28)
  2089. #define BNX2_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
  2090. #define BNX2_RPM_DEBUG5 0x00001998
  2091. #define BNX2_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0)
  2092. #define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5)
  2093. #define BNX2_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10)
  2094. #define BNX2_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15)
  2095. #define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
  2096. #define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
  2097. #define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
  2098. #define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
  2099. #define BNX2_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
  2100. #define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
  2101. #define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
  2102. #define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
  2103. #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
  2104. #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
  2105. #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
  2106. #define BNX2_RPM_DEBUG5_HOLDREG_RD (1L<<31)
  2107. #define BNX2_RPM_DEBUG6 0x0000199c
  2108. #define BNX2_RPM_DEBUG6_ACPI_VEC (0xffffL<<0)
  2109. #define BNX2_RPM_DEBUG6_VEC (0xffffL<<16)
  2110. #define BNX2_RPM_DEBUG7 0x000019a0
  2111. #define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0)
  2112. #define BNX2_RPM_DEBUG8 0x000019a4
  2113. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0)
  2114. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
  2115. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
  2116. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
  2117. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
  2118. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
  2119. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
  2120. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
  2121. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
  2122. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
  2123. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
  2124. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
  2125. #define BNX2_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
  2126. #define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
  2127. #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
  2128. #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
  2129. #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
  2130. #define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
  2131. #define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
  2132. #define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
  2133. #define BNX2_RPM_DEBUG8_EOF_DET (1L<<12)
  2134. #define BNX2_RPM_DEBUG8_SOF_DET (1L<<13)
  2135. #define BNX2_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
  2136. #define BNX2_RPM_DEBUG8_ALL_DONE (1L<<15)
  2137. #define BNX2_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16)
  2138. #define BNX2_RPM_DEBUG8_BYTE_CTR (0xffL<<24)
  2139. #define BNX2_RPM_DEBUG9 0x000019a8
  2140. #define BNX2_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0)
  2141. #define BNX2_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
  2142. #define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4)
  2143. #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
  2144. #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
  2145. #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
  2146. #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
  2147. #define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0
  2148. #define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4
  2149. #define BNX2_RPM_ACPI_DBG_BUF_W02 0x000019c8
  2150. #define BNX2_RPM_ACPI_DBG_BUF_W03 0x000019cc
  2151. #define BNX2_RPM_ACPI_DBG_BUF_W10 0x000019d0
  2152. #define BNX2_RPM_ACPI_DBG_BUF_W11 0x000019d4
  2153. #define BNX2_RPM_ACPI_DBG_BUF_W12 0x000019d8
  2154. #define BNX2_RPM_ACPI_DBG_BUF_W13 0x000019dc
  2155. #define BNX2_RPM_ACPI_DBG_BUF_W20 0x000019e0
  2156. #define BNX2_RPM_ACPI_DBG_BUF_W21 0x000019e4
  2157. #define BNX2_RPM_ACPI_DBG_BUF_W22 0x000019e8
  2158. #define BNX2_RPM_ACPI_DBG_BUF_W23 0x000019ec
  2159. #define BNX2_RPM_ACPI_DBG_BUF_W30 0x000019f0
  2160. #define BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4
  2161. #define BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8
  2162. #define BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc
  2163. /*
  2164. * rbuf_reg definition
  2165. * offset: 0x200000
  2166. */
  2167. #define BNX2_RBUF_COMMAND 0x00200000
  2168. #define BNX2_RBUF_COMMAND_ENABLED (1L<<0)
  2169. #define BNX2_RBUF_COMMAND_FREE_INIT (1L<<1)
  2170. #define BNX2_RBUF_COMMAND_RAM_INIT (1L<<2)
  2171. #define BNX2_RBUF_COMMAND_OVER_FREE (1L<<4)
  2172. #define BNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5)
  2173. #define BNX2_RBUF_STATUS1 0x00200004
  2174. #define BNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
  2175. #define BNX2_RBUF_STATUS2 0x00200008
  2176. #define BNX2_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0)
  2177. #define BNX2_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16)
  2178. #define BNX2_RBUF_CONFIG 0x0020000c
  2179. #define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
  2180. #define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
  2181. #define BNX2_RBUF_FW_BUF_ALLOC 0x00200010
  2182. #define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
  2183. #define BNX2_RBUF_FW_BUF_FREE 0x00200014
  2184. #define BNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
  2185. #define BNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
  2186. #define BNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
  2187. #define BNX2_RBUF_FW_BUF_SEL 0x00200018
  2188. #define BNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
  2189. #define BNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
  2190. #define BNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
  2191. #define BNX2_RBUF_CONFIG2 0x0020001c
  2192. #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
  2193. #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
  2194. #define BNX2_RBUF_CONFIG3 0x00200020
  2195. #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
  2196. #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
  2197. #define BNX2_RBUF_PKT_DATA 0x00208000
  2198. #define BNX2_RBUF_CLIST_DATA 0x00210000
  2199. #define BNX2_RBUF_BUF_DATA 0x00220000
  2200. /*
  2201. * rv2p_reg definition
  2202. * offset: 0x2800
  2203. */
  2204. #define BNX2_RV2P_COMMAND 0x00002800
  2205. #define BNX2_RV2P_COMMAND_ENABLED (1L<<0)
  2206. #define BNX2_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
  2207. #define BNX2_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
  2208. #define BNX2_RV2P_COMMAND_ABORT0 (1L<<4)
  2209. #define BNX2_RV2P_COMMAND_ABORT1 (1L<<5)
  2210. #define BNX2_RV2P_COMMAND_ABORT2 (1L<<6)
  2211. #define BNX2_RV2P_COMMAND_ABORT3 (1L<<7)
  2212. #define BNX2_RV2P_COMMAND_ABORT4 (1L<<8)
  2213. #define BNX2_RV2P_COMMAND_ABORT5 (1L<<9)
  2214. #define BNX2_RV2P_COMMAND_PROC1_RESET (1L<<16)
  2215. #define BNX2_RV2P_COMMAND_PROC2_RESET (1L<<17)
  2216. #define BNX2_RV2P_COMMAND_CTXIF_RESET (1L<<18)
  2217. #define BNX2_RV2P_STATUS 0x00002804
  2218. #define BNX2_RV2P_STATUS_ALWAYS_0 (1L<<0)
  2219. #define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
  2220. #define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
  2221. #define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
  2222. #define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
  2223. #define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
  2224. #define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
  2225. #define BNX2_RV2P_CONFIG 0x00002808
  2226. #define BNX2_RV2P_CONFIG_STALL_PROC1 (1L<<0)
  2227. #define BNX2_RV2P_CONFIG_STALL_PROC2 (1L<<1)
  2228. #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
  2229. #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
  2230. #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
  2231. #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
  2232. #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
  2233. #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
  2234. #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
  2235. #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
  2236. #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
  2237. #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
  2238. #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
  2239. #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
  2240. #define BNX2_RV2P_CONFIG_PAGE_SIZE (0xfL<<24)
  2241. #define BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
  2242. #define BNX2_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
  2243. #define BNX2_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
  2244. #define BNX2_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
  2245. #define BNX2_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
  2246. #define BNX2_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
  2247. #define BNX2_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
  2248. #define BNX2_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
  2249. #define BNX2_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
  2250. #define BNX2_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
  2251. #define BNX2_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
  2252. #define BNX2_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
  2253. #define BNX2_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
  2254. #define BNX2_RV2P_GEN_BFR_ADDR_0 0x00002810
  2255. #define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16)
  2256. #define BNX2_RV2P_GEN_BFR_ADDR_1 0x00002814
  2257. #define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16)
  2258. #define BNX2_RV2P_GEN_BFR_ADDR_2 0x00002818
  2259. #define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16)
  2260. #define BNX2_RV2P_GEN_BFR_ADDR_3 0x0000281c
  2261. #define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16)
  2262. #define BNX2_RV2P_INSTR_HIGH 0x00002830
  2263. #define BNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
  2264. #define BNX2_RV2P_INSTR_LOW 0x00002834
  2265. #define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838
  2266. #define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
  2267. #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
  2268. #define BNX2_RV2P_PROC2_ADDR_CMD 0x0000283c
  2269. #define BNX2_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0)
  2270. #define BNX2_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
  2271. #define BNX2_RV2P_PROC1_GRC_DEBUG 0x00002840
  2272. #define BNX2_RV2P_PROC2_GRC_DEBUG 0x00002844
  2273. #define BNX2_RV2P_GRC_PROC_DEBUG 0x00002848
  2274. #define BNX2_RV2P_DEBUG_VECT_PEEK 0x0000284c
  2275. #define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  2276. #define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  2277. #define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  2278. #define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  2279. #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  2280. #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  2281. #define BNX2_RV2P_PFTQ_DATA 0x00002b40
  2282. #define BNX2_RV2P_PFTQ_CMD 0x00002b78
  2283. #define BNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0)
  2284. #define BNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
  2285. #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
  2286. #define BNX2_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10)
  2287. #define BNX2_RV2P_PFTQ_CMD_SFT_RESET (1L<<25)
  2288. #define BNX2_RV2P_PFTQ_CMD_RD_DATA (1L<<26)
  2289. #define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27)
  2290. #define BNX2_RV2P_PFTQ_CMD_ADD_DATA (1L<<28)
  2291. #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29)
  2292. #define BNX2_RV2P_PFTQ_CMD_POP (1L<<30)
  2293. #define BNX2_RV2P_PFTQ_CMD_BUSY (1L<<31)
  2294. #define BNX2_RV2P_PFTQ_CTL 0x00002b7c
  2295. #define BNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
  2296. #define BNX2_RV2P_PFTQ_CTL_OVERFLOW (1L<<1)
  2297. #define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2)
  2298. #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  2299. #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  2300. #define BNX2_RV2P_TFTQ_DATA 0x00002b80
  2301. #define BNX2_RV2P_TFTQ_CMD 0x00002bb8
  2302. #define BNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0)
  2303. #define BNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
  2304. #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
  2305. #define BNX2_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10)
  2306. #define BNX2_RV2P_TFTQ_CMD_SFT_RESET (1L<<25)
  2307. #define BNX2_RV2P_TFTQ_CMD_RD_DATA (1L<<26)
  2308. #define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27)
  2309. #define BNX2_RV2P_TFTQ_CMD_ADD_DATA (1L<<28)
  2310. #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29)
  2311. #define BNX2_RV2P_TFTQ_CMD_POP (1L<<30)
  2312. #define BNX2_RV2P_TFTQ_CMD_BUSY (1L<<31)
  2313. #define BNX2_RV2P_TFTQ_CTL 0x00002bbc
  2314. #define BNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
  2315. #define BNX2_RV2P_TFTQ_CTL_OVERFLOW (1L<<1)
  2316. #define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2)
  2317. #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  2318. #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  2319. #define BNX2_RV2P_MFTQ_DATA 0x00002bc0
  2320. #define BNX2_RV2P_MFTQ_CMD 0x00002bf8
  2321. #define BNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0)
  2322. #define BNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
  2323. #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
  2324. #define BNX2_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10)
  2325. #define BNX2_RV2P_MFTQ_CMD_SFT_RESET (1L<<25)
  2326. #define BNX2_RV2P_MFTQ_CMD_RD_DATA (1L<<26)
  2327. #define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27)
  2328. #define BNX2_RV2P_MFTQ_CMD_ADD_DATA (1L<<28)
  2329. #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29)
  2330. #define BNX2_RV2P_MFTQ_CMD_POP (1L<<30)
  2331. #define BNX2_RV2P_MFTQ_CMD_BUSY (1L<<31)
  2332. #define BNX2_RV2P_MFTQ_CTL 0x00002bfc
  2333. #define BNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
  2334. #define BNX2_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
  2335. #define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
  2336. #define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  2337. #define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  2338. /*
  2339. * mq_reg definition
  2340. * offset: 0x3c00
  2341. */
  2342. #define BNX2_MQ_COMMAND 0x00003c00
  2343. #define BNX2_MQ_COMMAND_ENABLED (1L<<0)
  2344. #define BNX2_MQ_COMMAND_OVERFLOW (1L<<4)
  2345. #define BNX2_MQ_COMMAND_WR_ERROR (1L<<5)
  2346. #define BNX2_MQ_COMMAND_RD_ERROR (1L<<6)
  2347. #define BNX2_MQ_STATUS 0x00003c04
  2348. #define BNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
  2349. #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
  2350. #define BNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18)
  2351. #define BNX2_MQ_CONFIG 0x00003c08
  2352. #define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
  2353. #define BNX2_MQ_CONFIG_HALT_DIS (1L<<1)
  2354. #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
  2355. #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
  2356. #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
  2357. #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
  2358. #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
  2359. #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
  2360. #define BNX2_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
  2361. #define BNX2_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
  2362. #define BNX2_MQ_ENQUEUE1 0x00003c0c
  2363. #define BNX2_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
  2364. #define BNX2_MQ_ENQUEUE1_CID (0x3fffL<<8)
  2365. #define BNX2_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
  2366. #define BNX2_MQ_ENQUEUE1_KNL_MODE (1L<<28)
  2367. #define BNX2_MQ_ENQUEUE2 0x00003c10
  2368. #define BNX2_MQ_BAD_WR_ADDR 0x00003c14
  2369. #define BNX2_MQ_BAD_RD_ADDR 0x00003c18
  2370. #define BNX2_MQ_KNL_BYP_WIND_START 0x00003c1c
  2371. #define BNX2_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
  2372. #define BNX2_MQ_KNL_WIND_END 0x00003c20
  2373. #define BNX2_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
  2374. #define BNX2_MQ_KNL_WRITE_MASK1 0x00003c24
  2375. #define BNX2_MQ_KNL_TX_MASK1 0x00003c28
  2376. #define BNX2_MQ_KNL_CMD_MASK1 0x00003c2c
  2377. #define BNX2_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
  2378. #define BNX2_MQ_KNL_RX_V2P_MASK1 0x00003c34
  2379. #define BNX2_MQ_KNL_WRITE_MASK2 0x00003c38
  2380. #define BNX2_MQ_KNL_TX_MASK2 0x00003c3c
  2381. #define BNX2_MQ_KNL_CMD_MASK2 0x00003c40
  2382. #define BNX2_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
  2383. #define BNX2_MQ_KNL_RX_V2P_MASK2 0x00003c48
  2384. #define BNX2_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
  2385. #define BNX2_MQ_KNL_BYP_TX_MASK1 0x00003c50
  2386. #define BNX2_MQ_KNL_BYP_CMD_MASK1 0x00003c54
  2387. #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
  2388. #define BNX2_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
  2389. #define BNX2_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
  2390. #define BNX2_MQ_KNL_BYP_TX_MASK2 0x00003c64
  2391. #define BNX2_MQ_KNL_BYP_CMD_MASK2 0x00003c68
  2392. #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
  2393. #define BNX2_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
  2394. #define BNX2_MQ_MEM_WR_ADDR 0x00003c74
  2395. #define BNX2_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
  2396. #define BNX2_MQ_MEM_WR_DATA0 0x00003c78
  2397. #define BNX2_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
  2398. #define BNX2_MQ_MEM_WR_DATA1 0x00003c7c
  2399. #define BNX2_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
  2400. #define BNX2_MQ_MEM_WR_DATA2 0x00003c80
  2401. #define BNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
  2402. #define BNX2_MQ_MEM_RD_ADDR 0x00003c84
  2403. #define BNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
  2404. #define BNX2_MQ_MEM_RD_DATA0 0x00003c88
  2405. #define BNX2_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
  2406. #define BNX2_MQ_MEM_RD_DATA1 0x00003c8c
  2407. #define BNX2_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
  2408. #define BNX2_MQ_MEM_RD_DATA2 0x00003c90
  2409. #define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
  2410. /*
  2411. * tbdr_reg definition
  2412. * offset: 0x5000
  2413. */
  2414. #define BNX2_TBDR_COMMAND 0x00005000
  2415. #define BNX2_TBDR_COMMAND_ENABLE (1L<<0)
  2416. #define BNX2_TBDR_COMMAND_SOFT_RST (1L<<1)
  2417. #define BNX2_TBDR_COMMAND_MSTR_ABORT (1L<<4)
  2418. #define BNX2_TBDR_STATUS 0x00005004
  2419. #define BNX2_TBDR_STATUS_DMA_WAIT (1L<<0)
  2420. #define BNX2_TBDR_STATUS_FTQ_WAIT (1L<<1)
  2421. #define BNX2_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
  2422. #define BNX2_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
  2423. #define BNX2_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
  2424. #define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
  2425. #define BNX2_TBDR_STATUS_BURST_CNT (1L<<6)
  2426. #define BNX2_TBDR_CONFIG 0x00005008
  2427. #define BNX2_TBDR_CONFIG_MAX_BDS (0xffL<<0)
  2428. #define BNX2_TBDR_CONFIG_SWAP_MODE (1L<<8)
  2429. #define BNX2_TBDR_CONFIG_PRIORITY (1L<<9)
  2430. #define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
  2431. #define BNX2_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
  2432. #define BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
  2433. #define BNX2_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
  2434. #define BNX2_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
  2435. #define BNX2_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
  2436. #define BNX2_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
  2437. #define BNX2_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
  2438. #define BNX2_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
  2439. #define BNX2_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
  2440. #define BNX2_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
  2441. #define BNX2_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
  2442. #define BNX2_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
  2443. #define BNX2_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
  2444. #define BNX2_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
  2445. #define BNX2_TBDR_DEBUG_VECT_PEEK 0x0000500c
  2446. #define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  2447. #define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  2448. #define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  2449. #define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  2450. #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  2451. #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  2452. #define BNX2_TBDR_FTQ_DATA 0x000053c0
  2453. #define BNX2_TBDR_FTQ_CMD 0x000053f8
  2454. #define BNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
  2455. #define BNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10)
  2456. #define BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
  2457. #define BNX2_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
  2458. #define BNX2_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
  2459. #define BNX2_TBDR_FTQ_CMD_RD_DATA (1L<<26)
  2460. #define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
  2461. #define BNX2_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
  2462. #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
  2463. #define BNX2_TBDR_FTQ_CMD_POP (1L<<30)
  2464. #define BNX2_TBDR_FTQ_CMD_BUSY (1L<<31)
  2465. #define BNX2_TBDR_FTQ_CTL 0x000053fc
  2466. #define BNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0)
  2467. #define BNX2_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
  2468. #define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  2469. #define BNX2_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  2470. #define BNX2_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  2471. /*
  2472. * tdma_reg definition
  2473. * offset: 0x5c00
  2474. */
  2475. #define BNX2_TDMA_COMMAND 0x00005c00
  2476. #define BNX2_TDMA_COMMAND_ENABLED (1L<<0)
  2477. #define BNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4)
  2478. #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
  2479. #define BNX2_TDMA_STATUS 0x00005c04
  2480. #define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0)
  2481. #define BNX2_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
  2482. #define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
  2483. #define BNX2_TDMA_STATUS_LOCK_WAIT (1L<<3)
  2484. #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
  2485. #define BNX2_TDMA_STATUS_BURST_CNT (1L<<17)
  2486. #define BNX2_TDMA_CONFIG 0x00005c08
  2487. #define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0)
  2488. #define BNX2_TDMA_CONFIG_ONE_RECORD (1L<<1)
  2489. #define BNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)
  2490. #define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
  2491. #define BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4)
  2492. #define BNX2_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4)
  2493. #define BNX2_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4)
  2494. #define BNX2_TDMA_CONFIG_LINE_SZ (0xfL<<8)
  2495. #define BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
  2496. #define BNX2_TDMA_CONFIG_LINE_SZ_128 (4L<<8)
  2497. #define BNX2_TDMA_CONFIG_LINE_SZ_256 (6L<<8)
  2498. #define BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
  2499. #define BNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15)
  2500. #define BNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16)
  2501. #define BNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20)
  2502. #define BNX2_TDMA_PAYLOAD_PROD 0x00005c0c
  2503. #define BNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3)
  2504. #define BNX2_TDMA_DBG_WATCHDOG 0x00005c10
  2505. #define BNX2_TDMA_DBG_TRIGGER 0x00005c14
  2506. #define BNX2_TDMA_DMAD_FSM 0x00005c80
  2507. #define BNX2_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
  2508. #define BNX2_TDMA_DMAD_FSM_PUSH (0xfL<<4)
  2509. #define BNX2_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8)
  2510. #define BNX2_TDMA_DMAD_FSM_ARB_CTX (1L<<12)
  2511. #define BNX2_TDMA_DMAD_FSM_DR_INTF (1L<<16)
  2512. #define BNX2_TDMA_DMAD_FSM_DMAD (0x7L<<20)
  2513. #define BNX2_TDMA_DMAD_FSM_BD (0xfL<<24)
  2514. #define BNX2_TDMA_DMAD_STATUS 0x00005c84
  2515. #define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0)
  2516. #define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4)
  2517. #define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8)
  2518. #define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12)
  2519. #define BNX2_TDMA_DR_INTF_FSM 0x00005c88
  2520. #define BNX2_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0)
  2521. #define BNX2_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4)
  2522. #define BNX2_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8)
  2523. #define BNX2_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12)
  2524. #define BNX2_TDMA_DR_INTF_FSM_DMAD (0x7L<<16)
  2525. #define BNX2_TDMA_DR_INTF_STATUS 0x00005c8c
  2526. #define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0)
  2527. #define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4)
  2528. #define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8)
  2529. #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12)
  2530. #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16)
  2531. #define BNX2_TDMA_FTQ_DATA 0x00005fc0
  2532. #define BNX2_TDMA_FTQ_CMD 0x00005ff8
  2533. #define BNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0)
  2534. #define BNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10)
  2535. #define BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
  2536. #define BNX2_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10)
  2537. #define BNX2_TDMA_FTQ_CMD_SFT_RESET (1L<<25)
  2538. #define BNX2_TDMA_FTQ_CMD_RD_DATA (1L<<26)
  2539. #define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27)
  2540. #define BNX2_TDMA_FTQ_CMD_ADD_DATA (1L<<28)
  2541. #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29)
  2542. #define BNX2_TDMA_FTQ_CMD_POP (1L<<30)
  2543. #define BNX2_TDMA_FTQ_CMD_BUSY (1L<<31)
  2544. #define BNX2_TDMA_FTQ_CTL 0x00005ffc
  2545. #define BNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0)
  2546. #define BNX2_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
  2547. #define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  2548. #define BNX2_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  2549. #define BNX2_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  2550. /*
  2551. * hc_reg definition
  2552. * offset: 0x6800
  2553. */
  2554. #define BNX2_HC_COMMAND 0x00006800
  2555. #define BNX2_HC_COMMAND_ENABLE (1L<<0)
  2556. #define BNX2_HC_COMMAND_SKIP_ABORT (1L<<4)
  2557. #define BNX2_HC_COMMAND_COAL_NOW (1L<<16)
  2558. #define BNX2_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
  2559. #define BNX2_HC_COMMAND_STATS_NOW (1L<<18)
  2560. #define BNX2_HC_COMMAND_FORCE_INT (0x3L<<19)
  2561. #define BNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19)
  2562. #define BNX2_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
  2563. #define BNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19)
  2564. #define BNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19)
  2565. #define BNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21)
  2566. #define BNX2_HC_STATUS 0x00006804
  2567. #define BNX2_HC_STATUS_MASTER_ABORT (1L<<0)
  2568. #define BNX2_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
  2569. #define BNX2_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
  2570. #define BNX2_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
  2571. #define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
  2572. #define BNX2_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)
  2573. #define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20)
  2574. #define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23)
  2575. #define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24)
  2576. #define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25)
  2577. #define BNX2_HC_CONFIG 0x00006808
  2578. #define BNX2_HC_CONFIG_COLLECT_STATS (1L<<0)
  2579. #define BNX2_HC_CONFIG_RX_TMR_MODE (1L<<1)
  2580. #define BNX2_HC_CONFIG_TX_TMR_MODE (1L<<2)
  2581. #define BNX2_HC_CONFIG_COM_TMR_MODE (1L<<3)
  2582. #define BNX2_HC_CONFIG_CMD_TMR_MODE (1L<<4)
  2583. #define BNX2_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
  2584. #define BNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6)
  2585. #define BNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
  2586. #define BNX2_HC_ATTN_BITS_ENABLE 0x0000680c
  2587. #define BNX2_HC_STATUS_ADDR_L 0x00006810
  2588. #define BNX2_HC_STATUS_ADDR_H 0x00006814
  2589. #define BNX2_HC_STATISTICS_ADDR_L 0x00006818
  2590. #define BNX2_HC_STATISTICS_ADDR_H 0x0000681c
  2591. #define BNX2_HC_TX_QUICK_CONS_TRIP 0x00006820
  2592. #define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
  2593. #define BNX2_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16)
  2594. #define BNX2_HC_COMP_PROD_TRIP 0x00006824
  2595. #define BNX2_HC_COMP_PROD_TRIP_VALUE (0xffL<<0)
  2596. #define BNX2_HC_COMP_PROD_TRIP_INT (0xffL<<16)
  2597. #define BNX2_HC_RX_QUICK_CONS_TRIP 0x00006828
  2598. #define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
  2599. #define BNX2_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16)
  2600. #define BNX2_HC_RX_TICKS 0x0000682c
  2601. #define BNX2_HC_RX_TICKS_VALUE (0x3ffL<<0)
  2602. #define BNX2_HC_RX_TICKS_INT (0x3ffL<<16)
  2603. #define BNX2_HC_TX_TICKS 0x00006830
  2604. #define BNX2_HC_TX_TICKS_VALUE (0x3ffL<<0)
  2605. #define BNX2_HC_TX_TICKS_INT (0x3ffL<<16)
  2606. #define BNX2_HC_COM_TICKS 0x00006834
  2607. #define BNX2_HC_COM_TICKS_VALUE (0x3ffL<<0)
  2608. #define BNX2_HC_COM_TICKS_INT (0x3ffL<<16)
  2609. #define BNX2_HC_CMD_TICKS 0x00006838
  2610. #define BNX2_HC_CMD_TICKS_VALUE (0x3ffL<<0)
  2611. #define BNX2_HC_CMD_TICKS_INT (0x3ffL<<16)
  2612. #define BNX2_HC_PERIODIC_TICKS 0x0000683c
  2613. #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
  2614. #define BNX2_HC_STAT_COLLECT_TICKS 0x00006840
  2615. #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
  2616. #define BNX2_HC_STATS_TICKS 0x00006844
  2617. #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
  2618. #define BNX2_HC_STAT_MEM_DATA 0x0000684c
  2619. #define BNX2_HC_STAT_GEN_SEL_0 0x00006850
  2620. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
  2621. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
  2622. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
  2623. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
  2624. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
  2625. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
  2626. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
  2627. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
  2628. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
  2629. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
  2630. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
  2631. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
  2632. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
  2633. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
  2634. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
  2635. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
  2636. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
  2637. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
  2638. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
  2639. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
  2640. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
  2641. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
  2642. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
  2643. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
  2644. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
  2645. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
  2646. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
  2647. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
  2648. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
  2649. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
  2650. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
  2651. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
  2652. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
  2653. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
  2654. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
  2655. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
  2656. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
  2657. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
  2658. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
  2659. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
  2660. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
  2661. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
  2662. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
  2663. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
  2664. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
  2665. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
  2666. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
  2667. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
  2668. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
  2669. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
  2670. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
  2671. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
  2672. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
  2673. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
  2674. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
  2675. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
  2676. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
  2677. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
  2678. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
  2679. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
  2680. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
  2681. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
  2682. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
  2683. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
  2684. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
  2685. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
  2686. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
  2687. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
  2688. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
  2689. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
  2690. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
  2691. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
  2692. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
  2693. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
  2694. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
  2695. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
  2696. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
  2697. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
  2698. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
  2699. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
  2700. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
  2701. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
  2702. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
  2703. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
  2704. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
  2705. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
  2706. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
  2707. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0)
  2708. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0)
  2709. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
  2710. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
  2711. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
  2712. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0)
  2713. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0)
  2714. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
  2715. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
  2716. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
  2717. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
  2718. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
  2719. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
  2720. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
  2721. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
  2722. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
  2723. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
  2724. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
  2725. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
  2726. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
  2727. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
  2728. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
  2729. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
  2730. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
  2731. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
  2732. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
  2733. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
  2734. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
  2735. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
  2736. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
  2737. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
  2738. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
  2739. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
  2740. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
  2741. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
  2742. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
  2743. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
  2744. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
  2745. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
  2746. #define BNX2_HC_STAT_GEN_SEL_1 0x00006854
  2747. #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
  2748. #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
  2749. #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
  2750. #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
  2751. #define BNX2_HC_STAT_GEN_SEL_2 0x00006858
  2752. #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
  2753. #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
  2754. #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
  2755. #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
  2756. #define BNX2_HC_STAT_GEN_SEL_3 0x0000685c
  2757. #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
  2758. #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
  2759. #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
  2760. #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
  2761. #define BNX2_HC_STAT_GEN_STAT0 0x00006888
  2762. #define BNX2_HC_STAT_GEN_STAT1 0x0000688c
  2763. #define BNX2_HC_STAT_GEN_STAT2 0x00006890
  2764. #define BNX2_HC_STAT_GEN_STAT3 0x00006894
  2765. #define BNX2_HC_STAT_GEN_STAT4 0x00006898
  2766. #define BNX2_HC_STAT_GEN_STAT5 0x0000689c
  2767. #define BNX2_HC_STAT_GEN_STAT6 0x000068a0
  2768. #define BNX2_HC_STAT_GEN_STAT7 0x000068a4
  2769. #define BNX2_HC_STAT_GEN_STAT8 0x000068a8
  2770. #define BNX2_HC_STAT_GEN_STAT9 0x000068ac
  2771. #define BNX2_HC_STAT_GEN_STAT10 0x000068b0
  2772. #define BNX2_HC_STAT_GEN_STAT11 0x000068b4
  2773. #define BNX2_HC_STAT_GEN_STAT12 0x000068b8
  2774. #define BNX2_HC_STAT_GEN_STAT13 0x000068bc
  2775. #define BNX2_HC_STAT_GEN_STAT14 0x000068c0
  2776. #define BNX2_HC_STAT_GEN_STAT15 0x000068c4
  2777. #define BNX2_HC_STAT_GEN_STAT_AC0 0x000068c8
  2778. #define BNX2_HC_STAT_GEN_STAT_AC1 0x000068cc
  2779. #define BNX2_HC_STAT_GEN_STAT_AC2 0x000068d0
  2780. #define BNX2_HC_STAT_GEN_STAT_AC3 0x000068d4
  2781. #define BNX2_HC_STAT_GEN_STAT_AC4 0x000068d8
  2782. #define BNX2_HC_STAT_GEN_STAT_AC5 0x000068dc
  2783. #define BNX2_HC_STAT_GEN_STAT_AC6 0x000068e0
  2784. #define BNX2_HC_STAT_GEN_STAT_AC7 0x000068e4
  2785. #define BNX2_HC_STAT_GEN_STAT_AC8 0x000068e8
  2786. #define BNX2_HC_STAT_GEN_STAT_AC9 0x000068ec
  2787. #define BNX2_HC_STAT_GEN_STAT_AC10 0x000068f0
  2788. #define BNX2_HC_STAT_GEN_STAT_AC11 0x000068f4
  2789. #define BNX2_HC_STAT_GEN_STAT_AC12 0x000068f8
  2790. #define BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc
  2791. #define BNX2_HC_STAT_GEN_STAT_AC14 0x00006900
  2792. #define BNX2_HC_STAT_GEN_STAT_AC15 0x00006904
  2793. #define BNX2_HC_VIS 0x00006908
  2794. #define BNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
  2795. #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
  2796. #define BNX2_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
  2797. #define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
  2798. #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
  2799. #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
  2800. #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
  2801. #define BNX2_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
  2802. #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
  2803. #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
  2804. #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
  2805. #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
  2806. #define BNX2_HC_VIS_DMA_STAT_STATE (0xfL<<8)
  2807. #define BNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
  2808. #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8)
  2809. #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8)
  2810. #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8)
  2811. #define BNX2_HC_VIS_DMA_STAT_STATE_COMP (4L<<8)
  2812. #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8)
  2813. #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8)
  2814. #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8)
  2815. #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8)
  2816. #define BNX2_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8)
  2817. #define BNX2_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8)
  2818. #define BNX2_HC_VIS_DMA_MSI_STATE (0x7L<<12)
  2819. #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15)
  2820. #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
  2821. #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15)
  2822. #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15)
  2823. #define BNX2_HC_VIS_1 0x0000690c
  2824. #define BNX2_HC_VIS_1_HW_INTACK_STATE (1L<<4)
  2825. #define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
  2826. #define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4)
  2827. #define BNX2_HC_VIS_1_SW_INTACK_STATE (1L<<5)
  2828. #define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
  2829. #define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5)
  2830. #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6)
  2831. #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
  2832. #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6)
  2833. #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7)
  2834. #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
  2835. #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7)
  2836. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17)
  2837. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
  2838. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17)
  2839. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17)
  2840. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17)
  2841. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17)
  2842. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
  2843. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
  2844. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17)
  2845. #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21)
  2846. #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
  2847. #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21)
  2848. #define BNX2_HC_VIS_1_INT_GEN_STATE (1L<<23)
  2849. #define BNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
  2850. #define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23)
  2851. #define BNX2_HC_VIS_1_STAT_CHAN_ID (0x7L<<24)
  2852. #define BNX2_HC_VIS_1_INT_B (1L<<27)
  2853. #define BNX2_HC_DEBUG_VECT_PEEK 0x00006910
  2854. #define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  2855. #define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  2856. #define BNX2_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  2857. #define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  2858. #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  2859. #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  2860. /*
  2861. * txp_reg definition
  2862. * offset: 0x40000
  2863. */
  2864. #define BNX2_TXP_CPU_MODE 0x00045000
  2865. #define BNX2_TXP_CPU_MODE_LOCAL_RST (1L<<0)
  2866. #define BNX2_TXP_CPU_MODE_STEP_ENA (1L<<1)
  2867. #define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
  2868. #define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
  2869. #define BNX2_TXP_CPU_MODE_MSG_BIT1 (1L<<6)
  2870. #define BNX2_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
  2871. #define BNX2_TXP_CPU_MODE_SOFT_HALT (1L<<10)
  2872. #define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
  2873. #define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
  2874. #define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
  2875. #define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
  2876. #define BNX2_TXP_CPU_STATE 0x00045004
  2877. #define BNX2_TXP_CPU_STATE_BREAKPOINT (1L<<0)
  2878. #define BNX2_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
  2879. #define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
  2880. #define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
  2881. #define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
  2882. #define BNX2_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
  2883. #define BNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
  2884. #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
  2885. #define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
  2886. #define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
  2887. #define BNX2_TXP_CPU_STATE_INTERRRUPT (1L<<12)
  2888. #define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
  2889. #define BNX2_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
  2890. #define BNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
  2891. #define BNX2_TXP_CPU_EVENT_MASK 0x00045008
  2892. #define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
  2893. #define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
  2894. #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
  2895. #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
  2896. #define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
  2897. #define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
  2898. #define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
  2899. #define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
  2900. #define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
  2901. #define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
  2902. #define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
  2903. #define BNX2_TXP_CPU_PROGRAM_COUNTER 0x0004501c
  2904. #define BNX2_TXP_CPU_INSTRUCTION 0x00045020
  2905. #define BNX2_TXP_CPU_DATA_ACCESS 0x00045024
  2906. #define BNX2_TXP_CPU_INTERRUPT_ENABLE 0x00045028
  2907. #define BNX2_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
  2908. #define BNX2_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
  2909. #define BNX2_TXP_CPU_HW_BREAKPOINT 0x00045034
  2910. #define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
  2911. #define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
  2912. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK 0x00045038
  2913. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  2914. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  2915. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  2916. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  2917. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  2918. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  2919. #define BNX2_TXP_CPU_LAST_BRANCH_ADDR 0x00045048
  2920. #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
  2921. #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
  2922. #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
  2923. #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
  2924. #define BNX2_TXP_CPU_REG_FILE 0x00045200
  2925. #define BNX2_TXP_FTQ_DATA 0x000453c0
  2926. #define BNX2_TXP_FTQ_CMD 0x000453f8
  2927. #define BNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
  2928. #define BNX2_TXP_FTQ_CMD_WR_TOP (1L<<10)
  2929. #define BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
  2930. #define BNX2_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
  2931. #define BNX2_TXP_FTQ_CMD_SFT_RESET (1L<<25)
  2932. #define BNX2_TXP_FTQ_CMD_RD_DATA (1L<<26)
  2933. #define BNX2_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
  2934. #define BNX2_TXP_FTQ_CMD_ADD_DATA (1L<<28)
  2935. #define BNX2_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
  2936. #define BNX2_TXP_FTQ_CMD_POP (1L<<30)
  2937. #define BNX2_TXP_FTQ_CMD_BUSY (1L<<31)
  2938. #define BNX2_TXP_FTQ_CTL 0x000453fc
  2939. #define BNX2_TXP_FTQ_CTL_INTERVENE (1L<<0)
  2940. #define BNX2_TXP_FTQ_CTL_OVERFLOW (1L<<1)
  2941. #define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  2942. #define BNX2_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  2943. #define BNX2_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  2944. #define BNX2_TXP_SCRATCH 0x00060000
  2945. /*
  2946. * tpat_reg definition
  2947. * offset: 0x80000
  2948. */
  2949. #define BNX2_TPAT_CPU_MODE 0x00085000
  2950. #define BNX2_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
  2951. #define BNX2_TPAT_CPU_MODE_STEP_ENA (1L<<1)
  2952. #define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
  2953. #define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
  2954. #define BNX2_TPAT_CPU_MODE_MSG_BIT1 (1L<<6)
  2955. #define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7)
  2956. #define BNX2_TPAT_CPU_MODE_SOFT_HALT (1L<<10)
  2957. #define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
  2958. #define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
  2959. #define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
  2960. #define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
  2961. #define BNX2_TPAT_CPU_STATE 0x00085004
  2962. #define BNX2_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
  2963. #define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2)
  2964. #define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
  2965. #define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
  2966. #define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
  2967. #define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6)
  2968. #define BNX2_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
  2969. #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
  2970. #define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
  2971. #define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
  2972. #define BNX2_TPAT_CPU_STATE_INTERRRUPT (1L<<12)
  2973. #define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
  2974. #define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15)
  2975. #define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1L<<31)
  2976. #define BNX2_TPAT_CPU_EVENT_MASK 0x00085008
  2977. #define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
  2978. #define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
  2979. #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
  2980. #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
  2981. #define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
  2982. #define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
  2983. #define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
  2984. #define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
  2985. #define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
  2986. #define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
  2987. #define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
  2988. #define BNX2_TPAT_CPU_PROGRAM_COUNTER 0x0008501c
  2989. #define BNX2_TPAT_CPU_INSTRUCTION 0x00085020
  2990. #define BNX2_TPAT_CPU_DATA_ACCESS 0x00085024
  2991. #define BNX2_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
  2992. #define BNX2_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
  2993. #define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
  2994. #define BNX2_TPAT_CPU_HW_BREAKPOINT 0x00085034
  2995. #define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
  2996. #define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
  2997. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038
  2998. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  2999. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  3000. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  3001. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  3002. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  3003. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  3004. #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048
  3005. #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
  3006. #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
  3007. #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
  3008. #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
  3009. #define BNX2_TPAT_CPU_REG_FILE 0x00085200
  3010. #define BNX2_TPAT_FTQ_DATA 0x000853c0
  3011. #define BNX2_TPAT_FTQ_CMD 0x000853f8
  3012. #define BNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
  3013. #define BNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10)
  3014. #define BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
  3015. #define BNX2_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
  3016. #define BNX2_TPAT_FTQ_CMD_SFT_RESET (1L<<25)
  3017. #define BNX2_TPAT_FTQ_CMD_RD_DATA (1L<<26)
  3018. #define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27)
  3019. #define BNX2_TPAT_FTQ_CMD_ADD_DATA (1L<<28)
  3020. #define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29)
  3021. #define BNX2_TPAT_FTQ_CMD_POP (1L<<30)
  3022. #define BNX2_TPAT_FTQ_CMD_BUSY (1L<<31)
  3023. #define BNX2_TPAT_FTQ_CTL 0x000853fc
  3024. #define BNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0)
  3025. #define BNX2_TPAT_FTQ_CTL_OVERFLOW (1L<<1)
  3026. #define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  3027. #define BNX2_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  3028. #define BNX2_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  3029. #define BNX2_TPAT_SCRATCH 0x000a0000
  3030. /*
  3031. * rxp_reg definition
  3032. * offset: 0xc0000
  3033. */
  3034. #define BNX2_RXP_CPU_MODE 0x000c5000
  3035. #define BNX2_RXP_CPU_MODE_LOCAL_RST (1L<<0)
  3036. #define BNX2_RXP_CPU_MODE_STEP_ENA (1L<<1)
  3037. #define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
  3038. #define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
  3039. #define BNX2_RXP_CPU_MODE_MSG_BIT1 (1L<<6)
  3040. #define BNX2_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
  3041. #define BNX2_RXP_CPU_MODE_SOFT_HALT (1L<<10)
  3042. #define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
  3043. #define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
  3044. #define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
  3045. #define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
  3046. #define BNX2_RXP_CPU_STATE 0x000c5004
  3047. #define BNX2_RXP_CPU_STATE_BREAKPOINT (1L<<0)
  3048. #define BNX2_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
  3049. #define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
  3050. #define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
  3051. #define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
  3052. #define BNX2_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
  3053. #define BNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
  3054. #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
  3055. #define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
  3056. #define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
  3057. #define BNX2_RXP_CPU_STATE_INTERRRUPT (1L<<12)
  3058. #define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
  3059. #define BNX2_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
  3060. #define BNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31)
  3061. #define BNX2_RXP_CPU_EVENT_MASK 0x000c5008
  3062. #define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
  3063. #define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
  3064. #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
  3065. #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
  3066. #define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
  3067. #define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
  3068. #define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
  3069. #define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
  3070. #define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
  3071. #define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
  3072. #define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
  3073. #define BNX2_RXP_CPU_PROGRAM_COUNTER 0x000c501c
  3074. #define BNX2_RXP_CPU_INSTRUCTION 0x000c5020
  3075. #define BNX2_RXP_CPU_DATA_ACCESS 0x000c5024
  3076. #define BNX2_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
  3077. #define BNX2_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
  3078. #define BNX2_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
  3079. #define BNX2_RXP_CPU_HW_BREAKPOINT 0x000c5034
  3080. #define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
  3081. #define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
  3082. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038
  3083. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  3084. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  3085. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  3086. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  3087. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  3088. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  3089. #define BNX2_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048
  3090. #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
  3091. #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
  3092. #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
  3093. #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
  3094. #define BNX2_RXP_CPU_REG_FILE 0x000c5200
  3095. #define BNX2_RXP_CFTQ_DATA 0x000c5380
  3096. #define BNX2_RXP_CFTQ_CMD 0x000c53b8
  3097. #define BNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
  3098. #define BNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10)
  3099. #define BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
  3100. #define BNX2_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
  3101. #define BNX2_RXP_CFTQ_CMD_SFT_RESET (1L<<25)
  3102. #define BNX2_RXP_CFTQ_CMD_RD_DATA (1L<<26)
  3103. #define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27)
  3104. #define BNX2_RXP_CFTQ_CMD_ADD_DATA (1L<<28)
  3105. #define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29)
  3106. #define BNX2_RXP_CFTQ_CMD_POP (1L<<30)
  3107. #define BNX2_RXP_CFTQ_CMD_BUSY (1L<<31)
  3108. #define BNX2_RXP_CFTQ_CTL 0x000c53bc
  3109. #define BNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0)
  3110. #define BNX2_RXP_CFTQ_CTL_OVERFLOW (1L<<1)
  3111. #define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2)
  3112. #define BNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  3113. #define BNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  3114. #define BNX2_RXP_FTQ_DATA 0x000c53c0
  3115. #define BNX2_RXP_FTQ_CMD 0x000c53f8
  3116. #define BNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0)
  3117. #define BNX2_RXP_FTQ_CMD_WR_TOP (1L<<10)
  3118. #define BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
  3119. #define BNX2_RXP_FTQ_CMD_WR_TOP_1 (1L<<10)
  3120. #define BNX2_RXP_FTQ_CMD_SFT_RESET (1L<<25)
  3121. #define BNX2_RXP_FTQ_CMD_RD_DATA (1L<<26)
  3122. #define BNX2_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
  3123. #define BNX2_RXP_FTQ_CMD_ADD_DATA (1L<<28)
  3124. #define BNX2_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
  3125. #define BNX2_RXP_FTQ_CMD_POP (1L<<30)
  3126. #define BNX2_RXP_FTQ_CMD_BUSY (1L<<31)
  3127. #define BNX2_RXP_FTQ_CTL 0x000c53fc
  3128. #define BNX2_RXP_FTQ_CTL_INTERVENE (1L<<0)
  3129. #define BNX2_RXP_FTQ_CTL_OVERFLOW (1L<<1)
  3130. #define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  3131. #define BNX2_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  3132. #define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  3133. #define BNX2_RXP_SCRATCH 0x000e0000
  3134. /*
  3135. * com_reg definition
  3136. * offset: 0x100000
  3137. */
  3138. #define BNX2_COM_CPU_MODE 0x00105000
  3139. #define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0)
  3140. #define BNX2_COM_CPU_MODE_STEP_ENA (1L<<1)
  3141. #define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
  3142. #define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
  3143. #define BNX2_COM_CPU_MODE_MSG_BIT1 (1L<<6)
  3144. #define BNX2_COM_CPU_MODE_INTERRUPT_ENA (1L<<7)
  3145. #define BNX2_COM_CPU_MODE_SOFT_HALT (1L<<10)
  3146. #define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
  3147. #define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
  3148. #define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
  3149. #define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
  3150. #define BNX2_COM_CPU_STATE 0x00105004
  3151. #define BNX2_COM_CPU_STATE_BREAKPOINT (1L<<0)
  3152. #define BNX2_COM_CPU_STATE_BAD_INST_HALTED (1L<<2)
  3153. #define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
  3154. #define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
  3155. #define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
  3156. #define BNX2_COM_CPU_STATE_BAD_pc_HALTED (1L<<6)
  3157. #define BNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
  3158. #define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
  3159. #define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10)
  3160. #define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
  3161. #define BNX2_COM_CPU_STATE_INTERRRUPT (1L<<12)
  3162. #define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
  3163. #define BNX2_COM_CPU_STATE_INST_FETCH_STALL (1L<<15)
  3164. #define BNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31)
  3165. #define BNX2_COM_CPU_EVENT_MASK 0x00105008
  3166. #define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
  3167. #define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
  3168. #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
  3169. #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
  3170. #define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
  3171. #define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
  3172. #define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
  3173. #define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
  3174. #define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
  3175. #define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
  3176. #define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
  3177. #define BNX2_COM_CPU_PROGRAM_COUNTER 0x0010501c
  3178. #define BNX2_COM_CPU_INSTRUCTION 0x00105020
  3179. #define BNX2_COM_CPU_DATA_ACCESS 0x00105024
  3180. #define BNX2_COM_CPU_INTERRUPT_ENABLE 0x00105028
  3181. #define BNX2_COM_CPU_INTERRUPT_VECTOR 0x0010502c
  3182. #define BNX2_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
  3183. #define BNX2_COM_CPU_HW_BREAKPOINT 0x00105034
  3184. #define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
  3185. #define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
  3186. #define BNX2_COM_CPU_DEBUG_VECT_PEEK 0x00105038
  3187. #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  3188. #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  3189. #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  3190. #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  3191. #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  3192. #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  3193. #define BNX2_COM_CPU_LAST_BRANCH_ADDR 0x00105048
  3194. #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
  3195. #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
  3196. #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
  3197. #define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
  3198. #define BNX2_COM_CPU_REG_FILE 0x00105200
  3199. #define BNX2_COM_COMXQ_FTQ_DATA 0x00105340
  3200. #define BNX2_COM_COMXQ_FTQ_CMD 0x00105378
  3201. #define BNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
  3202. #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
  3203. #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
  3204. #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
  3205. #define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)
  3206. #define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26)
  3207. #define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
  3208. #define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28)
  3209. #define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
  3210. #define BNX2_COM_COMXQ_FTQ_CMD_POP (1L<<30)
  3211. #define BNX2_COM_COMXQ_FTQ_CMD_BUSY (1L<<31)
  3212. #define BNX2_COM_COMXQ_FTQ_CTL 0x0010537c
  3213. #define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
  3214. #define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1)
  3215. #define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  3216. #define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  3217. #define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  3218. #define BNX2_COM_COMTQ_FTQ_DATA 0x00105380
  3219. #define BNX2_COM_COMTQ_FTQ_CMD 0x001053b8
  3220. #define BNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0)
  3221. #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
  3222. #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
  3223. #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10)
  3224. #define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25)
  3225. #define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26)
  3226. #define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
  3227. #define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28)
  3228. #define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
  3229. #define BNX2_COM_COMTQ_FTQ_CMD_POP (1L<<30)
  3230. #define BNX2_COM_COMTQ_FTQ_CMD_BUSY (1L<<31)
  3231. #define BNX2_COM_COMTQ_FTQ_CTL 0x001053bc
  3232. #define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
  3233. #define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1)
  3234. #define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  3235. #define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  3236. #define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  3237. #define BNX2_COM_COMQ_FTQ_DATA 0x001053c0
  3238. #define BNX2_COM_COMQ_FTQ_CMD 0x001053f8
  3239. #define BNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0)
  3240. #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
  3241. #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
  3242. #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10)
  3243. #define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25)
  3244. #define BNX2_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26)
  3245. #define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
  3246. #define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28)
  3247. #define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
  3248. #define BNX2_COM_COMQ_FTQ_CMD_POP (1L<<30)
  3249. #define BNX2_COM_COMQ_FTQ_CMD_BUSY (1L<<31)
  3250. #define BNX2_COM_COMQ_FTQ_CTL 0x001053fc
  3251. #define BNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
  3252. #define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1)
  3253. #define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  3254. #define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  3255. #define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  3256. #define BNX2_COM_SCRATCH 0x00120000
  3257. /*
  3258. * cp_reg definition
  3259. * offset: 0x180000
  3260. */
  3261. #define BNX2_CP_CPU_MODE 0x00185000
  3262. #define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0)
  3263. #define BNX2_CP_CPU_MODE_STEP_ENA (1L<<1)
  3264. #define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
  3265. #define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
  3266. #define BNX2_CP_CPU_MODE_MSG_BIT1 (1L<<6)
  3267. #define BNX2_CP_CPU_MODE_INTERRUPT_ENA (1L<<7)
  3268. #define BNX2_CP_CPU_MODE_SOFT_HALT (1L<<10)
  3269. #define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
  3270. #define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
  3271. #define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
  3272. #define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
  3273. #define BNX2_CP_CPU_STATE 0x00185004
  3274. #define BNX2_CP_CPU_STATE_BREAKPOINT (1L<<0)
  3275. #define BNX2_CP_CPU_STATE_BAD_INST_HALTED (1L<<2)
  3276. #define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
  3277. #define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
  3278. #define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
  3279. #define BNX2_CP_CPU_STATE_BAD_pc_HALTED (1L<<6)
  3280. #define BNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
  3281. #define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
  3282. #define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10)
  3283. #define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
  3284. #define BNX2_CP_CPU_STATE_INTERRRUPT (1L<<12)
  3285. #define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
  3286. #define BNX2_CP_CPU_STATE_INST_FETCH_STALL (1L<<15)
  3287. #define BNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31)
  3288. #define BNX2_CP_CPU_EVENT_MASK 0x00185008
  3289. #define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
  3290. #define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
  3291. #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
  3292. #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
  3293. #define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
  3294. #define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
  3295. #define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
  3296. #define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
  3297. #define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
  3298. #define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
  3299. #define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
  3300. #define BNX2_CP_CPU_PROGRAM_COUNTER 0x0018501c
  3301. #define BNX2_CP_CPU_INSTRUCTION 0x00185020
  3302. #define BNX2_CP_CPU_DATA_ACCESS 0x00185024
  3303. #define BNX2_CP_CPU_INTERRUPT_ENABLE 0x00185028
  3304. #define BNX2_CP_CPU_INTERRUPT_VECTOR 0x0018502c
  3305. #define BNX2_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
  3306. #define BNX2_CP_CPU_HW_BREAKPOINT 0x00185034
  3307. #define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
  3308. #define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
  3309. #define BNX2_CP_CPU_DEBUG_VECT_PEEK 0x00185038
  3310. #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  3311. #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  3312. #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  3313. #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  3314. #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  3315. #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  3316. #define BNX2_CP_CPU_LAST_BRANCH_ADDR 0x00185048
  3317. #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
  3318. #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
  3319. #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
  3320. #define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
  3321. #define BNX2_CP_CPU_REG_FILE 0x00185200
  3322. #define BNX2_CP_CPQ_FTQ_DATA 0x001853c0
  3323. #define BNX2_CP_CPQ_FTQ_CMD 0x001853f8
  3324. #define BNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
  3325. #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
  3326. #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
  3327. #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
  3328. #define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)
  3329. #define BNX2_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26)
  3330. #define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
  3331. #define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28)
  3332. #define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
  3333. #define BNX2_CP_CPQ_FTQ_CMD_POP (1L<<30)
  3334. #define BNX2_CP_CPQ_FTQ_CMD_BUSY (1L<<31)
  3335. #define BNX2_CP_CPQ_FTQ_CTL 0x001853fc
  3336. #define BNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
  3337. #define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1)
  3338. #define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  3339. #define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  3340. #define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  3341. #define BNX2_CP_SCRATCH 0x001a0000
  3342. /*
  3343. * mcp_reg definition
  3344. * offset: 0x140000
  3345. */
  3346. #define BNX2_MCP_CPU_MODE 0x00145000
  3347. #define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0)
  3348. #define BNX2_MCP_CPU_MODE_STEP_ENA (1L<<1)
  3349. #define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
  3350. #define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
  3351. #define BNX2_MCP_CPU_MODE_MSG_BIT1 (1L<<6)
  3352. #define BNX2_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7)
  3353. #define BNX2_MCP_CPU_MODE_SOFT_HALT (1L<<10)
  3354. #define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
  3355. #define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
  3356. #define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
  3357. #define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
  3358. #define BNX2_MCP_CPU_STATE 0x00145004
  3359. #define BNX2_MCP_CPU_STATE_BREAKPOINT (1L<<0)
  3360. #define BNX2_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2)
  3361. #define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
  3362. #define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
  3363. #define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
  3364. #define BNX2_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6)
  3365. #define BNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
  3366. #define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
  3367. #define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
  3368. #define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
  3369. #define BNX2_MCP_CPU_STATE_INTERRRUPT (1L<<12)
  3370. #define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
  3371. #define BNX2_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15)
  3372. #define BNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31)
  3373. #define BNX2_MCP_CPU_EVENT_MASK 0x00145008
  3374. #define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
  3375. #define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
  3376. #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
  3377. #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
  3378. #define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
  3379. #define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
  3380. #define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
  3381. #define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
  3382. #define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
  3383. #define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
  3384. #define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
  3385. #define BNX2_MCP_CPU_PROGRAM_COUNTER 0x0014501c
  3386. #define BNX2_MCP_CPU_INSTRUCTION 0x00145020
  3387. #define BNX2_MCP_CPU_DATA_ACCESS 0x00145024
  3388. #define BNX2_MCP_CPU_INTERRUPT_ENABLE 0x00145028
  3389. #define BNX2_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
  3390. #define BNX2_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
  3391. #define BNX2_MCP_CPU_HW_BREAKPOINT 0x00145034
  3392. #define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
  3393. #define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
  3394. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK 0x00145038
  3395. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  3396. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  3397. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  3398. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  3399. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  3400. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  3401. #define BNX2_MCP_CPU_LAST_BRANCH_ADDR 0x00145048
  3402. #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
  3403. #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
  3404. #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
  3405. #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
  3406. #define BNX2_MCP_CPU_REG_FILE 0x00145200
  3407. #define BNX2_MCP_MCPQ_FTQ_DATA 0x001453c0
  3408. #define BNX2_MCP_MCPQ_FTQ_CMD 0x001453f8
  3409. #define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
  3410. #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
  3411. #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
  3412. #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
  3413. #define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
  3414. #define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
  3415. #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
  3416. #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
  3417. #define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
  3418. #define BNX2_MCP_MCPQ_FTQ_CMD_POP (1L<<30)
  3419. #define BNX2_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31)
  3420. #define BNX2_MCP_MCPQ_FTQ_CTL 0x001453fc
  3421. #define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
  3422. #define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
  3423. #define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  3424. #define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  3425. #define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  3426. #define BNX2_MCP_ROM 0x00150000
  3427. #define BNX2_MCP_SCRATCH 0x00160000
  3428. #define BNX2_SHM_HDR_SIGNATURE BNX2_MCP_SCRATCH
  3429. #define BNX2_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000
  3430. #define BNX2_SHM_HDR_SIGNATURE_SIG 0x53530000
  3431. #define BNX2_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff
  3432. #define BNX2_SHM_HDR_SIGNATURE_VER_ONE 0x00000001
  3433. #define BNX2_SHM_HDR_ADDR_0 BNX2_MCP_SCRATCH + 4
  3434. #define BNX2_SHM_HDR_ADDR_1 BNX2_MCP_SCRATCH + 8
  3435. #define NUM_MC_HASH_REGISTERS 8
  3436. /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
  3437. #define PHY_BCM5706_PHY_ID 0x00206160
  3438. #define PHY_ID(id) ((id) & 0xfffffff0)
  3439. #define PHY_REV_ID(id) ((id) & 0xf)
  3440. /* 5708 Serdes PHY registers */
  3441. #define BCM5708S_UP1 0xb
  3442. #define BCM5708S_UP1_2G5 0x1
  3443. #define BCM5708S_BLK_ADDR 0x1f
  3444. #define BCM5708S_BLK_ADDR_DIG 0x0000
  3445. #define BCM5708S_BLK_ADDR_DIG3 0x0002
  3446. #define BCM5708S_BLK_ADDR_TX_MISC 0x0005
  3447. /* Digital Block */
  3448. #define BCM5708S_1000X_CTL1 0x10
  3449. #define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001
  3450. #define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010
  3451. #define BCM5708S_1000X_CTL2 0x11
  3452. #define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001
  3453. #define BCM5708S_1000X_STAT1 0x14
  3454. #define BCM5708S_1000X_STAT1_SGMII 0x0001
  3455. #define BCM5708S_1000X_STAT1_LINK 0x0002
  3456. #define BCM5708S_1000X_STAT1_FD 0x0004
  3457. #define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018
  3458. #define BCM5708S_1000X_STAT1_SPEED_10 0x0000
  3459. #define BCM5708S_1000X_STAT1_SPEED_100 0x0008
  3460. #define BCM5708S_1000X_STAT1_SPEED_1G 0x0010
  3461. #define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018
  3462. #define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020
  3463. #define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040
  3464. /* Digital3 Block */
  3465. #define BCM5708S_DIG_3_0 0x10
  3466. #define BCM5708S_DIG_3_0_USE_IEEE 0x0001
  3467. /* Tx/Misc Block */
  3468. #define BCM5708S_TX_ACTL1 0x15
  3469. #define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30
  3470. #define BCM5708S_TX_ACTL3 0x17
  3471. #define MIN_ETHERNET_PACKET_SIZE 60
  3472. #define MAX_ETHERNET_PACKET_SIZE 1514
  3473. #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
  3474. #define RX_COPY_THRESH 92
  3475. #define DMA_READ_CHANS 5
  3476. #define DMA_WRITE_CHANS 3
  3477. #define BCM_PAGE_BITS 12
  3478. #define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
  3479. #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd))
  3480. #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
  3481. #define MAX_RX_RINGS 4
  3482. #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd))
  3483. #define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
  3484. #define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS)
  3485. #define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \
  3486. (MAX_TX_DESC_CNT - 1)) ? \
  3487. (x) + 2 : (x) + 1
  3488. #define PREV_TX_BD(x) ((((x)-1) & (MAX_TX_DESC_CNT)) == \
  3489. (MAX_TX_DESC_CNT)) ? \
  3490. (x) - 2 : (x) - 1
  3491. #define TX_RING_IDX(x) ((x) & MAX_TX_DESC_CNT)
  3492. #define NEXT_RX_BD(x) (((x) & (MAX_RX_DESC_CNT - 1)) == \
  3493. (MAX_RX_DESC_CNT - 1)) ? \
  3494. (x) + 2 : (x) + 1
  3495. #define RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)
  3496. //#define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> 8)
  3497. #define RX_IDX(x) ((x) & MAX_RX_DESC_CNT)
  3498. /* Context size. */
  3499. #define CTX_SHIFT 7
  3500. #define CTX_SIZE (1 << CTX_SHIFT)
  3501. #define CTX_MASK (CTX_SIZE - 1)
  3502. #define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT)
  3503. #define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT)
  3504. #define PHY_CTX_SHIFT 6
  3505. #define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT)
  3506. #define PHY_CTX_MASK (PHY_CTX_SIZE - 1)
  3507. #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT)
  3508. #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT)
  3509. #define MB_KERNEL_CTX_SHIFT 8
  3510. #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT)
  3511. #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1)
  3512. #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
  3513. #define MAX_CID_CNT 0x4000
  3514. #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
  3515. #define INVALID_CID_ADDR 0xffffffff
  3516. #define TX_CID 16
  3517. #define RX_CID 0
  3518. #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
  3519. #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
  3520. #if 0
  3521. struct sw_bd {
  3522. struct sk_buff *skb;
  3523. DECLARE_PCI_UNMAP_ADDR(mapping)
  3524. };
  3525. #endif
  3526. /* Buffered flash (Atmel: AT45DB011B) specific information */
  3527. #define SEEPROM_PAGE_BITS 2
  3528. #define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS)
  3529. #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1)
  3530. #define SEEPROM_PAGE_SIZE 4
  3531. #define SEEPROM_TOTAL_SIZE 65536
  3532. #define BUFFERED_FLASH_PAGE_BITS 9
  3533. #define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS)
  3534. #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
  3535. #define BUFFERED_FLASH_PAGE_SIZE 264
  3536. #define BUFFERED_FLASH_TOTAL_SIZE 0x21000
  3537. #define SAIFUN_FLASH_PAGE_BITS 8
  3538. #define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS)
  3539. #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
  3540. #define SAIFUN_FLASH_PAGE_SIZE 256
  3541. #define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
  3542. #define ST_MICRO_FLASH_PAGE_BITS 8
  3543. #define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS)
  3544. #define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
  3545. #define ST_MICRO_FLASH_PAGE_SIZE 256
  3546. #define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536
  3547. #define NVRAM_TIMEOUT_COUNT 30000
  3548. #define FLASH_STRAP_MASK (BNX2_NVM_CFG1_FLASH_MODE | \
  3549. BNX2_NVM_CFG1_BUFFER_MODE | \
  3550. BNX2_NVM_CFG1_PROTECT_MODE | \
  3551. BNX2_NVM_CFG1_FLASH_SIZE)
  3552. #define FLASH_BACKUP_STRAP_MASK (0xf << 26)
  3553. struct flash_spec {
  3554. u32 strapping;
  3555. u32 config1;
  3556. u32 config2;
  3557. u32 config3;
  3558. u32 write1;
  3559. u32 buffered;
  3560. u32 page_bits;
  3561. u32 page_size;
  3562. u32 addr_mask;
  3563. u32 total_size;
  3564. char *name;
  3565. };
  3566. struct bnx2 {
  3567. /* Fields used in the tx and intr/napi performance paths are grouped */
  3568. /* together in the beginning of the structure. */
  3569. void /*__iomem*/ *regview;
  3570. struct nic *nic;
  3571. struct pci_device *pdev;
  3572. /* atomic_t intr_sem; */
  3573. struct status_block *status_blk;
  3574. u32 last_status_idx;
  3575. u32 flags;
  3576. #define PCIX_FLAG 1
  3577. #define PCI_32BIT_FLAG 2
  3578. #define ONE_TDMA_FLAG 4 /* no longer used */
  3579. #define NO_WOL_FLAG 8
  3580. #define USING_DAC_FLAG 0x10
  3581. #define USING_MSI_FLAG 0x20
  3582. #define ASF_ENABLE_FLAG 0x40
  3583. /* Put tx producer and consumer fields in separate cache lines. */
  3584. u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
  3585. u16 tx_prod;
  3586. struct tx_bd *tx_desc_ring;
  3587. struct sw_bd *tx_buf_ring;
  3588. int tx_ring_size;
  3589. u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
  3590. u16 hw_tx_cons;
  3591. #ifdef BCM_VLAN
  3592. struct vlan_group *vlgrp;
  3593. #endif
  3594. u32 rx_offset;
  3595. u32 rx_buf_use_size; /* useable size */
  3596. u32 rx_buf_size; /* with alignment */
  3597. u32 rx_max_ring_idx;
  3598. u32 rx_prod_bseq;
  3599. u16 rx_prod;
  3600. u16 rx_cons;
  3601. u16 hw_rx_cons;
  3602. u32 rx_csum;
  3603. #if 0
  3604. struct rx_bd *rx_desc_ring[MAX_RX_RINGS];
  3605. #endif
  3606. struct rx_bd *rx_desc_ring;
  3607. /* End of fields used in the performance code paths. */
  3608. char *name;
  3609. #if 0
  3610. int timer_interval;
  3611. int current_interval;
  3612. struct timer_list timer;
  3613. struct work_struct reset_task;
  3614. int in_reset_task;
  3615. /* Used to synchronize phy accesses. */
  3616. spinlock_t phy_lock;
  3617. #endif
  3618. u32 phy_flags;
  3619. #define PHY_SERDES_FLAG 1
  3620. #define PHY_CRC_FIX_FLAG 2
  3621. #define PHY_PARALLEL_DETECT_FLAG 4
  3622. #define PHY_2_5G_CAPABLE_FLAG 8
  3623. #define PHY_INT_MODE_MASK_FLAG 0x300
  3624. #define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
  3625. #define PHY_INT_MODE_LINK_READY_FLAG 0x200
  3626. u32 chip_id;
  3627. /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
  3628. #define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
  3629. #define CHIP_NUM_5706 0x57060000
  3630. #define CHIP_NUM_5708 0x57080000
  3631. #define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
  3632. #define CHIP_REV_Ax 0x00000000
  3633. #define CHIP_REV_Bx 0x00001000
  3634. #define CHIP_REV_Cx 0x00002000
  3635. #define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
  3636. #define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f)
  3637. #define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
  3638. #define CHIP_ID_5706_A0 0x57060000
  3639. #define CHIP_ID_5706_A1 0x57060010
  3640. #define CHIP_ID_5706_A2 0x57060020
  3641. #define CHIP_ID_5708_A0 0x57080000
  3642. #define CHIP_ID_5708_B0 0x57081000
  3643. #define CHIP_ID_5708_B1 0x57081010
  3644. #define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf)
  3645. /* A serdes chip will have the first bit of the bond id set. */
  3646. #define CHIP_BOND_ID_SERDES_BIT 0x01
  3647. u32 phy_addr;
  3648. u32 phy_id;
  3649. u16 bus_speed_mhz;
  3650. u8 wol;
  3651. u8 pad;
  3652. u16 fw_wr_seq;
  3653. u16 fw_drv_pulse_wr_seq;
  3654. dma_addr_t tx_desc_mapping;
  3655. int rx_max_ring;
  3656. int rx_ring_size;
  3657. #if 0
  3658. dma_addr_t rx_desc_mapping[MAX_RX_RINGS];
  3659. #endif
  3660. dma_addr_t rx_desc_mapping;
  3661. u16 tx_quick_cons_trip;
  3662. u16 tx_quick_cons_trip_int;
  3663. u16 rx_quick_cons_trip;
  3664. u16 rx_quick_cons_trip_int;
  3665. u16 comp_prod_trip;
  3666. u16 comp_prod_trip_int;
  3667. u16 tx_ticks;
  3668. u16 tx_ticks_int;
  3669. u16 com_ticks;
  3670. u16 com_ticks_int;
  3671. u16 cmd_ticks;
  3672. u16 cmd_ticks_int;
  3673. u16 rx_ticks;
  3674. u16 rx_ticks_int;
  3675. u32 stats_ticks;
  3676. dma_addr_t status_blk_mapping;
  3677. struct statistics_block *stats_blk;
  3678. dma_addr_t stats_blk_mapping;
  3679. u32 hc_cmd;
  3680. u32 rx_mode;
  3681. u16 req_line_speed;
  3682. u8 req_duplex;
  3683. u8 link_up;
  3684. u16 line_speed;
  3685. u8 duplex;
  3686. u8 flow_ctrl; /* actual flow ctrl settings */
  3687. /* may be different from */
  3688. /* req_flow_ctrl if autoneg */
  3689. #define FLOW_CTRL_TX 1
  3690. #define FLOW_CTRL_RX 2
  3691. u32 advertising;
  3692. u8 req_flow_ctrl; /* flow ctrl advertisement */
  3693. /* settings or forced */
  3694. /* settings */
  3695. u8 autoneg;
  3696. #define AUTONEG_SPEED 1
  3697. #define AUTONEG_FLOW_CTRL 2
  3698. u8 loopback;
  3699. #define MAC_LOOPBACK 1
  3700. #define PHY_LOOPBACK 2
  3701. u8 serdes_an_pending;
  3702. #define SERDES_AN_TIMEOUT (HZ / 3)
  3703. u8 mac_addr[8];
  3704. u32 shmem_base;
  3705. u32 fw_ver;
  3706. int pm_cap;
  3707. int pcix_cap;
  3708. /* struct net_device_stats net_stats; */
  3709. struct flash_spec *flash_info;
  3710. u32 flash_size;
  3711. int status_stats_size;
  3712. };
  3713. static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
  3714. static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val);
  3715. #define REG_RD(bp, offset) \
  3716. readl(bp->regview + offset)
  3717. #define REG_WR(bp, offset, val) \
  3718. writel(val, bp->regview + offset)
  3719. #define REG_WR16(bp, offset, val) \
  3720. writew(val, bp->regview + offset)
  3721. #define REG_RD_IND(bp, offset) \
  3722. bnx2_reg_rd_ind(bp, offset)
  3723. #define REG_WR_IND(bp, offset, val) \
  3724. bnx2_reg_wr_ind(bp, offset, val)
  3725. /* Indirect context access. Unlike the MBQ_WR, these macros will not
  3726. * trigger a chip event. */
  3727. static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val);
  3728. #define CTX_WR(bp, cid_addr, offset, val) \
  3729. bnx2_ctx_wr(bp, cid_addr, offset, val)
  3730. struct cpu_reg {
  3731. u32 mode;
  3732. u32 mode_value_halt;
  3733. u32 mode_value_sstep;
  3734. u32 state;
  3735. u32 state_value_clear;
  3736. u32 gpr0;
  3737. u32 evmask;
  3738. u32 pc;
  3739. u32 inst;
  3740. u32 bp;
  3741. u32 spad_base;
  3742. u32 mips_view_base;
  3743. };
  3744. struct fw_info {
  3745. u32 ver_major;
  3746. u32 ver_minor;
  3747. u32 ver_fix;
  3748. u32 start_addr;
  3749. /* Text section. */
  3750. u32 text_addr;
  3751. u32 text_len;
  3752. u32 text_index;
  3753. u32 *text;
  3754. /* Data section. */
  3755. u32 data_addr;
  3756. u32 data_len;
  3757. u32 data_index;
  3758. u32 *data;
  3759. /* SBSS section. */
  3760. u32 sbss_addr;
  3761. u32 sbss_len;
  3762. u32 sbss_index;
  3763. u32 *sbss;
  3764. /* BSS section. */
  3765. u32 bss_addr;
  3766. u32 bss_len;
  3767. u32 bss_index;
  3768. u32 *bss;
  3769. /* Read-only section. */
  3770. u32 rodata_addr;
  3771. u32 rodata_len;
  3772. u32 rodata_index;
  3773. u32 *rodata;
  3774. };
  3775. #define RV2P_PROC1 0
  3776. #define RV2P_PROC2 1
  3777. /* This value (in milliseconds) determines the frequency of the driver
  3778. * issuing the PULSE message code. The firmware monitors this periodic
  3779. * pulse to determine when to switch to an OS-absent mode. */
  3780. #define DRV_PULSE_PERIOD_MS 250
  3781. /* This value (in milliseconds) determines how long the driver should
  3782. * wait for an acknowledgement from the firmware before timing out. Once
  3783. * the firmware has timed out, the driver will assume there is no firmware
  3784. * running and there won't be any firmware-driver synchronization during a
  3785. * driver reset. */
  3786. #define FW_ACK_TIME_OUT_MS 100
  3787. #define BNX2_DRV_RESET_SIGNATURE 0x00000000
  3788. #define BNX2_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
  3789. //#define DRV_RESET_SIGNATURE_MAGIC 0x47495352 /* RSIG */
  3790. #define BNX2_DRV_MB 0x00000004
  3791. #define BNX2_DRV_MSG_CODE 0xff000000
  3792. #define BNX2_DRV_MSG_CODE_RESET 0x01000000
  3793. #define BNX2_DRV_MSG_CODE_UNLOAD 0x02000000
  3794. #define BNX2_DRV_MSG_CODE_SHUTDOWN 0x03000000
  3795. #define BNX2_DRV_MSG_CODE_SUSPEND_WOL 0x04000000
  3796. #define BNX2_DRV_MSG_CODE_FW_TIMEOUT 0x05000000
  3797. #define BNX2_DRV_MSG_CODE_PULSE 0x06000000
  3798. #define BNX2_DRV_MSG_CODE_DIAG 0x07000000
  3799. #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
  3800. #define BNX2_DRV_MSG_DATA 0x00ff0000
  3801. #define BNX2_DRV_MSG_DATA_WAIT0 0x00010000
  3802. #define BNX2_DRV_MSG_DATA_WAIT1 0x00020000
  3803. #define BNX2_DRV_MSG_DATA_WAIT2 0x00030000
  3804. #define BNX2_DRV_MSG_DATA_WAIT3 0x00040000
  3805. #define BNX2_DRV_MSG_SEQ 0x0000ffff
  3806. #define BNX2_FW_MB 0x00000008
  3807. #define BNX2_FW_MSG_ACK 0x0000ffff
  3808. #define BNX2_FW_MSG_STATUS_MASK 0x00ff0000
  3809. #define BNX2_FW_MSG_STATUS_OK 0x00000000
  3810. #define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000
  3811. #define BNX2_LINK_STATUS 0x0000000c
  3812. #define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff
  3813. #define BNX2_LINK_STATUS_LINK_UP 0x1
  3814. #define BNX2_LINK_STATUS_LINK_DOWN 0x0
  3815. #define BNX2_LINK_STATUS_SPEED_MASK 0x1e
  3816. #define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1)
  3817. #define BNX2_LINK_STATUS_10HALF (1<<1)
  3818. #define BNX2_LINK_STATUS_10FULL (2<<1)
  3819. #define BNX2_LINK_STATUS_100HALF (3<<1)
  3820. #define BNX2_LINK_STATUS_100BASE_T4 (4<<1)
  3821. #define BNX2_LINK_STATUS_100FULL (5<<1)
  3822. #define BNX2_LINK_STATUS_1000HALF (6<<1)
  3823. #define BNX2_LINK_STATUS_1000FULL (7<<1)
  3824. #define BNX2_LINK_STATUS_2500HALF (8<<1)
  3825. #define BNX2_LINK_STATUS_2500FULL (9<<1)
  3826. #define BNX2_LINK_STATUS_AN_ENABLED (1<<5)
  3827. #define BNX2_LINK_STATUS_AN_COMPLETE (1<<6)
  3828. #define BNX2_LINK_STATUS_PARALLEL_DET (1<<7)
  3829. #define BNX2_LINK_STATUS_RESERVED (1<<8)
  3830. #define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9)
  3831. #define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10)
  3832. #define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11)
  3833. #define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12)
  3834. #define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13)
  3835. #define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14)
  3836. #define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15)
  3837. #define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16)
  3838. #define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17)
  3839. #define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18)
  3840. #define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19)
  3841. #define BNX2_LINK_STATUS_SERDES_LINK (1<<20)
  3842. #define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21)
  3843. #define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22)
  3844. #define BNX2_DRV_PULSE_MB 0x00000010
  3845. #define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff
  3846. /* Indicate to the firmware not to go into the
  3847. * OS absent when it is not getting driver pulse.
  3848. * This is used for debugging. */
  3849. #define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000
  3850. #define BNX2_DEV_INFO_SIGNATURE 0x00000020
  3851. #define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900
  3852. #define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00
  3853. #define BNX2_DEV_INFO_FEATURE_CFG_VALID 0x01
  3854. #define BNX2_DEV_INFO_SECONDARY_PORT 0x80
  3855. #define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE 0x40
  3856. #define BNX2_SHARED_HW_CFG_PART_NUM 0x00000024
  3857. #define BNX2_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034
  3858. #define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000
  3859. #define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000
  3860. #define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00
  3861. #define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff
  3862. #define BNX2_SHARED_HW_CFG POWER_CONSUMED 0x00000038
  3863. #define BNX2_SHARED_HW_CFG_CONFIG 0x0000003c
  3864. #define BNX2_SHARED_HW_CFG_DESIGN_NIC 0
  3865. #define BNX2_SHARED_HW_CFG_DESIGN_LOM 0x1
  3866. #define BNX2_SHARED_HW_CFG_PHY_COPPER 0
  3867. #define BNX2_SHARED_HW_CFG_PHY_FIBER 0x2
  3868. #define BNX2_SHARED_HW_CFG_PHY_2_5G 0x20
  3869. #define BNX2_SHARED_HW_CFG_PHY_BACKPLANE 0x40
  3870. #define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8
  3871. #define BNX2_SHARED_HW_CFG_LED_MODE_MASK 0x300
  3872. #define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0
  3873. #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1 0x100
  3874. #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2 0x200
  3875. #define BNX2_SHARED_HW_CFG_CONFIG2 0x00000040
  3876. #define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000
  3877. #define BNX2_DEV_INFO_BC_REV 0x0000004c
  3878. #define BNX2_PORT_HW_CFG_MAC_UPPER 0x00000050
  3879. #define BNX2_PORT_HW_CFG_UPPERMAC_MASK 0xffff
  3880. #define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054
  3881. #define BNX2_PORT_HW_CFG_CONFIG 0x00000058
  3882. #define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff
  3883. #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000
  3884. #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000
  3885. #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000
  3886. #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000
  3887. #define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
  3888. #define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
  3889. #define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070
  3890. #define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074
  3891. #define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078
  3892. #define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c
  3893. #define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4
  3894. #define BNX2_DEV_INFO_FORMAT_REV 0x000000c4
  3895. #define BNX2_DEV_INFO_FORMAT_REV_MASK 0xff000000
  3896. #define BNX2_DEV_INFO_FORMAT_REV_ID ('A' << 24)
  3897. #define BNX2_SHARED_FEATURE 0x000000c8
  3898. #define BNX2_SHARED_FEATURE_MASK 0xffffffff
  3899. #define BNX2_PORT_FEATURE 0x000000d8
  3900. #define BNX2_PORT2_FEATURE 0x00000014c
  3901. #define BNX2_PORT_FEATURE_WOL_ENABLED 0x01000000
  3902. #define BNX2_PORT_FEATURE_MBA_ENABLED 0x02000000
  3903. #define BNX2_PORT_FEATURE_ASF_ENABLED 0x04000000
  3904. #define BNX2_PORT_FEATURE_IMD_ENABLED 0x08000000
  3905. #define BNX2_PORT_FEATURE_BAR1_SIZE_MASK 0xf
  3906. #define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0
  3907. #define BNX2_PORT_FEATURE_BAR1_SIZE_64K 0x1
  3908. #define BNX2_PORT_FEATURE_BAR1_SIZE_128K 0x2
  3909. #define BNX2_PORT_FEATURE_BAR1_SIZE_256K 0x3
  3910. #define BNX2_PORT_FEATURE_BAR1_SIZE_512K 0x4
  3911. #define BNX2_PORT_FEATURE_BAR1_SIZE_1M 0x5
  3912. #define BNX2_PORT_FEATURE_BAR1_SIZE_2M 0x6
  3913. #define BNX2_PORT_FEATURE_BAR1_SIZE_4M 0x7
  3914. #define BNX2_PORT_FEATURE_BAR1_SIZE_8M 0x8
  3915. #define BNX2_PORT_FEATURE_BAR1_SIZE_16M 0x9
  3916. #define BNX2_PORT_FEATURE_BAR1_SIZE_32M 0xa
  3917. #define BNX2_PORT_FEATURE_BAR1_SIZE_64M 0xb
  3918. #define BNX2_PORT_FEATURE_BAR1_SIZE_128M 0xc
  3919. #define BNX2_PORT_FEATURE_BAR1_SIZE_256M 0xd
  3920. #define BNX2_PORT_FEATURE_BAR1_SIZE_512M 0xe
  3921. #define BNX2_PORT_FEATURE_BAR1_SIZE_1G 0xf
  3922. #define BNX2_PORT_FEATURE_WOL 0xdc
  3923. #define BNX2_PORT2_FEATURE_WOL 0x150
  3924. #define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4
  3925. #define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK 0x30
  3926. #define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE 0
  3927. #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10
  3928. #define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20
  3929. #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30
  3930. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf
  3931. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0
  3932. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1
  3933. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2
  3934. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
  3935. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
  3936. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5
  3937. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6
  3938. #define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40
  3939. #define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
  3940. #define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800
  3941. #define BNX2_PORT_FEATURE_MBA 0xe0
  3942. #define BNX2_PORT2_FEATURE_MBA 0x154
  3943. #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0
  3944. #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3
  3945. #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0
  3946. #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1
  3947. #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2
  3948. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2
  3949. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c
  3950. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0
  3951. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4
  3952. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8
  3953. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc
  3954. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10
  3955. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
  3956. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
  3957. #define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
  3958. #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0
  3959. #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80
  3960. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8
  3961. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00
  3962. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0
  3963. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100
  3964. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200
  3965. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300
  3966. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400
  3967. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500
  3968. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600
  3969. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700
  3970. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800
  3971. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900
  3972. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00
  3973. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00
  3974. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00
  3975. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00
  3976. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00
  3977. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00
  3978. #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16
  3979. #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000
  3980. #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20
  3981. #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000
  3982. #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0
  3983. #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000
  3984. #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000
  3985. #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000
  3986. #define BNX2_PORT_FEATURE_IMD 0xe4
  3987. #define BNX2_PORT2_FEATURE_IMD 0x158
  3988. #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0
  3989. #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1
  3990. #define BNX2_PORT_FEATURE_VLAN 0xe8
  3991. #define BNX2_PORT2_FEATURE_VLAN 0x15c
  3992. #define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff
  3993. #define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000
  3994. #define BNX2_BC_STATE_RESET_TYPE 0x000001c0
  3995. #define BNX2_BC_STATE_RESET_TYPE_SIG 0x00005254
  3996. #define BNX2_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff
  3997. #define BNX2_BC_STATE_RESET_TYPE_NONE (BNX2_BC_STATE_RESET_TYPE_SIG | \
  3998. 0x00010000)
  3999. #define BNX2_BC_STATE_RESET_TYPE_PCI (BNX2_BC_STATE_RESET_TYPE_SIG | \
  4000. 0x00020000)
  4001. #define BNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \
  4002. 0x00030000)
  4003. #define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE
  4004. #define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \
  4005. DRV_MSG_CODE_RESET)
  4006. #define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \
  4007. DRV_MSG_CODE_UNLOAD)
  4008. #define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX2_BC_STATE_RESET_TYPE_SIG | \
  4009. DRV_MSG_CODE_SHUTDOWN)
  4010. #define BNX2_BC_STATE_RESET_TYPE_DRV_WOL (BNX2_BC_STATE_RESET_TYPE_SIG | \
  4011. DRV_MSG_CODE_WOL)
  4012. #define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG (BNX2_BC_STATE_RESET_TYPE_SIG | \
  4013. DRV_MSG_CODE_DIAG)
  4014. #define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) (BNX2_BC_STATE_RESET_TYPE_SIG | \
  4015. (msg))
  4016. #define BNX2_BC_STATE 0x000001c4
  4017. #define BNX2_BC_STATE_ERR_MASK 0x0000ff00
  4018. #define BNX2_BC_STATE_SIGN 0x42530000
  4019. #define BNX2_BC_STATE_SIGN_MASK 0xffff0000
  4020. #define BNX2_BC_STATE_BC1_START (BNX2_BC_STATE_SIGN | 0x1)
  4021. #define BNX2_BC_STATE_GET_NVM_CFG1 (BNX2_BC_STATE_SIGN | 0x2)
  4022. #define BNX2_BC_STATE_PROG_BAR (BNX2_BC_STATE_SIGN | 0x3)
  4023. #define BNX2_BC_STATE_INIT_VID (BNX2_BC_STATE_SIGN | 0x4)
  4024. #define BNX2_BC_STATE_GET_NVM_CFG2 (BNX2_BC_STATE_SIGN | 0x5)
  4025. #define BNX2_BC_STATE_APPLY_WKARND (BNX2_BC_STATE_SIGN | 0x6)
  4026. #define BNX2_BC_STATE_LOAD_BC2 (BNX2_BC_STATE_SIGN | 0x7)
  4027. #define BNX2_BC_STATE_GOING_BC2 (BNX2_BC_STATE_SIGN | 0x8)
  4028. #define BNX2_BC_STATE_GOING_DIAG (BNX2_BC_STATE_SIGN | 0x9)
  4029. #define BNX2_BC_STATE_RT_FINAL_INIT (BNX2_BC_STATE_SIGN | 0x81)
  4030. #define BNX2_BC_STATE_RT_WKARND (BNX2_BC_STATE_SIGN | 0x82)
  4031. #define BNX2_BC_STATE_RT_DRV_PULSE (BNX2_BC_STATE_SIGN | 0x83)
  4032. #define BNX2_BC_STATE_RT_FIOEVTS (BNX2_BC_STATE_SIGN | 0x84)
  4033. #define BNX2_BC_STATE_RT_DRV_CMD (BNX2_BC_STATE_SIGN | 0x85)
  4034. #define BNX2_BC_STATE_RT_LOW_POWER (BNX2_BC_STATE_SIGN | 0x86)
  4035. #define BNX2_BC_STATE_RT_SET_WOL (BNX2_BC_STATE_SIGN | 0x87)
  4036. #define BNX2_BC_STATE_RT_OTHER_FW (BNX2_BC_STATE_SIGN | 0x88)
  4037. #define BNX2_BC_STATE_RT_GOING_D3 (BNX2_BC_STATE_SIGN | 0x89)
  4038. #define BNX2_BC_STATE_ERR_BAD_VERSION (BNX2_BC_STATE_SIGN | 0x0100)
  4039. #define BNX2_BC_STATE_ERR_BAD_BC2_CRC (BNX2_BC_STATE_SIGN | 0x0200)
  4040. #define BNX2_BC_STATE_ERR_BC1_LOOP (BNX2_BC_STATE_SIGN | 0x0300)
  4041. #define BNX2_BC_STATE_ERR_UNKNOWN_CMD (BNX2_BC_STATE_SIGN | 0x0400)
  4042. #define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500)
  4043. #define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600)
  4044. #define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700)
  4045. #define BNX2_BC_STATE_DEBUG_CMD 0x1dc
  4046. #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000
  4047. #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000
  4048. #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff
  4049. #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff
  4050. #define HOST_VIEW_SHMEM_BASE 0x167c00
  4051. /* Enable or disable autonegotiation. If this is set to enable,
  4052. * the forced link modes above are completely ignored.
  4053. */
  4054. #define AUTONEG_DISABLE 0x00
  4055. #define AUTONEG_ENABLE 0x01
  4056. #define RX_OFFSET (sizeof(struct l2_fhdr) + 2)
  4057. #define RX_BUF_CNT 20
  4058. /* 8 for CRC and VLAN */
  4059. #define RX_BUF_USE_SIZE (ETH_MAX_MTU + ETH_HLEN + RX_OFFSET + 8)
  4060. /* 8 for alignment */
  4061. //#define RX_BUF_SIZE (RX_BUF_USE_SIZE + 8)
  4062. #define RX_BUF_SIZE (L1_CACHE_ALIGN(RX_BUF_USE_SIZE + 8))
  4063. #endif