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ath.h 6.1KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
  5. * Original from Linux kernel 3.0.1
  6. *
  7. * Permission to use, copy, modify, and/or distribute this software for any
  8. * purpose with or without fee is hereby granted, provided that the above
  9. * copyright notice and this permission notice appear in all copies.
  10. *
  11. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef ATH_H
  20. #define ATH_H
  21. FILE_LICENCE ( BSD2 );
  22. #include <unistd.h>
  23. #include <ipxe/net80211.h>
  24. /* This block of functions are from kernel.h v3.0.1 */
  25. #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
  26. #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
  27. #define BITS_PER_BYTE 8
  28. #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
  29. #define BIT(nr) (1UL << (nr))
  30. #define min(x, y) ({ \
  31. typeof(x) _min1 = (x); \
  32. typeof(y) _min2 = (y); \
  33. (void) (&_min1 == &_min2); \
  34. _min1 < _min2 ? _min1 : _min2; })
  35. #define max(x, y) ({ \
  36. typeof(x) _max1 = (x); \
  37. typeof(y) _max2 = (y); \
  38. (void) (&_max1 == &_max2); \
  39. _max1 > _max2 ? _max1 : _max2; })
  40. #define abs(x) ({ \
  41. long ret; \
  42. if (sizeof(x) == sizeof(long)) { \
  43. long __x = (x); \
  44. ret = (__x < 0) ? -__x : __x; \
  45. } else { \
  46. int __x = (x); \
  47. ret = (__x < 0) ? -__x : __x; \
  48. } \
  49. ret; \
  50. })
  51. #define ___constant_swab16(x) ((uint16_t)( \
  52. (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \
  53. (((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
  54. #define ___constant_swab32(x) ((uint32_t)( \
  55. (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \
  56. (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \
  57. (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \
  58. (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
  59. #define __swab16(x) ___constant_swab16(x)
  60. #define __swab32(x) ___constant_swab32(x)
  61. #define swab16 __swab16
  62. #define swab32 __swab32
  63. static inline int32_t sign_extend32(uint32_t value, int index)
  64. {
  65. uint8_t shift = 31 - index;
  66. return (int32_t)(value << shift) >> shift;
  67. }
  68. static inline u16 __get_unaligned_le16(const u8 *p)
  69. {
  70. return p[0] | p[1] << 8;
  71. }
  72. static inline u32 __get_unaligned_le32(const u8 *p)
  73. {
  74. return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24;
  75. }
  76. static inline u16 get_unaligned_le16(const void *p)
  77. {
  78. return __get_unaligned_le16((const u8 *)p);
  79. }
  80. static inline u32 get_unaligned_le32(const void *p)
  81. {
  82. return __get_unaligned_le32((const u8 *)p);
  83. }
  84. /* End Kernel Block */
  85. /*
  86. * The key cache is used for h/w cipher state and also for
  87. * tracking station state such as the current tx antenna.
  88. * We also setup a mapping table between key cache slot indices
  89. * and station state to short-circuit node lookups on rx.
  90. * Different parts have different size key caches. We handle
  91. * up to ATH_KEYMAX entries (could dynamically allocate state).
  92. */
  93. #define ATH_KEYMAX 128 /* max key cache size we handle */
  94. static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  95. struct ath_ani {
  96. int caldone;
  97. unsigned int longcal_timer;
  98. unsigned int shortcal_timer;
  99. unsigned int resetcal_timer;
  100. unsigned int checkani_timer;
  101. int timer;
  102. };
  103. struct ath_cycle_counters {
  104. u32 cycles;
  105. u32 rx_busy;
  106. u32 rx_frame;
  107. u32 tx_frame;
  108. };
  109. enum ath_device_state {
  110. ATH_HW_UNAVAILABLE,
  111. ATH_HW_INITIALIZED,
  112. };
  113. enum ath_bus_type {
  114. ATH_PCI,
  115. ATH_AHB,
  116. ATH_USB,
  117. };
  118. struct reg_dmn_pair_mapping {
  119. u16 regDmnEnum;
  120. u16 reg_5ghz_ctl;
  121. u16 reg_2ghz_ctl;
  122. };
  123. struct ath_regulatory {
  124. char alpha2[2];
  125. u16 country_code;
  126. u16 max_power_level;
  127. u32 tp_scale;
  128. u16 current_rd;
  129. u16 current_rd_ext;
  130. int16_t power_limit;
  131. struct reg_dmn_pair_mapping *regpair;
  132. };
  133. enum ath_crypt_caps {
  134. ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
  135. ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
  136. };
  137. struct ath_keyval {
  138. u8 kv_type;
  139. u8 kv_pad;
  140. u16 kv_len;
  141. u8 kv_val[16]; /* TK */
  142. u8 kv_mic[8]; /* Michael MIC key */
  143. u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
  144. * supports both MIC keys in the same key cache entry;
  145. * in that case, kv_mic is the RX key) */
  146. };
  147. enum ath_cipher {
  148. ATH_CIPHER_WEP = 0,
  149. ATH_CIPHER_AES_OCB = 1,
  150. ATH_CIPHER_AES_CCM = 2,
  151. ATH_CIPHER_CKIP = 3,
  152. ATH_CIPHER_TKIP = 4,
  153. ATH_CIPHER_CLR = 5,
  154. ATH_CIPHER_MIC = 127
  155. };
  156. /**
  157. * struct ath_ops - Register read/write operations
  158. *
  159. * @read: Register read
  160. * @multi_read: Multiple register read
  161. * @write: Register write
  162. * @enable_write_buffer: Enable multiple register writes
  163. * @write_flush: flush buffered register writes and disable buffering
  164. */
  165. struct ath_ops {
  166. unsigned int (*read)(void *, u32 reg_offset);
  167. void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
  168. void (*write)(void *, u32 val, u32 reg_offset);
  169. void (*enable_write_buffer)(void *);
  170. void (*write_flush) (void *);
  171. u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
  172. };
  173. struct ath_common;
  174. struct ath_bus_ops;
  175. struct ath_common {
  176. void *ah;
  177. void *priv;
  178. struct net80211_device *dev;
  179. int debug_mask;
  180. enum ath_device_state state;
  181. struct ath_ani ani;
  182. u16 cachelsz;
  183. u16 curaid;
  184. u8 macaddr[ETH_ALEN];
  185. u8 curbssid[ETH_ALEN];
  186. u8 bssidmask[ETH_ALEN];
  187. u8 tx_chainmask;
  188. u8 rx_chainmask;
  189. u32 rx_bufsize;
  190. u32 keymax;
  191. enum ath_crypt_caps crypt_caps;
  192. unsigned int clockrate;
  193. struct ath_cycle_counters cc_ani;
  194. struct ath_cycle_counters cc_survey;
  195. struct ath_regulatory regulatory;
  196. const struct ath_ops *ops;
  197. const struct ath_bus_ops *bus_ops;
  198. int btcoex_enabled;
  199. };
  200. struct io_buffer *ath_rxbuf_alloc(struct ath_common *common,
  201. u32 len,
  202. u32 *iob_addr);
  203. void ath_hw_setbssidmask(struct ath_common *common);
  204. int ath_hw_keyreset(struct ath_common *common, u16 entry);
  205. void ath_hw_cycle_counters_update(struct ath_common *common);
  206. int32_t ath_hw_get_listen_time(struct ath_common *common);
  207. #endif /* ATH_H */