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phantom.h 8.6KB

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  1. #ifndef _PHANTOM_H
  2. #define _PHANTOM_H
  3. /*
  4. * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
  5. * Copyright (C) 2008 NetXen, Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of the
  10. * License, or any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. /**
  22. * @file
  23. *
  24. * NetXen Phantom NICs
  25. *
  26. */
  27. #include <stdint.h>
  28. /* Drag in hardware definitions */
  29. #include "nx_bitops.h"
  30. #include "phantom_hw.h"
  31. struct phantom_rds { NX_PSEUDO_BIT_STRUCT ( struct phantom_rds_pb ) };
  32. struct phantom_sds { NX_PSEUDO_BIT_STRUCT ( struct phantom_sds_pb ) };
  33. union phantom_cds { NX_PSEUDO_BIT_STRUCT ( union phantom_cds_pb ) };
  34. /* Drag in firmware interface definitions */
  35. typedef uint8_t U8;
  36. typedef uint16_t U16;
  37. typedef uint32_t U32;
  38. typedef uint64_t U64;
  39. typedef uint32_t nx_rcode_t;
  40. #define NXHAL_VERSION 1
  41. #include "nxhal_nic_interface.h"
  42. /** SPI controller maximum block size */
  43. #define UNM_SPI_BLKSIZE 4
  44. /** DMA buffer alignment */
  45. #define UNM_DMA_BUFFER_ALIGN 16
  46. /** Mark structure as DMA-aligned */
  47. #define __unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) ))
  48. /** Dummy DMA buffer size */
  49. #define UNM_DUMMY_DMA_SIZE 1024
  50. /******************************************************************************
  51. *
  52. * Register definitions
  53. *
  54. */
  55. #define UNM_128M_CRB_WINDOW 0x6110210UL
  56. #define UNM_32M_CRB_WINDOW 0x0110210UL
  57. #define UNM_2M_CRB_WINDOW 0x0130060UL
  58. /**
  59. * Phantom register blocks
  60. *
  61. * The upper address bits vary between cards. We define an abstract
  62. * address space in which the upper 8 bits of the 32-bit register
  63. * address encode the register block. This gets translated to a bus
  64. * address by the phantom_crb_access_xxx() methods.
  65. */
  66. enum unm_reg_blocks {
  67. UNM_CRB_BLK_PCIE,
  68. UNM_CRB_BLK_CAM,
  69. UNM_CRB_BLK_ROMUSB,
  70. UNM_CRB_BLK_TEST,
  71. };
  72. #define UNM_CRB_BASE(blk) ( (blk) << 24 )
  73. #define UNM_CRB_BLK(reg) ( (reg) >> 24 )
  74. #define UNM_CRB_OFFSET(reg) ( (reg) & 0x00ffffff )
  75. #define UNM_CRB_PCIE UNM_CRB_BASE ( UNM_CRB_BLK_PCIE )
  76. #define UNM_PCIE_SEM2_LOCK ( UNM_CRB_PCIE + 0x1c010 )
  77. #define UNM_PCIE_SEM2_UNLOCK ( UNM_CRB_PCIE + 0x1c014 )
  78. #define UNM_CRB_CAM UNM_CRB_BASE ( UNM_CRB_BLK_CAM )
  79. #define UNM_CAM_RAM ( UNM_CRB_CAM + 0x02000 )
  80. #define UNM_CAM_RAM_PORT_MODE ( UNM_CAM_RAM + 0x00024 )
  81. #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG 4
  82. #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G 5
  83. #define UNM_CAM_RAM_DMESG_HEAD(n) ( UNM_CAM_RAM + 0x00030 + (n) * 0x10 )
  84. #define UNM_CAM_RAM_DMESG_LEN(n) ( UNM_CAM_RAM + 0x00034 + (n) * 0x10 )
  85. #define UNM_CAM_RAM_DMESG_TAIL(n) ( UNM_CAM_RAM + 0x00038 + (n) * 0x10 )
  86. #define UNM_CAM_RAM_DMESG_SIG(n) ( UNM_CAM_RAM + 0x0003c + (n) * 0x10 )
  87. #define UNM_CAM_RAM_DMESG_SIG_MAGIC 0xcafebabeUL
  88. #define UNM_CAM_RAM_NUM_DMESG_BUFFERS 5
  89. #define UNM_CAM_RAM_WOL_PORT_MODE ( UNM_CAM_RAM + 0x00198 )
  90. #define UNM_CAM_RAM_MAC_ADDRS ( UNM_CAM_RAM + 0x001c0 )
  91. #define UNM_CAM_RAM_COLD_BOOT ( UNM_CAM_RAM + 0x001fc )
  92. #define UNM_CAM_RAM_COLD_BOOT_MAGIC 0x55555555UL
  93. #define UNM_NIC_REG ( UNM_CRB_CAM + 0x02200 )
  94. #define UNM_NIC_REG_NX_CDRP ( UNM_NIC_REG + 0x00018 )
  95. #define UNM_NIC_REG_NX_ARG1 ( UNM_NIC_REG + 0x0001c )
  96. #define UNM_NIC_REG_NX_ARG2 ( UNM_NIC_REG + 0x00020 )
  97. #define UNM_NIC_REG_NX_ARG3 ( UNM_NIC_REG + 0x00024 )
  98. #define UNM_NIC_REG_NX_SIGN ( UNM_NIC_REG + 0x00028 )
  99. #define UNM_NIC_REG_DUMMY_BUF_ADDR_HI ( UNM_NIC_REG + 0x0003c )
  100. #define UNM_NIC_REG_DUMMY_BUF_ADDR_LO ( UNM_NIC_REG + 0x00040 )
  101. #define UNM_NIC_REG_CMDPEG_STATE ( UNM_NIC_REG + 0x00050 )
  102. #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZED 0xff01
  103. #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK 0xf00f
  104. #define UNM_NIC_REG_DUMMY_BUF ( UNM_NIC_REG + 0x000fc )
  105. #define UNM_NIC_REG_DUMMY_BUF_INIT 0
  106. #define UNM_NIC_REG_XG_STATE_P3 ( UNM_NIC_REG + 0x00098 )
  107. #define UNM_NIC_REG_XG_STATE_P3_LINK( port, state_p3 ) \
  108. ( ( (state_p3) >> ( (port) * 4 ) ) & 0x0f )
  109. #define UNM_NIC_REG_XG_STATE_P3_LINK_UP 0x01
  110. #define UNM_NIC_REG_XG_STATE_P3_LINK_DOWN 0x02
  111. #define UNM_NIC_REG_RCVPEG_STATE ( UNM_NIC_REG + 0x0013c )
  112. #define UNM_NIC_REG_RCVPEG_STATE_INITIALIZED 0xff01
  113. #define UNM_NIC_REG_SW_INT_MASK_0 ( UNM_NIC_REG + 0x001d8 )
  114. #define UNM_NIC_REG_SW_INT_MASK_1 ( UNM_NIC_REG + 0x001e0 )
  115. #define UNM_NIC_REG_SW_INT_MASK_2 ( UNM_NIC_REG + 0x001e4 )
  116. #define UNM_NIC_REG_SW_INT_MASK_3 ( UNM_NIC_REG + 0x001e8 )
  117. #define UNM_CRB_ROMUSB UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB )
  118. #define UNM_ROMUSB_GLB ( UNM_CRB_ROMUSB + 0x00000 )
  119. #define UNM_ROMUSB_GLB_STATUS ( UNM_ROMUSB_GLB + 0x00004 )
  120. #define UNM_ROMUSB_GLB_STATUS_ROM_DONE ( 1 << 1 )
  121. #define UNM_ROMUSB_GLB_SW_RESET ( UNM_ROMUSB_GLB + 0x00008 )
  122. #define UNM_ROMUSB_GLB_SW_RESET_MAGIC 0x0080000fUL
  123. #define UNM_ROMUSB_GLB_PEGTUNE_DONE ( UNM_ROMUSB_GLB + 0x0005c )
  124. #define UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGIC 0x31
  125. #define UNM_ROMUSB_ROM ( UNM_CRB_ROMUSB + 0x10000 )
  126. #define UNM_ROMUSB_ROM_INSTR_OPCODE ( UNM_ROMUSB_ROM + 0x00004 )
  127. #define UNM_ROMUSB_ROM_ADDRESS ( UNM_ROMUSB_ROM + 0x00008 )
  128. #define UNM_ROMUSB_ROM_WDATA ( UNM_ROMUSB_ROM + 0x0000c )
  129. #define UNM_ROMUSB_ROM_ABYTE_CNT ( UNM_ROMUSB_ROM + 0x00010 )
  130. #define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT ( UNM_ROMUSB_ROM + 0x00014 )
  131. #define UNM_ROMUSB_ROM_RDATA ( UNM_ROMUSB_ROM + 0x00018 )
  132. #define UNM_CRB_TEST UNM_CRB_BASE ( UNM_CRB_BLK_TEST )
  133. #define UNM_TEST_CONTROL ( UNM_CRB_TEST + 0x00090 )
  134. #define UNM_TEST_CONTROL_START 0x01
  135. #define UNM_TEST_CONTROL_ENABLE 0x02
  136. #define UNM_TEST_CONTROL_BUSY 0x08
  137. #define UNM_TEST_ADDR_LO ( UNM_CRB_TEST + 0x00094 )
  138. #define UNM_TEST_ADDR_HI ( UNM_CRB_TEST + 0x00098 )
  139. #define UNM_TEST_RDDATA_LO ( UNM_CRB_TEST + 0x000a8 )
  140. #define UNM_TEST_RDDATA_HI ( UNM_CRB_TEST + 0x000ac )
  141. /******************************************************************************
  142. *
  143. * Flash layout
  144. *
  145. */
  146. /* Board configuration */
  147. #define UNM_BRDCFG_START 0x4000
  148. struct unm_board_info {
  149. uint32_t header_version;
  150. uint32_t board_mfg;
  151. uint32_t board_type;
  152. uint32_t board_num;
  153. uint32_t chip_id;
  154. uint32_t chip_minor;
  155. uint32_t chip_major;
  156. uint32_t chip_pkg;
  157. uint32_t chip_lot;
  158. uint32_t port_mask;
  159. uint32_t peg_mask;
  160. uint32_t icache_ok;
  161. uint32_t dcache_ok;
  162. uint32_t casper_ok;
  163. uint32_t mac_addr_lo_0;
  164. uint32_t mac_addr_lo_1;
  165. uint32_t mac_addr_lo_2;
  166. uint32_t mac_addr_lo_3;
  167. uint32_t mn_sync_mode;
  168. uint32_t mn_sync_shift_cclk;
  169. uint32_t mn_sync_shift_mclk;
  170. uint32_t mn_wb_en;
  171. uint32_t mn_crystal_freq;
  172. uint32_t mn_speed;
  173. uint32_t mn_org;
  174. uint32_t mn_depth;
  175. uint32_t mn_ranks_0;
  176. uint32_t mn_ranks_1;
  177. uint32_t mn_rd_latency_0;
  178. uint32_t mn_rd_latency_1;
  179. uint32_t mn_rd_latency_2;
  180. uint32_t mn_rd_latency_3;
  181. uint32_t mn_rd_latency_4;
  182. uint32_t mn_rd_latency_5;
  183. uint32_t mn_rd_latency_6;
  184. uint32_t mn_rd_latency_7;
  185. uint32_t mn_rd_latency_8;
  186. uint32_t mn_dll_val[18];
  187. uint32_t mn_mode_reg;
  188. uint32_t mn_ext_mode_reg;
  189. uint32_t mn_timing_0;
  190. uint32_t mn_timing_1;
  191. uint32_t mn_timing_2;
  192. uint32_t sn_sync_mode;
  193. uint32_t sn_pt_mode;
  194. uint32_t sn_ecc_en;
  195. uint32_t sn_wb_en;
  196. uint32_t sn_crystal_freq;
  197. uint32_t sn_speed;
  198. uint32_t sn_org;
  199. uint32_t sn_depth;
  200. uint32_t sn_dll_tap;
  201. uint32_t sn_rd_latency;
  202. uint32_t mac_addr_hi_0;
  203. uint32_t mac_addr_hi_1;
  204. uint32_t mac_addr_hi_2;
  205. uint32_t mac_addr_hi_3;
  206. uint32_t magic;
  207. uint32_t mn_rdimm;
  208. uint32_t mn_dll_override;
  209. };
  210. #define UNM_BDINFO_VERSION 1
  211. #define UNM_BRDTYPE_P3_HMEZ 0x0022
  212. #define UNM_BRDTYPE_P3_10G_CX4_LP 0x0023
  213. #define UNM_BRDTYPE_P3_4_GB 0x0024
  214. #define UNM_BRDTYPE_P3_IMEZ 0x0025
  215. #define UNM_BRDTYPE_P3_10G_SFP_PLUS 0x0026
  216. #define UNM_BRDTYPE_P3_10000_BASE_T 0x0027
  217. #define UNM_BRDTYPE_P3_XG_LOM 0x0028
  218. #define UNM_BRDTYPE_P3_4_GB_MM 0x0029
  219. #define UNM_BRDTYPE_P3_10G_CX4 0x0031
  220. #define UNM_BRDTYPE_P3_10G_XFP 0x0032
  221. #define UNM_BDINFO_MAGIC 0x12345678
  222. /* User defined region */
  223. #define UNM_USER_START 0x3e8000
  224. #define UNM_FLASH_NUM_PORTS 4
  225. #define UNM_FLASH_NUM_MAC_PER_PORT 32
  226. struct unm_user_info {
  227. uint8_t flash_md5[16 * 64];
  228. uint32_t bootld_version;
  229. uint32_t bootld_size;
  230. uint32_t image_version;
  231. uint32_t image_size;
  232. uint32_t primary_status;
  233. uint32_t secondary_present;
  234. /* MAC address , 4 ports, 32 address per port */
  235. uint64_t mac_addr[UNM_FLASH_NUM_PORTS * UNM_FLASH_NUM_MAC_PER_PORT];
  236. uint32_t sub_sys_id;
  237. uint8_t serial_num[32];
  238. uint32_t bios_version;
  239. uint32_t pxe_enable;
  240. uint32_t vlan_tag[UNM_FLASH_NUM_PORTS];
  241. };
  242. #endif /* _PHANTOM_H */