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intelxl.h 23KB

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  1. #ifndef _INTELX_H
  2. #define _INTELX_H
  3. /** @file
  4. *
  5. * Intel 40 Gigabit Ethernet network card driver
  6. *
  7. */
  8. FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
  9. #include <stdint.h>
  10. #include <ipxe/if_ether.h>
  11. struct intelxl_nic;
  12. /** BAR size */
  13. #define INTELXL_BAR_SIZE 0x200000
  14. /** Alignment
  15. *
  16. * No data structure requires greater than 128 byte alignment.
  17. */
  18. #define INTELXL_ALIGN 128
  19. /******************************************************************************
  20. *
  21. * Admin queue
  22. *
  23. ******************************************************************************
  24. */
  25. /** PF Admin Command Queue register block */
  26. #define INTELXL_ADMIN_CMD 0x080000
  27. /** PF Admin Event Queue register block */
  28. #define INTELXL_ADMIN_EVT 0x080080
  29. /** Admin Queue Base Address Low Register (offset) */
  30. #define INTELXL_ADMIN_BAL 0x000
  31. /** Admin Queue Base Address High Register (offset) */
  32. #define INTELXL_ADMIN_BAH 0x100
  33. /** Admin Queue Length Register (offset) */
  34. #define INTELXL_ADMIN_LEN 0x200
  35. #define INTELXL_ADMIN_LEN_LEN(x) ( (x) << 0 ) /**< Queue length */
  36. #define INTELXL_ADMIN_LEN_ENABLE 0x80000000UL /**< Queue enable */
  37. /** Admin Queue Head Register (offset) */
  38. #define INTELXL_ADMIN_HEAD 0x300
  39. /** Admin Queue Tail Register (offset) */
  40. #define INTELXL_ADMIN_TAIL 0x400
  41. /** Admin queue register offsets
  42. *
  43. * The physical and virtual function register maps have no discernible
  44. * relationship.
  45. */
  46. struct intelxl_admin_offsets {
  47. /** Base Address Low Register offset */
  48. unsigned int bal;
  49. /** Base Address High Register offset */
  50. unsigned int bah;
  51. /** Length Register offset */
  52. unsigned int len;
  53. /** Head Register offset */
  54. unsigned int head;
  55. /** Tail Register offset */
  56. unsigned int tail;
  57. };
  58. /** Admin queue data buffer command parameters */
  59. struct intelxl_admin_buffer_params {
  60. /** Reserved */
  61. uint8_t reserved[8];
  62. /** Buffer address high */
  63. uint32_t high;
  64. /** Buffer address low */
  65. uint32_t low;
  66. } __attribute__ (( packed ));
  67. /** Admin queue Get Version command */
  68. #define INTELXL_ADMIN_VERSION 0x0001
  69. /** Admin queue version number */
  70. struct intelxl_admin_version {
  71. /** Major version number */
  72. uint16_t major;
  73. /** Minor version number */
  74. uint16_t minor;
  75. } __attribute__ (( packed ));
  76. /** Admin queue Get Version command parameters */
  77. struct intelxl_admin_version_params {
  78. /** ROM version */
  79. uint32_t rom;
  80. /** Firmware build ID */
  81. uint32_t build;
  82. /** Firmware version */
  83. struct intelxl_admin_version firmware;
  84. /** API version */
  85. struct intelxl_admin_version api;
  86. } __attribute__ (( packed ));
  87. /** Admin queue Driver Version command */
  88. #define INTELXL_ADMIN_DRIVER 0x0002
  89. /** Admin queue Driver Version command parameters */
  90. struct intelxl_admin_driver_params {
  91. /** Driver version */
  92. uint8_t major;
  93. /** Minor version */
  94. uint8_t minor;
  95. /** Build version */
  96. uint8_t build;
  97. /** Sub-build version */
  98. uint8_t sub;
  99. /** Reserved */
  100. uint8_t reserved[4];
  101. /** Data buffer address */
  102. uint64_t address;
  103. } __attribute__ (( packed ));
  104. /** Admin queue Driver Version data buffer */
  105. struct intelxl_admin_driver_buffer {
  106. /** Driver name */
  107. char name[32];
  108. } __attribute__ (( packed ));
  109. /** Admin queue Shutdown command */
  110. #define INTELXL_ADMIN_SHUTDOWN 0x0003
  111. /** Admin queue Shutdown command parameters */
  112. struct intelxl_admin_shutdown_params {
  113. /** Driver unloading */
  114. uint8_t unloading;
  115. /** Reserved */
  116. uint8_t reserved[15];
  117. } __attribute__ (( packed ));
  118. /** Driver is unloading */
  119. #define INTELXL_ADMIN_SHUTDOWN_UNLOADING 0x01
  120. /** Admin queue Get Switch Configuration command */
  121. #define INTELXL_ADMIN_SWITCH 0x0200
  122. /** Switching element configuration */
  123. struct intelxl_admin_switch_config {
  124. /** Switching element type */
  125. uint8_t type;
  126. /** Revision */
  127. uint8_t revision;
  128. /** Switching element ID */
  129. uint16_t seid;
  130. /** Uplink switching element ID */
  131. uint16_t uplink;
  132. /** Downlink switching element ID */
  133. uint16_t downlink;
  134. /** Reserved */
  135. uint8_t reserved_b[3];
  136. /** Connection type */
  137. uint8_t connection;
  138. /** Reserved */
  139. uint8_t reserved_c[2];
  140. /** Element specific information */
  141. uint16_t info;
  142. } __attribute__ (( packed ));
  143. /** Virtual Station Inferface element type */
  144. #define INTELXL_ADMIN_SWITCH_TYPE_VSI 19
  145. /** Admin queue Get Switch Configuration command parameters */
  146. struct intelxl_admin_switch_params {
  147. /** Starting switching element identifier */
  148. uint16_t next;
  149. /** Reserved */
  150. uint8_t reserved[6];
  151. /** Data buffer address */
  152. uint64_t address;
  153. } __attribute__ (( packed ));
  154. /** Admin queue Get Switch Configuration data buffer */
  155. struct intelxl_admin_switch_buffer {
  156. /** Number of switching elements reported */
  157. uint16_t count;
  158. /** Total number of switching elements */
  159. uint16_t total;
  160. /** Reserved */
  161. uint8_t reserved_a[12];
  162. /** Switch configuration */
  163. struct intelxl_admin_switch_config cfg;
  164. } __attribute__ (( packed ));
  165. /** Admin queue Get VSI Parameters command */
  166. #define INTELXL_ADMIN_VSI 0x0212
  167. /** Admin queue Get VSI Parameters command parameters */
  168. struct intelxl_admin_vsi_params {
  169. /** VSI switching element ID */
  170. uint16_t vsi;
  171. /** Reserved */
  172. uint8_t reserved[6];
  173. /** Data buffer address */
  174. uint64_t address;
  175. } __attribute__ (( packed ));
  176. /** Admin queue Get VSI Parameters data buffer */
  177. struct intelxl_admin_vsi_buffer {
  178. /** Reserved */
  179. uint8_t reserved_a[30];
  180. /** Queue numbers */
  181. uint16_t queue[16];
  182. /** Reserved */
  183. uint8_t reserved_b[34];
  184. /** Queue set handles for each traffic class */
  185. uint16_t qset[8];
  186. /** Reserved */
  187. uint8_t reserved_c[16];
  188. } __attribute__ (( packed ));
  189. /** Admin queue Set VSI Promiscuous Modes command */
  190. #define INTELXL_ADMIN_PROMISC 0x0254
  191. /** Admin queue Set VSI Promiscuous Modes command parameters */
  192. struct intelxl_admin_promisc_params {
  193. /** Flags */
  194. uint16_t flags;
  195. /** Valid flags */
  196. uint16_t valid;
  197. /** VSI switching element ID */
  198. uint16_t vsi;
  199. /** Reserved */
  200. uint8_t reserved[10];
  201. } __attribute__ (( packed ));
  202. /** Promiscuous unicast mode */
  203. #define INTELXL_ADMIN_PROMISC_FL_UNICAST 0x0001
  204. /** Promiscuous multicast mode */
  205. #define INTELXL_ADMIN_PROMISC_FL_MULTICAST 0x0002
  206. /** Promiscuous broadcast mode */
  207. #define INTELXL_ADMIN_PROMISC_FL_BROADCAST 0x0004
  208. /** Promiscuous VLAN mode */
  209. #define INTELXL_ADMIN_PROMISC_FL_VLAN 0x0010
  210. /** Admin queue Restart Autonegotiation command */
  211. #define INTELXL_ADMIN_AUTONEG 0x0605
  212. /** Admin queue Restart Autonegotiation command parameters */
  213. struct intelxl_admin_autoneg_params {
  214. /** Flags */
  215. uint8_t flags;
  216. /** Reserved */
  217. uint8_t reserved[15];
  218. } __attribute__ (( packed ));
  219. /** Restart autonegotiation */
  220. #define INTELXL_ADMIN_AUTONEG_FL_RESTART 0x02
  221. /** Enable link */
  222. #define INTELXL_ADMIN_AUTONEG_FL_ENABLE 0x04
  223. /** Admin queue Get Link Status command */
  224. #define INTELXL_ADMIN_LINK 0x0607
  225. /** Admin queue Get Link Status command parameters */
  226. struct intelxl_admin_link_params {
  227. /** Link status notification */
  228. uint8_t notify;
  229. /** Reserved */
  230. uint8_t reserved_a;
  231. /** PHY type */
  232. uint8_t phy;
  233. /** Link speed */
  234. uint8_t speed;
  235. /** Link status */
  236. uint8_t status;
  237. /** Reserved */
  238. uint8_t reserved_b[11];
  239. } __attribute__ (( packed ));
  240. /** Notify driver of link status changes */
  241. #define INTELXL_ADMIN_LINK_NOTIFY 0x03
  242. /** Link is up */
  243. #define INTELXL_ADMIN_LINK_UP 0x01
  244. /** Admin queue Send Message to PF command */
  245. #define INTELXL_ADMIN_SEND_TO_PF 0x0801
  246. /** Admin queue Send Message to VF command */
  247. #define INTELXL_ADMIN_SEND_TO_VF 0x0802
  248. /** Admin queue command parameters */
  249. union intelxl_admin_params {
  250. /** Additional data buffer command parameters */
  251. struct intelxl_admin_buffer_params buffer;
  252. /** Get Version command parameters */
  253. struct intelxl_admin_version_params version;
  254. /** Driver Version command parameters */
  255. struct intelxl_admin_driver_params driver;
  256. /** Shutdown command parameters */
  257. struct intelxl_admin_shutdown_params shutdown;
  258. /** Get Switch Configuration command parameters */
  259. struct intelxl_admin_switch_params sw;
  260. /** Get VSI Parameters command parameters */
  261. struct intelxl_admin_vsi_params vsi;
  262. /** Set VSI Promiscuous Modes command parameters */
  263. struct intelxl_admin_promisc_params promisc;
  264. /** Restart Autonegotiation command parameters */
  265. struct intelxl_admin_autoneg_params autoneg;
  266. /** Get Link Status command parameters */
  267. struct intelxl_admin_link_params link;
  268. } __attribute__ (( packed ));
  269. /** Admin queue data buffer */
  270. union intelxl_admin_buffer {
  271. /** Driver Version data buffer */
  272. struct intelxl_admin_driver_buffer driver;
  273. /** Get Switch Configuration data buffer */
  274. struct intelxl_admin_switch_buffer sw;
  275. /** Get VSI Parameters data buffer */
  276. struct intelxl_admin_vsi_buffer vsi;
  277. /** Alignment padding */
  278. uint8_t pad[INTELXL_ALIGN];
  279. } __attribute__ (( packed ));
  280. /** Admin queue descriptor */
  281. struct intelxl_admin_descriptor {
  282. /** Flags */
  283. uint16_t flags;
  284. /** Opcode */
  285. uint16_t opcode;
  286. /** Data length */
  287. uint16_t len;
  288. /** Return value */
  289. uint16_t ret;
  290. /** Opaque cookie / VF opcode */
  291. union {
  292. /** Cookie */
  293. uint32_t cookie;
  294. /** VF opcode */
  295. uint32_t vopcode;
  296. };
  297. /** VF return value */
  298. int32_t vret;
  299. /** Parameters */
  300. union intelxl_admin_params params;
  301. } __attribute__ (( packed ));
  302. /** Admin descriptor done */
  303. #define INTELXL_ADMIN_FL_DD 0x0001
  304. /** Admin descriptor contains a completion */
  305. #define INTELXL_ADMIN_FL_CMP 0x0002
  306. /** Admin descriptor completed in error */
  307. #define INTELXL_ADMIN_FL_ERR 0x0004
  308. /** Admin descriptor uses data buffer for command parameters */
  309. #define INTELXL_ADMIN_FL_RD 0x0400
  310. /** Admin descriptor uses data buffer */
  311. #define INTELXL_ADMIN_FL_BUF 0x1000
  312. /** Admin queue */
  313. struct intelxl_admin {
  314. /** Descriptors */
  315. struct intelxl_admin_descriptor *desc;
  316. /** Data buffers */
  317. union intelxl_admin_buffer *buf;
  318. /** Queue index */
  319. unsigned int index;
  320. /** Register block base */
  321. unsigned int base;
  322. /** Register offsets */
  323. const struct intelxl_admin_offsets *regs;
  324. };
  325. /**
  326. * Initialise admin queue
  327. *
  328. * @v admin Admin queue
  329. * @v base Register block base
  330. * @v regs Register offsets
  331. */
  332. static inline __attribute__ (( always_inline )) void
  333. intelxl_init_admin ( struct intelxl_admin *admin, unsigned int base,
  334. const struct intelxl_admin_offsets *regs ) {
  335. admin->base = base;
  336. admin->regs = regs;
  337. }
  338. /** Number of admin queue descriptors */
  339. #define INTELXL_ADMIN_NUM_DESC 4
  340. /** Maximum time to wait for an admin request to complete */
  341. #define INTELXL_ADMIN_MAX_WAIT_MS 100
  342. /** Admin queue API major version */
  343. #define INTELXL_ADMIN_API_MAJOR 1
  344. /******************************************************************************
  345. *
  346. * Transmit and receive queue context
  347. *
  348. ******************************************************************************
  349. */
  350. /** CMLAN Context Data Register */
  351. #define INTELXL_PFCM_LANCTXDATA(x) ( 0x10c100 + ( 0x80 * (x) ) )
  352. /** CMLAN Context Control Register */
  353. #define INTELXL_PFCM_LANCTXCTL 0x10c300
  354. #define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x) \
  355. ( (x) << 0 ) /**< Queue number */
  356. #define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x) \
  357. ( (x) << 12 ) /**< Sub-line */
  358. #define INTELXL_PFCM_LANCTXCTL_TYPE(x) \
  359. ( (x) << 15 ) /**< Queue type */
  360. #define INTELXL_PFCM_LANCTXCTL_TYPE_RX \
  361. INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 ) /**< RX queue type */
  362. #define INTELXL_PFCM_LANCTXCTL_TYPE_TX \
  363. INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 ) /**< TX queue type */
  364. #define INTELXL_PFCM_LANCTXCTL_OP_CODE(x) \
  365. ( (x) << 17 ) /**< Op code */
  366. #define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ \
  367. INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 ) /**< Read context */
  368. #define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE \
  369. INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 ) /**< Write context */
  370. /** CMLAN Context Status Register */
  371. #define INTELXL_PFCM_LANCTXSTAT 0x10c380
  372. #define INTELXL_PFCM_LANCTXSTAT_DONE 0x00000001UL /**< Complete */
  373. /** Queue context line */
  374. struct intelxl_context_line {
  375. /** Raw data */
  376. uint32_t raw[4];
  377. } __attribute__ (( packed ));
  378. /** Transmit queue context */
  379. struct intelxl_context_tx {
  380. /** Head pointer */
  381. uint16_t head;
  382. /** Flags */
  383. uint16_t flags;
  384. /** Base address */
  385. uint64_t base;
  386. /** Reserved */
  387. uint8_t reserved_a[8];
  388. /** Queue count */
  389. uint16_t count;
  390. /** Reserved */
  391. uint8_t reserved_b[100];
  392. /** Queue set */
  393. uint16_t qset;
  394. /** Reserved */
  395. uint8_t reserved_c[4];
  396. } __attribute__ (( packed ));
  397. /** New transmit queue context */
  398. #define INTELXL_CTX_TX_FL_NEW 0x4000
  399. /** Transmit queue base address */
  400. #define INTELXL_CTX_TX_BASE( base ) ( (base) >> 7 )
  401. /** Transmit queue count */
  402. #define INTELXL_CTX_TX_COUNT( count ) ( (count) << 1 )
  403. /** Transmit queue set */
  404. #define INTELXL_CTX_TX_QSET( qset) ( (qset) << 4 )
  405. /** Receive queue context */
  406. struct intelxl_context_rx {
  407. /** Head pointer */
  408. uint16_t head;
  409. /** Reserved */
  410. uint8_t reserved_a[2];
  411. /** Base address and queue count */
  412. uint64_t base_count;
  413. /** Data buffer length */
  414. uint16_t len;
  415. /** Flags */
  416. uint8_t flags;
  417. /** Reserved */
  418. uint8_t reserved_b[7];
  419. /** Maximum frame size */
  420. uint16_t mfs;
  421. } __attribute__ (( packed ));
  422. /** Receive queue base address and queue count */
  423. #define INTELXL_CTX_RX_BASE_COUNT( base, count ) \
  424. ( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )
  425. /** Receive queue data buffer length */
  426. #define INTELXL_CTX_RX_LEN( len ) ( (len) >> 1 )
  427. /** Use 32-byte receive descriptors */
  428. #define INTELXL_CTX_RX_FL_DSIZE 0x10
  429. /** Strip CRC from received packets */
  430. #define INTELXL_CTX_RX_FL_CRCSTRIP 0x20
  431. /** Receive queue maximum frame size */
  432. #define INTELXL_CTX_RX_MFS( mfs ) ( (mfs) >> 2 )
  433. /** Maximum time to wait for a context operation to complete */
  434. #define INTELXL_CTX_MAX_WAIT_MS 100
  435. /** Time to wait for a queue to become enabled */
  436. #define INTELXL_QUEUE_ENABLE_DELAY_US 20
  437. /** Time to wait for a transmit queue to become pre-disabled */
  438. #define INTELXL_QUEUE_PRE_DISABLE_DELAY_US 400
  439. /** Maximum time to wait for a queue to become disabled */
  440. #define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS 1000
  441. /******************************************************************************
  442. *
  443. * Transmit and receive descriptors
  444. *
  445. ******************************************************************************
  446. */
  447. /** Global Transmit Queue Head register */
  448. #define INTELXL_QTX_HEAD(x) ( 0x0e4000 + ( 0x4 * (x) ) )
  449. /** Global Transmit Pre Queue Disable register */
  450. #define INTELXL_GLLAN_TXPRE_QDIS(x) ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )
  451. #define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x) \
  452. ( (x) << 0 ) /**< Queue index */
  453. #define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS \
  454. 0x40000000UL /**< Set disable */
  455. #define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS \
  456. 0x80000000UL /**< Clear disable */
  457. /** Global Transmit Queue register block */
  458. #define INTELXL_QTX(x) ( 0x100000 + ( 0x4 * (x) ) )
  459. /** Global Receive Queue register block */
  460. #define INTELXL_QRX(x) ( 0x120000 + ( 0x4 * (x) ) )
  461. /** Queue Enable Register (offset) */
  462. #define INTELXL_QXX_ENA 0x0000
  463. #define INTELXL_QXX_ENA_REQ 0x00000001UL /**< Enable request */
  464. #define INTELXL_QXX_ENA_STAT 0x00000004UL /**< Enabled status */
  465. /** Queue Control Register (offset) */
  466. #define INTELXL_QXX_CTL 0x4000
  467. #define INTELXL_QXX_CTL_PFVF_Q(x) ( (x) << 0 ) /**< PF/VF queue */
  468. #define INTELXL_QXX_CTL_PFVF_Q_PF \
  469. INTELXL_QXX_CTL_PFVF_Q ( 0x2 ) /**< PF queue */
  470. #define INTELXL_QXX_CTL_PFVF_PF_INDX(x) ( (x) << 2 ) /**< PF index */
  471. /** Queue Tail Pointer Register (offset) */
  472. #define INTELXL_QXX_TAIL 0x8000
  473. /** Transmit data descriptor */
  474. struct intelxl_tx_data_descriptor {
  475. /** Buffer address */
  476. uint64_t address;
  477. /** Flags */
  478. uint32_t flags;
  479. /** Length */
  480. uint32_t len;
  481. } __attribute__ (( packed ));
  482. /** Transmit data descriptor type */
  483. #define INTELXL_TX_DATA_DTYP 0x0
  484. /** Transmit data descriptor end of packet */
  485. #define INTELXL_TX_DATA_EOP 0x10
  486. /** Transmit data descriptor report status */
  487. #define INTELXL_TX_DATA_RS 0x20
  488. /** Transmit data descriptor pretty please
  489. *
  490. * This bit is completely missing from older versions of the XL710
  491. * datasheet. Later versions describe it innocuously as "reserved,
  492. * must be 1". Without this bit, everything will appear to work (up
  493. * to and including the port "transmit good octets" counter), but no
  494. * packet will actually be sent.
  495. */
  496. #define INTELXL_TX_DATA_JFDI 0x40
  497. /** Transmit data descriptor length */
  498. #define INTELXL_TX_DATA_LEN( len ) ( (len) << 2 )
  499. /** Transmit writeback descriptor */
  500. struct intelxl_tx_writeback_descriptor {
  501. /** Reserved */
  502. uint8_t reserved_a[8];
  503. /** Flags */
  504. uint8_t flags;
  505. /** Reserved */
  506. uint8_t reserved_b[7];
  507. } __attribute__ (( packed ));
  508. /** Transmit writeback descriptor complete */
  509. #define INTELXL_TX_WB_FL_DD 0x01
  510. /** Transmit descriptor */
  511. union intelxl_tx_descriptor {
  512. /** Transmit data descriptor */
  513. struct intelxl_tx_data_descriptor data;
  514. /** Transmit writeback descriptor */
  515. struct intelxl_tx_writeback_descriptor wb;
  516. };
  517. /** Receive data descriptor */
  518. struct intelxl_rx_data_descriptor {
  519. /** Buffer address */
  520. uint64_t address;
  521. /** Flags */
  522. uint32_t flags;
  523. /** Reserved */
  524. uint8_t reserved[20];
  525. } __attribute__ (( packed ));
  526. /** Receive writeback descriptor */
  527. struct intelxl_rx_writeback_descriptor {
  528. /** Reserved */
  529. uint8_t reserved_a[2];
  530. /** VLAN tag */
  531. uint16_t vlan;
  532. /** Reserved */
  533. uint8_t reserved_b[4];
  534. /** Flags */
  535. uint32_t flags;
  536. /** Length */
  537. uint32_t len;
  538. /** Reserved */
  539. uint8_t reserved_c[16];
  540. } __attribute__ (( packed ));
  541. /** Receive writeback descriptor complete */
  542. #define INTELXL_RX_WB_FL_DD 0x00000001UL
  543. /** Receive writeback descriptor VLAN tag present */
  544. #define INTELXL_RX_WB_FL_VLAN 0x00000004UL
  545. /** Receive writeback descriptor error */
  546. #define INTELXL_RX_WB_FL_RXE 0x00080000UL
  547. /** Receive writeback descriptor length */
  548. #define INTELXL_RX_WB_LEN(len) ( ( (len) >> 6 ) & 0x3fff )
  549. /** Packet descriptor */
  550. union intelxl_rx_descriptor {
  551. /** Receive data descriptor */
  552. struct intelxl_rx_data_descriptor data;
  553. /** Receive writeback descriptor */
  554. struct intelxl_rx_writeback_descriptor wb;
  555. };
  556. /** Descriptor ring */
  557. struct intelxl_ring {
  558. /** Descriptors */
  559. union {
  560. /** Transmit descriptors */
  561. union intelxl_tx_descriptor *tx;
  562. /** Receive descriptors */
  563. union intelxl_rx_descriptor *rx;
  564. /** Raw data */
  565. void *raw;
  566. } desc;
  567. /** Producer index */
  568. unsigned int prod;
  569. /** Consumer index */
  570. unsigned int cons;
  571. /** Register block */
  572. unsigned int reg;
  573. /** Length (in bytes) */
  574. size_t len;
  575. /** Program queue context
  576. *
  577. * @v intelxl Intel device
  578. * @v address Descriptor ring base address
  579. */
  580. int ( * context ) ( struct intelxl_nic *intelxl, physaddr_t address );
  581. };
  582. /**
  583. * Initialise descriptor ring
  584. *
  585. * @v ring Descriptor ring
  586. * @v count Number of descriptors
  587. * @v len Length of a single descriptor
  588. * @v context Method to program queue context
  589. */
  590. static inline __attribute__ (( always_inline)) void
  591. intelxl_init_ring ( struct intelxl_ring *ring, unsigned int count, size_t len,
  592. int ( * context ) ( struct intelxl_nic *intelxl,
  593. physaddr_t address ) ) {
  594. ring->len = ( count * len );
  595. ring->context = context;
  596. }
  597. /** Number of transmit descriptors */
  598. #define INTELXL_TX_NUM_DESC 16
  599. /** Transmit descriptor ring maximum fill level */
  600. #define INTELXL_TX_FILL ( INTELXL_TX_NUM_DESC - 1 )
  601. /** Number of receive descriptors
  602. *
  603. * In PXE mode (i.e. able to post single receive descriptors), 8
  604. * descriptors is the only permitted value covering all possible
  605. * numbers of PFs.
  606. */
  607. #define INTELXL_RX_NUM_DESC 8
  608. /** Receive descriptor ring fill level */
  609. #define INTELXL_RX_FILL ( INTELXL_RX_NUM_DESC - 1 )
  610. /******************************************************************************
  611. *
  612. * Top level
  613. *
  614. ******************************************************************************
  615. */
  616. /** PF Interrupt Zero Dynamic Control Register */
  617. #define INTELXL_PFINT_DYN_CTL0 0x038480
  618. #define INTELXL_PFINT_DYN_CTL0_INTENA 0x00000001UL /**< Enable */
  619. #define INTELXL_PFINT_DYN_CTL0_CLEARPBA 0x00000002UL /**< Acknowledge */
  620. #define INTELXL_PFINT_DYN_CTL0_INTENA_MASK 0x80000000UL /**< Ignore enable */
  621. /** PF Interrupt Zero Linked List Register */
  622. #define INTELXL_PFINT_LNKLST0 0x038500
  623. #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x) \
  624. ( (x) << 0 ) /**< Queue index */
  625. #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE \
  626. INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff ) /**< End of list */
  627. #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE(x) \
  628. ( (x) << 11 ) /**< Queue type */
  629. #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX \
  630. INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 ) /**< Receive queue */
  631. #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX \
  632. INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 ) /**< Transmit queue */
  633. /** PF Interrupt Zero Cause Enablement Register */
  634. #define INTELXL_PFINT_ICR0_ENA 0x038800
  635. #define INTELXL_PFINT_ICR0_ENA_ADMINQ 0x40000000UL /**< Admin event */
  636. /** Receive Queue Interrupt Cause Control Register */
  637. #define INTELXL_QINT_RQCTL(x) ( 0x03a000 + ( 0x4 * (x) ) )
  638. #define INTELXL_QINT_RQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
  639. #define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE \
  640. INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
  641. #define INTELXL_QINT_RQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
  642. #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX \
  643. INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
  644. #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX \
  645. INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
  646. #define INTELXL_QINT_RQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
  647. /** Transmit Queue Interrupt Cause Control Register */
  648. #define INTELXL_QINT_TQCTL(x) ( 0x03c000 + ( 0x4 * (x) ) )
  649. #define INTELXL_QINT_TQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
  650. #define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE \
  651. INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
  652. #define INTELXL_QINT_TQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
  653. #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX \
  654. INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
  655. #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX \
  656. INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
  657. #define INTELXL_QINT_TQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
  658. /** PF Control Register */
  659. #define INTELXL_PFGEN_CTRL 0x092400
  660. #define INTELXL_PFGEN_CTRL_PFSWR 0x00000001UL /**< Software Reset */
  661. /** Time to delay for device reset, in milliseconds */
  662. #define INTELXL_RESET_DELAY_MS 100
  663. /** PF Queue Allocation Register */
  664. #define INTELXL_PFLAN_QALLOC 0x1c0400
  665. #define INTELXL_PFLAN_QALLOC_FIRSTQ(x) \
  666. ( ( (x) >> 0 ) & 0x7ff ) /**< First queue */
  667. #define INTELXL_PFLAN_QALLOC_LASTQ(x) \
  668. ( ( (x) >> 16 ) & 0x7ff ) /**< Last queue */
  669. /** PF LAN Port Number Register */
  670. #define INTELXL_PFGEN_PORTNUM 0x1c0480
  671. #define INTELXL_PFGEN_PORTNUM_PORT_NUM(x) \
  672. ( ( (x) >> 0 ) & 0x3 ) /**< Port number */
  673. /** Port MAC Address Low Register */
  674. #define INTELXL_PRTGL_SAL 0x1e2120
  675. /** Port MAC Address High Register */
  676. #define INTELXL_PRTGL_SAH 0x1e2140
  677. #define INTELXL_PRTGL_SAH_MFS_GET(x) ( (x) >> 16 ) /**< Max frame size */
  678. #define INTELXL_PRTGL_SAH_MFS_SET(x) ( (x) << 16 ) /**< Max frame size */
  679. /** Receive address */
  680. union intelxl_receive_address {
  681. struct {
  682. uint32_t low;
  683. uint32_t high;
  684. } __attribute__ (( packed )) reg;
  685. uint8_t raw[ETH_ALEN];
  686. };
  687. /** An Intel 40Gigabit network card */
  688. struct intelxl_nic {
  689. /** Registers */
  690. void *regs;
  691. /** Maximum frame size */
  692. size_t mfs;
  693. /** Physical function number */
  694. unsigned int pf;
  695. /** Absolute queue number base */
  696. unsigned int base;
  697. /** Port number */
  698. unsigned int port;
  699. /** Queue number */
  700. unsigned int queue;
  701. /** Virtual Station Interface switching element ID */
  702. unsigned int vsi;
  703. /** Queue set handle */
  704. unsigned int qset;
  705. /** Admin command queue */
  706. struct intelxl_admin command;
  707. /** Admin event queue */
  708. struct intelxl_admin event;
  709. /** Transmit descriptor ring */
  710. struct intelxl_ring tx;
  711. /** Receive descriptor ring */
  712. struct intelxl_ring rx;
  713. /** Receive I/O buffers */
  714. struct io_buffer *rx_iobuf[INTELXL_RX_NUM_DESC];
  715. };
  716. extern void intelxlvf_admin_event ( struct net_device *netdev,
  717. struct intelxl_admin_descriptor *evt,
  718. union intelxl_admin_buffer *buf );
  719. #endif /* _INTELXL_H */