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etherfabric.c 111KB

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  1. /**************************************************************************
  2. *
  3. * Etherboot driver for Level 5 Etherfabric network cards
  4. *
  5. * Written by Michael Brown <mbrown@fensystems.co.uk>
  6. *
  7. * Copyright Fen Systems Ltd. 2005
  8. * Copyright Level 5 Networks Inc. 2005
  9. *
  10. * This software may be used and distributed according to the terms of
  11. * the GNU General Public License (GPL), incorporated herein by
  12. * reference. Drivers based on or derived from this code fall under
  13. * the GPL and must retain the authorship, copyright and license
  14. * notice.
  15. *
  16. **************************************************************************
  17. */
  18. FILE_LICENCE ( GPL_ANY );
  19. #include <stdint.h>
  20. #include <stdlib.h>
  21. #include <stdio.h>
  22. #include <unistd.h>
  23. #include <errno.h>
  24. #include <assert.h>
  25. #include <byteswap.h>
  26. #include <ipxe/io.h>
  27. #include <ipxe/pci.h>
  28. #include <ipxe/malloc.h>
  29. #include <ipxe/ethernet.h>
  30. #include <ipxe/iobuf.h>
  31. #include <ipxe/netdevice.h>
  32. #include <ipxe/timer.h>
  33. #include <mii.h>
  34. #include "etherfabric.h"
  35. #include "etherfabric_nic.h"
  36. /**************************************************************************
  37. *
  38. * Constants and macros
  39. *
  40. **************************************************************************
  41. */
  42. #define EFAB_REGDUMP(...)
  43. #define EFAB_TRACE(...) DBGP(__VA_ARGS__)
  44. // printf() is not allowed within drivers. Use DBG() instead.
  45. #define EFAB_LOG(...) DBG(__VA_ARGS__)
  46. #define EFAB_ERR(...) DBG(__VA_ARGS__)
  47. #define FALCON_USE_IO_BAR 0
  48. #define HZ 100
  49. #define EFAB_BYTE 1
  50. /**************************************************************************
  51. *
  52. * Hardware data structures and sizing
  53. *
  54. **************************************************************************
  55. */
  56. extern int __invalid_queue_size;
  57. #define FQS(_prefix, _x) \
  58. ( ( (_x) == 512 ) ? _prefix ## _SIZE_512 : \
  59. ( ( (_x) == 1024 ) ? _prefix ## _SIZE_1K : \
  60. ( ( (_x) == 2048 ) ? _prefix ## _SIZE_2K : \
  61. ( ( (_x) == 4096) ? _prefix ## _SIZE_4K : \
  62. __invalid_queue_size ) ) ) )
  63. #define EFAB_MAX_FRAME_LEN(mtu) \
  64. ( ( ( ( mtu ) + 4/* FCS */ ) + 7 ) & ~7 )
  65. /**************************************************************************
  66. *
  67. * GMII routines
  68. *
  69. **************************************************************************
  70. */
  71. static void falcon_mdio_write (struct efab_nic *efab, int device,
  72. int location, int value );
  73. static int falcon_mdio_read ( struct efab_nic *efab, int device, int location );
  74. /* GMII registers */
  75. #define GMII_PSSR 0x11 /* PHY-specific status register */
  76. /* Pseudo extensions to the link partner ability register */
  77. #define LPA_EF_1000FULL 0x00020000
  78. #define LPA_EF_1000HALF 0x00010000
  79. #define LPA_EF_10000FULL 0x00040000
  80. #define LPA_EF_10000HALF 0x00080000
  81. #define LPA_EF_1000 ( LPA_EF_1000FULL | LPA_EF_1000HALF )
  82. #define LPA_EF_10000 ( LPA_EF_10000FULL | LPA_EF_10000HALF )
  83. #define LPA_EF_DUPLEX ( LPA_10FULL | LPA_100FULL | LPA_EF_1000FULL | \
  84. LPA_EF_10000FULL )
  85. /* Mask of bits not associated with speed or duplexity. */
  86. #define LPA_OTHER ~( LPA_10FULL | LPA_10HALF | LPA_100FULL | \
  87. LPA_100HALF | LPA_EF_1000FULL | LPA_EF_1000HALF )
  88. /* PHY-specific status register */
  89. #define PSSR_LSTATUS 0x0400 /* Bit 10 - link status */
  90. /**
  91. * Retrieve GMII autonegotiation advertised abilities
  92. *
  93. */
  94. static unsigned int
  95. gmii_autoneg_advertised ( struct efab_nic *efab )
  96. {
  97. unsigned int mii_advertise;
  98. unsigned int gmii_advertise;
  99. /* Extended bits are in bits 8 and 9 of MII_CTRL1000 */
  100. mii_advertise = falcon_mdio_read ( efab, 0, MII_ADVERTISE );
  101. gmii_advertise = ( ( falcon_mdio_read ( efab, 0, MII_CTRL1000 ) >> 8 )
  102. & 0x03 );
  103. return ( ( gmii_advertise << 16 ) | mii_advertise );
  104. }
  105. /**
  106. * Retrieve GMII autonegotiation link partner abilities
  107. *
  108. */
  109. static unsigned int
  110. gmii_autoneg_lpa ( struct efab_nic *efab )
  111. {
  112. unsigned int mii_lpa;
  113. unsigned int gmii_lpa;
  114. /* Extended bits are in bits 10 and 11 of MII_STAT1000 */
  115. mii_lpa = falcon_mdio_read ( efab, 0, MII_LPA );
  116. gmii_lpa = ( falcon_mdio_read ( efab, 0, MII_STAT1000 ) >> 10 ) & 0x03;
  117. return ( ( gmii_lpa << 16 ) | mii_lpa );
  118. }
  119. /**
  120. * Calculate GMII autonegotiated link technology
  121. *
  122. */
  123. static unsigned int
  124. gmii_nway_result ( unsigned int negotiated )
  125. {
  126. unsigned int other_bits;
  127. /* Mask out the speed and duplexity bits */
  128. other_bits = negotiated & LPA_OTHER;
  129. if ( negotiated & LPA_EF_1000FULL )
  130. return ( other_bits | LPA_EF_1000FULL );
  131. else if ( negotiated & LPA_EF_1000HALF )
  132. return ( other_bits | LPA_EF_1000HALF );
  133. else if ( negotiated & LPA_100FULL )
  134. return ( other_bits | LPA_100FULL );
  135. else if ( negotiated & LPA_100BASE4 )
  136. return ( other_bits | LPA_100BASE4 );
  137. else if ( negotiated & LPA_100HALF )
  138. return ( other_bits | LPA_100HALF );
  139. else if ( negotiated & LPA_10FULL )
  140. return ( other_bits | LPA_10FULL );
  141. else return ( other_bits | LPA_10HALF );
  142. }
  143. /**
  144. * Check GMII PHY link status
  145. *
  146. */
  147. static int
  148. gmii_link_ok ( struct efab_nic *efab )
  149. {
  150. int status;
  151. int phy_status;
  152. /* BMSR is latching - it returns "link down" if the link has
  153. * been down at any point since the last read. To get a
  154. * real-time status, we therefore read the register twice and
  155. * use the result of the second read.
  156. */
  157. (void) falcon_mdio_read ( efab, 0, MII_BMSR );
  158. status = falcon_mdio_read ( efab, 0, MII_BMSR );
  159. /* Read the PHY-specific Status Register. This is
  160. * non-latching, so we need do only a single read.
  161. */
  162. phy_status = falcon_mdio_read ( efab, 0, GMII_PSSR );
  163. return ( ( status & BMSR_LSTATUS ) && ( phy_status & PSSR_LSTATUS ) );
  164. }
  165. /**************************************************************************
  166. *
  167. * MDIO routines
  168. *
  169. **************************************************************************
  170. */
  171. /* Numbering of the MDIO Manageable Devices (MMDs) */
  172. /* Physical Medium Attachment/ Physical Medium Dependent sublayer */
  173. #define MDIO_MMD_PMAPMD (1)
  174. /* WAN Interface Sublayer */
  175. #define MDIO_MMD_WIS (2)
  176. /* Physical Coding Sublayer */
  177. #define MDIO_MMD_PCS (3)
  178. /* PHY Extender Sublayer */
  179. #define MDIO_MMD_PHYXS (4)
  180. /* Extender Sublayer */
  181. #define MDIO_MMD_DTEXS (5)
  182. /* Transmission convergence */
  183. #define MDIO_MMD_TC (6)
  184. /* Auto negotiation */
  185. #define MDIO_MMD_AN (7)
  186. /* Generic register locations */
  187. #define MDIO_MMDREG_CTRL1 (0)
  188. #define MDIO_MMDREG_STAT1 (1)
  189. #define MDIO_MMDREG_DEVS0 (5)
  190. #define MDIO_MMDREG_STAT2 (8)
  191. /* Bits in MMDREG_CTRL1 */
  192. /* Reset */
  193. #define MDIO_MMDREG_CTRL1_RESET_LBN (15)
  194. #define MDIO_MMDREG_CTRL1_RESET_WIDTH (1)
  195. /* Bits in MMDREG_STAT1 */
  196. #define MDIO_MMDREG_STAT1_FAULT_LBN (7)
  197. #define MDIO_MMDREG_STAT1_FAULT_WIDTH (1)
  198. /* Link state */
  199. #define MDIO_MMDREG_STAT1_LINK_LBN (2)
  200. #define MDIO_MMDREG_STAT1_LINK_WIDTH (1)
  201. /* Bits in MMDREG_DEVS0. */
  202. #define DEV_PRESENT_BIT(_b) (1 << _b)
  203. #define MDIO_MMDREG_DEVS0_DTEXS DEV_PRESENT_BIT(MDIO_MMD_DTEXS)
  204. #define MDIO_MMDREG_DEVS0_PHYXS DEV_PRESENT_BIT(MDIO_MMD_PHYXS)
  205. #define MDIO_MMDREG_DEVS0_PCS DEV_PRESENT_BIT(MDIO_MMD_PCS)
  206. #define MDIO_MMDREG_DEVS0_WIS DEV_PRESENT_BIT(MDIO_MMD_WIS)
  207. #define MDIO_MMDREG_DEVS0_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD)
  208. #define MDIO_MMDREG_DEVS0_AN DEV_PRESENT_BIT(MDIO_MMD_AN)
  209. /* Bits in MMDREG_STAT2 */
  210. #define MDIO_MMDREG_STAT2_PRESENT_VAL (2)
  211. #define MDIO_MMDREG_STAT2_PRESENT_LBN (14)
  212. #define MDIO_MMDREG_STAT2_PRESENT_WIDTH (2)
  213. /* PHY XGXS lane state */
  214. #define MDIO_PHYXS_LANE_STATE (0x18)
  215. #define MDIO_PHYXS_LANE_ALIGNED_LBN (12)
  216. #define MDIO_PHYXS_LANE_SYNC0_LBN (0)
  217. #define MDIO_PHYXS_LANE_SYNC1_LBN (1)
  218. #define MDIO_PHYXS_LANE_SYNC2_LBN (2)
  219. #define MDIO_PHYXS_LANE_SYNC3_LBN (3)
  220. /* This ought to be ridiculous overkill. We expect it to fail rarely */
  221. #define MDIO45_RESET_TRIES 100
  222. #define MDIO45_RESET_SPINTIME 10
  223. static int
  224. mdio_clause45_wait_reset_mmds ( struct efab_nic* efab )
  225. {
  226. int tries = MDIO45_RESET_TRIES;
  227. int in_reset;
  228. while(tries) {
  229. int mask = efab->phy_op->mmds;
  230. int mmd = 0;
  231. in_reset = 0;
  232. while(mask) {
  233. if (mask & 1) {
  234. int stat = falcon_mdio_read ( efab, mmd,
  235. MDIO_MMDREG_CTRL1 );
  236. if (stat < 0) {
  237. EFAB_ERR("Failed to read status of MMD %d\n",
  238. mmd );
  239. in_reset = 1;
  240. break;
  241. }
  242. if (stat & (1 << MDIO_MMDREG_CTRL1_RESET_LBN))
  243. in_reset |= (1 << mmd);
  244. }
  245. mask = mask >> 1;
  246. mmd++;
  247. }
  248. if (!in_reset)
  249. break;
  250. tries--;
  251. mdelay ( MDIO45_RESET_SPINTIME );
  252. }
  253. if (in_reset != 0) {
  254. EFAB_ERR("Not all MMDs came out of reset in time. MMDs "
  255. "still in reset: %x\n", in_reset);
  256. return -ETIMEDOUT;
  257. }
  258. return 0;
  259. }
  260. static int
  261. mdio_clause45_reset_mmd ( struct efab_nic *efab, int mmd )
  262. {
  263. int tries = MDIO45_RESET_TRIES;
  264. int ctrl;
  265. falcon_mdio_write ( efab, mmd, MDIO_MMDREG_CTRL1,
  266. ( 1 << MDIO_MMDREG_CTRL1_RESET_LBN ) );
  267. /* Wait for the reset bit to clear. */
  268. do {
  269. mdelay ( MDIO45_RESET_SPINTIME );
  270. ctrl = falcon_mdio_read ( efab, mmd, MDIO_MMDREG_CTRL1 );
  271. if ( ~ctrl & ( 1 << MDIO_MMDREG_CTRL1_RESET_LBN ) )
  272. return 0;
  273. } while ( --tries );
  274. EFAB_ERR ( "Failed to reset mmd %d\n", mmd );
  275. return -ETIMEDOUT;
  276. }
  277. static int
  278. mdio_clause45_links_ok(struct efab_nic *efab )
  279. {
  280. int status, good;
  281. int ok = 1;
  282. int mmd = 0;
  283. int mmd_mask = efab->phy_op->mmds;
  284. while (mmd_mask) {
  285. if (mmd_mask & 1) {
  286. /* Double reads because link state is latched, and a
  287. * read moves the current state into the register */
  288. status = falcon_mdio_read ( efab, mmd,
  289. MDIO_MMDREG_STAT1 );
  290. status = falcon_mdio_read ( efab, mmd,
  291. MDIO_MMDREG_STAT1 );
  292. good = status & (1 << MDIO_MMDREG_STAT1_LINK_LBN);
  293. ok = ok && good;
  294. }
  295. mmd_mask = (mmd_mask >> 1);
  296. mmd++;
  297. }
  298. return ok;
  299. }
  300. static int
  301. mdio_clause45_check_mmds ( struct efab_nic *efab )
  302. {
  303. int mmd = 0;
  304. int devices = falcon_mdio_read ( efab, MDIO_MMD_PHYXS,
  305. MDIO_MMDREG_DEVS0 );
  306. int mmd_mask = efab->phy_op->mmds;
  307. /* Check all the expected MMDs are present */
  308. if ( devices < 0 ) {
  309. EFAB_ERR ( "Failed to read devices present\n" );
  310. return -EIO;
  311. }
  312. if ( ( devices & mmd_mask ) != mmd_mask ) {
  313. EFAB_ERR ( "required MMDs not present: got %x, wanted %x\n",
  314. devices, mmd_mask );
  315. return -EIO;
  316. }
  317. /* Check all required MMDs are responding and happy. */
  318. while ( mmd_mask ) {
  319. if ( mmd_mask & 1 ) {
  320. efab_dword_t reg;
  321. int status;
  322. reg.opaque = falcon_mdio_read ( efab, mmd,
  323. MDIO_MMDREG_STAT2 );
  324. status = EFAB_DWORD_FIELD ( reg,
  325. MDIO_MMDREG_STAT2_PRESENT );
  326. if ( status != MDIO_MMDREG_STAT2_PRESENT_VAL ) {
  327. return -EIO;
  328. }
  329. }
  330. mmd_mask >>= 1;
  331. mmd++;
  332. }
  333. return 0;
  334. }
  335. /* I/O BAR address register */
  336. #define FCN_IOM_IND_ADR_REG 0x0
  337. /* I/O BAR data register */
  338. #define FCN_IOM_IND_DAT_REG 0x4
  339. /* Address region register */
  340. #define FCN_ADR_REGION_REG_KER 0x00
  341. #define FCN_ADR_REGION0_LBN 0
  342. #define FCN_ADR_REGION0_WIDTH 18
  343. #define FCN_ADR_REGION1_LBN 32
  344. #define FCN_ADR_REGION1_WIDTH 18
  345. #define FCN_ADR_REGION2_LBN 64
  346. #define FCN_ADR_REGION2_WIDTH 18
  347. #define FCN_ADR_REGION3_LBN 96
  348. #define FCN_ADR_REGION3_WIDTH 18
  349. /* Interrupt enable register */
  350. #define FCN_INT_EN_REG_KER 0x0010
  351. #define FCN_MEM_PERR_INT_EN_KER_LBN 5
  352. #define FCN_MEM_PERR_INT_EN_KER_WIDTH 1
  353. #define FCN_KER_INT_CHAR_LBN 4
  354. #define FCN_KER_INT_CHAR_WIDTH 1
  355. #define FCN_KER_INT_KER_LBN 3
  356. #define FCN_KER_INT_KER_WIDTH 1
  357. #define FCN_ILL_ADR_ERR_INT_EN_KER_LBN 2
  358. #define FCN_ILL_ADR_ERR_INT_EN_KER_WIDTH 1
  359. #define FCN_SRM_PERR_INT_EN_KER_LBN 1
  360. #define FCN_SRM_PERR_INT_EN_KER_WIDTH 1
  361. #define FCN_DRV_INT_EN_KER_LBN 0
  362. #define FCN_DRV_INT_EN_KER_WIDTH 1
  363. /* Interrupt status register */
  364. #define FCN_INT_ADR_REG_KER 0x0030
  365. #define FCN_INT_ADR_KER_LBN 0
  366. #define FCN_INT_ADR_KER_WIDTH EFAB_DMA_TYPE_WIDTH ( 64 )
  367. /* Interrupt status register (B0 only) */
  368. #define INT_ISR0_B0 0x90
  369. #define INT_ISR1_B0 0xA0
  370. /* Interrupt acknowledge register (A0/A1 only) */
  371. #define FCN_INT_ACK_KER_REG_A1 0x0050
  372. #define INT_ACK_DUMMY_DATA_LBN 0
  373. #define INT_ACK_DUMMY_DATA_WIDTH 32
  374. /* Interrupt acknowledge work-around register (A0/A1 only )*/
  375. #define WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 0x0070
  376. /* Hardware initialisation register */
  377. #define FCN_HW_INIT_REG_KER 0x00c0
  378. #define FCN_BCSR_TARGET_MASK_LBN 101
  379. #define FCN_BCSR_TARGET_MASK_WIDTH 4
  380. /* SPI host command register */
  381. #define FCN_EE_SPI_HCMD_REG 0x0100
  382. #define FCN_EE_SPI_HCMD_CMD_EN_LBN 31
  383. #define FCN_EE_SPI_HCMD_CMD_EN_WIDTH 1
  384. #define FCN_EE_WR_TIMER_ACTIVE_LBN 28
  385. #define FCN_EE_WR_TIMER_ACTIVE_WIDTH 1
  386. #define FCN_EE_SPI_HCMD_SF_SEL_LBN 24
  387. #define FCN_EE_SPI_HCMD_SF_SEL_WIDTH 1
  388. #define FCN_EE_SPI_EEPROM 0
  389. #define FCN_EE_SPI_FLASH 1
  390. #define FCN_EE_SPI_HCMD_DABCNT_LBN 16
  391. #define FCN_EE_SPI_HCMD_DABCNT_WIDTH 5
  392. #define FCN_EE_SPI_HCMD_READ_LBN 15
  393. #define FCN_EE_SPI_HCMD_READ_WIDTH 1
  394. #define FCN_EE_SPI_READ 1
  395. #define FCN_EE_SPI_WRITE 0
  396. #define FCN_EE_SPI_HCMD_DUBCNT_LBN 12
  397. #define FCN_EE_SPI_HCMD_DUBCNT_WIDTH 2
  398. #define FCN_EE_SPI_HCMD_ADBCNT_LBN 8
  399. #define FCN_EE_SPI_HCMD_ADBCNT_WIDTH 2
  400. #define FCN_EE_SPI_HCMD_ENC_LBN 0
  401. #define FCN_EE_SPI_HCMD_ENC_WIDTH 8
  402. /* SPI host address register */
  403. #define FCN_EE_SPI_HADR_REG 0x0110
  404. #define FCN_EE_SPI_HADR_DUBYTE_LBN 24
  405. #define FCN_EE_SPI_HADR_DUBYTE_WIDTH 8
  406. #define FCN_EE_SPI_HADR_ADR_LBN 0
  407. #define FCN_EE_SPI_HADR_ADR_WIDTH 24
  408. /* SPI host data register */
  409. #define FCN_EE_SPI_HDATA_REG 0x0120
  410. #define FCN_EE_SPI_HDATA3_LBN 96
  411. #define FCN_EE_SPI_HDATA3_WIDTH 32
  412. #define FCN_EE_SPI_HDATA2_LBN 64
  413. #define FCN_EE_SPI_HDATA2_WIDTH 32
  414. #define FCN_EE_SPI_HDATA1_LBN 32
  415. #define FCN_EE_SPI_HDATA1_WIDTH 32
  416. #define FCN_EE_SPI_HDATA0_LBN 0
  417. #define FCN_EE_SPI_HDATA0_WIDTH 32
  418. /* VPD Config 0 Register register */
  419. #define FCN_EE_VPD_CFG_REG 0x0140
  420. #define FCN_EE_VPD_EN_LBN 0
  421. #define FCN_EE_VPD_EN_WIDTH 1
  422. #define FCN_EE_VPD_EN_AD9_MODE_LBN 1
  423. #define FCN_EE_VPD_EN_AD9_MODE_WIDTH 1
  424. #define FCN_EE_EE_CLOCK_DIV_LBN 112
  425. #define FCN_EE_EE_CLOCK_DIV_WIDTH 7
  426. #define FCN_EE_SF_CLOCK_DIV_LBN 120
  427. #define FCN_EE_SF_CLOCK_DIV_WIDTH 7
  428. /* NIC status register */
  429. #define FCN_NIC_STAT_REG 0x0200
  430. #define FCN_ONCHIP_SRAM_LBN 16
  431. #define FCN_ONCHIP_SRAM_WIDTH 1
  432. #define FCN_SF_PRST_LBN 9
  433. #define FCN_SF_PRST_WIDTH 1
  434. #define FCN_EE_PRST_LBN 8
  435. #define FCN_EE_PRST_WIDTH 1
  436. #define FCN_EE_STRAP_LBN 7
  437. #define FCN_EE_STRAP_WIDTH 1
  438. #define FCN_PCI_PCIX_MODE_LBN 4
  439. #define FCN_PCI_PCIX_MODE_WIDTH 3
  440. #define FCN_PCI_PCIX_MODE_PCI33_DECODE 0
  441. #define FCN_PCI_PCIX_MODE_PCI66_DECODE 1
  442. #define FCN_PCI_PCIX_MODE_PCIX66_DECODE 5
  443. #define FCN_PCI_PCIX_MODE_PCIX100_DECODE 6
  444. #define FCN_PCI_PCIX_MODE_PCIX133_DECODE 7
  445. #define FCN_STRAP_ISCSI_EN_LBN 3
  446. #define FCN_STRAP_ISCSI_EN_WIDTH 1
  447. #define FCN_STRAP_PINS_LBN 0
  448. #define FCN_STRAP_PINS_WIDTH 3
  449. #define FCN_STRAP_10G_LBN 2
  450. #define FCN_STRAP_10G_WIDTH 1
  451. #define FCN_STRAP_DUAL_PORT_LBN 1
  452. #define FCN_STRAP_DUAL_PORT_WIDTH 1
  453. #define FCN_STRAP_PCIE_LBN 0
  454. #define FCN_STRAP_PCIE_WIDTH 1
  455. /* Falcon revisions */
  456. #define FALCON_REV_A0 0
  457. #define FALCON_REV_A1 1
  458. #define FALCON_REV_B0 2
  459. /* GPIO control register */
  460. #define FCN_GPIO_CTL_REG_KER 0x0210
  461. #define FCN_GPIO_CTL_REG_KER 0x0210
  462. #define FCN_GPIO3_OEN_LBN 27
  463. #define FCN_GPIO3_OEN_WIDTH 1
  464. #define FCN_GPIO2_OEN_LBN 26
  465. #define FCN_GPIO2_OEN_WIDTH 1
  466. #define FCN_GPIO1_OEN_LBN 25
  467. #define FCN_GPIO1_OEN_WIDTH 1
  468. #define FCN_GPIO0_OEN_LBN 24
  469. #define FCN_GPIO0_OEN_WIDTH 1
  470. #define FCN_GPIO3_OUT_LBN 19
  471. #define FCN_GPIO3_OUT_WIDTH 1
  472. #define FCN_GPIO2_OUT_LBN 18
  473. #define FCN_GPIO2_OUT_WIDTH 1
  474. #define FCN_GPIO1_OUT_LBN 17
  475. #define FCN_GPIO1_OUT_WIDTH 1
  476. #define FCN_GPIO0_OUT_LBN 16
  477. #define FCN_GPIO0_OUT_WIDTH 1
  478. #define FCN_GPIO3_IN_LBN 11
  479. #define FCN_GPIO3_IN_WIDTH 1
  480. #define FCN_GPIO2_IN_LBN 10
  481. #define FCN_GPIO2_IN_WIDTH 1
  482. #define FCN_GPIO1_IN_LBN 9
  483. #define FCN_GPIO1_IN_WIDTH 1
  484. #define FCN_GPIO0_IN_LBN 8
  485. #define FCN_GPIO0_IN_WIDTH 1
  486. #define FCN_FLASH_PRESENT_LBN 7
  487. #define FCN_FLASH_PRESENT_WIDTH 1
  488. #define FCN_EEPROM_PRESENT_LBN 6
  489. #define FCN_EEPROM_PRESENT_WIDTH 1
  490. #define FCN_BOOTED_USING_NVDEVICE_LBN 3
  491. #define FCN_BOOTED_USING_NVDEVICE_WIDTH 1
  492. /* Defines for extra non-volatile storage */
  493. #define FCN_NV_MAGIC_NUMBER 0xFA1C
  494. /* Global control register */
  495. #define FCN_GLB_CTL_REG_KER 0x0220
  496. #define FCN_EXT_PHY_RST_CTL_LBN 63
  497. #define FCN_EXT_PHY_RST_CTL_WIDTH 1
  498. #define FCN_PCIE_SD_RST_CTL_LBN 61
  499. #define FCN_PCIE_SD_RST_CTL_WIDTH 1
  500. #define FCN_PCIE_STCK_RST_CTL_LBN 59
  501. #define FCN_PCIE_STCK_RST_CTL_WIDTH 1
  502. #define FCN_PCIE_NSTCK_RST_CTL_LBN 58
  503. #define FCN_PCIE_NSTCK_RST_CTL_WIDTH 1
  504. #define FCN_PCIE_CORE_RST_CTL_LBN 57
  505. #define FCN_PCIE_CORE_RST_CTL_WIDTH 1
  506. #define FCN_EE_RST_CTL_LBN 49
  507. #define FCN_EE_RST_CTL_WIDTH 1
  508. #define FCN_RST_EXT_PHY_LBN 31
  509. #define FCN_RST_EXT_PHY_WIDTH 1
  510. #define FCN_EXT_PHY_RST_DUR_LBN 1
  511. #define FCN_EXT_PHY_RST_DUR_WIDTH 3
  512. #define FCN_SWRST_LBN 0
  513. #define FCN_SWRST_WIDTH 1
  514. #define INCLUDE_IN_RESET 0
  515. #define EXCLUDE_FROM_RESET 1
  516. /* FPGA build version */
  517. #define FCN_ALTERA_BUILD_REG_KER 0x0300
  518. #define FCN_VER_MAJOR_LBN 24
  519. #define FCN_VER_MAJOR_WIDTH 8
  520. #define FCN_VER_MINOR_LBN 16
  521. #define FCN_VER_MINOR_WIDTH 8
  522. #define FCN_VER_BUILD_LBN 0
  523. #define FCN_VER_BUILD_WIDTH 16
  524. #define FCN_VER_ALL_LBN 0
  525. #define FCN_VER_ALL_WIDTH 32
  526. /* Spare EEPROM bits register (flash 0x390) */
  527. #define FCN_SPARE_REG_KER 0x310
  528. #define FCN_MEM_PERR_EN_TX_DATA_LBN 72
  529. #define FCN_MEM_PERR_EN_TX_DATA_WIDTH 2
  530. /* Timer table for kernel access */
  531. #define FCN_TIMER_CMD_REG_KER 0x420
  532. #define FCN_TIMER_MODE_LBN 12
  533. #define FCN_TIMER_MODE_WIDTH 2
  534. #define FCN_TIMER_MODE_DIS 0
  535. #define FCN_TIMER_MODE_INT_HLDOFF 1
  536. #define FCN_TIMER_VAL_LBN 0
  537. #define FCN_TIMER_VAL_WIDTH 12
  538. /* Receive configuration register */
  539. #define FCN_RX_CFG_REG_KER 0x800
  540. #define FCN_RX_XOFF_EN_LBN 0
  541. #define FCN_RX_XOFF_EN_WIDTH 1
  542. /* SRAM receive descriptor cache configuration register */
  543. #define FCN_SRM_RX_DC_CFG_REG_KER 0x610
  544. #define FCN_SRM_RX_DC_BASE_ADR_LBN 0
  545. #define FCN_SRM_RX_DC_BASE_ADR_WIDTH 21
  546. /* SRAM transmit descriptor cache configuration register */
  547. #define FCN_SRM_TX_DC_CFG_REG_KER 0x620
  548. #define FCN_SRM_TX_DC_BASE_ADR_LBN 0
  549. #define FCN_SRM_TX_DC_BASE_ADR_WIDTH 21
  550. /* SRAM configuration register */
  551. #define FCN_SRM_CFG_REG_KER 0x630
  552. #define FCN_SRAM_OOB_ADR_INTEN_LBN 5
  553. #define FCN_SRAM_OOB_ADR_INTEN_WIDTH 1
  554. #define FCN_SRAM_OOB_BUF_INTEN_LBN 4
  555. #define FCN_SRAM_OOB_BUF_INTEN_WIDTH 1
  556. #define FCN_SRAM_OOB_BT_INIT_EN_LBN 3
  557. #define FCN_SRAM_OOB_BT_INIT_EN_WIDTH 1
  558. #define FCN_SRM_NUM_BANK_LBN 2
  559. #define FCN_SRM_NUM_BANK_WIDTH 1
  560. #define FCN_SRM_BANK_SIZE_LBN 0
  561. #define FCN_SRM_BANK_SIZE_WIDTH 2
  562. #define FCN_SRM_NUM_BANKS_AND_BANK_SIZE_LBN 0
  563. #define FCN_SRM_NUM_BANKS_AND_BANK_SIZE_WIDTH 3
  564. #define FCN_RX_CFG_REG_KER 0x800
  565. #define FCN_RX_INGR_EN_B0_LBN 47
  566. #define FCN_RX_INGR_EN_B0_WIDTH 1
  567. #define FCN_RX_USR_BUF_SIZE_B0_LBN 19
  568. #define FCN_RX_USR_BUF_SIZE_B0_WIDTH 9
  569. #define FCN_RX_XON_MAC_TH_B0_LBN 10
  570. #define FCN_RX_XON_MAC_TH_B0_WIDTH 9
  571. #define FCN_RX_XOFF_MAC_TH_B0_LBN 1
  572. #define FCN_RX_XOFF_MAC_TH_B0_WIDTH 9
  573. #define FCN_RX_XOFF_MAC_EN_B0_LBN 0
  574. #define FCN_RX_XOFF_MAC_EN_B0_WIDTH 1
  575. #define FCN_RX_USR_BUF_SIZE_A1_LBN 11
  576. #define FCN_RX_USR_BUF_SIZE_A1_WIDTH 9
  577. #define FCN_RX_XON_MAC_TH_A1_LBN 6
  578. #define FCN_RX_XON_MAC_TH_A1_WIDTH 5
  579. #define FCN_RX_XOFF_MAC_TH_A1_LBN 1
  580. #define FCN_RX_XOFF_MAC_TH_A1_WIDTH 5
  581. #define FCN_RX_XOFF_MAC_EN_A1_LBN 0
  582. #define FCN_RX_XOFF_MAC_EN_A1_WIDTH 1
  583. #define FCN_RX_USR_BUF_SIZE_A1_LBN 11
  584. #define FCN_RX_USR_BUF_SIZE_A1_WIDTH 9
  585. #define FCN_RX_XOFF_MAC_EN_A1_LBN 0
  586. #define FCN_RX_XOFF_MAC_EN_A1_WIDTH 1
  587. /* Receive filter control register */
  588. #define FCN_RX_FILTER_CTL_REG_KER 0x810
  589. #define FCN_UDP_FULL_SRCH_LIMIT_LBN 32
  590. #define FCN_UDP_FULL_SRCH_LIMIT_WIDTH 8
  591. #define FCN_NUM_KER_LBN 24
  592. #define FCN_NUM_KER_WIDTH 2
  593. #define FCN_UDP_WILD_SRCH_LIMIT_LBN 16
  594. #define FCN_UDP_WILD_SRCH_LIMIT_WIDTH 8
  595. #define FCN_TCP_WILD_SRCH_LIMIT_LBN 8
  596. #define FCN_TCP_WILD_SRCH_LIMIT_WIDTH 8
  597. #define FCN_TCP_FULL_SRCH_LIMIT_LBN 0
  598. #define FCN_TCP_FULL_SRCH_LIMIT_WIDTH 8
  599. /* RX queue flush register */
  600. #define FCN_RX_FLUSH_DESCQ_REG_KER 0x0820
  601. #define FCN_RX_FLUSH_DESCQ_CMD_LBN 24
  602. #define FCN_RX_FLUSH_DESCQ_CMD_WIDTH 1
  603. #define FCN_RX_FLUSH_DESCQ_LBN 0
  604. #define FCN_RX_FLUSH_DESCQ_WIDTH 12
  605. /* Receive descriptor update register */
  606. #define FCN_RX_DESC_UPD_REG_KER 0x0830
  607. #define FCN_RX_DESC_WPTR_LBN 96
  608. #define FCN_RX_DESC_WPTR_WIDTH 12
  609. #define FCN_RX_DESC_UPD_REG_KER_DWORD ( FCN_RX_DESC_UPD_REG_KER + 12 )
  610. #define FCN_RX_DESC_WPTR_DWORD_LBN 0
  611. #define FCN_RX_DESC_WPTR_DWORD_WIDTH 12
  612. /* Receive descriptor cache configuration register */
  613. #define FCN_RX_DC_CFG_REG_KER 0x840
  614. #define FCN_RX_DC_SIZE_LBN 0
  615. #define FCN_RX_DC_SIZE_WIDTH 2
  616. #define FCN_RX_SELF_RST_REG_KER 0x890
  617. #define FCN_RX_ISCSI_DIS_LBN 17
  618. #define FCN_RX_ISCSI_DIS_WIDTH 1
  619. #define FCN_RX_NODESC_WAIT_DIS_LBN 9
  620. #define FCN_RX_NODESC_WAIT_DIS_WIDTH 1
  621. #define FCN_RX_RECOVERY_EN_LBN 8
  622. #define FCN_RX_RECOVERY_EN_WIDTH 1
  623. /* TX queue flush register */
  624. #define FCN_TX_FLUSH_DESCQ_REG_KER 0x0a00
  625. #define FCN_TX_FLUSH_DESCQ_CMD_LBN 12
  626. #define FCN_TX_FLUSH_DESCQ_CMD_WIDTH 1
  627. #define FCN_TX_FLUSH_DESCQ_LBN 0
  628. #define FCN_TX_FLUSH_DESCQ_WIDTH 12
  629. /* Transmit configuration register 2 */
  630. #define FCN_TX_CFG2_REG_KER 0xa80
  631. #define FCN_TX_DIS_NON_IP_EV_LBN 17
  632. #define FCN_TX_DIS_NON_IP_EV_WIDTH 1
  633. /* Transmit descriptor update register */
  634. #define FCN_TX_DESC_UPD_REG_KER 0x0a10
  635. #define FCN_TX_DESC_WPTR_LBN 96
  636. #define FCN_TX_DESC_WPTR_WIDTH 12
  637. #define FCN_TX_DESC_UPD_REG_KER_DWORD ( FCN_TX_DESC_UPD_REG_KER + 12 )
  638. #define FCN_TX_DESC_WPTR_DWORD_LBN 0
  639. #define FCN_TX_DESC_WPTR_DWORD_WIDTH 12
  640. /* Transmit descriptor cache configuration register */
  641. #define FCN_TX_DC_CFG_REG_KER 0xa20
  642. #define FCN_TX_DC_SIZE_LBN 0
  643. #define FCN_TX_DC_SIZE_WIDTH 2
  644. /* PHY management transmit data register */
  645. #define FCN_MD_TXD_REG_KER 0xc00
  646. #define FCN_MD_TXD_LBN 0
  647. #define FCN_MD_TXD_WIDTH 16
  648. /* PHY management receive data register */
  649. #define FCN_MD_RXD_REG_KER 0xc10
  650. #define FCN_MD_RXD_LBN 0
  651. #define FCN_MD_RXD_WIDTH 16
  652. /* PHY management configuration & status register */
  653. #define FCN_MD_CS_REG_KER 0xc20
  654. #define FCN_MD_GC_LBN 4
  655. #define FCN_MD_GC_WIDTH 1
  656. #define FCN_MD_RIC_LBN 2
  657. #define FCN_MD_RIC_WIDTH 1
  658. #define FCN_MD_RDC_LBN 1
  659. #define FCN_MD_RDC_WIDTH 1
  660. #define FCN_MD_WRC_LBN 0
  661. #define FCN_MD_WRC_WIDTH 1
  662. /* PHY management PHY address register */
  663. #define FCN_MD_PHY_ADR_REG_KER 0xc30
  664. #define FCN_MD_PHY_ADR_LBN 0
  665. #define FCN_MD_PHY_ADR_WIDTH 16
  666. /* PHY management ID register */
  667. #define FCN_MD_ID_REG_KER 0xc40
  668. #define FCN_MD_PRT_ADR_LBN 11
  669. #define FCN_MD_PRT_ADR_WIDTH 5
  670. #define FCN_MD_DEV_ADR_LBN 6
  671. #define FCN_MD_DEV_ADR_WIDTH 5
  672. /* PHY management status & mask register */
  673. #define FCN_MD_STAT_REG_KER 0xc50
  674. #define FCN_MD_PINT_LBN 4
  675. #define FCN_MD_PINT_WIDTH 1
  676. #define FCN_MD_DONE_LBN 3
  677. #define FCN_MD_DONE_WIDTH 1
  678. #define FCN_MD_BSERR_LBN 2
  679. #define FCN_MD_BSERR_WIDTH 1
  680. #define FCN_MD_LNFL_LBN 1
  681. #define FCN_MD_LNFL_WIDTH 1
  682. #define FCN_MD_BSY_LBN 0
  683. #define FCN_MD_BSY_WIDTH 1
  684. /* Port 0 and 1 MAC control registers */
  685. #define FCN_MAC0_CTRL_REG_KER 0xc80
  686. #define FCN_MAC1_CTRL_REG_KER 0xc90
  687. #define FCN_MAC_XOFF_VAL_LBN 16
  688. #define FCN_MAC_XOFF_VAL_WIDTH 16
  689. #define FCN_MAC_BCAD_ACPT_LBN 4
  690. #define FCN_MAC_BCAD_ACPT_WIDTH 1
  691. #define FCN_MAC_UC_PROM_LBN 3
  692. #define FCN_MAC_UC_PROM_WIDTH 1
  693. #define FCN_MAC_LINK_STATUS_LBN 2
  694. #define FCN_MAC_LINK_STATUS_WIDTH 1
  695. #define FCN_MAC_SPEED_LBN 0
  696. #define FCN_MAC_SPEED_WIDTH 2
  697. /* 10Gig Xaui XGXS Default Values */
  698. #define XX_TXDRV_DEQ_DEFAULT 0xe /* deq=.6 */
  699. #define XX_TXDRV_DTX_DEFAULT 0x5 /* 1.25 */
  700. #define XX_SD_CTL_DRV_DEFAULT 0 /* 20mA */
  701. /* GMAC registers */
  702. #define FALCON_GMAC_REGBANK 0xe00
  703. #define FALCON_GMAC_REGBANK_SIZE 0x200
  704. #define FALCON_GMAC_REG_SIZE 0x10
  705. /* XGMAC registers */
  706. #define FALCON_XMAC_REGBANK 0x1200
  707. #define FALCON_XMAC_REGBANK_SIZE 0x200
  708. #define FALCON_XMAC_REG_SIZE 0x10
  709. /* XGMAC address register low */
  710. #define FCN_XM_ADR_LO_REG_MAC 0x00
  711. #define FCN_XM_ADR_3_LBN 24
  712. #define FCN_XM_ADR_3_WIDTH 8
  713. #define FCN_XM_ADR_2_LBN 16
  714. #define FCN_XM_ADR_2_WIDTH 8
  715. #define FCN_XM_ADR_1_LBN 8
  716. #define FCN_XM_ADR_1_WIDTH 8
  717. #define FCN_XM_ADR_0_LBN 0
  718. #define FCN_XM_ADR_0_WIDTH 8
  719. /* XGMAC address register high */
  720. #define FCN_XM_ADR_HI_REG_MAC 0x01
  721. #define FCN_XM_ADR_5_LBN 8
  722. #define FCN_XM_ADR_5_WIDTH 8
  723. #define FCN_XM_ADR_4_LBN 0
  724. #define FCN_XM_ADR_4_WIDTH 8
  725. /* XGMAC global configuration - port 0*/
  726. #define FCN_XM_GLB_CFG_REG_MAC 0x02
  727. #define FCN_XM_RX_STAT_EN_LBN 11
  728. #define FCN_XM_RX_STAT_EN_WIDTH 1
  729. #define FCN_XM_TX_STAT_EN_LBN 10
  730. #define FCN_XM_TX_STAT_EN_WIDTH 1
  731. #define FCN_XM_RX_JUMBO_MODE_LBN 6
  732. #define FCN_XM_RX_JUMBO_MODE_WIDTH 1
  733. #define FCN_XM_CORE_RST_LBN 0
  734. #define FCN_XM_CORE_RST_WIDTH 1
  735. /* XGMAC transmit configuration - port 0 */
  736. #define FCN_XM_TX_CFG_REG_MAC 0x03
  737. #define FCN_XM_IPG_LBN 16
  738. #define FCN_XM_IPG_WIDTH 4
  739. #define FCN_XM_FCNTL_LBN 10
  740. #define FCN_XM_FCNTL_WIDTH 1
  741. #define FCN_XM_TXCRC_LBN 8
  742. #define FCN_XM_TXCRC_WIDTH 1
  743. #define FCN_XM_AUTO_PAD_LBN 5
  744. #define FCN_XM_AUTO_PAD_WIDTH 1
  745. #define FCN_XM_TX_PRMBL_LBN 2
  746. #define FCN_XM_TX_PRMBL_WIDTH 1
  747. #define FCN_XM_TXEN_LBN 1
  748. #define FCN_XM_TXEN_WIDTH 1
  749. /* XGMAC receive configuration - port 0 */
  750. #define FCN_XM_RX_CFG_REG_MAC 0x04
  751. #define FCN_XM_PASS_CRC_ERR_LBN 25
  752. #define FCN_XM_PASS_CRC_ERR_WIDTH 1
  753. #define FCN_XM_AUTO_DEPAD_LBN 8
  754. #define FCN_XM_AUTO_DEPAD_WIDTH 1
  755. #define FCN_XM_RXEN_LBN 1
  756. #define FCN_XM_RXEN_WIDTH 1
  757. /* XGMAC management interrupt mask register */
  758. #define FCN_XM_MGT_INT_MSK_REG_MAC_B0 0x5
  759. #define FCN_XM_MSK_PRMBLE_ERR_LBN 2
  760. #define FCN_XM_MSK_PRMBLE_ERR_WIDTH 1
  761. #define FCN_XM_MSK_RMTFLT_LBN 1
  762. #define FCN_XM_MSK_RMTFLT_WIDTH 1
  763. #define FCN_XM_MSK_LCLFLT_LBN 0
  764. #define FCN_XM_MSK_LCLFLT_WIDTH 1
  765. /* XGMAC flow control register */
  766. #define FCN_XM_FC_REG_MAC 0x7
  767. #define FCN_XM_PAUSE_TIME_LBN 16
  768. #define FCN_XM_PAUSE_TIME_WIDTH 16
  769. #define FCN_XM_DIS_FCNTL_LBN 0
  770. #define FCN_XM_DIS_FCNTL_WIDTH 1
  771. /* XGMAC transmit parameter register */
  772. #define FCN_XM_TX_PARAM_REG_MAC 0x0d
  773. #define FCN_XM_TX_JUMBO_MODE_LBN 31
  774. #define FCN_XM_TX_JUMBO_MODE_WIDTH 1
  775. #define FCN_XM_MAX_TX_FRM_SIZE_LBN 16
  776. #define FCN_XM_MAX_TX_FRM_SIZE_WIDTH 14
  777. #define FCN_XM_ACPT_ALL_MCAST_LBN 11
  778. #define FCN_XM_ACPT_ALL_MCAST_WIDTH 1
  779. /* XGMAC receive parameter register */
  780. #define FCN_XM_RX_PARAM_REG_MAC 0x0e
  781. #define FCN_XM_MAX_RX_FRM_SIZE_LBN 0
  782. #define FCN_XM_MAX_RX_FRM_SIZE_WIDTH 14
  783. /* XGMAC management interrupt status register */
  784. #define FCN_XM_MGT_INT_REG_MAC_B0 0x0f
  785. #define FCN_XM_PRMBLE_ERR 2
  786. #define FCN_XM_PRMBLE_WIDTH 1
  787. #define FCN_XM_RMTFLT_LBN 1
  788. #define FCN_XM_RMTFLT_WIDTH 1
  789. #define FCN_XM_LCLFLT_LBN 0
  790. #define FCN_XM_LCLFLT_WIDTH 1
  791. /* XAUI XGXS core status register */
  792. #define FCN_XX_ALIGN_DONE_LBN 20
  793. #define FCN_XX_ALIGN_DONE_WIDTH 1
  794. #define FCN_XX_CORE_STAT_REG_MAC 0x16
  795. #define FCN_XX_SYNC_STAT_LBN 16
  796. #define FCN_XX_SYNC_STAT_WIDTH 4
  797. #define FCN_XX_SYNC_STAT_DECODE_SYNCED 0xf
  798. #define FCN_XX_COMMA_DET_LBN 12
  799. #define FCN_XX_COMMA_DET_WIDTH 4
  800. #define FCN_XX_COMMA_DET_RESET 0xf
  801. #define FCN_XX_CHARERR_LBN 4
  802. #define FCN_XX_CHARERR_WIDTH 4
  803. #define FCN_XX_CHARERR_RESET 0xf
  804. #define FCN_XX_DISPERR_LBN 0
  805. #define FCN_XX_DISPERR_WIDTH 4
  806. #define FCN_XX_DISPERR_RESET 0xf
  807. /* XGXS/XAUI powerdown/reset register */
  808. #define FCN_XX_PWR_RST_REG_MAC 0x10
  809. #define FCN_XX_PWRDND_EN_LBN 15
  810. #define FCN_XX_PWRDND_EN_WIDTH 1
  811. #define FCN_XX_PWRDNC_EN_LBN 14
  812. #define FCN_XX_PWRDNC_EN_WIDTH 1
  813. #define FCN_XX_PWRDNB_EN_LBN 13
  814. #define FCN_XX_PWRDNB_EN_WIDTH 1
  815. #define FCN_XX_PWRDNA_EN_LBN 12
  816. #define FCN_XX_PWRDNA_EN_WIDTH 1
  817. #define FCN_XX_RSTPLLCD_EN_LBN 9
  818. #define FCN_XX_RSTPLLCD_EN_WIDTH 1
  819. #define FCN_XX_RSTPLLAB_EN_LBN 8
  820. #define FCN_XX_RSTPLLAB_EN_WIDTH 1
  821. #define FCN_XX_RESETD_EN_LBN 7
  822. #define FCN_XX_RESETD_EN_WIDTH 1
  823. #define FCN_XX_RESETC_EN_LBN 6
  824. #define FCN_XX_RESETC_EN_WIDTH 1
  825. #define FCN_XX_RESETB_EN_LBN 5
  826. #define FCN_XX_RESETB_EN_WIDTH 1
  827. #define FCN_XX_RESETA_EN_LBN 4
  828. #define FCN_XX_RESETA_EN_WIDTH 1
  829. #define FCN_XX_RSTXGXSRX_EN_LBN 2
  830. #define FCN_XX_RSTXGXSRX_EN_WIDTH 1
  831. #define FCN_XX_RSTXGXSTX_EN_LBN 1
  832. #define FCN_XX_RSTXGXSTX_EN_WIDTH 1
  833. #define FCN_XX_RST_XX_EN_LBN 0
  834. #define FCN_XX_RST_XX_EN_WIDTH 1
  835. /* XGXS/XAUI powerdown/reset control register */
  836. #define FCN_XX_SD_CTL_REG_MAC 0x11
  837. #define FCN_XX_TERMADJ1_LBN 17
  838. #define FCN_XX_TERMADJ1_WIDTH 1
  839. #define FCN_XX_TERMADJ0_LBN 16
  840. #define FCN_XX_TERMADJ0_WIDTH 1
  841. #define FCN_XX_HIDRVD_LBN 15
  842. #define FCN_XX_HIDRVD_WIDTH 1
  843. #define FCN_XX_LODRVD_LBN 14
  844. #define FCN_XX_LODRVD_WIDTH 1
  845. #define FCN_XX_HIDRVC_LBN 13
  846. #define FCN_XX_HIDRVC_WIDTH 1
  847. #define FCN_XX_LODRVC_LBN 12
  848. #define FCN_XX_LODRVC_WIDTH 1
  849. #define FCN_XX_HIDRVB_LBN 11
  850. #define FCN_XX_HIDRVB_WIDTH 1
  851. #define FCN_XX_LODRVB_LBN 10
  852. #define FCN_XX_LODRVB_WIDTH 1
  853. #define FCN_XX_HIDRVA_LBN 9
  854. #define FCN_XX_HIDRVA_WIDTH 1
  855. #define FCN_XX_LODRVA_LBN 8
  856. #define FCN_XX_LODRVA_WIDTH 1
  857. #define FCN_XX_LPBKD_LBN 3
  858. #define FCN_XX_LPBKD_WIDTH 1
  859. #define FCN_XX_LPBKC_LBN 2
  860. #define FCN_XX_LPBKC_WIDTH 1
  861. #define FCN_XX_LPBKB_LBN 1
  862. #define FCN_XX_LPBKB_WIDTH 1
  863. #define FCN_XX_LPBKA_LBN 0
  864. #define FCN_XX_LPBKA_WIDTH 1
  865. #define FCN_XX_TXDRV_CTL_REG_MAC 0x12
  866. #define FCN_XX_DEQD_LBN 28
  867. #define FCN_XX_DEQD_WIDTH 4
  868. #define FCN_XX_DEQC_LBN 24
  869. #define FCN_XX_DEQC_WIDTH 4
  870. #define FCN_XX_DEQB_LBN 20
  871. #define FCN_XX_DEQB_WIDTH 4
  872. #define FCN_XX_DEQA_LBN 16
  873. #define FCN_XX_DEQA_WIDTH 4
  874. #define FCN_XX_DTXD_LBN 12
  875. #define FCN_XX_DTXD_WIDTH 4
  876. #define FCN_XX_DTXC_LBN 8
  877. #define FCN_XX_DTXC_WIDTH 4
  878. #define FCN_XX_DTXB_LBN 4
  879. #define FCN_XX_DTXB_WIDTH 4
  880. #define FCN_XX_DTXA_LBN 0
  881. #define FCN_XX_DTXA_WIDTH 4
  882. /* Receive filter table */
  883. #define FCN_RX_FILTER_TBL0 0xF00000
  884. /* Receive descriptor pointer table */
  885. #define FCN_RX_DESC_PTR_TBL_KER_A1 0x11800
  886. #define FCN_RX_DESC_PTR_TBL_KER_B0 0xF40000
  887. #define FCN_RX_ISCSI_DDIG_EN_LBN 88
  888. #define FCN_RX_ISCSI_DDIG_EN_WIDTH 1
  889. #define FCN_RX_ISCSI_HDIG_EN_LBN 87
  890. #define FCN_RX_ISCSI_HDIG_EN_WIDTH 1
  891. #define FCN_RX_DESCQ_BUF_BASE_ID_LBN 36
  892. #define FCN_RX_DESCQ_BUF_BASE_ID_WIDTH 20
  893. #define FCN_RX_DESCQ_EVQ_ID_LBN 24
  894. #define FCN_RX_DESCQ_EVQ_ID_WIDTH 12
  895. #define FCN_RX_DESCQ_OWNER_ID_LBN 10
  896. #define FCN_RX_DESCQ_OWNER_ID_WIDTH 14
  897. #define FCN_RX_DESCQ_SIZE_LBN 3
  898. #define FCN_RX_DESCQ_SIZE_WIDTH 2
  899. #define FCN_RX_DESCQ_SIZE_4K 3
  900. #define FCN_RX_DESCQ_SIZE_2K 2
  901. #define FCN_RX_DESCQ_SIZE_1K 1
  902. #define FCN_RX_DESCQ_SIZE_512 0
  903. #define FCN_RX_DESCQ_TYPE_LBN 2
  904. #define FCN_RX_DESCQ_TYPE_WIDTH 1
  905. #define FCN_RX_DESCQ_JUMBO_LBN 1
  906. #define FCN_RX_DESCQ_JUMBO_WIDTH 1
  907. #define FCN_RX_DESCQ_EN_LBN 0
  908. #define FCN_RX_DESCQ_EN_WIDTH 1
  909. /* Transmit descriptor pointer table */
  910. #define FCN_TX_DESC_PTR_TBL_KER_A1 0x11900
  911. #define FCN_TX_DESC_PTR_TBL_KER_B0 0xF50000
  912. #define FCN_TX_NON_IP_DROP_DIS_B0_LBN 91
  913. #define FCN_TX_NON_IP_DROP_DIS_B0_WIDTH 1
  914. #define FCN_TX_DESCQ_EN_LBN 88
  915. #define FCN_TX_DESCQ_EN_WIDTH 1
  916. #define FCN_TX_ISCSI_DDIG_EN_LBN 87
  917. #define FCN_TX_ISCSI_DDIG_EN_WIDTH 1
  918. #define FCN_TX_ISCSI_HDIG_EN_LBN 86
  919. #define FCN_TX_ISCSI_HDIG_EN_WIDTH 1
  920. #define FCN_TX_DESCQ_BUF_BASE_ID_LBN 36
  921. #define FCN_TX_DESCQ_BUF_BASE_ID_WIDTH 20
  922. #define FCN_TX_DESCQ_EVQ_ID_LBN 24
  923. #define FCN_TX_DESCQ_EVQ_ID_WIDTH 12
  924. #define FCN_TX_DESCQ_OWNER_ID_LBN 10
  925. #define FCN_TX_DESCQ_OWNER_ID_WIDTH 14
  926. #define FCN_TX_DESCQ_SIZE_LBN 3
  927. #define FCN_TX_DESCQ_SIZE_WIDTH 2
  928. #define FCN_TX_DESCQ_SIZE_4K 3
  929. #define FCN_TX_DESCQ_SIZE_2K 2
  930. #define FCN_TX_DESCQ_SIZE_1K 1
  931. #define FCN_TX_DESCQ_SIZE_512 0
  932. #define FCN_TX_DESCQ_TYPE_LBN 1
  933. #define FCN_TX_DESCQ_TYPE_WIDTH 2
  934. #define FCN_TX_DESCQ_FLUSH_LBN 0
  935. #define FCN_TX_DESCQ_FLUSH_WIDTH 1
  936. /* Event queue pointer */
  937. #define FCN_EVQ_PTR_TBL_KER_A1 0x11a00
  938. #define FCN_EVQ_PTR_TBL_KER_B0 0xf60000
  939. #define FCN_EVQ_EN_LBN 23
  940. #define FCN_EVQ_EN_WIDTH 1
  941. #define FCN_EVQ_SIZE_LBN 20
  942. #define FCN_EVQ_SIZE_WIDTH 3
  943. #define FCN_EVQ_SIZE_32K 6
  944. #define FCN_EVQ_SIZE_16K 5
  945. #define FCN_EVQ_SIZE_8K 4
  946. #define FCN_EVQ_SIZE_4K 3
  947. #define FCN_EVQ_SIZE_2K 2
  948. #define FCN_EVQ_SIZE_1K 1
  949. #define FCN_EVQ_SIZE_512 0
  950. #define FCN_EVQ_BUF_BASE_ID_LBN 0
  951. #define FCN_EVQ_BUF_BASE_ID_WIDTH 20
  952. /* RSS indirection table */
  953. #define FCN_RX_RSS_INDIR_TBL_B0 0xFB0000
  954. /* Event queue read pointer */
  955. #define FCN_EVQ_RPTR_REG_KER_A1 0x11b00
  956. #define FCN_EVQ_RPTR_REG_KER_B0 0xfa0000
  957. #define FCN_EVQ_RPTR_LBN 0
  958. #define FCN_EVQ_RPTR_WIDTH 14
  959. #define FCN_EVQ_RPTR_REG_KER_DWORD_A1 ( FCN_EVQ_RPTR_REG_KER_A1 + 0 )
  960. #define FCN_EVQ_RPTR_REG_KER_DWORD_B0 ( FCN_EVQ_RPTR_REG_KER_B0 + 0 )
  961. #define FCN_EVQ_RPTR_DWORD_LBN 0
  962. #define FCN_EVQ_RPTR_DWORD_WIDTH 14
  963. /* Special buffer descriptors */
  964. #define FCN_BUF_FULL_TBL_KER_A1 0x18000
  965. #define FCN_BUF_FULL_TBL_KER_B0 0x800000
  966. #define FCN_IP_DAT_BUF_SIZE_LBN 50
  967. #define FCN_IP_DAT_BUF_SIZE_WIDTH 1
  968. #define FCN_IP_DAT_BUF_SIZE_8K 1
  969. #define FCN_IP_DAT_BUF_SIZE_4K 0
  970. #define FCN_BUF_ADR_FBUF_LBN 14
  971. #define FCN_BUF_ADR_FBUF_WIDTH 34
  972. #define FCN_BUF_OWNER_ID_FBUF_LBN 0
  973. #define FCN_BUF_OWNER_ID_FBUF_WIDTH 14
  974. /** Offset of a GMAC register within Falcon */
  975. #define FALCON_GMAC_REG( efab, mac_reg ) \
  976. ( FALCON_GMAC_REGBANK + \
  977. ( (mac_reg) * FALCON_GMAC_REG_SIZE ) )
  978. /** Offset of an XMAC register within Falcon */
  979. #define FALCON_XMAC_REG( efab_port, mac_reg ) \
  980. ( FALCON_XMAC_REGBANK + \
  981. ( (mac_reg) * FALCON_XMAC_REG_SIZE ) )
  982. #define FCN_MAC_DATA_LBN 0
  983. #define FCN_MAC_DATA_WIDTH 32
  984. /* Transmit descriptor */
  985. #define FCN_TX_KER_PORT_LBN 63
  986. #define FCN_TX_KER_PORT_WIDTH 1
  987. #define FCN_TX_KER_BYTE_CNT_LBN 48
  988. #define FCN_TX_KER_BYTE_CNT_WIDTH 14
  989. #define FCN_TX_KER_BUF_ADR_LBN 0
  990. #define FCN_TX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 )
  991. /* Receive descriptor */
  992. #define FCN_RX_KER_BUF_SIZE_LBN 48
  993. #define FCN_RX_KER_BUF_SIZE_WIDTH 14
  994. #define FCN_RX_KER_BUF_ADR_LBN 0
  995. #define FCN_RX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 )
  996. /* Event queue entries */
  997. #define FCN_EV_CODE_LBN 60
  998. #define FCN_EV_CODE_WIDTH 4
  999. #define FCN_RX_IP_EV_DECODE 0
  1000. #define FCN_TX_IP_EV_DECODE 2
  1001. #define FCN_DRIVER_EV_DECODE 5
  1002. /* Receive events */
  1003. #define FCN_RX_EV_PKT_OK_LBN 56
  1004. #define FCN_RX_EV_PKT_OK_WIDTH 1
  1005. #define FCN_RX_PORT_LBN 30
  1006. #define FCN_RX_PORT_WIDTH 1
  1007. #define FCN_RX_EV_BYTE_CNT_LBN 16
  1008. #define FCN_RX_EV_BYTE_CNT_WIDTH 14
  1009. #define FCN_RX_EV_DESC_PTR_LBN 0
  1010. #define FCN_RX_EV_DESC_PTR_WIDTH 12
  1011. /* Transmit events */
  1012. #define FCN_TX_EV_DESC_PTR_LBN 0
  1013. #define FCN_TX_EV_DESC_PTR_WIDTH 12
  1014. /*******************************************************************************
  1015. *
  1016. *
  1017. * Low-level hardware access
  1018. *
  1019. *
  1020. *******************************************************************************/
  1021. #define FCN_REVISION_REG(efab, reg) \
  1022. ( ( efab->pci_revision == FALCON_REV_B0 ) ? reg ## _B0 : reg ## _A1 )
  1023. #define EFAB_SET_OWORD_FIELD_VER(efab, reg, field, val) \
  1024. if ( efab->pci_revision == FALCON_REV_B0 ) \
  1025. EFAB_SET_OWORD_FIELD ( reg, field ## _B0, val ); \
  1026. else \
  1027. EFAB_SET_OWORD_FIELD ( reg, field ## _A1, val );
  1028. #if FALCON_USE_IO_BAR
  1029. /* Write dword via the I/O BAR */
  1030. static inline void _falcon_writel ( struct efab_nic *efab, uint32_t value,
  1031. unsigned int reg ) {
  1032. outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG );
  1033. outl ( value, efab->iobase + FCN_IOM_IND_DAT_REG );
  1034. }
  1035. /* Read dword via the I/O BAR */
  1036. static inline uint32_t _falcon_readl ( struct efab_nic *efab,
  1037. unsigned int reg ) {
  1038. outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG );
  1039. return inl ( efab->iobase + FCN_IOM_IND_DAT_REG );
  1040. }
  1041. #else /* FALCON_USE_IO_BAR */
  1042. #define _falcon_writel( efab, value, reg ) \
  1043. writel ( (value), (efab)->membase + (reg) )
  1044. #define _falcon_readl( efab, reg ) readl ( (efab)->membase + (reg) )
  1045. #endif /* FALCON_USE_IO_BAR */
  1046. /**
  1047. * Write to a Falcon register
  1048. *
  1049. */
  1050. static inline void
  1051. falcon_write ( struct efab_nic *efab, efab_oword_t *value, unsigned int reg )
  1052. {
  1053. EFAB_REGDUMP ( "Writing register %x with " EFAB_OWORD_FMT "\n",
  1054. reg, EFAB_OWORD_VAL ( *value ) );
  1055. _falcon_writel ( efab, value->u32[0], reg + 0 );
  1056. _falcon_writel ( efab, value->u32[1], reg + 4 );
  1057. _falcon_writel ( efab, value->u32[2], reg + 8 );
  1058. wmb();
  1059. _falcon_writel ( efab, value->u32[3], reg + 12 );
  1060. wmb();
  1061. }
  1062. /**
  1063. * Write to Falcon SRAM
  1064. *
  1065. */
  1066. static inline void
  1067. falcon_write_sram ( struct efab_nic *efab, efab_qword_t *value,
  1068. unsigned int index )
  1069. {
  1070. unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) +
  1071. ( index * sizeof ( *value ) ) );
  1072. EFAB_REGDUMP ( "Writing SRAM register %x with " EFAB_QWORD_FMT "\n",
  1073. reg, EFAB_QWORD_VAL ( *value ) );
  1074. _falcon_writel ( efab, value->u32[0], reg + 0 );
  1075. _falcon_writel ( efab, value->u32[1], reg + 4 );
  1076. wmb();
  1077. }
  1078. /**
  1079. * Write dword to Falcon register that allows partial writes
  1080. *
  1081. */
  1082. static inline void
  1083. falcon_writel ( struct efab_nic *efab, efab_dword_t *value, unsigned int reg )
  1084. {
  1085. EFAB_REGDUMP ( "Writing partial register %x with " EFAB_DWORD_FMT "\n",
  1086. reg, EFAB_DWORD_VAL ( *value ) );
  1087. _falcon_writel ( efab, value->u32[0], reg );
  1088. }
  1089. /**
  1090. * Read from a Falcon register
  1091. *
  1092. */
  1093. static inline void
  1094. falcon_read ( struct efab_nic *efab, efab_oword_t *value, unsigned int reg )
  1095. {
  1096. value->u32[0] = _falcon_readl ( efab, reg + 0 );
  1097. wmb();
  1098. value->u32[1] = _falcon_readl ( efab, reg + 4 );
  1099. value->u32[2] = _falcon_readl ( efab, reg + 8 );
  1100. value->u32[3] = _falcon_readl ( efab, reg + 12 );
  1101. EFAB_REGDUMP ( "Read from register %x, got " EFAB_OWORD_FMT "\n",
  1102. reg, EFAB_OWORD_VAL ( *value ) );
  1103. }
  1104. /**
  1105. * Read from Falcon SRAM
  1106. *
  1107. */
  1108. static inline void
  1109. falcon_read_sram ( struct efab_nic *efab, efab_qword_t *value,
  1110. unsigned int index )
  1111. {
  1112. unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) +
  1113. ( index * sizeof ( *value ) ) );
  1114. value->u32[0] = _falcon_readl ( efab, reg + 0 );
  1115. value->u32[1] = _falcon_readl ( efab, reg + 4 );
  1116. EFAB_REGDUMP ( "Read from SRAM register %x, got " EFAB_QWORD_FMT "\n",
  1117. reg, EFAB_QWORD_VAL ( *value ) );
  1118. }
  1119. /**
  1120. * Read dword from a portion of a Falcon register
  1121. *
  1122. */
  1123. static inline void
  1124. falcon_readl ( struct efab_nic *efab, efab_dword_t *value, unsigned int reg )
  1125. {
  1126. value->u32[0] = _falcon_readl ( efab, reg );
  1127. EFAB_REGDUMP ( "Read from register %x, got " EFAB_DWORD_FMT "\n",
  1128. reg, EFAB_DWORD_VAL ( *value ) );
  1129. }
  1130. #define FCN_DUMP_REG( efab, _reg ) do { \
  1131. efab_oword_t reg; \
  1132. falcon_read ( efab, &reg, _reg ); \
  1133. EFAB_LOG ( #_reg " = " EFAB_OWORD_FMT "\n", \
  1134. EFAB_OWORD_VAL ( reg ) ); \
  1135. } while ( 0 );
  1136. #define FCN_DUMP_MAC_REG( efab, _mac_reg ) do { \
  1137. efab_dword_t reg; \
  1138. efab->mac_op->mac_readl ( efab, &reg, _mac_reg ); \
  1139. EFAB_LOG ( #_mac_reg " = " EFAB_DWORD_FMT "\n", \
  1140. EFAB_DWORD_VAL ( reg ) ); \
  1141. } while ( 0 );
  1142. /**
  1143. * See if an event is present
  1144. *
  1145. * @v event Falcon event structure
  1146. * @ret True An event is pending
  1147. * @ret False No event is pending
  1148. *
  1149. * We check both the high and low dword of the event for all ones. We
  1150. * wrote all ones when we cleared the event, and no valid event can
  1151. * have all ones in either its high or low dwords. This approach is
  1152. * robust against reordering.
  1153. *
  1154. * Note that using a single 64-bit comparison is incorrect; even
  1155. * though the CPU read will be atomic, the DMA write may not be.
  1156. */
  1157. static inline int
  1158. falcon_event_present ( falcon_event_t* event )
  1159. {
  1160. return ( ! ( EFAB_DWORD_IS_ALL_ONES ( event->dword[0] ) |
  1161. EFAB_DWORD_IS_ALL_ONES ( event->dword[1] ) ) );
  1162. }
  1163. static void
  1164. falcon_eventq_read_ack ( struct efab_nic *efab, struct efab_ev_queue *ev_queue )
  1165. {
  1166. efab_dword_t reg;
  1167. EFAB_POPULATE_DWORD_1 ( reg, FCN_EVQ_RPTR_DWORD, ev_queue->read_ptr );
  1168. falcon_writel ( efab, &reg,
  1169. FCN_REVISION_REG ( efab, FCN_EVQ_RPTR_REG_KER_DWORD ) );
  1170. }
  1171. #if 0
  1172. /**
  1173. * Dump register contents (for debugging)
  1174. *
  1175. * Marked as static inline so that it will not be compiled in if not
  1176. * used.
  1177. */
  1178. static inline void
  1179. falcon_dump_regs ( struct efab_nic *efab )
  1180. {
  1181. FCN_DUMP_REG ( efab, FCN_INT_EN_REG_KER );
  1182. FCN_DUMP_REG ( efab, FCN_INT_ADR_REG_KER );
  1183. FCN_DUMP_REG ( efab, FCN_GLB_CTL_REG_KER );
  1184. FCN_DUMP_REG ( efab, FCN_TIMER_CMD_REG_KER );
  1185. FCN_DUMP_REG ( efab, FCN_SRM_RX_DC_CFG_REG_KER );
  1186. FCN_DUMP_REG ( efab, FCN_SRM_TX_DC_CFG_REG_KER );
  1187. FCN_DUMP_REG ( efab, FCN_RX_FILTER_CTL_REG_KER );
  1188. FCN_DUMP_REG ( efab, FCN_RX_DC_CFG_REG_KER );
  1189. FCN_DUMP_REG ( efab, FCN_TX_DC_CFG_REG_KER );
  1190. FCN_DUMP_REG ( efab, FCN_MAC0_CTRL_REG_KER );
  1191. FCN_DUMP_REG ( efab, FCN_MAC1_CTRL_REG_KER );
  1192. FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
  1193. FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
  1194. FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) );
  1195. FCN_DUMP_MAC_REG ( efab, GM_CFG1_REG_MAC );
  1196. FCN_DUMP_MAC_REG ( efab, GM_CFG2_REG_MAC );
  1197. FCN_DUMP_MAC_REG ( efab, GM_MAX_FLEN_REG_MAC );
  1198. FCN_DUMP_MAC_REG ( efab, GM_MII_MGMT_CFG_REG_MAC );
  1199. FCN_DUMP_MAC_REG ( efab, GM_ADR1_REG_MAC );
  1200. FCN_DUMP_MAC_REG ( efab, GM_ADR2_REG_MAC );
  1201. FCN_DUMP_MAC_REG ( efab, GMF_CFG0_REG_MAC );
  1202. FCN_DUMP_MAC_REG ( efab, GMF_CFG1_REG_MAC );
  1203. FCN_DUMP_MAC_REG ( efab, GMF_CFG2_REG_MAC );
  1204. FCN_DUMP_MAC_REG ( efab, GMF_CFG3_REG_MAC );
  1205. FCN_DUMP_MAC_REG ( efab, GMF_CFG4_REG_MAC );
  1206. FCN_DUMP_MAC_REG ( efab, GMF_CFG5_REG_MAC );
  1207. }
  1208. #endif
  1209. static void
  1210. falcon_interrupts ( struct efab_nic *efab, int enabled, int force )
  1211. {
  1212. efab_oword_t int_en_reg_ker;
  1213. EFAB_POPULATE_OWORD_2 ( int_en_reg_ker,
  1214. FCN_KER_INT_KER, force,
  1215. FCN_DRV_INT_EN_KER, enabled );
  1216. falcon_write ( efab, &int_en_reg_ker, FCN_INT_EN_REG_KER );
  1217. }
  1218. /*******************************************************************************
  1219. *
  1220. *
  1221. * SPI access
  1222. *
  1223. *
  1224. *******************************************************************************/
  1225. /** Maximum length for a single SPI transaction */
  1226. #define FALCON_SPI_MAX_LEN 16
  1227. static int
  1228. falcon_spi_wait ( struct efab_nic *efab )
  1229. {
  1230. efab_oword_t reg;
  1231. int count;
  1232. count = 0;
  1233. do {
  1234. udelay ( 100 );
  1235. falcon_read ( efab, &reg, FCN_EE_SPI_HCMD_REG );
  1236. if ( EFAB_OWORD_FIELD ( reg, FCN_EE_SPI_HCMD_CMD_EN ) == 0 )
  1237. return 0;
  1238. } while ( ++count < 1000 );
  1239. EFAB_ERR ( "Timed out waiting for SPI\n" );
  1240. return -ETIMEDOUT;
  1241. }
  1242. static int
  1243. falcon_spi_rw ( struct spi_bus* bus, struct spi_device *device,
  1244. unsigned int command, int address,
  1245. const void* data_out, void *data_in, size_t len )
  1246. {
  1247. struct efab_nic *efab = container_of ( bus, struct efab_nic, spi_bus );
  1248. int address_len, rc, device_id, read_cmd;
  1249. efab_oword_t reg;
  1250. /* falcon_init_spi_device() should have reduced the block size
  1251. * down so this constraint holds */
  1252. assert ( len <= FALCON_SPI_MAX_LEN );
  1253. /* Is this the FLASH or EEPROM device? */
  1254. if ( device == &efab->spi_flash )
  1255. device_id = FCN_EE_SPI_FLASH;
  1256. else if ( device == &efab->spi_eeprom )
  1257. device_id = FCN_EE_SPI_EEPROM;
  1258. else {
  1259. EFAB_ERR ( "Unknown device %p\n", device );
  1260. return -EINVAL;
  1261. }
  1262. EFAB_TRACE ( "Executing spi command %d on device %d at %d for %zd bytes\n",
  1263. command, device_id, address, len );
  1264. /* The bus must be idle */
  1265. rc = falcon_spi_wait ( efab );
  1266. if ( rc )
  1267. goto fail1;
  1268. /* Copy data out */
  1269. if ( data_out ) {
  1270. memcpy ( &reg, data_out, len );
  1271. falcon_write ( efab, &reg, FCN_EE_SPI_HDATA_REG );
  1272. }
  1273. /* Program address register */
  1274. if ( address >= 0 ) {
  1275. EFAB_POPULATE_OWORD_1 ( reg, FCN_EE_SPI_HADR_ADR, address );
  1276. falcon_write ( efab, &reg, FCN_EE_SPI_HADR_REG );
  1277. }
  1278. /* Issue command */
  1279. address_len = ( address >= 0 ) ? device->address_len / 8 : 0;
  1280. read_cmd = ( data_in ? FCN_EE_SPI_READ : FCN_EE_SPI_WRITE );
  1281. EFAB_POPULATE_OWORD_7 ( reg,
  1282. FCN_EE_SPI_HCMD_CMD_EN, 1,
  1283. FCN_EE_SPI_HCMD_SF_SEL, device_id,
  1284. FCN_EE_SPI_HCMD_DABCNT, len,
  1285. FCN_EE_SPI_HCMD_READ, read_cmd,
  1286. FCN_EE_SPI_HCMD_DUBCNT, 0,
  1287. FCN_EE_SPI_HCMD_ADBCNT, address_len,
  1288. FCN_EE_SPI_HCMD_ENC, command );
  1289. falcon_write ( efab, &reg, FCN_EE_SPI_HCMD_REG );
  1290. /* Wait for the command to complete */
  1291. rc = falcon_spi_wait ( efab );
  1292. if ( rc )
  1293. goto fail2;
  1294. /* Copy data in */
  1295. if ( data_in ) {
  1296. falcon_read ( efab, &reg, FCN_EE_SPI_HDATA_REG );
  1297. memcpy ( data_in, &reg, len );
  1298. }
  1299. return 0;
  1300. fail2:
  1301. fail1:
  1302. EFAB_ERR ( "Failed SPI command %d to device %d address 0x%x len 0x%zx\n",
  1303. command, device_id, address, len );
  1304. return rc;
  1305. }
  1306. /*******************************************************************************
  1307. *
  1308. *
  1309. * Falcon bit-bashed I2C interface
  1310. *
  1311. *
  1312. *******************************************************************************/
  1313. static void
  1314. falcon_i2c_bit_write ( struct bit_basher *basher, unsigned int bit_id,
  1315. unsigned long data )
  1316. {
  1317. struct efab_nic *efab = container_of ( basher, struct efab_nic,
  1318. i2c_bb.basher );
  1319. efab_oword_t reg;
  1320. falcon_read ( efab, &reg, FCN_GPIO_CTL_REG_KER );
  1321. switch ( bit_id ) {
  1322. case I2C_BIT_SCL:
  1323. EFAB_SET_OWORD_FIELD ( reg, FCN_GPIO0_OEN, ( data ? 0 : 1 ) );
  1324. break;
  1325. case I2C_BIT_SDA:
  1326. EFAB_SET_OWORD_FIELD ( reg, FCN_GPIO3_OEN, ( data ? 0 : 1 ) );
  1327. break;
  1328. default:
  1329. EFAB_ERR ( "%s bit=%d\n", __func__, bit_id );
  1330. break;
  1331. }
  1332. falcon_write ( efab, &reg, FCN_GPIO_CTL_REG_KER );
  1333. }
  1334. static int
  1335. falcon_i2c_bit_read ( struct bit_basher *basher, unsigned int bit_id )
  1336. {
  1337. struct efab_nic *efab = container_of ( basher, struct efab_nic,
  1338. i2c_bb.basher );
  1339. efab_oword_t reg;
  1340. falcon_read ( efab, &reg, FCN_GPIO_CTL_REG_KER );
  1341. switch ( bit_id ) {
  1342. case I2C_BIT_SCL:
  1343. return EFAB_OWORD_FIELD ( reg, FCN_GPIO0_IN );
  1344. break;
  1345. case I2C_BIT_SDA:
  1346. return EFAB_OWORD_FIELD ( reg, FCN_GPIO3_IN );
  1347. break;
  1348. default:
  1349. EFAB_ERR ( "%s bit=%d\n", __func__, bit_id );
  1350. break;
  1351. }
  1352. return -1;
  1353. }
  1354. static struct bit_basher_operations falcon_i2c_bit_ops = {
  1355. .read = falcon_i2c_bit_read,
  1356. .write = falcon_i2c_bit_write,
  1357. };
  1358. /*******************************************************************************
  1359. *
  1360. *
  1361. * MDIO access
  1362. *
  1363. *
  1364. *******************************************************************************/
  1365. static int
  1366. falcon_gmii_wait ( struct efab_nic *efab )
  1367. {
  1368. efab_dword_t md_stat;
  1369. int count;
  1370. /* wait up to 10ms */
  1371. for (count = 0; count < 1000; count++) {
  1372. falcon_readl ( efab, &md_stat, FCN_MD_STAT_REG_KER );
  1373. if ( EFAB_DWORD_FIELD ( md_stat, FCN_MD_BSY ) == 0 ) {
  1374. if ( EFAB_DWORD_FIELD ( md_stat, FCN_MD_LNFL ) != 0 ||
  1375. EFAB_DWORD_FIELD ( md_stat, FCN_MD_BSERR ) != 0 ) {
  1376. EFAB_ERR ( "Error from GMII access "
  1377. EFAB_DWORD_FMT"\n",
  1378. EFAB_DWORD_VAL ( md_stat ));
  1379. return -EIO;
  1380. }
  1381. return 0;
  1382. }
  1383. udelay(10);
  1384. }
  1385. EFAB_ERR ( "Timed out waiting for GMII\n" );
  1386. return -ETIMEDOUT;
  1387. }
  1388. static void
  1389. falcon_mdio_write ( struct efab_nic *efab, int device,
  1390. int location, int value )
  1391. {
  1392. efab_oword_t reg;
  1393. EFAB_TRACE ( "Writing GMII %d register %02x with %04x\n",
  1394. device, location, value );
  1395. /* Check MII not currently being accessed */
  1396. if ( falcon_gmii_wait ( efab ) )
  1397. return;
  1398. /* Write the address/ID register */
  1399. EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, location );
  1400. falcon_write ( efab, &reg, FCN_MD_PHY_ADR_REG_KER );
  1401. if ( efab->phy_10g ) {
  1402. /* clause45 */
  1403. EFAB_POPULATE_OWORD_2 ( reg,
  1404. FCN_MD_PRT_ADR, efab->phy_addr,
  1405. FCN_MD_DEV_ADR, device );
  1406. }
  1407. else {
  1408. /* clause22 */
  1409. assert ( device == 0 );
  1410. EFAB_POPULATE_OWORD_2 ( reg,
  1411. FCN_MD_PRT_ADR, efab->phy_addr,
  1412. FCN_MD_DEV_ADR, location );
  1413. }
  1414. falcon_write ( efab, &reg, FCN_MD_ID_REG_KER );
  1415. /* Write data */
  1416. EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_TXD, value );
  1417. falcon_write ( efab, &reg, FCN_MD_TXD_REG_KER );
  1418. EFAB_POPULATE_OWORD_2 ( reg,
  1419. FCN_MD_WRC, 1,
  1420. FCN_MD_GC, ( efab->phy_10g ? 0 : 1 ) );
  1421. falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
  1422. /* Wait for data to be written */
  1423. if ( falcon_gmii_wait ( efab ) ) {
  1424. /* Abort the write operation */
  1425. EFAB_POPULATE_OWORD_2 ( reg,
  1426. FCN_MD_WRC, 0,
  1427. FCN_MD_GC, 1);
  1428. falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
  1429. udelay(10);
  1430. }
  1431. }
  1432. static int
  1433. falcon_mdio_read ( struct efab_nic *efab, int device, int location )
  1434. {
  1435. efab_oword_t reg;
  1436. int value;
  1437. /* Check MII not currently being accessed */
  1438. if ( falcon_gmii_wait ( efab ) )
  1439. return -1;
  1440. if ( efab->phy_10g ) {
  1441. /* clause45 */
  1442. EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, location );
  1443. falcon_write ( efab, &reg, FCN_MD_PHY_ADR_REG_KER );
  1444. EFAB_POPULATE_OWORD_2 ( reg,
  1445. FCN_MD_PRT_ADR, efab->phy_addr,
  1446. FCN_MD_DEV_ADR, device );
  1447. falcon_write ( efab, &reg, FCN_MD_ID_REG_KER);
  1448. /* request data to be read */
  1449. EFAB_POPULATE_OWORD_2 ( reg,
  1450. FCN_MD_RDC, 1,
  1451. FCN_MD_GC, 0 );
  1452. }
  1453. else {
  1454. /* clause22 */
  1455. assert ( device == 0 );
  1456. EFAB_POPULATE_OWORD_2 ( reg,
  1457. FCN_MD_PRT_ADR, efab->phy_addr,
  1458. FCN_MD_DEV_ADR, location );
  1459. falcon_write ( efab, &reg, FCN_MD_ID_REG_KER );
  1460. /* Request data to be read */
  1461. EFAB_POPULATE_OWORD_2 ( reg,
  1462. FCN_MD_RIC, 1,
  1463. FCN_MD_GC, 1 );
  1464. }
  1465. falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
  1466. /* Wait for data to become available */
  1467. if ( falcon_gmii_wait ( efab ) ) {
  1468. /* Abort the read operation */
  1469. EFAB_POPULATE_OWORD_2 ( reg,
  1470. FCN_MD_RIC, 0,
  1471. FCN_MD_GC, 1 );
  1472. falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
  1473. udelay ( 10 );
  1474. value = -1;
  1475. }
  1476. else {
  1477. /* Read the data */
  1478. falcon_read ( efab, &reg, FCN_MD_RXD_REG_KER );
  1479. value = EFAB_OWORD_FIELD ( reg, FCN_MD_RXD );
  1480. }
  1481. EFAB_TRACE ( "Read from GMII %d register %02x, got %04x\n",
  1482. device, location, value );
  1483. return value;
  1484. }
  1485. /*******************************************************************************
  1486. *
  1487. *
  1488. * MAC wrapper
  1489. *
  1490. *
  1491. *******************************************************************************/
  1492. static void
  1493. falcon_reconfigure_mac_wrapper ( struct efab_nic *efab )
  1494. {
  1495. efab_oword_t reg;
  1496. int link_speed;
  1497. if ( efab->link_options & LPA_EF_10000 ) {
  1498. link_speed = 0x3;
  1499. } else if ( efab->link_options & LPA_EF_1000 ) {
  1500. link_speed = 0x2;
  1501. } else if ( efab->link_options & LPA_100 ) {
  1502. link_speed = 0x1;
  1503. } else {
  1504. link_speed = 0x0;
  1505. }
  1506. EFAB_POPULATE_OWORD_5 ( reg,
  1507. FCN_MAC_XOFF_VAL, 0xffff /* datasheet */,
  1508. FCN_MAC_BCAD_ACPT, 1,
  1509. FCN_MAC_UC_PROM, 0,
  1510. FCN_MAC_LINK_STATUS, 1,
  1511. FCN_MAC_SPEED, link_speed );
  1512. falcon_write ( efab, &reg, FCN_MAC0_CTRL_REG_KER );
  1513. }
  1514. /*******************************************************************************
  1515. *
  1516. *
  1517. * GMAC handling
  1518. *
  1519. *
  1520. *******************************************************************************/
  1521. /* GMAC configuration register 1 */
  1522. #define GM_CFG1_REG_MAC 0x00
  1523. #define GM_SW_RST_LBN 31
  1524. #define GM_SW_RST_WIDTH 1
  1525. #define GM_RX_FC_EN_LBN 5
  1526. #define GM_RX_FC_EN_WIDTH 1
  1527. #define GM_TX_FC_EN_LBN 4
  1528. #define GM_TX_FC_EN_WIDTH 1
  1529. #define GM_RX_EN_LBN 2
  1530. #define GM_RX_EN_WIDTH 1
  1531. #define GM_TX_EN_LBN 0
  1532. #define GM_TX_EN_WIDTH 1
  1533. /* GMAC configuration register 2 */
  1534. #define GM_CFG2_REG_MAC 0x01
  1535. #define GM_PAMBL_LEN_LBN 12
  1536. #define GM_PAMBL_LEN_WIDTH 4
  1537. #define GM_IF_MODE_LBN 8
  1538. #define GM_IF_MODE_WIDTH 2
  1539. #define GM_PAD_CRC_EN_LBN 2
  1540. #define GM_PAD_CRC_EN_WIDTH 1
  1541. #define GM_FD_LBN 0
  1542. #define GM_FD_WIDTH 1
  1543. /* GMAC maximum frame length register */
  1544. #define GM_MAX_FLEN_REG_MAC 0x04
  1545. #define GM_MAX_FLEN_LBN 0
  1546. #define GM_MAX_FLEN_WIDTH 16
  1547. /* GMAC MII management configuration register */
  1548. #define GM_MII_MGMT_CFG_REG_MAC 0x08
  1549. #define GM_MGMT_CLK_SEL_LBN 0
  1550. #define GM_MGMT_CLK_SEL_WIDTH 3
  1551. /* GMAC MII management command register */
  1552. #define GM_MII_MGMT_CMD_REG_MAC 0x09
  1553. #define GM_MGMT_SCAN_CYC_LBN 1
  1554. #define GM_MGMT_SCAN_CYC_WIDTH 1
  1555. #define GM_MGMT_RD_CYC_LBN 0
  1556. #define GM_MGMT_RD_CYC_WIDTH 1
  1557. /* GMAC MII management address register */
  1558. #define GM_MII_MGMT_ADR_REG_MAC 0x0a
  1559. #define GM_MGMT_PHY_ADDR_LBN 8
  1560. #define GM_MGMT_PHY_ADDR_WIDTH 5
  1561. #define GM_MGMT_REG_ADDR_LBN 0
  1562. #define GM_MGMT_REG_ADDR_WIDTH 5
  1563. /* GMAC MII management control register */
  1564. #define GM_MII_MGMT_CTL_REG_MAC 0x0b
  1565. #define GM_MGMT_CTL_LBN 0
  1566. #define GM_MGMT_CTL_WIDTH 16
  1567. /* GMAC MII management status register */
  1568. #define GM_MII_MGMT_STAT_REG_MAC 0x0c
  1569. #define GM_MGMT_STAT_LBN 0
  1570. #define GM_MGMT_STAT_WIDTH 16
  1571. /* GMAC MII management indicators register */
  1572. #define GM_MII_MGMT_IND_REG_MAC 0x0d
  1573. #define GM_MGMT_BUSY_LBN 0
  1574. #define GM_MGMT_BUSY_WIDTH 1
  1575. /* GMAC station address register 1 */
  1576. #define GM_ADR1_REG_MAC 0x10
  1577. #define GM_HWADDR_5_LBN 24
  1578. #define GM_HWADDR_5_WIDTH 8
  1579. #define GM_HWADDR_4_LBN 16
  1580. #define GM_HWADDR_4_WIDTH 8
  1581. #define GM_HWADDR_3_LBN 8
  1582. #define GM_HWADDR_3_WIDTH 8
  1583. #define GM_HWADDR_2_LBN 0
  1584. #define GM_HWADDR_2_WIDTH 8
  1585. /* GMAC station address register 2 */
  1586. #define GM_ADR2_REG_MAC 0x11
  1587. #define GM_HWADDR_1_LBN 24
  1588. #define GM_HWADDR_1_WIDTH 8
  1589. #define GM_HWADDR_0_LBN 16
  1590. #define GM_HWADDR_0_WIDTH 8
  1591. /* GMAC FIFO configuration register 0 */
  1592. #define GMF_CFG0_REG_MAC 0x12
  1593. #define GMF_FTFENREQ_LBN 12
  1594. #define GMF_FTFENREQ_WIDTH 1
  1595. #define GMF_STFENREQ_LBN 11
  1596. #define GMF_STFENREQ_WIDTH 1
  1597. #define GMF_FRFENREQ_LBN 10
  1598. #define GMF_FRFENREQ_WIDTH 1
  1599. #define GMF_SRFENREQ_LBN 9
  1600. #define GMF_SRFENREQ_WIDTH 1
  1601. #define GMF_WTMENREQ_LBN 8
  1602. #define GMF_WTMENREQ_WIDTH 1
  1603. /* GMAC FIFO configuration register 1 */
  1604. #define GMF_CFG1_REG_MAC 0x13
  1605. #define GMF_CFGFRTH_LBN 16
  1606. #define GMF_CFGFRTH_WIDTH 5
  1607. #define GMF_CFGXOFFRTX_LBN 0
  1608. #define GMF_CFGXOFFRTX_WIDTH 16
  1609. /* GMAC FIFO configuration register 2 */
  1610. #define GMF_CFG2_REG_MAC 0x14
  1611. #define GMF_CFGHWM_LBN 16
  1612. #define GMF_CFGHWM_WIDTH 6
  1613. #define GMF_CFGLWM_LBN 0
  1614. #define GMF_CFGLWM_WIDTH 6
  1615. /* GMAC FIFO configuration register 3 */
  1616. #define GMF_CFG3_REG_MAC 0x15
  1617. #define GMF_CFGHWMFT_LBN 16
  1618. #define GMF_CFGHWMFT_WIDTH 6
  1619. #define GMF_CFGFTTH_LBN 0
  1620. #define GMF_CFGFTTH_WIDTH 6
  1621. /* GMAC FIFO configuration register 4 */
  1622. #define GMF_CFG4_REG_MAC 0x16
  1623. #define GMF_HSTFLTRFRM_PAUSE_LBN 12
  1624. #define GMF_HSTFLTRFRM_PAUSE_WIDTH 12
  1625. /* GMAC FIFO configuration register 5 */
  1626. #define GMF_CFG5_REG_MAC 0x17
  1627. #define GMF_CFGHDPLX_LBN 22
  1628. #define GMF_CFGHDPLX_WIDTH 1
  1629. #define GMF_CFGBYTMODE_LBN 19
  1630. #define GMF_CFGBYTMODE_WIDTH 1
  1631. #define GMF_HSTDRPLT64_LBN 18
  1632. #define GMF_HSTDRPLT64_WIDTH 1
  1633. #define GMF_HSTFLTRFRMDC_PAUSE_LBN 12
  1634. #define GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1
  1635. static void
  1636. falcon_gmac_writel ( struct efab_nic *efab, efab_dword_t *value,
  1637. unsigned int mac_reg )
  1638. {
  1639. efab_oword_t temp;
  1640. EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA,
  1641. EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) );
  1642. falcon_write ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) );
  1643. }
  1644. static void
  1645. falcon_gmac_readl ( struct efab_nic *efab, efab_dword_t *value,
  1646. unsigned int mac_reg )
  1647. {
  1648. efab_oword_t temp;
  1649. falcon_read ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) );
  1650. EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA,
  1651. EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) );
  1652. }
  1653. static void
  1654. mentormac_reset ( struct efab_nic *efab )
  1655. {
  1656. efab_dword_t reg;
  1657. /* Take into reset */
  1658. EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 1 );
  1659. falcon_gmac_writel ( efab, &reg, GM_CFG1_REG_MAC );
  1660. udelay ( 1000 );
  1661. /* Take out of reset */
  1662. EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 0 );
  1663. falcon_gmac_writel ( efab, &reg, GM_CFG1_REG_MAC );
  1664. udelay ( 1000 );
  1665. /* Configure GMII interface so PHY is accessible. Note that
  1666. * GMII interface is connected only to port 0, and that on
  1667. * Falcon this is a no-op.
  1668. */
  1669. EFAB_POPULATE_DWORD_1 ( reg, GM_MGMT_CLK_SEL, 0x4 );
  1670. falcon_gmac_writel ( efab, &reg, GM_MII_MGMT_CFG_REG_MAC );
  1671. udelay ( 10 );
  1672. }
  1673. static void
  1674. mentormac_init ( struct efab_nic *efab )
  1675. {
  1676. int pause, if_mode, full_duplex, bytemode, half_duplex;
  1677. efab_dword_t reg;
  1678. /* Configuration register 1 */
  1679. pause = ( efab->link_options & LPA_PAUSE_CAP ) ? 1 : 0;
  1680. if ( ! ( efab->link_options & LPA_EF_DUPLEX ) ) {
  1681. /* Half-duplex operation requires TX flow control */
  1682. pause = 1;
  1683. }
  1684. EFAB_POPULATE_DWORD_4 ( reg,
  1685. GM_TX_EN, 1,
  1686. GM_TX_FC_EN, pause,
  1687. GM_RX_EN, 1,
  1688. GM_RX_FC_EN, 1 );
  1689. falcon_gmac_writel ( efab, &reg, GM_CFG1_REG_MAC );
  1690. udelay ( 10 );
  1691. /* Configuration register 2 */
  1692. if_mode = ( efab->link_options & LPA_EF_1000 ) ? 2 : 1;
  1693. full_duplex = ( efab->link_options & LPA_EF_DUPLEX ) ? 1 : 0;
  1694. EFAB_POPULATE_DWORD_4 ( reg,
  1695. GM_IF_MODE, if_mode,
  1696. GM_PAD_CRC_EN, 1,
  1697. GM_FD, full_duplex,
  1698. GM_PAMBL_LEN, 0x7 /* ? */ );
  1699. falcon_gmac_writel ( efab, &reg, GM_CFG2_REG_MAC );
  1700. udelay ( 10 );
  1701. /* Max frame len register */
  1702. EFAB_POPULATE_DWORD_1 ( reg, GM_MAX_FLEN,
  1703. EFAB_MAX_FRAME_LEN ( ETH_FRAME_LEN ) );
  1704. falcon_gmac_writel ( efab, &reg, GM_MAX_FLEN_REG_MAC );
  1705. udelay ( 10 );
  1706. /* FIFO configuration register 0 */
  1707. EFAB_POPULATE_DWORD_5 ( reg,
  1708. GMF_FTFENREQ, 1,
  1709. GMF_STFENREQ, 1,
  1710. GMF_FRFENREQ, 1,
  1711. GMF_SRFENREQ, 1,
  1712. GMF_WTMENREQ, 1 );
  1713. falcon_gmac_writel ( efab, &reg, GMF_CFG0_REG_MAC );
  1714. udelay ( 10 );
  1715. /* FIFO configuration register 1 */
  1716. EFAB_POPULATE_DWORD_2 ( reg,
  1717. GMF_CFGFRTH, 0x12,
  1718. GMF_CFGXOFFRTX, 0xffff );
  1719. falcon_gmac_writel ( efab, &reg, GMF_CFG1_REG_MAC );
  1720. udelay ( 10 );
  1721. /* FIFO configuration register 2 */
  1722. EFAB_POPULATE_DWORD_2 ( reg,
  1723. GMF_CFGHWM, 0x3f,
  1724. GMF_CFGLWM, 0xa );
  1725. falcon_gmac_writel ( efab, &reg, GMF_CFG2_REG_MAC );
  1726. udelay ( 10 );
  1727. /* FIFO configuration register 3 */
  1728. EFAB_POPULATE_DWORD_2 ( reg,
  1729. GMF_CFGHWMFT, 0x1c,
  1730. GMF_CFGFTTH, 0x08 );
  1731. falcon_gmac_writel ( efab, &reg, GMF_CFG3_REG_MAC );
  1732. udelay ( 10 );
  1733. /* FIFO configuration register 4 */
  1734. EFAB_POPULATE_DWORD_1 ( reg, GMF_HSTFLTRFRM_PAUSE, 1 );
  1735. falcon_gmac_writel ( efab, &reg, GMF_CFG4_REG_MAC );
  1736. udelay ( 10 );
  1737. /* FIFO configuration register 5 */
  1738. bytemode = ( efab->link_options & LPA_EF_1000 ) ? 1 : 0;
  1739. half_duplex = ( efab->link_options & LPA_EF_DUPLEX ) ? 0 : 1;
  1740. falcon_gmac_readl ( efab, &reg, GMF_CFG5_REG_MAC );
  1741. EFAB_SET_DWORD_FIELD ( reg, GMF_CFGBYTMODE, bytemode );
  1742. EFAB_SET_DWORD_FIELD ( reg, GMF_CFGHDPLX, half_duplex );
  1743. EFAB_SET_DWORD_FIELD ( reg, GMF_HSTDRPLT64, half_duplex );
  1744. EFAB_SET_DWORD_FIELD ( reg, GMF_HSTFLTRFRMDC_PAUSE, 0 );
  1745. falcon_gmac_writel ( efab, &reg, GMF_CFG5_REG_MAC );
  1746. udelay ( 10 );
  1747. /* MAC address */
  1748. EFAB_POPULATE_DWORD_4 ( reg,
  1749. GM_HWADDR_5, efab->mac_addr[5],
  1750. GM_HWADDR_4, efab->mac_addr[4],
  1751. GM_HWADDR_3, efab->mac_addr[3],
  1752. GM_HWADDR_2, efab->mac_addr[2] );
  1753. falcon_gmac_writel ( efab, &reg, GM_ADR1_REG_MAC );
  1754. udelay ( 10 );
  1755. EFAB_POPULATE_DWORD_2 ( reg,
  1756. GM_HWADDR_1, efab->mac_addr[1],
  1757. GM_HWADDR_0, efab->mac_addr[0] );
  1758. falcon_gmac_writel ( efab, &reg, GM_ADR2_REG_MAC );
  1759. udelay ( 10 );
  1760. }
  1761. static int
  1762. falcon_init_gmac ( struct efab_nic *efab )
  1763. {
  1764. /* Reset the MAC */
  1765. mentormac_reset ( efab );
  1766. /* Initialise PHY */
  1767. efab->phy_op->init ( efab );
  1768. /* check the link is up */
  1769. if ( !efab->link_up )
  1770. return -EAGAIN;
  1771. /* Initialise MAC */
  1772. mentormac_init ( efab );
  1773. /* reconfigure the MAC wrapper */
  1774. falcon_reconfigure_mac_wrapper ( efab );
  1775. return 0;
  1776. }
  1777. static struct efab_mac_operations falcon_gmac_operations = {
  1778. .init = falcon_init_gmac,
  1779. };
  1780. /*******************************************************************************
  1781. *
  1782. *
  1783. * XMAC handling
  1784. *
  1785. *
  1786. *******************************************************************************/
  1787. /**
  1788. * Write dword to a Falcon XMAC register
  1789. *
  1790. */
  1791. static void
  1792. falcon_xmac_writel ( struct efab_nic *efab, efab_dword_t *value,
  1793. unsigned int mac_reg )
  1794. {
  1795. efab_oword_t temp;
  1796. EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA,
  1797. EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) );
  1798. falcon_write ( efab, &temp,
  1799. FALCON_XMAC_REG ( efab, mac_reg ) );
  1800. }
  1801. /**
  1802. * Read dword from a Falcon XMAC register
  1803. *
  1804. */
  1805. static void
  1806. falcon_xmac_readl ( struct efab_nic *efab, efab_dword_t *value,
  1807. unsigned int mac_reg )
  1808. {
  1809. efab_oword_t temp;
  1810. falcon_read ( efab, &temp,
  1811. FALCON_XMAC_REG ( efab, mac_reg ) );
  1812. EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA,
  1813. EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) );
  1814. }
  1815. /**
  1816. * Configure Falcon XAUI output
  1817. */
  1818. static void
  1819. falcon_setup_xaui ( struct efab_nic *efab )
  1820. {
  1821. efab_dword_t sdctl, txdrv;
  1822. falcon_xmac_readl ( efab, &sdctl, FCN_XX_SD_CTL_REG_MAC );
  1823. EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT );
  1824. EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVD, XX_SD_CTL_DRV_DEFAULT );
  1825. EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT );
  1826. EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVC, XX_SD_CTL_DRV_DEFAULT );
  1827. EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT );
  1828. EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVB, XX_SD_CTL_DRV_DEFAULT );
  1829. EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT );
  1830. EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVA, XX_SD_CTL_DRV_DEFAULT );
  1831. falcon_xmac_writel ( efab, &sdctl, FCN_XX_SD_CTL_REG_MAC );
  1832. EFAB_POPULATE_DWORD_8 ( txdrv,
  1833. FCN_XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
  1834. FCN_XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
  1835. FCN_XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
  1836. FCN_XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
  1837. FCN_XX_DTXD, XX_TXDRV_DTX_DEFAULT,
  1838. FCN_XX_DTXC, XX_TXDRV_DTX_DEFAULT,
  1839. FCN_XX_DTXB, XX_TXDRV_DTX_DEFAULT,
  1840. FCN_XX_DTXA, XX_TXDRV_DTX_DEFAULT);
  1841. falcon_xmac_writel ( efab, &txdrv, FCN_XX_TXDRV_CTL_REG_MAC);
  1842. }
  1843. static int
  1844. falcon_xgmii_status ( struct efab_nic *efab )
  1845. {
  1846. efab_dword_t reg;
  1847. if ( efab->pci_revision < FALCON_REV_B0 )
  1848. return 1;
  1849. /* The ISR latches, so clear it and re-read */
  1850. falcon_xmac_readl ( efab, &reg, FCN_XM_MGT_INT_REG_MAC_B0 );
  1851. falcon_xmac_readl ( efab, &reg, FCN_XM_MGT_INT_REG_MAC_B0 );
  1852. if ( EFAB_DWORD_FIELD ( reg, FCN_XM_LCLFLT ) ||
  1853. EFAB_DWORD_FIELD ( reg, FCN_XM_RMTFLT ) ) {
  1854. EFAB_TRACE ( "MGT_INT: "EFAB_DWORD_FMT"\n",
  1855. EFAB_DWORD_VAL ( reg ) );
  1856. return 0;
  1857. }
  1858. return 1;
  1859. }
  1860. static void
  1861. falcon_mask_status_intr ( struct efab_nic *efab, int enable )
  1862. {
  1863. efab_dword_t reg;
  1864. if ( efab->pci_revision < FALCON_REV_B0 )
  1865. return;
  1866. /* Flush the ISR */
  1867. if ( enable )
  1868. falcon_xmac_readl ( efab, &reg, FCN_XM_MGT_INT_REG_MAC_B0 );
  1869. EFAB_POPULATE_DWORD_2 ( reg,
  1870. FCN_XM_MSK_RMTFLT, !enable,
  1871. FCN_XM_MSK_LCLFLT, !enable);
  1872. falcon_xmac_readl ( efab, &reg, FCN_XM_MGT_INT_MSK_REG_MAC_B0 );
  1873. }
  1874. /**
  1875. * Reset 10G MAC connected to port
  1876. *
  1877. */
  1878. static int
  1879. falcon_reset_xmac ( struct efab_nic *efab )
  1880. {
  1881. efab_dword_t reg;
  1882. int count;
  1883. EFAB_POPULATE_DWORD_1 ( reg, FCN_XM_CORE_RST, 1 );
  1884. falcon_xmac_writel ( efab, &reg, FCN_XM_GLB_CFG_REG_MAC );
  1885. for ( count = 0 ; count < 1000 ; count++ ) {
  1886. udelay ( 10 );
  1887. falcon_xmac_readl ( efab, &reg,
  1888. FCN_XM_GLB_CFG_REG_MAC );
  1889. if ( EFAB_DWORD_FIELD ( reg, FCN_XM_CORE_RST ) == 0 )
  1890. return 0;
  1891. }
  1892. return -ETIMEDOUT;
  1893. }
  1894. static int
  1895. falcon_reset_xaui ( struct efab_nic *efab )
  1896. {
  1897. efab_dword_t reg;
  1898. int count;
  1899. if (!efab->is_asic)
  1900. return 0;
  1901. EFAB_POPULATE_DWORD_1 ( reg, FCN_XX_RST_XX_EN, 1 );
  1902. falcon_xmac_writel ( efab, &reg, FCN_XX_PWR_RST_REG_MAC );
  1903. /* Give some time for the link to establish */
  1904. for (count = 0; count < 1000; count++) { /* wait up to 10ms */
  1905. falcon_xmac_readl ( efab, &reg, FCN_XX_PWR_RST_REG_MAC );
  1906. if ( EFAB_DWORD_FIELD ( reg, FCN_XX_RST_XX_EN ) == 0 ) {
  1907. falcon_setup_xaui ( efab );
  1908. return 0;
  1909. }
  1910. udelay(10);
  1911. }
  1912. EFAB_ERR ( "timed out waiting for XAUI/XGXS reset\n" );
  1913. return -ETIMEDOUT;
  1914. }
  1915. static int
  1916. falcon_xaui_link_ok ( struct efab_nic *efab )
  1917. {
  1918. efab_dword_t reg;
  1919. int align_done, lane_status, sync;
  1920. int has_phyxs;
  1921. int link_ok = 1;
  1922. /* Read Falcon XAUI side */
  1923. if ( efab->is_asic ) {
  1924. /* Read link status */
  1925. falcon_xmac_readl ( efab, &reg, FCN_XX_CORE_STAT_REG_MAC );
  1926. align_done = EFAB_DWORD_FIELD ( reg, FCN_XX_ALIGN_DONE );
  1927. sync = EFAB_DWORD_FIELD ( reg, FCN_XX_SYNC_STAT );
  1928. sync = ( sync == FCN_XX_SYNC_STAT_DECODE_SYNCED );
  1929. link_ok = align_done && sync;
  1930. }
  1931. /* Clear link status ready for next read */
  1932. EFAB_SET_DWORD_FIELD ( reg, FCN_XX_COMMA_DET, FCN_XX_COMMA_DET_RESET );
  1933. EFAB_SET_DWORD_FIELD ( reg, FCN_XX_CHARERR, FCN_XX_CHARERR_RESET);
  1934. EFAB_SET_DWORD_FIELD ( reg, FCN_XX_DISPERR, FCN_XX_DISPERR_RESET);
  1935. falcon_xmac_writel ( efab, &reg, FCN_XX_CORE_STAT_REG_MAC );
  1936. has_phyxs = ( efab->phy_op->mmds & ( 1 << MDIO_MMD_PHYXS ) );
  1937. if ( link_ok && has_phyxs ) {
  1938. lane_status = falcon_mdio_read ( efab, MDIO_MMD_PHYXS,
  1939. MDIO_PHYXS_LANE_STATE );
  1940. link_ok = ( lane_status & ( 1 << MDIO_PHYXS_LANE_ALIGNED_LBN ) );
  1941. if (!link_ok )
  1942. EFAB_LOG ( "XGXS lane status: %x\n", lane_status );
  1943. }
  1944. return link_ok;
  1945. }
  1946. /**
  1947. * Initialise XMAC
  1948. *
  1949. */
  1950. static void
  1951. falcon_reconfigure_xmac ( struct efab_nic *efab )
  1952. {
  1953. efab_dword_t reg;
  1954. int max_frame_len;
  1955. /* Configure MAC - cut-thru mode is hard wired on */
  1956. EFAB_POPULATE_DWORD_3 ( reg,
  1957. FCN_XM_RX_JUMBO_MODE, 1,
  1958. FCN_XM_TX_STAT_EN, 1,
  1959. FCN_XM_RX_STAT_EN, 1);
  1960. falcon_xmac_writel ( efab, &reg, FCN_XM_GLB_CFG_REG_MAC );
  1961. /* Configure TX */
  1962. EFAB_POPULATE_DWORD_6 ( reg,
  1963. FCN_XM_TXEN, 1,
  1964. FCN_XM_TX_PRMBL, 1,
  1965. FCN_XM_AUTO_PAD, 1,
  1966. FCN_XM_TXCRC, 1,
  1967. FCN_XM_FCNTL, 1,
  1968. FCN_XM_IPG, 0x3 );
  1969. falcon_xmac_writel ( efab, &reg, FCN_XM_TX_CFG_REG_MAC );
  1970. /* Configure RX */
  1971. EFAB_POPULATE_DWORD_4 ( reg,
  1972. FCN_XM_RXEN, 1,
  1973. FCN_XM_AUTO_DEPAD, 0,
  1974. FCN_XM_ACPT_ALL_MCAST, 1,
  1975. FCN_XM_PASS_CRC_ERR, 1 );
  1976. falcon_xmac_writel ( efab, &reg, FCN_XM_RX_CFG_REG_MAC );
  1977. /* Set frame length */
  1978. max_frame_len = EFAB_MAX_FRAME_LEN ( ETH_FRAME_LEN );
  1979. EFAB_POPULATE_DWORD_1 ( reg,
  1980. FCN_XM_MAX_RX_FRM_SIZE, max_frame_len );
  1981. falcon_xmac_writel ( efab, &reg, FCN_XM_RX_PARAM_REG_MAC );
  1982. EFAB_POPULATE_DWORD_2 ( reg,
  1983. FCN_XM_MAX_TX_FRM_SIZE, max_frame_len,
  1984. FCN_XM_TX_JUMBO_MODE, 1 );
  1985. falcon_xmac_writel ( efab, &reg, FCN_XM_TX_PARAM_REG_MAC );
  1986. /* Enable flow control receipt */
  1987. EFAB_POPULATE_DWORD_2 ( reg,
  1988. FCN_XM_PAUSE_TIME, 0xfffe,
  1989. FCN_XM_DIS_FCNTL, 0 );
  1990. falcon_xmac_writel ( efab, &reg, FCN_XM_FC_REG_MAC );
  1991. /* Set MAC address */
  1992. EFAB_POPULATE_DWORD_4 ( reg,
  1993. FCN_XM_ADR_0, efab->mac_addr[0],
  1994. FCN_XM_ADR_1, efab->mac_addr[1],
  1995. FCN_XM_ADR_2, efab->mac_addr[2],
  1996. FCN_XM_ADR_3, efab->mac_addr[3] );
  1997. falcon_xmac_writel ( efab, &reg, FCN_XM_ADR_LO_REG_MAC );
  1998. EFAB_POPULATE_DWORD_2 ( reg,
  1999. FCN_XM_ADR_4, efab->mac_addr[4],
  2000. FCN_XM_ADR_5, efab->mac_addr[5] );
  2001. falcon_xmac_writel ( efab, &reg, FCN_XM_ADR_HI_REG_MAC );
  2002. }
  2003. static int
  2004. falcon_init_xmac ( struct efab_nic *efab )
  2005. {
  2006. int count, rc;
  2007. /* Mask the PHY management interrupt */
  2008. falcon_mask_status_intr ( efab, 0 );
  2009. /* Initialise the PHY to instantiate the clock. */
  2010. rc = efab->phy_op->init ( efab );
  2011. if ( rc ) {
  2012. EFAB_ERR ( "unable to initialise PHY\n" );
  2013. goto fail1;
  2014. }
  2015. falcon_reset_xaui ( efab );
  2016. /* Give the PHY and MAC time to faff */
  2017. mdelay ( 100 );
  2018. /* Reset and reconfigure the XMAC */
  2019. rc = falcon_reset_xmac ( efab );
  2020. if ( rc )
  2021. goto fail2;
  2022. falcon_reconfigure_xmac ( efab );
  2023. falcon_reconfigure_mac_wrapper ( efab );
  2024. /**
  2025. * Now wait for the link to come up. This may take a while
  2026. * for some slower PHY's.
  2027. */
  2028. for (count=0; count<50; count++) {
  2029. int link_ok = 1;
  2030. /* Wait a while for the link to come up. */
  2031. mdelay ( 100 );
  2032. if ((count % 5) == 0)
  2033. putchar ( '.' );
  2034. /* Does the PHY think the wire-side link is up? */
  2035. link_ok = mdio_clause45_links_ok ( efab );
  2036. /* Ensure the XAUI link to the PHY is good */
  2037. if ( link_ok ) {
  2038. link_ok = falcon_xaui_link_ok ( efab );
  2039. if ( !link_ok )
  2040. falcon_reset_xaui ( efab );
  2041. }
  2042. /* Check fault indication */
  2043. if ( link_ok )
  2044. link_ok = falcon_xgmii_status ( efab );
  2045. efab->link_up = link_ok;
  2046. if ( link_ok ) {
  2047. /* unmask the status interrupt */
  2048. falcon_mask_status_intr ( efab, 1 );
  2049. return 0;
  2050. }
  2051. }
  2052. /* Link failed to come up, but initialisation was fine. */
  2053. rc = -ETIMEDOUT;
  2054. fail2:
  2055. fail1:
  2056. return rc;
  2057. }
  2058. static struct efab_mac_operations falcon_xmac_operations = {
  2059. .init = falcon_init_xmac,
  2060. };
  2061. /*******************************************************************************
  2062. *
  2063. *
  2064. * Null PHY handling
  2065. *
  2066. *
  2067. *******************************************************************************/
  2068. static int
  2069. falcon_xaui_phy_init ( struct efab_nic *efab )
  2070. {
  2071. /* CX4 is always 10000FD only */
  2072. efab->link_options = LPA_EF_10000FULL;
  2073. /* There is no PHY! */
  2074. return 0;
  2075. }
  2076. static struct efab_phy_operations falcon_xaui_phy_ops = {
  2077. .init = falcon_xaui_phy_init,
  2078. .mmds = 0,
  2079. };
  2080. /*******************************************************************************
  2081. *
  2082. *
  2083. * Alaska PHY
  2084. *
  2085. *
  2086. *******************************************************************************/
  2087. /**
  2088. * Initialise Alaska PHY
  2089. *
  2090. */
  2091. static int
  2092. alaska_init ( struct efab_nic *efab )
  2093. {
  2094. unsigned int advertised, lpa;
  2095. /* Read link up status */
  2096. efab->link_up = gmii_link_ok ( efab );
  2097. if ( ! efab->link_up )
  2098. return -EIO;
  2099. /* Determine link options from PHY. */
  2100. advertised = gmii_autoneg_advertised ( efab );
  2101. lpa = gmii_autoneg_lpa ( efab );
  2102. efab->link_options = gmii_nway_result ( advertised & lpa );
  2103. return 0;
  2104. }
  2105. static struct efab_phy_operations falcon_alaska_phy_ops = {
  2106. .init = alaska_init,
  2107. };
  2108. /*******************************************************************************
  2109. *
  2110. *
  2111. * xfp
  2112. *
  2113. *
  2114. *******************************************************************************/
  2115. #define XFP_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS | \
  2116. MDIO_MMDREG_DEVS0_PMAPMD | \
  2117. MDIO_MMDREG_DEVS0_PHYXS )
  2118. static int
  2119. falcon_xfp_phy_init ( struct efab_nic *efab )
  2120. {
  2121. int rc;
  2122. /* Optical link is always 10000FD only */
  2123. efab->link_options = LPA_EF_10000FULL;
  2124. /* Reset the PHY */
  2125. rc = mdio_clause45_reset_mmd ( efab, MDIO_MMD_PHYXS );
  2126. if ( rc )
  2127. return rc;
  2128. return 0;
  2129. }
  2130. static struct efab_phy_operations falcon_xfp_phy_ops = {
  2131. .init = falcon_xfp_phy_init,
  2132. .mmds = XFP_REQUIRED_DEVS,
  2133. };
  2134. /*******************************************************************************
  2135. *
  2136. *
  2137. * txc43128
  2138. *
  2139. *
  2140. *******************************************************************************/
  2141. /* Command register */
  2142. #define TXC_GLRGS_GLCMD (0xc004)
  2143. #define TXC_GLCMD_LMTSWRST_LBN (14)
  2144. /* Amplitude on lanes 0+1, 2+3 */
  2145. #define TXC_ALRGS_ATXAMP0 (0xc041)
  2146. #define TXC_ALRGS_ATXAMP1 (0xc042)
  2147. /* Bit position of value for lane 0+2, 1+3 */
  2148. #define TXC_ATXAMP_LANE02_LBN (3)
  2149. #define TXC_ATXAMP_LANE13_LBN (11)
  2150. #define TXC_ATXAMP_1280_mV (0)
  2151. #define TXC_ATXAMP_1200_mV (8)
  2152. #define TXC_ATXAMP_1120_mV (12)
  2153. #define TXC_ATXAMP_1060_mV (14)
  2154. #define TXC_ATXAMP_0820_mV (25)
  2155. #define TXC_ATXAMP_0720_mV (26)
  2156. #define TXC_ATXAMP_0580_mV (27)
  2157. #define TXC_ATXAMP_0440_mV (28)
  2158. #define TXC_ATXAMP_0820_BOTH ( (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE02_LBN) | \
  2159. (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE13_LBN) )
  2160. #define TXC_ATXAMP_DEFAULT (0x6060) /* From databook */
  2161. /* Preemphasis on lanes 0+1, 2+3 */
  2162. #define TXC_ALRGS_ATXPRE0 (0xc043)
  2163. #define TXC_ALRGS_ATXPRE1 (0xc044)
  2164. #define TXC_ATXPRE_NONE (0)
  2165. #define TXC_ATXPRE_DEFAULT (0x1010) /* From databook */
  2166. #define TXC_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS | \
  2167. MDIO_MMDREG_DEVS0_PMAPMD | \
  2168. MDIO_MMDREG_DEVS0_PHYXS )
  2169. static int
  2170. falcon_txc_logic_reset ( struct efab_nic *efab )
  2171. {
  2172. int val;
  2173. int tries = 50;
  2174. val = falcon_mdio_read ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD );
  2175. val |= (1 << TXC_GLCMD_LMTSWRST_LBN);
  2176. falcon_mdio_write ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD, val );
  2177. while ( tries--) {
  2178. val = falcon_mdio_read ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD );
  2179. if ( ~val & ( 1 << TXC_GLCMD_LMTSWRST_LBN ) )
  2180. return 0;
  2181. udelay(1);
  2182. }
  2183. EFAB_ERR ( "logic reset failed\n" );
  2184. return -ETIMEDOUT;
  2185. }
  2186. static int
  2187. falcon_txc_phy_init ( struct efab_nic *efab )
  2188. {
  2189. int rc;
  2190. /* CX4 is always 10000FD only */
  2191. efab->link_options = LPA_EF_10000FULL;
  2192. /* reset the phy */
  2193. rc = mdio_clause45_reset_mmd ( efab, MDIO_MMD_PMAPMD );
  2194. if ( rc )
  2195. goto fail1;
  2196. rc = mdio_clause45_check_mmds ( efab );
  2197. if ( rc )
  2198. goto fail2;
  2199. /* Turn amplitude down and preemphasis off on the host side
  2200. * (PHY<->MAC) as this is believed less likely to upset falcon
  2201. * and no adverse effects have been noted. It probably also
  2202. * saves a picowatt or two */
  2203. /* Turn off preemphasis */
  2204. falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE0,
  2205. TXC_ATXPRE_NONE );
  2206. falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE1,
  2207. TXC_ATXPRE_NONE );
  2208. /* Turn down the amplitude */
  2209. falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXAMP0,
  2210. TXC_ATXAMP_0820_BOTH );
  2211. falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXAMP1,
  2212. TXC_ATXAMP_0820_BOTH );
  2213. /* Set the line side amplitude and preemphasis to the databook
  2214. * defaults as an erratum causes them to be 0 on at least some
  2215. * PHY rev.s */
  2216. falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXPRE0,
  2217. TXC_ATXPRE_DEFAULT );
  2218. falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXPRE1,
  2219. TXC_ATXPRE_DEFAULT );
  2220. falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXAMP0,
  2221. TXC_ATXAMP_DEFAULT );
  2222. falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXAMP1,
  2223. TXC_ATXAMP_DEFAULT );
  2224. rc = falcon_txc_logic_reset ( efab );
  2225. if ( rc )
  2226. goto fail3;
  2227. return 0;
  2228. fail3:
  2229. fail2:
  2230. fail1:
  2231. return rc;
  2232. }
  2233. static struct efab_phy_operations falcon_txc_phy_ops = {
  2234. .init = falcon_txc_phy_init,
  2235. .mmds = TXC_REQUIRED_DEVS,
  2236. };
  2237. /*******************************************************************************
  2238. *
  2239. *
  2240. * tenxpress
  2241. *
  2242. *
  2243. *******************************************************************************/
  2244. #define TENXPRESS_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PMAPMD | \
  2245. MDIO_MMDREG_DEVS0_PCS | \
  2246. MDIO_MMDREG_DEVS0_PHYXS )
  2247. #define PCS_TEST_SELECT_REG 0xd807 /* PRM 10.5.8 */
  2248. #define CLK312_EN_LBN 3
  2249. #define CLK312_EN_WIDTH 1
  2250. #define PCS_CLOCK_CTRL_REG 0xd801
  2251. #define PLL312_RST_N_LBN 2
  2252. /* Special Software reset register */
  2253. #define PMA_PMD_EXT_CTRL_REG 49152
  2254. #define PMA_PMD_EXT_SSR_LBN 15
  2255. /* Boot status register */
  2256. #define PCS_BOOT_STATUS_REG 0xd000
  2257. #define PCS_BOOT_FATAL_ERR_LBN 0
  2258. #define PCS_BOOT_PROGRESS_LBN 1
  2259. #define PCS_BOOT_PROGRESS_WIDTH 2
  2260. #define PCS_BOOT_COMPLETE_LBN 3
  2261. #define PCS_SOFT_RST2_REG 0xd806
  2262. #define SERDES_RST_N_LBN 13
  2263. #define XGXS_RST_N_LBN 12
  2264. static int
  2265. falcon_tenxpress_check_c11 ( struct efab_nic *efab )
  2266. {
  2267. int count;
  2268. uint32_t boot_stat;
  2269. /* Check that the C11 CPU has booted */
  2270. for (count=0; count<10; count++) {
  2271. boot_stat = falcon_mdio_read ( efab, MDIO_MMD_PCS,
  2272. PCS_BOOT_STATUS_REG );
  2273. if ( boot_stat & ( 1 << PCS_BOOT_COMPLETE_LBN ) )
  2274. return 0;
  2275. udelay(10);
  2276. }
  2277. EFAB_ERR ( "C11 failed to boot\n" );
  2278. return -ETIMEDOUT;
  2279. }
  2280. static int
  2281. falcon_tenxpress_phy_init ( struct efab_nic *efab )
  2282. {
  2283. int rc, reg;
  2284. /* 10XPRESS is always 10000FD (at the moment) */
  2285. efab->link_options = LPA_EF_10000FULL;
  2286. /* Wait for the blocks to come out of reset */
  2287. rc = mdio_clause45_wait_reset_mmds ( efab );
  2288. if ( rc )
  2289. goto fail1;
  2290. rc = mdio_clause45_check_mmds ( efab );
  2291. if ( rc )
  2292. goto fail2;
  2293. /* Turn on the clock */
  2294. reg = (1 << CLK312_EN_LBN);
  2295. falcon_mdio_write ( efab, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, reg);
  2296. /* Wait 200ms for the PHY to boot */
  2297. mdelay(200);
  2298. rc = falcon_tenxpress_check_c11 ( efab );
  2299. if ( rc )
  2300. goto fail3;
  2301. return 0;
  2302. fail3:
  2303. fail2:
  2304. fail1:
  2305. return rc;
  2306. }
  2307. static struct efab_phy_operations falcon_tenxpress_phy_ops = {
  2308. .init = falcon_tenxpress_phy_init,
  2309. .mmds = TENXPRESS_REQUIRED_DEVS,
  2310. };
  2311. /*******************************************************************************
  2312. *
  2313. *
  2314. * PM8358
  2315. *
  2316. *
  2317. *******************************************************************************/
  2318. /* The PM8358 just presents a DTE XS */
  2319. #define PM8358_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_DTEXS)
  2320. /* PHY-specific definitions */
  2321. /* Master ID and Global Performance Monitor Update */
  2322. #define PMC_MASTER_REG (0xd000)
  2323. /* Analog Tx Rx settings under software control */
  2324. #define PMC_MASTER_ANLG_CTRL (1<< 11)
  2325. /* Master Configuration register 2 */
  2326. #define PMC_MCONF2_REG (0xd002)
  2327. /* Drive Tx off centre of data eye (1) vs. clock edge (0) */
  2328. #define PMC_MCONF2_TEDGE (1 << 2)
  2329. /* Drive Rx off centre of data eye (1) vs. clock edge (0) */
  2330. #define PMC_MCONF2_REDGE (1 << 3)
  2331. /* Analog Rx settings */
  2332. #define PMC_ANALOG_RX_CFG0 (0xd025)
  2333. #define PMC_ANALOG_RX_CFG1 (0xd02d)
  2334. #define PMC_ANALOG_RX_CFG2 (0xd035)
  2335. #define PMC_ANALOG_RX_CFG3 (0xd03d)
  2336. #define PMC_ANALOG_RX_TERM (1 << 15) /* Bit 15 of RX CFG: 0 for 100 ohms float,
  2337. 1 for 50 to 1.2V */
  2338. #define PMC_ANALOG_RX_EQ_MASK (3 << 8)
  2339. #define PMC_ANALOG_RX_EQ_NONE (0 << 8)
  2340. #define PMC_ANALOG_RX_EQ_HALF (1 << 8)
  2341. #define PMC_ANALOG_RX_EQ_FULL (2 << 8)
  2342. #define PMC_ANALOG_RX_EQ_RSVD (3 << 8)
  2343. static int
  2344. falcon_pm8358_phy_init ( struct efab_nic *efab )
  2345. {
  2346. int rc, reg, i;
  2347. /* This is a XAUI retimer part */
  2348. efab->link_options = LPA_EF_10000FULL;
  2349. rc = mdio_clause45_reset_mmd ( efab, MDIO_MMDREG_DEVS0_DTEXS );
  2350. if ( rc )
  2351. return rc;
  2352. /* Enable software control of analogue settings */
  2353. reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, PMC_MASTER_REG );
  2354. reg |= PMC_MASTER_ANLG_CTRL;
  2355. falcon_mdio_write ( efab, MDIO_MMD_DTEXS, PMC_MASTER_REG, reg );
  2356. /* Turn rx eq on for all channels */
  2357. for (i=0; i< 3; i++) {
  2358. /* The analog CFG registers are evenly spaced 8 apart */
  2359. uint16_t addr = PMC_ANALOG_RX_CFG0 + 8*i;
  2360. reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, addr );
  2361. reg = ( reg & ~PMC_ANALOG_RX_EQ_MASK ) | PMC_ANALOG_RX_EQ_FULL;
  2362. falcon_mdio_write ( efab, MDIO_MMD_DTEXS, addr, reg );
  2363. }
  2364. /* Set TEDGE, clear REDGE */
  2365. reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, PMC_MCONF2_REG );
  2366. reg = ( reg & ~PMC_MCONF2_REDGE) | PMC_MCONF2_TEDGE;
  2367. falcon_mdio_write ( efab, MDIO_MMD_DTEXS, PMC_MCONF2_REG, reg );
  2368. return 0;
  2369. }
  2370. static struct efab_phy_operations falcon_pm8358_phy_ops = {
  2371. .init = falcon_pm8358_phy_init,
  2372. .mmds = PM8358_REQUIRED_DEVS,
  2373. };
  2374. /*******************************************************************************
  2375. *
  2376. *
  2377. * SFE4001 support
  2378. *
  2379. *
  2380. *******************************************************************************/
  2381. #define MAX_TEMP_THRESH 90
  2382. /* I2C Expander */
  2383. #define PCA9539 0x74
  2384. #define P0_IN 0x00
  2385. #define P0_OUT 0x02
  2386. #define P0_CONFIG 0x06
  2387. #define P0_EN_1V0X_LBN 0
  2388. #define P0_EN_1V0X_WIDTH 1
  2389. #define P0_EN_1V2_LBN 1
  2390. #define P0_EN_1V2_WIDTH 1
  2391. #define P0_EN_2V5_LBN 2
  2392. #define P0_EN_2V5_WIDTH 1
  2393. #define P0_EN_3V3X_LBN 3
  2394. #define P0_EN_3V3X_WIDTH 1
  2395. #define P0_EN_5V_LBN 4
  2396. #define P0_EN_5V_WIDTH 1
  2397. #define P0_X_TRST_LBN 6
  2398. #define P0_X_TRST_WIDTH 1
  2399. #define P1_IN 0x01
  2400. #define P1_CONFIG 0x07
  2401. #define P1_AFE_PWD_LBN 0
  2402. #define P1_AFE_PWD_WIDTH 1
  2403. #define P1_DSP_PWD25_LBN 1
  2404. #define P1_DSP_PWD25_WIDTH 1
  2405. #define P1_SPARE_LBN 4
  2406. #define P1_SPARE_WIDTH 4
  2407. /* Temperature Sensor */
  2408. #define MAX6647 0x4e
  2409. #define RSL 0x02
  2410. #define RLHN 0x05
  2411. #define WLHO 0x0b
  2412. static struct i2c_device i2c_pca9539 = {
  2413. .dev_addr = PCA9539,
  2414. .dev_addr_len = 1,
  2415. .word_addr_len = 1,
  2416. };
  2417. static struct i2c_device i2c_max6647 = {
  2418. .dev_addr = MAX6647,
  2419. .dev_addr_len = 1,
  2420. .word_addr_len = 1,
  2421. };
  2422. static int
  2423. sfe4001_init ( struct efab_nic *efab )
  2424. {
  2425. struct i2c_interface *i2c = &efab->i2c_bb.i2c;
  2426. efab_dword_t reg;
  2427. uint8_t in, cfg, out;
  2428. int count, rc;
  2429. EFAB_LOG ( "Initialise SFE4001 board\n" );
  2430. /* Ensure XGXS and XAUI SerDes are held in reset */
  2431. EFAB_POPULATE_DWORD_7 ( reg,
  2432. FCN_XX_PWRDNA_EN, 1,
  2433. FCN_XX_PWRDNB_EN, 1,
  2434. FCN_XX_RSTPLLAB_EN, 1,
  2435. FCN_XX_RESETA_EN, 1,
  2436. FCN_XX_RESETB_EN, 1,
  2437. FCN_XX_RSTXGXSRX_EN, 1,
  2438. FCN_XX_RSTXGXSTX_EN, 1 );
  2439. falcon_xmac_writel ( efab, &reg, FCN_XX_PWR_RST_REG_MAC);
  2440. udelay(10);
  2441. /* Set DSP over-temperature alert threshold */
  2442. cfg = MAX_TEMP_THRESH;
  2443. rc = i2c->write ( i2c, &i2c_max6647, WLHO, &cfg, EFAB_BYTE );
  2444. if ( rc )
  2445. goto fail1;
  2446. /* Read it back and verify */
  2447. rc = i2c->read ( i2c, &i2c_max6647, RLHN, &in, EFAB_BYTE );
  2448. if ( rc )
  2449. goto fail2;
  2450. if ( in != MAX_TEMP_THRESH ) {
  2451. EFAB_ERR ( "Unable to verify MAX6647 limit (requested=%d "
  2452. "confirmed=%d)\n", cfg, in );
  2453. rc = -EIO;
  2454. goto fail3;
  2455. }
  2456. /* Clear any previous over-temperature alert */
  2457. rc = i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE );
  2458. if ( rc )
  2459. goto fail4;
  2460. /* Enable port 0 and 1 outputs on IO expander */
  2461. cfg = 0x00;
  2462. rc = i2c->write ( i2c, &i2c_pca9539, P0_CONFIG, &cfg, EFAB_BYTE );
  2463. if ( rc )
  2464. goto fail5;
  2465. cfg = 0xff & ~(1 << P1_SPARE_LBN);
  2466. rc = i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &cfg, EFAB_BYTE );
  2467. if ( rc )
  2468. goto fail6;
  2469. /* Turn all power off then wait 1 sec. This ensures PHY is reset */
  2470. out = 0xff & ~((0 << P0_EN_1V2_LBN) | (0 << P0_EN_2V5_LBN) |
  2471. (0 << P0_EN_3V3X_LBN) | (0 << P0_EN_5V_LBN) |
  2472. (0 << P0_EN_1V0X_LBN));
  2473. rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
  2474. if ( rc )
  2475. goto fail7;
  2476. mdelay(1000);
  2477. for (count=0; count<20; count++) {
  2478. /* Turn on 1.2V, 2.5V, 3.3V and 5V power rails */
  2479. out = 0xff & ~( (1 << P0_EN_1V2_LBN) | (1 << P0_EN_2V5_LBN) |
  2480. (1 << P0_EN_3V3X_LBN) | (1 << P0_EN_5V_LBN) |
  2481. (1 << P0_X_TRST_LBN) );
  2482. rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
  2483. if ( rc )
  2484. goto fail8;
  2485. mdelay ( 10 );
  2486. /* Turn on the 1V power rail */
  2487. out &= ~( 1 << P0_EN_1V0X_LBN );
  2488. rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
  2489. if ( rc )
  2490. goto fail9;
  2491. EFAB_LOG ( "Waiting for power...(attempt %d)\n", count);
  2492. mdelay ( 1000 );
  2493. /* Check DSP is powered */
  2494. rc = i2c->read ( i2c, &i2c_pca9539, P1_IN, &in, EFAB_BYTE );
  2495. if ( rc )
  2496. goto fail10;
  2497. if ( in & ( 1 << P1_AFE_PWD_LBN ) )
  2498. return 0;
  2499. }
  2500. rc = -ETIMEDOUT;
  2501. fail10:
  2502. fail9:
  2503. fail8:
  2504. fail7:
  2505. /* Turn off power rails */
  2506. out = 0xff;
  2507. (void) i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
  2508. /* Disable port 1 outputs on IO expander */
  2509. out = 0xff;
  2510. (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &out, EFAB_BYTE );
  2511. fail6:
  2512. /* Disable port 0 outputs */
  2513. out = 0xff;
  2514. (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &out, EFAB_BYTE );
  2515. fail5:
  2516. fail4:
  2517. fail3:
  2518. fail2:
  2519. fail1:
  2520. EFAB_ERR ( "Failed initialising SFE4001 board\n" );
  2521. return rc;
  2522. }
  2523. static void
  2524. sfe4001_fini ( struct efab_nic *efab )
  2525. {
  2526. struct i2c_interface *i2c = &efab->i2c_bb.i2c;
  2527. uint8_t in, cfg, out;
  2528. EFAB_ERR ( "Turning off SFE4001\n" );
  2529. /* Turn off all power rails */
  2530. out = 0xff;
  2531. (void) i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
  2532. /* Disable port 1 outputs on IO expander */
  2533. cfg = 0xff;
  2534. (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &cfg, EFAB_BYTE );
  2535. /* Disable port 0 outputs on IO expander */
  2536. cfg = 0xff;
  2537. (void) i2c->write ( i2c, &i2c_pca9539, P0_CONFIG, &cfg, EFAB_BYTE );
  2538. /* Clear any over-temperature alert */
  2539. (void) i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE );
  2540. }
  2541. struct efab_board_operations sfe4001_ops = {
  2542. .init = sfe4001_init,
  2543. .fini = sfe4001_fini,
  2544. };
  2545. static int sfe4002_init ( struct efab_nic *efab __attribute__((unused)) )
  2546. {
  2547. return 0;
  2548. }
  2549. static void sfe4002_fini ( struct efab_nic *efab __attribute__((unused)) )
  2550. {
  2551. }
  2552. struct efab_board_operations sfe4002_ops = {
  2553. .init = sfe4002_init,
  2554. .fini = sfe4002_fini,
  2555. };
  2556. static int sfe4003_init ( struct efab_nic *efab __attribute__((unused)) )
  2557. {
  2558. return 0;
  2559. }
  2560. static void sfe4003_fini ( struct efab_nic *efab __attribute__((unused)) )
  2561. {
  2562. }
  2563. struct efab_board_operations sfe4003_ops = {
  2564. .init = sfe4003_init,
  2565. .fini = sfe4003_fini,
  2566. };
  2567. /*******************************************************************************
  2568. *
  2569. *
  2570. * Hardware initialisation
  2571. *
  2572. *
  2573. *******************************************************************************/
  2574. static void
  2575. falcon_free_special_buffer ( void *p )
  2576. {
  2577. /* We don't bother cleaning up the buffer table entries -
  2578. * we're hardly limited */
  2579. free_dma ( p, EFAB_BUF_ALIGN );
  2580. }
  2581. static void*
  2582. falcon_alloc_special_buffer ( struct efab_nic *efab, int bytes,
  2583. struct efab_special_buffer *entry )
  2584. {
  2585. void* buffer;
  2586. int remaining;
  2587. efab_qword_t buf_desc;
  2588. unsigned long dma_addr;
  2589. /* Allocate the buffer, aligned on a buffer address boundary */
  2590. buffer = malloc_dma ( bytes, EFAB_BUF_ALIGN );
  2591. if ( ! buffer )
  2592. return NULL;
  2593. /* Push buffer table entries to back the buffer */
  2594. entry->id = efab->buffer_head;
  2595. entry->dma_addr = dma_addr = virt_to_bus ( buffer );
  2596. assert ( ( dma_addr & ( EFAB_BUF_ALIGN - 1 ) ) == 0 );
  2597. remaining = bytes;
  2598. while ( remaining > 0 ) {
  2599. EFAB_POPULATE_QWORD_3 ( buf_desc,
  2600. FCN_IP_DAT_BUF_SIZE, FCN_IP_DAT_BUF_SIZE_4K,
  2601. FCN_BUF_ADR_FBUF, ( dma_addr >> 12 ),
  2602. FCN_BUF_OWNER_ID_FBUF, 0 );
  2603. falcon_write_sram ( efab, &buf_desc, efab->buffer_head );
  2604. ++efab->buffer_head;
  2605. dma_addr += EFAB_BUF_ALIGN;
  2606. remaining -= EFAB_BUF_ALIGN;
  2607. }
  2608. EFAB_TRACE ( "Allocated 0x%x bytes at %p backed by buffer table "
  2609. "entries 0x%x..0x%x\n", bytes, buffer, entry->id,
  2610. efab->buffer_head - 1 );
  2611. return buffer;
  2612. }
  2613. static void
  2614. clear_b0_fpga_memories ( struct efab_nic *efab)
  2615. {
  2616. efab_oword_t blanko, temp;
  2617. int offset;
  2618. EFAB_ZERO_OWORD ( blanko );
  2619. /* Clear the address region register */
  2620. EFAB_POPULATE_OWORD_4 ( temp,
  2621. FCN_ADR_REGION0, 0,
  2622. FCN_ADR_REGION1, ( 1 << 16 ),
  2623. FCN_ADR_REGION2, ( 2 << 16 ),
  2624. FCN_ADR_REGION3, ( 3 << 16 ) );
  2625. falcon_write ( efab, &temp, FCN_ADR_REGION_REG_KER );
  2626. EFAB_TRACE ( "Clearing filter and RSS tables\n" );
  2627. for ( offset = FCN_RX_FILTER_TBL0 ;
  2628. offset < FCN_RX_RSS_INDIR_TBL_B0+0x800 ;
  2629. offset += 0x10 ) {
  2630. falcon_write ( efab, &blanko, offset );
  2631. }
  2632. EFAB_TRACE ( "Wiping buffer tables\n" );
  2633. /* Notice the 8 byte access mode */
  2634. for ( offset = 0x2800000 ;
  2635. offset < 0x3000000 ;
  2636. offset += 0x8) {
  2637. _falcon_writel ( efab, 0, offset );
  2638. _falcon_writel ( efab, 0, offset + 4 );
  2639. wmb();
  2640. }
  2641. }
  2642. static int
  2643. falcon_reset ( struct efab_nic *efab )
  2644. {
  2645. efab_oword_t glb_ctl_reg_ker;
  2646. /* Initiate software reset */
  2647. EFAB_POPULATE_OWORD_6 ( glb_ctl_reg_ker,
  2648. FCN_PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
  2649. FCN_PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
  2650. FCN_PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
  2651. FCN_EE_RST_CTL, EXCLUDE_FROM_RESET,
  2652. FCN_EXT_PHY_RST_DUR, 0x7, /* 10ms */
  2653. FCN_SWRST, 1 );
  2654. falcon_write ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER );
  2655. /* Allow 50ms for reset */
  2656. mdelay ( 50 );
  2657. /* Check for device reset complete */
  2658. falcon_read ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER );
  2659. if ( EFAB_OWORD_FIELD ( glb_ctl_reg_ker, FCN_SWRST ) != 0 ) {
  2660. EFAB_ERR ( "Reset failed\n" );
  2661. return -ETIMEDOUT;
  2662. }
  2663. if ( ( efab->pci_revision == FALCON_REV_B0 ) && !efab->is_asic ) {
  2664. clear_b0_fpga_memories ( efab );
  2665. }
  2666. return 0;
  2667. }
  2668. /** Offset of MAC address within EEPROM or Flash */
  2669. #define FALCON_MAC_ADDRESS_OFFSET 0x310
  2670. /*
  2671. * Falcon EEPROM structure
  2672. */
  2673. #define SF_NV_CONFIG_BASE 0x300
  2674. #define SF_NV_CONFIG_EXTRA 0xA0
  2675. struct falcon_nv_config_ver2 {
  2676. uint16_t nports;
  2677. uint8_t port0_phy_addr;
  2678. uint8_t port0_phy_type;
  2679. uint8_t port1_phy_addr;
  2680. uint8_t port1_phy_type;
  2681. uint16_t asic_sub_revision;
  2682. uint16_t board_revision;
  2683. uint8_t mac_location;
  2684. };
  2685. struct falcon_nv_extra {
  2686. uint16_t magicnumber;
  2687. uint16_t structure_version;
  2688. uint16_t checksum;
  2689. union {
  2690. struct falcon_nv_config_ver2 ver2;
  2691. } ver_specific;
  2692. };
  2693. #define BOARD_TYPE(_rev) (_rev >> 8)
  2694. static void
  2695. falcon_probe_nic_variant ( struct efab_nic *efab, struct pci_device *pci )
  2696. {
  2697. efab_oword_t altera_build, nic_stat;
  2698. int fpga_version;
  2699. uint8_t revision;
  2700. /* PCI revision */
  2701. pci_read_config_byte ( pci, PCI_REVISION, &revision );
  2702. efab->pci_revision = revision;
  2703. /* Asic vs FPGA */
  2704. falcon_read ( efab, &altera_build, FCN_ALTERA_BUILD_REG_KER );
  2705. fpga_version = EFAB_OWORD_FIELD ( altera_build, FCN_VER_ALL );
  2706. efab->is_asic = (fpga_version == 0);
  2707. /* MAC and PCI type */
  2708. falcon_read ( efab, &nic_stat, FCN_NIC_STAT_REG );
  2709. if ( efab->pci_revision == FALCON_REV_B0 ) {
  2710. efab->phy_10g = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_10G );
  2711. }
  2712. else if ( efab->is_asic ) {
  2713. efab->phy_10g = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_10G );
  2714. }
  2715. else {
  2716. int minor = EFAB_OWORD_FIELD ( altera_build, FCN_VER_MINOR );
  2717. efab->phy_10g = ( minor == 0x14 );
  2718. }
  2719. }
  2720. static void
  2721. falcon_init_spi_device ( struct efab_nic *efab, struct spi_device *spi )
  2722. {
  2723. /* Falcon's SPI interface only supports reads/writes of up to 16 bytes.
  2724. * Reduce the nvs block size down to satisfy this - which means callers
  2725. * should use the nvs_* functions rather than spi_*. */
  2726. if ( spi->nvs.block_size > FALCON_SPI_MAX_LEN )
  2727. spi->nvs.block_size = FALCON_SPI_MAX_LEN;
  2728. spi->bus = &efab->spi_bus;
  2729. efab->spi = spi;
  2730. }
  2731. static int
  2732. falcon_probe_spi ( struct efab_nic *efab )
  2733. {
  2734. efab_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
  2735. int has_flash, has_eeprom, ad9bit;
  2736. falcon_read ( efab, &nic_stat, FCN_NIC_STAT_REG );
  2737. falcon_read ( efab, &gpio_ctl, FCN_GPIO_CTL_REG_KER );
  2738. falcon_read ( efab, &ee_vpd_cfg, FCN_EE_VPD_CFG_REG );
  2739. /* determine if FLASH / EEPROM is present */
  2740. if ( ( efab->pci_revision >= FALCON_REV_B0 ) || efab->is_asic ) {
  2741. has_flash = EFAB_OWORD_FIELD ( nic_stat, FCN_SF_PRST );
  2742. has_eeprom = EFAB_OWORD_FIELD ( nic_stat, FCN_EE_PRST );
  2743. } else {
  2744. has_flash = EFAB_OWORD_FIELD ( gpio_ctl, FCN_FLASH_PRESENT );
  2745. has_eeprom = EFAB_OWORD_FIELD ( gpio_ctl, FCN_EEPROM_PRESENT );
  2746. }
  2747. ad9bit = EFAB_OWORD_FIELD ( ee_vpd_cfg, FCN_EE_VPD_EN_AD9_MODE );
  2748. /* Configure the SPI and I2C bus */
  2749. efab->spi_bus.rw = falcon_spi_rw;
  2750. init_i2c_bit_basher ( &efab->i2c_bb, &falcon_i2c_bit_ops );
  2751. /* Configure the EEPROM SPI device. Generally, an Atmel 25040
  2752. * (or similar) is used, but this is only possible if there is also
  2753. * a flash device present to store the boot-time chip configuration.
  2754. */
  2755. if ( has_eeprom ) {
  2756. if ( has_flash && ad9bit )
  2757. init_at25040 ( &efab->spi_eeprom );
  2758. else
  2759. init_mc25xx640 ( &efab->spi_eeprom );
  2760. falcon_init_spi_device ( efab, &efab->spi_eeprom );
  2761. }
  2762. /* Configure the FLASH SPI device */
  2763. if ( has_flash ) {
  2764. init_at25f1024 ( &efab->spi_flash );
  2765. falcon_init_spi_device ( efab, &efab->spi_flash );
  2766. }
  2767. EFAB_LOG ( "flash is %s, EEPROM is %s%s\n",
  2768. ( has_flash ? "present" : "absent" ),
  2769. ( has_eeprom ? "present " : "absent" ),
  2770. ( has_eeprom ? (ad9bit ? "(9bit)" : "(16bit)") : "") );
  2771. /* The device MUST have flash or eeprom */
  2772. if ( ! efab->spi ) {
  2773. EFAB_ERR ( "Device appears to have no flash or eeprom\n" );
  2774. return -EIO;
  2775. }
  2776. /* If the device has EEPROM attached, then advertise NVO space */
  2777. if ( has_eeprom ) {
  2778. nvo_init ( &efab->nvo, &efab->spi_eeprom.nvs, 0x100, 0xf0,
  2779. NULL, &efab->netdev->refcnt );
  2780. }
  2781. return 0;
  2782. }
  2783. static int
  2784. falcon_probe_nvram ( struct efab_nic *efab )
  2785. {
  2786. struct nvs_device *nvs = &efab->spi->nvs;
  2787. struct falcon_nv_extra nv;
  2788. int rc, board_revision;
  2789. /* Read the MAC address */
  2790. rc = nvs_read ( nvs, FALCON_MAC_ADDRESS_OFFSET,
  2791. efab->mac_addr, ETH_ALEN );
  2792. if ( rc )
  2793. return rc;
  2794. /* Poke through the NVRAM structure for the PHY type. */
  2795. rc = nvs_read ( nvs, SF_NV_CONFIG_BASE + SF_NV_CONFIG_EXTRA,
  2796. &nv, sizeof ( nv ) );
  2797. if ( rc )
  2798. return rc;
  2799. /* Handle each supported NVRAM version */
  2800. if ( ( le16_to_cpu ( nv.magicnumber ) == FCN_NV_MAGIC_NUMBER ) &&
  2801. ( le16_to_cpu ( nv.structure_version ) >= 2 ) ) {
  2802. struct falcon_nv_config_ver2* ver2 = &nv.ver_specific.ver2;
  2803. /* Get the PHY type */
  2804. efab->phy_addr = le16_to_cpu ( ver2->port0_phy_addr );
  2805. efab->phy_type = le16_to_cpu ( ver2->port0_phy_type );
  2806. board_revision = le16_to_cpu ( ver2->board_revision );
  2807. }
  2808. else {
  2809. EFAB_ERR ( "NVram is not recognised\n" );
  2810. return -EINVAL;
  2811. }
  2812. efab->board_type = BOARD_TYPE ( board_revision );
  2813. EFAB_TRACE ( "Falcon board %d phy %d @ addr %d\n",
  2814. efab->board_type, efab->phy_type, efab->phy_addr );
  2815. /* Patch in the board operations */
  2816. switch ( efab->board_type ) {
  2817. case EFAB_BOARD_SFE4001:
  2818. efab->board_op = &sfe4001_ops;
  2819. break;
  2820. case EFAB_BOARD_SFE4002:
  2821. efab->board_op = &sfe4002_ops;
  2822. break;
  2823. case EFAB_BOARD_SFE4003:
  2824. efab->board_op = &sfe4003_ops;
  2825. break;
  2826. default:
  2827. EFAB_ERR ( "Unrecognised board type\n" );
  2828. return -EINVAL;
  2829. }
  2830. /* Patch in MAC operations */
  2831. if ( efab->phy_10g )
  2832. efab->mac_op = &falcon_xmac_operations;
  2833. else
  2834. efab->mac_op = &falcon_gmac_operations;
  2835. /* Hook in the PHY ops */
  2836. switch ( efab->phy_type ) {
  2837. case PHY_TYPE_10XPRESS:
  2838. efab->phy_op = &falcon_tenxpress_phy_ops;
  2839. break;
  2840. case PHY_TYPE_CX4:
  2841. efab->phy_op = &falcon_xaui_phy_ops;
  2842. break;
  2843. case PHY_TYPE_XFP:
  2844. efab->phy_op = &falcon_xfp_phy_ops;
  2845. break;
  2846. case PHY_TYPE_CX4_RTMR:
  2847. efab->phy_op = &falcon_txc_phy_ops;
  2848. break;
  2849. case PHY_TYPE_PM8358:
  2850. efab->phy_op = &falcon_pm8358_phy_ops;
  2851. break;
  2852. case PHY_TYPE_1GIG_ALASKA:
  2853. efab->phy_op = &falcon_alaska_phy_ops;
  2854. break;
  2855. default:
  2856. EFAB_ERR ( "Unknown PHY type: %d\n", efab->phy_type );
  2857. return -EINVAL;
  2858. }
  2859. return 0;
  2860. }
  2861. static int
  2862. falcon_init_sram ( struct efab_nic *efab )
  2863. {
  2864. efab_oword_t reg;
  2865. int count;
  2866. /* use card in internal SRAM mode */
  2867. falcon_read ( efab, &reg, FCN_NIC_STAT_REG );
  2868. EFAB_SET_OWORD_FIELD ( reg, FCN_ONCHIP_SRAM, 1 );
  2869. falcon_write ( efab, &reg, FCN_NIC_STAT_REG );
  2870. /* Deactivate any external SRAM that might be present */
  2871. EFAB_POPULATE_OWORD_2 ( reg,
  2872. FCN_GPIO1_OEN, 1,
  2873. FCN_GPIO1_OUT, 1 );
  2874. falcon_write ( efab, &reg, FCN_GPIO_CTL_REG_KER );
  2875. /* Initiate SRAM reset */
  2876. EFAB_POPULATE_OWORD_2 ( reg,
  2877. FCN_SRAM_OOB_BT_INIT_EN, 1,
  2878. FCN_SRM_NUM_BANKS_AND_BANK_SIZE, 0 );
  2879. falcon_write ( efab, &reg, FCN_SRM_CFG_REG_KER );
  2880. /* Wait for SRAM reset to complete */
  2881. count = 0;
  2882. do {
  2883. /* SRAM reset is slow; expect around 16ms */
  2884. mdelay ( 20 );
  2885. /* Check for reset complete */
  2886. falcon_read ( efab, &reg, FCN_SRM_CFG_REG_KER );
  2887. if ( !EFAB_OWORD_FIELD ( reg, FCN_SRAM_OOB_BT_INIT_EN ) )
  2888. return 0;
  2889. } while (++count < 20); /* wait up to 0.4 sec */
  2890. EFAB_ERR ( "timed out waiting for SRAM reset\n");
  2891. return -ETIMEDOUT;
  2892. }
  2893. static void
  2894. falcon_setup_nic ( struct efab_nic *efab )
  2895. {
  2896. efab_dword_t timer_cmd;
  2897. efab_oword_t reg;
  2898. int tx_fc, xoff_thresh, xon_thresh;
  2899. /* bug5129: Clear the parity enables on the TX data fifos as
  2900. * they produce false parity errors because of timing issues
  2901. */
  2902. falcon_read ( efab, &reg, FCN_SPARE_REG_KER );
  2903. EFAB_SET_OWORD_FIELD ( reg, FCN_MEM_PERR_EN_TX_DATA, 0 );
  2904. falcon_write ( efab, &reg, FCN_SPARE_REG_KER );
  2905. /* Set up TX and RX descriptor caches in SRAM */
  2906. EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_TX_DC_BASE_ADR, 0x130000 );
  2907. falcon_write ( efab, &reg, FCN_SRM_TX_DC_CFG_REG_KER );
  2908. EFAB_POPULATE_OWORD_1 ( reg, FCN_TX_DC_SIZE, 1 /* 16 descriptors */ );
  2909. falcon_write ( efab, &reg, FCN_TX_DC_CFG_REG_KER );
  2910. EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_RX_DC_BASE_ADR, 0x100000 );
  2911. falcon_write ( efab, &reg, FCN_SRM_RX_DC_CFG_REG_KER );
  2912. EFAB_POPULATE_OWORD_1 ( reg, FCN_RX_DC_SIZE, 2 /* 32 descriptors */ );
  2913. falcon_write ( efab, &reg, FCN_RX_DC_CFG_REG_KER );
  2914. /* Set number of RSS CPUs
  2915. * bug7244: Increase filter depth to reduce RX_RESET likelihood
  2916. */
  2917. EFAB_POPULATE_OWORD_5 ( reg,
  2918. FCN_NUM_KER, 0,
  2919. FCN_UDP_FULL_SRCH_LIMIT, 8,
  2920. FCN_UDP_WILD_SRCH_LIMIT, 8,
  2921. FCN_TCP_WILD_SRCH_LIMIT, 8,
  2922. FCN_TCP_FULL_SRCH_LIMIT, 8);
  2923. falcon_write ( efab, &reg, FCN_RX_FILTER_CTL_REG_KER );
  2924. udelay ( 1000 );
  2925. /* Setup RX. Wait for descriptor is broken and must
  2926. * be disabled. RXDP recovery shouldn't be needed, but is.
  2927. * disable ISCSI parsing because we don't need it
  2928. */
  2929. falcon_read ( efab, &reg, FCN_RX_SELF_RST_REG_KER );
  2930. EFAB_SET_OWORD_FIELD ( reg, FCN_RX_NODESC_WAIT_DIS, 1 );
  2931. EFAB_SET_OWORD_FIELD ( reg, FCN_RX_RECOVERY_EN, 1 );
  2932. EFAB_SET_OWORD_FIELD ( reg, FCN_RX_ISCSI_DIS, 1 );
  2933. falcon_write ( efab, &reg, FCN_RX_SELF_RST_REG_KER );
  2934. /* Determine recommended flow control settings. *
  2935. * Flow control is qualified on B0 and A1/1G, not on A1/10G */
  2936. if ( efab->pci_revision == FALCON_REV_B0 ) {
  2937. tx_fc = 1;
  2938. xoff_thresh = 54272; /* ~80Kb - 3*max MTU */
  2939. xon_thresh = 27648; /* ~3*max MTU */
  2940. }
  2941. else if ( !efab->phy_10g ) {
  2942. tx_fc = 1;
  2943. xoff_thresh = 2048;
  2944. xon_thresh = 512;
  2945. }
  2946. else {
  2947. tx_fc = xoff_thresh = xon_thresh = 0;
  2948. }
  2949. /* Setup TX and RX */
  2950. falcon_read ( efab, &reg, FCN_TX_CFG2_REG_KER );
  2951. EFAB_SET_OWORD_FIELD ( reg, FCN_TX_DIS_NON_IP_EV, 1 );
  2952. falcon_write ( efab, &reg, FCN_TX_CFG2_REG_KER );
  2953. falcon_read ( efab, &reg, FCN_RX_CFG_REG_KER );
  2954. EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_USR_BUF_SIZE,
  2955. (3*4096) / 32 );
  2956. if ( efab->pci_revision == FALCON_REV_B0)
  2957. EFAB_SET_OWORD_FIELD ( reg, FCN_RX_INGR_EN_B0, 1 );
  2958. EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XON_MAC_TH,
  2959. xon_thresh / 256);
  2960. EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XOFF_MAC_TH,
  2961. xoff_thresh / 256);
  2962. EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XOFF_MAC_EN, tx_fc);
  2963. falcon_write ( efab, &reg, FCN_RX_CFG_REG_KER );
  2964. /* Set timer register */
  2965. EFAB_POPULATE_DWORD_2 ( timer_cmd,
  2966. FCN_TIMER_MODE, FCN_TIMER_MODE_DIS,
  2967. FCN_TIMER_VAL, 0 );
  2968. falcon_writel ( efab, &timer_cmd, FCN_TIMER_CMD_REG_KER );
  2969. }
  2970. static void
  2971. falcon_init_resources ( struct efab_nic *efab )
  2972. {
  2973. struct efab_ev_queue *ev_queue = &efab->ev_queue;
  2974. struct efab_rx_queue *rx_queue = &efab->rx_queue;
  2975. struct efab_tx_queue *tx_queue = &efab->tx_queue;
  2976. efab_oword_t reg;
  2977. int jumbo;
  2978. /* Initialise the ptrs */
  2979. tx_queue->read_ptr = tx_queue->write_ptr = 0;
  2980. rx_queue->read_ptr = rx_queue->write_ptr = 0;
  2981. ev_queue->read_ptr = 0;
  2982. /* Push the event queue to the hardware */
  2983. EFAB_POPULATE_OWORD_3 ( reg,
  2984. FCN_EVQ_EN, 1,
  2985. FCN_EVQ_SIZE, FQS(FCN_EVQ, EFAB_EVQ_SIZE),
  2986. FCN_EVQ_BUF_BASE_ID, ev_queue->entry.id );
  2987. falcon_write ( efab, &reg,
  2988. FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) );
  2989. /* Push the tx queue to the hardware */
  2990. EFAB_POPULATE_OWORD_8 ( reg,
  2991. FCN_TX_DESCQ_EN, 1,
  2992. FCN_TX_ISCSI_DDIG_EN, 0,
  2993. FCN_TX_ISCSI_DDIG_EN, 0,
  2994. FCN_TX_DESCQ_BUF_BASE_ID, tx_queue->entry.id,
  2995. FCN_TX_DESCQ_EVQ_ID, 0,
  2996. FCN_TX_DESCQ_SIZE, FQS(FCN_TX_DESCQ, EFAB_TXD_SIZE),
  2997. FCN_TX_DESCQ_TYPE, 0 /* kernel queue */,
  2998. FCN_TX_NON_IP_DROP_DIS_B0, 1 );
  2999. falcon_write ( efab, &reg,
  3000. FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
  3001. /* Push the rx queue to the hardware */
  3002. jumbo = ( efab->pci_revision == FALCON_REV_B0 ) ? 0 : 1;
  3003. EFAB_POPULATE_OWORD_8 ( reg,
  3004. FCN_RX_ISCSI_DDIG_EN, 0,
  3005. FCN_RX_ISCSI_HDIG_EN, 0,
  3006. FCN_RX_DESCQ_BUF_BASE_ID, rx_queue->entry.id,
  3007. FCN_RX_DESCQ_EVQ_ID, 0,
  3008. FCN_RX_DESCQ_SIZE, FQS(FCN_RX_DESCQ, EFAB_RXD_SIZE),
  3009. FCN_RX_DESCQ_TYPE, 0 /* kernel queue */,
  3010. FCN_RX_DESCQ_JUMBO, jumbo,
  3011. FCN_RX_DESCQ_EN, 1 );
  3012. falcon_write ( efab, &reg,
  3013. FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
  3014. /* Program INT_ADR_REG_KER */
  3015. EFAB_POPULATE_OWORD_1 ( reg,
  3016. FCN_INT_ADR_KER, virt_to_bus ( &efab->int_ker ) );
  3017. falcon_write ( efab, &reg, FCN_INT_ADR_REG_KER );
  3018. /* Ack the event queue */
  3019. falcon_eventq_read_ack ( efab, ev_queue );
  3020. }
  3021. static void
  3022. falcon_fini_resources ( struct efab_nic *efab )
  3023. {
  3024. efab_oword_t cmd;
  3025. /* Disable interrupts */
  3026. falcon_interrupts ( efab, 0, 0 );
  3027. /* Flush the dma queues */
  3028. EFAB_POPULATE_OWORD_2 ( cmd,
  3029. FCN_TX_FLUSH_DESCQ_CMD, 1,
  3030. FCN_TX_FLUSH_DESCQ, 0 );
  3031. falcon_write ( efab, &cmd,
  3032. FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
  3033. EFAB_POPULATE_OWORD_2 ( cmd,
  3034. FCN_RX_FLUSH_DESCQ_CMD, 1,
  3035. FCN_RX_FLUSH_DESCQ, 0 );
  3036. falcon_write ( efab, &cmd,
  3037. FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
  3038. mdelay ( 100 );
  3039. /* Remove descriptor rings from card */
  3040. EFAB_ZERO_OWORD ( cmd );
  3041. falcon_write ( efab, &cmd,
  3042. FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
  3043. falcon_write ( efab, &cmd,
  3044. FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
  3045. falcon_write ( efab, &cmd,
  3046. FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) );
  3047. }
  3048. /*******************************************************************************
  3049. *
  3050. *
  3051. * Hardware rx path
  3052. *
  3053. *
  3054. *******************************************************************************/
  3055. static void
  3056. falcon_build_rx_desc ( falcon_rx_desc_t *rxd, struct io_buffer *iob )
  3057. {
  3058. EFAB_POPULATE_QWORD_2 ( *rxd,
  3059. FCN_RX_KER_BUF_SIZE, EFAB_RX_BUF_SIZE,
  3060. FCN_RX_KER_BUF_ADR, virt_to_bus ( iob->data ) );
  3061. }
  3062. static void
  3063. falcon_notify_rx_desc ( struct efab_nic *efab, struct efab_rx_queue *rx_queue )
  3064. {
  3065. efab_dword_t reg;
  3066. int ptr = rx_queue->write_ptr % EFAB_RXD_SIZE;
  3067. EFAB_POPULATE_DWORD_1 ( reg, FCN_RX_DESC_WPTR_DWORD, ptr );
  3068. falcon_writel ( efab, &reg, FCN_RX_DESC_UPD_REG_KER_DWORD );
  3069. }
  3070. /*******************************************************************************
  3071. *
  3072. *
  3073. * Hardware tx path
  3074. *
  3075. *
  3076. *******************************************************************************/
  3077. static void
  3078. falcon_build_tx_desc ( falcon_tx_desc_t *txd, struct io_buffer *iob )
  3079. {
  3080. EFAB_POPULATE_QWORD_2 ( *txd,
  3081. FCN_TX_KER_BYTE_CNT, iob_len ( iob ),
  3082. FCN_TX_KER_BUF_ADR, virt_to_bus ( iob->data ) );
  3083. }
  3084. static void
  3085. falcon_notify_tx_desc ( struct efab_nic *efab,
  3086. struct efab_tx_queue *tx_queue )
  3087. {
  3088. efab_dword_t reg;
  3089. int ptr = tx_queue->write_ptr % EFAB_TXD_SIZE;
  3090. EFAB_POPULATE_DWORD_1 ( reg, FCN_TX_DESC_WPTR_DWORD, ptr );
  3091. falcon_writel ( efab, &reg, FCN_TX_DESC_UPD_REG_KER_DWORD );
  3092. }
  3093. /*******************************************************************************
  3094. *
  3095. *
  3096. * Software receive interface
  3097. *
  3098. *
  3099. *******************************************************************************/
  3100. static int
  3101. efab_fill_rx_queue ( struct efab_nic *efab,
  3102. struct efab_rx_queue *rx_queue )
  3103. {
  3104. int fill_level = rx_queue->write_ptr - rx_queue->read_ptr;
  3105. int space = EFAB_NUM_RX_DESC - fill_level - 1;
  3106. int pushed = 0;
  3107. while ( space ) {
  3108. int buf_id = rx_queue->write_ptr % EFAB_NUM_RX_DESC;
  3109. int desc_id = rx_queue->write_ptr % EFAB_RXD_SIZE;
  3110. struct io_buffer *iob;
  3111. falcon_rx_desc_t *rxd;
  3112. assert ( rx_queue->buf[buf_id] == NULL );
  3113. iob = alloc_iob ( EFAB_RX_BUF_SIZE );
  3114. if ( !iob )
  3115. break;
  3116. EFAB_TRACE ( "pushing rx_buf[%d] iob %p data %p\n",
  3117. buf_id, iob, iob->data );
  3118. rx_queue->buf[buf_id] = iob;
  3119. rxd = rx_queue->ring + desc_id;
  3120. falcon_build_rx_desc ( rxd, iob );
  3121. ++rx_queue->write_ptr;
  3122. ++pushed;
  3123. --space;
  3124. }
  3125. if ( pushed ) {
  3126. /* Push the ptr to hardware */
  3127. falcon_notify_rx_desc ( efab, rx_queue );
  3128. fill_level = rx_queue->write_ptr - rx_queue->read_ptr;
  3129. EFAB_TRACE ( "pushed %d rx buffers to fill level %d\n",
  3130. pushed, fill_level );
  3131. }
  3132. if ( fill_level == 0 )
  3133. return -ENOMEM;
  3134. return 0;
  3135. }
  3136. static void
  3137. efab_receive ( struct efab_nic *efab, unsigned int id, int len, int drop )
  3138. {
  3139. struct efab_rx_queue *rx_queue = &efab->rx_queue;
  3140. struct io_buffer *iob;
  3141. unsigned int read_ptr = rx_queue->read_ptr % EFAB_RXD_SIZE;
  3142. unsigned int buf_ptr = rx_queue->read_ptr % EFAB_NUM_RX_DESC;
  3143. assert ( id == read_ptr );
  3144. /* Pop this rx buffer out of the software ring */
  3145. iob = rx_queue->buf[buf_ptr];
  3146. rx_queue->buf[buf_ptr] = NULL;
  3147. EFAB_TRACE ( "popping rx_buf[%d] iob %p data %p with %d bytes %s\n",
  3148. id, iob, iob->data, len, drop ? "bad" : "ok" );
  3149. /* Pass the packet up if required */
  3150. if ( drop )
  3151. free_iob ( iob );
  3152. else {
  3153. iob_put ( iob, len );
  3154. netdev_rx ( efab->netdev, iob );
  3155. }
  3156. ++rx_queue->read_ptr;
  3157. }
  3158. /*******************************************************************************
  3159. *
  3160. *
  3161. * Software transmit interface
  3162. *
  3163. *
  3164. *******************************************************************************/
  3165. static int
  3166. efab_transmit ( struct net_device *netdev, struct io_buffer *iob )
  3167. {
  3168. struct efab_nic *efab = netdev_priv ( netdev );
  3169. struct efab_tx_queue *tx_queue = &efab->tx_queue;
  3170. int fill_level, space;
  3171. falcon_tx_desc_t *txd;
  3172. int buf_id;
  3173. fill_level = tx_queue->write_ptr - tx_queue->read_ptr;
  3174. space = EFAB_TXD_SIZE - fill_level - 1;
  3175. if ( space < 1 )
  3176. return -ENOBUFS;
  3177. /* Save the iobuffer for later completion */
  3178. buf_id = tx_queue->write_ptr % EFAB_TXD_SIZE;
  3179. assert ( tx_queue->buf[buf_id] == NULL );
  3180. tx_queue->buf[buf_id] = iob;
  3181. EFAB_TRACE ( "tx_buf[%d] for iob %p data %p len %zd\n",
  3182. buf_id, iob, iob->data, iob_len ( iob ) );
  3183. /* Form the descriptor, and push it to hardware */
  3184. txd = tx_queue->ring + buf_id;
  3185. falcon_build_tx_desc ( txd, iob );
  3186. ++tx_queue->write_ptr;
  3187. falcon_notify_tx_desc ( efab, tx_queue );
  3188. return 0;
  3189. }
  3190. static int
  3191. efab_transmit_done ( struct efab_nic *efab, int id )
  3192. {
  3193. struct efab_tx_queue *tx_queue = &efab->tx_queue;
  3194. unsigned int read_ptr, stop;
  3195. /* Complete all buffers from read_ptr up to and including id */
  3196. read_ptr = tx_queue->read_ptr % EFAB_TXD_SIZE;
  3197. stop = ( id + 1 ) % EFAB_TXD_SIZE;
  3198. while ( read_ptr != stop ) {
  3199. struct io_buffer *iob = tx_queue->buf[read_ptr];
  3200. assert ( iob );
  3201. /* Complete the tx buffer */
  3202. if ( iob )
  3203. netdev_tx_complete ( efab->netdev, iob );
  3204. tx_queue->buf[read_ptr] = NULL;
  3205. ++tx_queue->read_ptr;
  3206. read_ptr = tx_queue->read_ptr % EFAB_TXD_SIZE;
  3207. }
  3208. return 0;
  3209. }
  3210. /*******************************************************************************
  3211. *
  3212. *
  3213. * Hardware event path
  3214. *
  3215. *
  3216. *******************************************************************************/
  3217. static void
  3218. falcon_clear_interrupts ( struct efab_nic *efab )
  3219. {
  3220. efab_dword_t reg;
  3221. if ( efab->pci_revision == FALCON_REV_B0 ) {
  3222. /* read the ISR */
  3223. falcon_readl( efab, &reg, INT_ISR0_B0 );
  3224. }
  3225. else {
  3226. /* write to the INT_ACK register */
  3227. EFAB_ZERO_DWORD ( reg );
  3228. falcon_writel ( efab, &reg, FCN_INT_ACK_KER_REG_A1 );
  3229. mb();
  3230. falcon_readl ( efab, &reg,
  3231. WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 );
  3232. }
  3233. }
  3234. static void
  3235. falcon_handle_event ( struct efab_nic *efab, falcon_event_t *evt )
  3236. {
  3237. int ev_code, desc_ptr, len, drop;
  3238. /* Decode event */
  3239. ev_code = EFAB_QWORD_FIELD ( *evt, FCN_EV_CODE );
  3240. switch ( ev_code ) {
  3241. case FCN_TX_IP_EV_DECODE:
  3242. desc_ptr = EFAB_QWORD_FIELD ( *evt, FCN_TX_EV_DESC_PTR );
  3243. efab_transmit_done ( efab, desc_ptr );
  3244. break;
  3245. case FCN_RX_IP_EV_DECODE:
  3246. desc_ptr = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_DESC_PTR );
  3247. len = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_BYTE_CNT );
  3248. drop = !EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_PKT_OK );
  3249. efab_receive ( efab, desc_ptr, len, drop );
  3250. break;
  3251. default:
  3252. EFAB_TRACE ( "Unknown event type %d\n", ev_code );
  3253. break;
  3254. }
  3255. }
  3256. /*******************************************************************************
  3257. *
  3258. *
  3259. * Software (polling) interrupt handler
  3260. *
  3261. *
  3262. *******************************************************************************/
  3263. static void
  3264. efab_poll ( struct net_device *netdev )
  3265. {
  3266. struct efab_nic *efab = netdev_priv ( netdev );
  3267. struct efab_ev_queue *ev_queue = &efab->ev_queue;
  3268. struct efab_rx_queue *rx_queue = &efab->rx_queue;
  3269. falcon_event_t *evt;
  3270. /* Read the event queue by directly looking for events
  3271. * (we don't even bother to read the eventq write ptr) */
  3272. evt = ev_queue->ring + ev_queue->read_ptr;
  3273. while ( falcon_event_present ( evt ) ) {
  3274. EFAB_TRACE ( "Event at index 0x%x address %p is "
  3275. EFAB_QWORD_FMT "\n", ev_queue->read_ptr,
  3276. evt, EFAB_QWORD_VAL ( *evt ) );
  3277. falcon_handle_event ( efab, evt );
  3278. /* Clear the event */
  3279. EFAB_SET_QWORD ( *evt );
  3280. /* Move to the next event. We don't ack the event
  3281. * queue until the end */
  3282. ev_queue->read_ptr = ( ( ev_queue->read_ptr + 1 ) %
  3283. EFAB_EVQ_SIZE );
  3284. evt = ev_queue->ring + ev_queue->read_ptr;
  3285. }
  3286. /* Push more buffers if needed */
  3287. (void) efab_fill_rx_queue ( efab, rx_queue );
  3288. /* Clear any pending interrupts */
  3289. falcon_clear_interrupts ( efab );
  3290. /* Ack the event queue */
  3291. falcon_eventq_read_ack ( efab, ev_queue );
  3292. }
  3293. static void
  3294. efab_irq ( struct net_device *netdev, int enable )
  3295. {
  3296. struct efab_nic *efab = netdev_priv ( netdev );
  3297. struct efab_ev_queue *ev_queue = &efab->ev_queue;
  3298. switch ( enable ) {
  3299. case 0:
  3300. falcon_interrupts ( efab, 0, 0 );
  3301. break;
  3302. case 1:
  3303. falcon_interrupts ( efab, 1, 0 );
  3304. falcon_eventq_read_ack ( efab, ev_queue );
  3305. break;
  3306. case 2:
  3307. falcon_interrupts ( efab, 1, 1 );
  3308. break;
  3309. }
  3310. }
  3311. /*******************************************************************************
  3312. *
  3313. *
  3314. * Software open/close
  3315. *
  3316. *
  3317. *******************************************************************************/
  3318. static void
  3319. efab_free_resources ( struct efab_nic *efab )
  3320. {
  3321. struct efab_ev_queue *ev_queue = &efab->ev_queue;
  3322. struct efab_rx_queue *rx_queue = &efab->rx_queue;
  3323. struct efab_tx_queue *tx_queue = &efab->tx_queue;
  3324. int i;
  3325. for ( i = 0; i < EFAB_NUM_RX_DESC; i++ ) {
  3326. if ( rx_queue->buf[i] )
  3327. free_iob ( rx_queue->buf[i] );
  3328. }
  3329. for ( i = 0; i < EFAB_TXD_SIZE; i++ ) {
  3330. if ( tx_queue->buf[i] )
  3331. netdev_tx_complete ( efab->netdev, tx_queue->buf[i] );
  3332. }
  3333. if ( rx_queue->ring )
  3334. falcon_free_special_buffer ( rx_queue->ring );
  3335. if ( tx_queue->ring )
  3336. falcon_free_special_buffer ( tx_queue->ring );
  3337. if ( ev_queue->ring )
  3338. falcon_free_special_buffer ( ev_queue->ring );
  3339. memset ( rx_queue, 0, sizeof ( *rx_queue ) );
  3340. memset ( tx_queue, 0, sizeof ( *tx_queue ) );
  3341. memset ( ev_queue, 0, sizeof ( *ev_queue ) );
  3342. /* Ensure subsequent buffer allocations start at id 0 */
  3343. efab->buffer_head = 0;
  3344. }
  3345. static int
  3346. efab_alloc_resources ( struct efab_nic *efab )
  3347. {
  3348. struct efab_ev_queue *ev_queue = &efab->ev_queue;
  3349. struct efab_rx_queue *rx_queue = &efab->rx_queue;
  3350. struct efab_tx_queue *tx_queue = &efab->tx_queue;
  3351. size_t bytes;
  3352. /* Allocate the hardware event queue */
  3353. bytes = sizeof ( falcon_event_t ) * EFAB_TXD_SIZE;
  3354. ev_queue->ring = falcon_alloc_special_buffer ( efab, bytes,
  3355. &ev_queue->entry );
  3356. if ( !ev_queue->ring )
  3357. goto fail1;
  3358. /* Initialise the hardware event queue */
  3359. memset ( ev_queue->ring, 0xff, bytes );
  3360. /* Allocate the hardware tx queue */
  3361. bytes = sizeof ( falcon_tx_desc_t ) * EFAB_TXD_SIZE;
  3362. tx_queue->ring = falcon_alloc_special_buffer ( efab, bytes,
  3363. &tx_queue->entry );
  3364. if ( ! tx_queue->ring )
  3365. goto fail2;
  3366. /* Allocate the hardware rx queue */
  3367. bytes = sizeof ( falcon_rx_desc_t ) * EFAB_RXD_SIZE;
  3368. rx_queue->ring = falcon_alloc_special_buffer ( efab, bytes,
  3369. &rx_queue->entry );
  3370. if ( ! rx_queue->ring )
  3371. goto fail3;
  3372. return 0;
  3373. fail3:
  3374. falcon_free_special_buffer ( tx_queue->ring );
  3375. tx_queue->ring = NULL;
  3376. fail2:
  3377. falcon_free_special_buffer ( ev_queue->ring );
  3378. ev_queue->ring = NULL;
  3379. fail1:
  3380. return -ENOMEM;
  3381. }
  3382. static int
  3383. efab_init_mac ( struct efab_nic *efab )
  3384. {
  3385. int count, rc;
  3386. /* This can take several seconds */
  3387. EFAB_LOG ( "Waiting for link..\n" );
  3388. for ( count=0; count<5; count++ ) {
  3389. rc = efab->mac_op->init ( efab );
  3390. if ( rc ) {
  3391. EFAB_ERR ( "Failed reinitialising MAC, error %s\n",
  3392. strerror ( rc ));
  3393. return rc;
  3394. }
  3395. /* Sleep for 2s to wait for the link to settle, either
  3396. * because we want to use it, or because we're about
  3397. * to reset the mac anyway
  3398. */
  3399. mdelay ( 2000 );
  3400. if ( ! efab->link_up ) {
  3401. EFAB_ERR ( "!\n" );
  3402. continue;
  3403. }
  3404. EFAB_LOG ( "\n%dMbps %s-duplex\n",
  3405. ( efab->link_options & LPA_EF_10000 ? 10000 :
  3406. ( efab->link_options & LPA_EF_1000 ? 1000 :
  3407. ( efab->link_options & LPA_100 ? 100 : 10 ) ) ),
  3408. ( efab->link_options & LPA_EF_DUPLEX ?
  3409. "full" : "half" ) );
  3410. /* TODO: Move link state handling to the poll() routine */
  3411. netdev_link_up ( efab->netdev );
  3412. return 0;
  3413. }
  3414. EFAB_ERR ( "timed initialising MAC\n" );
  3415. return -ETIMEDOUT;
  3416. }
  3417. static void
  3418. efab_close ( struct net_device *netdev )
  3419. {
  3420. struct efab_nic *efab = netdev_priv ( netdev );
  3421. falcon_fini_resources ( efab );
  3422. efab_free_resources ( efab );
  3423. efab->board_op->fini ( efab );
  3424. falcon_reset ( efab );
  3425. }
  3426. static int
  3427. efab_open ( struct net_device *netdev )
  3428. {
  3429. struct efab_nic *efab = netdev_priv ( netdev );
  3430. struct efab_rx_queue *rx_queue = &efab->rx_queue;
  3431. int rc;
  3432. rc = falcon_reset ( efab );
  3433. if ( rc )
  3434. goto fail1;
  3435. rc = efab->board_op->init ( efab );
  3436. if ( rc )
  3437. goto fail2;
  3438. rc = falcon_init_sram ( efab );
  3439. if ( rc )
  3440. goto fail3;
  3441. /* Configure descriptor caches before pushing hardware queues */
  3442. falcon_setup_nic ( efab );
  3443. rc = efab_alloc_resources ( efab );
  3444. if ( rc )
  3445. goto fail4;
  3446. falcon_init_resources ( efab );
  3447. /* Push rx buffers */
  3448. rc = efab_fill_rx_queue ( efab, rx_queue );
  3449. if ( rc )
  3450. goto fail5;
  3451. /* Try and bring the interface up */
  3452. rc = efab_init_mac ( efab );
  3453. if ( rc )
  3454. goto fail6;
  3455. return 0;
  3456. fail6:
  3457. fail5:
  3458. efab_free_resources ( efab );
  3459. fail4:
  3460. fail3:
  3461. efab->board_op->fini ( efab );
  3462. fail2:
  3463. falcon_reset ( efab );
  3464. fail1:
  3465. return rc;
  3466. }
  3467. static struct net_device_operations efab_operations = {
  3468. .open = efab_open,
  3469. .close = efab_close,
  3470. .transmit = efab_transmit,
  3471. .poll = efab_poll,
  3472. .irq = efab_irq,
  3473. };
  3474. static void
  3475. efab_remove ( struct pci_device *pci )
  3476. {
  3477. struct net_device *netdev = pci_get_drvdata ( pci );
  3478. struct efab_nic *efab = netdev_priv ( netdev );
  3479. if ( efab->membase ) {
  3480. falcon_reset ( efab );
  3481. iounmap ( efab->membase );
  3482. efab->membase = NULL;
  3483. }
  3484. if ( efab->nvo.nvs ) {
  3485. unregister_nvo ( &efab->nvo );
  3486. efab->nvo.nvs = NULL;
  3487. }
  3488. unregister_netdev ( netdev );
  3489. netdev_nullify ( netdev );
  3490. netdev_put ( netdev );
  3491. }
  3492. static int
  3493. efab_probe ( struct pci_device *pci )
  3494. {
  3495. struct net_device *netdev;
  3496. struct efab_nic *efab;
  3497. unsigned long mmio_start, mmio_len;
  3498. int rc;
  3499. /* Create the network adapter */
  3500. netdev = alloc_etherdev ( sizeof ( struct efab_nic ) );
  3501. if ( ! netdev ) {
  3502. rc = -ENOMEM;
  3503. goto fail1;
  3504. }
  3505. /* Initialise the network adapter, and initialise private storage */
  3506. netdev_init ( netdev, &efab_operations );
  3507. pci_set_drvdata ( pci, netdev );
  3508. netdev->dev = &pci->dev;
  3509. efab = netdev_priv ( netdev );
  3510. memset ( efab, 0, sizeof ( *efab ) );
  3511. efab->netdev = netdev;
  3512. /* Get iobase/membase */
  3513. mmio_start = pci_bar_start ( pci, PCI_BASE_ADDRESS_2 );
  3514. mmio_len = pci_bar_size ( pci, PCI_BASE_ADDRESS_2 );
  3515. efab->membase = ioremap ( mmio_start, mmio_len );
  3516. EFAB_TRACE ( "BAR of %lx bytes at phys %lx mapped at %p\n",
  3517. mmio_len, mmio_start, efab->membase );
  3518. /* Enable the PCI device */
  3519. adjust_pci_device ( pci );
  3520. efab->iobase = pci->ioaddr & ~3;
  3521. /* Determine the NIC variant */
  3522. falcon_probe_nic_variant ( efab, pci );
  3523. /* Read the SPI interface and determine the MAC address,
  3524. * and the board and phy variant. Hook in the op tables */
  3525. rc = falcon_probe_spi ( efab );
  3526. if ( rc )
  3527. goto fail2;
  3528. rc = falcon_probe_nvram ( efab );
  3529. if ( rc )
  3530. goto fail3;
  3531. memcpy ( netdev->hw_addr, efab->mac_addr, ETH_ALEN );
  3532. rc = register_netdev ( netdev );
  3533. if ( rc )
  3534. goto fail4;
  3535. netdev_link_up ( netdev );
  3536. /* Advertise non-volatile storage */
  3537. if ( efab->nvo.nvs ) {
  3538. rc = register_nvo ( &efab->nvo, netdev_settings ( netdev ) );
  3539. if ( rc )
  3540. goto fail5;
  3541. }
  3542. EFAB_LOG ( "Found %s EtherFabric %s %s revision %d\n", pci->id->name,
  3543. efab->is_asic ? "ASIC" : "FPGA",
  3544. efab->phy_10g ? "10G" : "1G",
  3545. efab->pci_revision );
  3546. return 0;
  3547. fail5:
  3548. unregister_netdev ( netdev );
  3549. fail4:
  3550. fail3:
  3551. fail2:
  3552. iounmap ( efab->membase );
  3553. efab->membase = NULL;
  3554. netdev_put ( netdev );
  3555. fail1:
  3556. return rc;
  3557. }
  3558. static struct pci_device_id efab_nics[] = {
  3559. PCI_ROM(0x1924, 0x0703, "falcon", "EtherFabric Falcon", 0),
  3560. PCI_ROM(0x1924, 0x0710, "falconb0", "EtherFabric FalconB0", 0),
  3561. };
  3562. struct pci_driver etherfabric_driver __pci_driver = {
  3563. .ids = efab_nics,
  3564. .id_count = sizeof ( efab_nics ) / sizeof ( efab_nics[0] ),
  3565. .probe = efab_probe,
  3566. .remove = efab_remove,
  3567. };
  3568. /*
  3569. * Local variables:
  3570. * c-basic-offset: 8
  3571. * c-indent-level: 8
  3572. * tab-width: 8
  3573. * End:
  3574. */