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skge.c 63KB

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  1. /*
  2. * iPXE driver for Marvell Yukon chipset and SysKonnect Gigabit
  3. * Ethernet adapters. Derived from Linux skge driver (v1.13), which was
  4. * based on earlier sk98lin, e100 and FreeBSD if_sk drivers.
  5. *
  6. * This driver intentionally does not support all the features of the
  7. * original driver such as link fail-over and link management because
  8. * those should be done at higher levels.
  9. *
  10. * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
  11. *
  12. * Modified for iPXE, July 2008 by Michael Decker <mrd999@gmail.com>
  13. * Tested and Modified in December 2009 by
  14. * Thomas Miletich <thomas.miletich@gmail.com>
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License as published by
  18. * the Free Software Foundation; either version 2 of the License.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  28. * 02110-1301, USA.
  29. */
  30. FILE_LICENCE ( GPL2_ONLY );
  31. #include <stdint.h>
  32. #include <errno.h>
  33. #include <stdio.h>
  34. #include <unistd.h>
  35. #include <ipxe/netdevice.h>
  36. #include <ipxe/ethernet.h>
  37. #include <ipxe/if_ether.h>
  38. #include <ipxe/iobuf.h>
  39. #include <ipxe/malloc.h>
  40. #include <ipxe/pci.h>
  41. #include "skge.h"
  42. static struct pci_device_id skge_id_table[] = {
  43. PCI_ROM(0x10b7, 0x1700, "3C940", "3COM 3C940", 0),
  44. PCI_ROM(0x10b7, 0x80eb, "3C940B", "3COM 3C940", 0),
  45. PCI_ROM(0x1148, 0x4300, "GE", "Syskonnect GE", 0),
  46. PCI_ROM(0x1148, 0x4320, "YU", "Syskonnect YU", 0),
  47. PCI_ROM(0x1186, 0x4C00, "DGE510T", "DLink DGE-510T", 0),
  48. PCI_ROM(0x1186, 0x4b01, "DGE530T", "DLink DGE-530T", 0),
  49. PCI_ROM(0x11ab, 0x4320, "id4320", "Marvell id4320", 0),
  50. PCI_ROM(0x11ab, 0x5005, "id5005", "Marvell id5005", 0), /* Belkin */
  51. PCI_ROM(0x1371, 0x434e, "Gigacard", "CNET Gigacard", 0),
  52. PCI_ROM(0x1737, 0x1064, "EG1064", "Linksys EG1064", 0),
  53. PCI_ROM(0x1737, 0xffff, "id_any", "Linksys [any]", 0)
  54. };
  55. static int skge_up(struct net_device *dev);
  56. static void skge_down(struct net_device *dev);
  57. static void skge_tx_clean(struct net_device *dev);
  58. static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
  59. static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
  60. static void yukon_init(struct skge_hw *hw, int port);
  61. static void genesis_mac_init(struct skge_hw *hw, int port);
  62. static void genesis_link_up(struct skge_port *skge);
  63. static void skge_phyirq(struct skge_hw *hw);
  64. static void skge_poll(struct net_device *dev);
  65. static int skge_xmit_frame(struct net_device *dev, struct io_buffer *iob);
  66. static void skge_net_irq ( struct net_device *dev, int enable );
  67. static void skge_rx_refill(struct net_device *dev);
  68. static struct net_device_operations skge_operations = {
  69. .open = skge_up,
  70. .close = skge_down,
  71. .transmit = skge_xmit_frame,
  72. .poll = skge_poll,
  73. .irq = skge_net_irq
  74. };
  75. /* Avoid conditionals by using array */
  76. static const int txqaddr[] = { Q_XA1, Q_XA2 };
  77. static const int rxqaddr[] = { Q_R1, Q_R2 };
  78. static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
  79. /* Determine supported/advertised modes based on hardware.
  80. * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
  81. */
  82. static u32 skge_supported_modes(const struct skge_hw *hw)
  83. {
  84. u32 supported;
  85. if (hw->copper) {
  86. supported = SUPPORTED_10baseT_Half
  87. | SUPPORTED_10baseT_Full
  88. | SUPPORTED_100baseT_Half
  89. | SUPPORTED_100baseT_Full
  90. | SUPPORTED_1000baseT_Half
  91. | SUPPORTED_1000baseT_Full
  92. | SUPPORTED_Autoneg| SUPPORTED_TP;
  93. if (hw->chip_id == CHIP_ID_GENESIS)
  94. supported &= ~(SUPPORTED_10baseT_Half
  95. | SUPPORTED_10baseT_Full
  96. | SUPPORTED_100baseT_Half
  97. | SUPPORTED_100baseT_Full);
  98. else if (hw->chip_id == CHIP_ID_YUKON)
  99. supported &= ~SUPPORTED_1000baseT_Half;
  100. } else
  101. supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
  102. | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
  103. return supported;
  104. }
  105. /* Chip internal frequency for clock calculations */
  106. static inline u32 hwkhz(const struct skge_hw *hw)
  107. {
  108. return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
  109. }
  110. /* Microseconds to chip HZ */
  111. static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
  112. {
  113. return hwkhz(hw) * usec / 1000;
  114. }
  115. enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
  116. static void skge_led(struct skge_port *skge, enum led_mode mode)
  117. {
  118. struct skge_hw *hw = skge->hw;
  119. int port = skge->port;
  120. if (hw->chip_id == CHIP_ID_GENESIS) {
  121. switch (mode) {
  122. case LED_MODE_OFF:
  123. if (hw->phy_type == SK_PHY_BCOM)
  124. xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
  125. else {
  126. skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
  127. skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
  128. }
  129. skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
  130. skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
  131. skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
  132. break;
  133. case LED_MODE_ON:
  134. skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
  135. skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
  136. skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
  137. skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
  138. break;
  139. case LED_MODE_TST:
  140. skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
  141. skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
  142. skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
  143. if (hw->phy_type == SK_PHY_BCOM)
  144. xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
  145. else {
  146. skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
  147. skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
  148. skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
  149. }
  150. }
  151. } else {
  152. switch (mode) {
  153. case LED_MODE_OFF:
  154. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
  155. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  156. PHY_M_LED_MO_DUP(MO_LED_OFF) |
  157. PHY_M_LED_MO_10(MO_LED_OFF) |
  158. PHY_M_LED_MO_100(MO_LED_OFF) |
  159. PHY_M_LED_MO_1000(MO_LED_OFF) |
  160. PHY_M_LED_MO_RX(MO_LED_OFF));
  161. break;
  162. case LED_MODE_ON:
  163. gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
  164. PHY_M_LED_PULS_DUR(PULS_170MS) |
  165. PHY_M_LED_BLINK_RT(BLINK_84MS) |
  166. PHY_M_LEDC_TX_CTRL |
  167. PHY_M_LEDC_DP_CTRL);
  168. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  169. PHY_M_LED_MO_RX(MO_LED_OFF) |
  170. (skge->speed == SPEED_100 ?
  171. PHY_M_LED_MO_100(MO_LED_ON) : 0));
  172. break;
  173. case LED_MODE_TST:
  174. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
  175. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  176. PHY_M_LED_MO_DUP(MO_LED_ON) |
  177. PHY_M_LED_MO_10(MO_LED_ON) |
  178. PHY_M_LED_MO_100(MO_LED_ON) |
  179. PHY_M_LED_MO_1000(MO_LED_ON) |
  180. PHY_M_LED_MO_RX(MO_LED_ON));
  181. }
  182. }
  183. }
  184. /*
  185. * I've left in these EEPROM and VPD functions, as someone may desire to
  186. * integrate them in the future. -mdeck
  187. *
  188. * static int skge_get_eeprom_len(struct net_device *dev)
  189. * {
  190. * struct skge_port *skge = netdev_priv(dev);
  191. * u32 reg2;
  192. *
  193. * pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
  194. * return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
  195. * }
  196. *
  197. * static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
  198. * {
  199. * u32 val;
  200. *
  201. * pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
  202. *
  203. * do {
  204. * pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
  205. * } while (!(offset & PCI_VPD_ADDR_F));
  206. *
  207. * pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
  208. * return val;
  209. * }
  210. *
  211. * static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
  212. * {
  213. * pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
  214. * pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
  215. * offset | PCI_VPD_ADDR_F);
  216. *
  217. * do {
  218. * pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
  219. * } while (offset & PCI_VPD_ADDR_F);
  220. * }
  221. *
  222. * static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  223. * u8 *data)
  224. * {
  225. * struct skge_port *skge = netdev_priv(dev);
  226. * struct pci_dev *pdev = skge->hw->pdev;
  227. * int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
  228. * int length = eeprom->len;
  229. * u16 offset = eeprom->offset;
  230. *
  231. * if (!cap)
  232. * return -EINVAL;
  233. *
  234. * eeprom->magic = SKGE_EEPROM_MAGIC;
  235. *
  236. * while (length > 0) {
  237. * u32 val = skge_vpd_read(pdev, cap, offset);
  238. * int n = min_t(int, length, sizeof(val));
  239. *
  240. * memcpy(data, &val, n);
  241. * length -= n;
  242. * data += n;
  243. * offset += n;
  244. * }
  245. * return 0;
  246. * }
  247. *
  248. * static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  249. * u8 *data)
  250. * {
  251. * struct skge_port *skge = netdev_priv(dev);
  252. * struct pci_dev *pdev = skge->hw->pdev;
  253. * int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
  254. * int length = eeprom->len;
  255. * u16 offset = eeprom->offset;
  256. *
  257. * if (!cap)
  258. * return -EINVAL;
  259. *
  260. * if (eeprom->magic != SKGE_EEPROM_MAGIC)
  261. * return -EINVAL;
  262. *
  263. * while (length > 0) {
  264. * u32 val;
  265. * int n = min_t(int, length, sizeof(val));
  266. *
  267. * if (n < sizeof(val))
  268. * val = skge_vpd_read(pdev, cap, offset);
  269. * memcpy(&val, data, n);
  270. *
  271. * skge_vpd_write(pdev, cap, offset, val);
  272. *
  273. * length -= n;
  274. * data += n;
  275. * offset += n;
  276. * }
  277. * return 0;
  278. * }
  279. */
  280. /*
  281. * Allocate ring elements and chain them together
  282. * One-to-one association of board descriptors with ring elements
  283. */
  284. static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base,
  285. size_t num)
  286. {
  287. struct skge_tx_desc *d;
  288. struct skge_element *e;
  289. unsigned int i;
  290. ring->start = zalloc(num*sizeof(*e));
  291. if (!ring->start)
  292. return -ENOMEM;
  293. for (i = 0, e = ring->start, d = vaddr; i < num; i++, e++, d++) {
  294. e->desc = d;
  295. if (i == num - 1) {
  296. e->next = ring->start;
  297. d->next_offset = base;
  298. } else {
  299. e->next = e + 1;
  300. d->next_offset = base + (i+1) * sizeof(*d);
  301. }
  302. }
  303. ring->to_use = ring->to_clean = ring->start;
  304. return 0;
  305. }
  306. /* Allocate and setup a new buffer for receiving */
  307. static void skge_rx_setup(struct skge_port *skge __unused,
  308. struct skge_element *e,
  309. struct io_buffer *iob, unsigned int bufsize)
  310. {
  311. struct skge_rx_desc *rd = e->desc;
  312. u64 map;
  313. map = ( iob != NULL ) ? virt_to_bus(iob->data) : 0;
  314. rd->dma_lo = map;
  315. rd->dma_hi = map >> 32;
  316. e->iob = iob;
  317. rd->csum1_start = ETH_HLEN;
  318. rd->csum2_start = ETH_HLEN;
  319. rd->csum1 = 0;
  320. rd->csum2 = 0;
  321. wmb();
  322. rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
  323. }
  324. /* Resume receiving using existing skb,
  325. * Note: DMA address is not changed by chip.
  326. * MTU not changed while receiver active.
  327. */
  328. static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
  329. {
  330. struct skge_rx_desc *rd = e->desc;
  331. rd->csum2 = 0;
  332. rd->csum2_start = ETH_HLEN;
  333. wmb();
  334. rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
  335. }
  336. /* Free all buffers in receive ring, assumes receiver stopped */
  337. static void skge_rx_clean(struct skge_port *skge)
  338. {
  339. struct skge_ring *ring = &skge->rx_ring;
  340. struct skge_element *e;
  341. e = ring->start;
  342. do {
  343. struct skge_rx_desc *rd = e->desc;
  344. rd->control = 0;
  345. if (e->iob) {
  346. free_iob(e->iob);
  347. e->iob = NULL;
  348. }
  349. } while ((e = e->next) != ring->start);
  350. }
  351. static void skge_link_up(struct skge_port *skge)
  352. {
  353. skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
  354. LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
  355. netdev_link_up(skge->netdev);
  356. DBG2(PFX "%s: Link is up at %d Mbps, %s duplex\n",
  357. skge->netdev->name, skge->speed,
  358. skge->duplex == DUPLEX_FULL ? "full" : "half");
  359. }
  360. static void skge_link_down(struct skge_port *skge)
  361. {
  362. skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
  363. netdev_link_down(skge->netdev);
  364. DBG2(PFX "%s: Link is down.\n", skge->netdev->name);
  365. }
  366. static void xm_link_down(struct skge_hw *hw, int port)
  367. {
  368. struct net_device *dev = hw->dev[port];
  369. struct skge_port *skge = netdev_priv(dev);
  370. xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
  371. if (netdev_link_ok(dev))
  372. skge_link_down(skge);
  373. }
  374. static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
  375. {
  376. int i;
  377. xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
  378. *val = xm_read16(hw, port, XM_PHY_DATA);
  379. if (hw->phy_type == SK_PHY_XMAC)
  380. goto ready;
  381. for (i = 0; i < PHY_RETRIES; i++) {
  382. if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
  383. goto ready;
  384. udelay(1);
  385. }
  386. return -ETIMEDOUT;
  387. ready:
  388. *val = xm_read16(hw, port, XM_PHY_DATA);
  389. return 0;
  390. }
  391. static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
  392. {
  393. u16 v = 0;
  394. if (__xm_phy_read(hw, port, reg, &v))
  395. DBG(PFX "%s: phy read timed out\n",
  396. hw->dev[port]->name);
  397. return v;
  398. }
  399. static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
  400. {
  401. int i;
  402. xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
  403. for (i = 0; i < PHY_RETRIES; i++) {
  404. if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
  405. goto ready;
  406. udelay(1);
  407. }
  408. return -EIO;
  409. ready:
  410. xm_write16(hw, port, XM_PHY_DATA, val);
  411. for (i = 0; i < PHY_RETRIES; i++) {
  412. if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
  413. return 0;
  414. udelay(1);
  415. }
  416. return -ETIMEDOUT;
  417. }
  418. static void genesis_init(struct skge_hw *hw)
  419. {
  420. /* set blink source counter */
  421. skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
  422. skge_write8(hw, B2_BSC_CTRL, BSC_START);
  423. /* configure mac arbiter */
  424. skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
  425. /* configure mac arbiter timeout values */
  426. skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
  427. skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
  428. skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
  429. skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
  430. skge_write8(hw, B3_MA_RCINI_RX1, 0);
  431. skge_write8(hw, B3_MA_RCINI_RX2, 0);
  432. skge_write8(hw, B3_MA_RCINI_TX1, 0);
  433. skge_write8(hw, B3_MA_RCINI_TX2, 0);
  434. /* configure packet arbiter timeout */
  435. skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
  436. skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
  437. skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
  438. skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
  439. skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
  440. }
  441. static void genesis_reset(struct skge_hw *hw, int port)
  442. {
  443. const u8 zero[8] = { 0 };
  444. u32 reg;
  445. skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
  446. /* reset the statistics module */
  447. xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
  448. xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
  449. xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
  450. xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
  451. xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
  452. /* disable Broadcom PHY IRQ */
  453. if (hw->phy_type == SK_PHY_BCOM)
  454. xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
  455. xm_outhash(hw, port, XM_HSM, zero);
  456. /* Flush TX and RX fifo */
  457. reg = xm_read32(hw, port, XM_MODE);
  458. xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
  459. xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
  460. }
  461. /* Convert mode to MII values */
  462. static const u16 phy_pause_map[] = {
  463. [FLOW_MODE_NONE] = 0,
  464. [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
  465. [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
  466. [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
  467. };
  468. /* special defines for FIBER (88E1011S only) */
  469. static const u16 fiber_pause_map[] = {
  470. [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
  471. [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
  472. [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
  473. [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
  474. };
  475. /* Check status of Broadcom phy link */
  476. static void bcom_check_link(struct skge_hw *hw, int port)
  477. {
  478. struct net_device *dev = hw->dev[port];
  479. struct skge_port *skge = netdev_priv(dev);
  480. u16 status;
  481. /* read twice because of latch */
  482. xm_phy_read(hw, port, PHY_BCOM_STAT);
  483. status = xm_phy_read(hw, port, PHY_BCOM_STAT);
  484. if ((status & PHY_ST_LSYNC) == 0) {
  485. xm_link_down(hw, port);
  486. return;
  487. }
  488. if (skge->autoneg == AUTONEG_ENABLE) {
  489. u16 lpa, aux;
  490. if (!(status & PHY_ST_AN_OVER))
  491. return;
  492. lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
  493. if (lpa & PHY_B_AN_RF) {
  494. DBG(PFX "%s: remote fault\n",
  495. dev->name);
  496. return;
  497. }
  498. aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
  499. /* Check Duplex mismatch */
  500. switch (aux & PHY_B_AS_AN_RES_MSK) {
  501. case PHY_B_RES_1000FD:
  502. skge->duplex = DUPLEX_FULL;
  503. break;
  504. case PHY_B_RES_1000HD:
  505. skge->duplex = DUPLEX_HALF;
  506. break;
  507. default:
  508. DBG(PFX "%s: duplex mismatch\n",
  509. dev->name);
  510. return;
  511. }
  512. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  513. switch (aux & PHY_B_AS_PAUSE_MSK) {
  514. case PHY_B_AS_PAUSE_MSK:
  515. skge->flow_status = FLOW_STAT_SYMMETRIC;
  516. break;
  517. case PHY_B_AS_PRR:
  518. skge->flow_status = FLOW_STAT_REM_SEND;
  519. break;
  520. case PHY_B_AS_PRT:
  521. skge->flow_status = FLOW_STAT_LOC_SEND;
  522. break;
  523. default:
  524. skge->flow_status = FLOW_STAT_NONE;
  525. }
  526. skge->speed = SPEED_1000;
  527. }
  528. if (!netdev_link_ok(dev))
  529. genesis_link_up(skge);
  530. }
  531. /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
  532. * Phy on for 100 or 10Mbit operation
  533. */
  534. static void bcom_phy_init(struct skge_port *skge)
  535. {
  536. struct skge_hw *hw = skge->hw;
  537. int port = skge->port;
  538. unsigned int i;
  539. u16 id1, r, ext, ctl;
  540. /* magic workaround patterns for Broadcom */
  541. static const struct {
  542. u16 reg;
  543. u16 val;
  544. } A1hack[] = {
  545. { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
  546. { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
  547. { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
  548. { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
  549. }, C0hack[] = {
  550. { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
  551. { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
  552. };
  553. /* read Id from external PHY (all have the same address) */
  554. id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
  555. /* Optimize MDIO transfer by suppressing preamble. */
  556. r = xm_read16(hw, port, XM_MMU_CMD);
  557. r |= XM_MMU_NO_PRE;
  558. xm_write16(hw, port, XM_MMU_CMD,r);
  559. switch (id1) {
  560. case PHY_BCOM_ID1_C0:
  561. /*
  562. * Workaround BCOM Errata for the C0 type.
  563. * Write magic patterns to reserved registers.
  564. */
  565. for (i = 0; i < ARRAY_SIZE(C0hack); i++)
  566. xm_phy_write(hw, port,
  567. C0hack[i].reg, C0hack[i].val);
  568. break;
  569. case PHY_BCOM_ID1_A1:
  570. /*
  571. * Workaround BCOM Errata for the A1 type.
  572. * Write magic patterns to reserved registers.
  573. */
  574. for (i = 0; i < ARRAY_SIZE(A1hack); i++)
  575. xm_phy_write(hw, port,
  576. A1hack[i].reg, A1hack[i].val);
  577. break;
  578. }
  579. /*
  580. * Workaround BCOM Errata (#10523) for all BCom PHYs.
  581. * Disable Power Management after reset.
  582. */
  583. r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
  584. r |= PHY_B_AC_DIS_PM;
  585. xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
  586. /* Dummy read */
  587. xm_read16(hw, port, XM_ISRC);
  588. ext = PHY_B_PEC_EN_LTR; /* enable tx led */
  589. ctl = PHY_CT_SP1000; /* always 1000mbit */
  590. if (skge->autoneg == AUTONEG_ENABLE) {
  591. /*
  592. * Workaround BCOM Errata #1 for the C5 type.
  593. * 1000Base-T Link Acquisition Failure in Slave Mode
  594. * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
  595. */
  596. u16 adv = PHY_B_1000C_RD;
  597. if (skge->advertising & ADVERTISED_1000baseT_Half)
  598. adv |= PHY_B_1000C_AHD;
  599. if (skge->advertising & ADVERTISED_1000baseT_Full)
  600. adv |= PHY_B_1000C_AFD;
  601. xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
  602. ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
  603. } else {
  604. if (skge->duplex == DUPLEX_FULL)
  605. ctl |= PHY_CT_DUP_MD;
  606. /* Force to slave */
  607. xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
  608. }
  609. /* Set autonegotiation pause parameters */
  610. xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
  611. phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
  612. xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
  613. xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
  614. /* Use link status change interrupt */
  615. xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
  616. }
  617. static void xm_phy_init(struct skge_port *skge)
  618. {
  619. struct skge_hw *hw = skge->hw;
  620. int port = skge->port;
  621. u16 ctrl = 0;
  622. if (skge->autoneg == AUTONEG_ENABLE) {
  623. if (skge->advertising & ADVERTISED_1000baseT_Half)
  624. ctrl |= PHY_X_AN_HD;
  625. if (skge->advertising & ADVERTISED_1000baseT_Full)
  626. ctrl |= PHY_X_AN_FD;
  627. ctrl |= fiber_pause_map[skge->flow_control];
  628. xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
  629. /* Restart Auto-negotiation */
  630. ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
  631. } else {
  632. /* Set DuplexMode in Config register */
  633. if (skge->duplex == DUPLEX_FULL)
  634. ctrl |= PHY_CT_DUP_MD;
  635. /*
  636. * Do NOT enable Auto-negotiation here. This would hold
  637. * the link down because no IDLEs are transmitted
  638. */
  639. }
  640. xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
  641. /* Poll PHY for status changes */
  642. skge->use_xm_link_timer = 1;
  643. }
  644. static int xm_check_link(struct net_device *dev)
  645. {
  646. struct skge_port *skge = netdev_priv(dev);
  647. struct skge_hw *hw = skge->hw;
  648. int port = skge->port;
  649. u16 status;
  650. /* read twice because of latch */
  651. xm_phy_read(hw, port, PHY_XMAC_STAT);
  652. status = xm_phy_read(hw, port, PHY_XMAC_STAT);
  653. if ((status & PHY_ST_LSYNC) == 0) {
  654. xm_link_down(hw, port);
  655. return 0;
  656. }
  657. if (skge->autoneg == AUTONEG_ENABLE) {
  658. u16 lpa, res;
  659. if (!(status & PHY_ST_AN_OVER))
  660. return 0;
  661. lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
  662. if (lpa & PHY_B_AN_RF) {
  663. DBG(PFX "%s: remote fault\n",
  664. dev->name);
  665. return 0;
  666. }
  667. res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
  668. /* Check Duplex mismatch */
  669. switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
  670. case PHY_X_RS_FD:
  671. skge->duplex = DUPLEX_FULL;
  672. break;
  673. case PHY_X_RS_HD:
  674. skge->duplex = DUPLEX_HALF;
  675. break;
  676. default:
  677. DBG(PFX "%s: duplex mismatch\n",
  678. dev->name);
  679. return 0;
  680. }
  681. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  682. if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
  683. skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
  684. (lpa & PHY_X_P_SYM_MD))
  685. skge->flow_status = FLOW_STAT_SYMMETRIC;
  686. else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
  687. (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
  688. /* Enable PAUSE receive, disable PAUSE transmit */
  689. skge->flow_status = FLOW_STAT_REM_SEND;
  690. else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
  691. (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
  692. /* Disable PAUSE receive, enable PAUSE transmit */
  693. skge->flow_status = FLOW_STAT_LOC_SEND;
  694. else
  695. skge->flow_status = FLOW_STAT_NONE;
  696. skge->speed = SPEED_1000;
  697. }
  698. if (!netdev_link_ok(dev))
  699. genesis_link_up(skge);
  700. return 1;
  701. }
  702. /* Poll to check for link coming up.
  703. *
  704. * Since internal PHY is wired to a level triggered pin, can't
  705. * get an interrupt when carrier is detected, need to poll for
  706. * link coming up.
  707. */
  708. static void xm_link_timer(struct skge_port *skge)
  709. {
  710. struct net_device *dev = skge->netdev;
  711. struct skge_hw *hw = skge->hw;
  712. int port = skge->port;
  713. int i;
  714. /*
  715. * Verify that the link by checking GPIO register three times.
  716. * This pin has the signal from the link_sync pin connected to it.
  717. */
  718. for (i = 0; i < 3; i++) {
  719. if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
  720. return;
  721. }
  722. /* Re-enable interrupt to detect link down */
  723. if (xm_check_link(dev)) {
  724. u16 msk = xm_read16(hw, port, XM_IMSK);
  725. msk &= ~XM_IS_INP_ASS;
  726. xm_write16(hw, port, XM_IMSK, msk);
  727. xm_read16(hw, port, XM_ISRC);
  728. }
  729. }
  730. static void genesis_mac_init(struct skge_hw *hw, int port)
  731. {
  732. struct net_device *dev = hw->dev[port];
  733. struct skge_port *skge = netdev_priv(dev);
  734. int i;
  735. u32 r;
  736. const u8 zero[6] = { 0 };
  737. for (i = 0; i < 10; i++) {
  738. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
  739. MFF_SET_MAC_RST);
  740. if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
  741. goto reset_ok;
  742. udelay(1);
  743. }
  744. DBG(PFX "%s: genesis reset failed\n", dev->name);
  745. reset_ok:
  746. /* Unreset the XMAC. */
  747. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
  748. /*
  749. * Perform additional initialization for external PHYs,
  750. * namely for the 1000baseTX cards that use the XMAC's
  751. * GMII mode.
  752. */
  753. if (hw->phy_type != SK_PHY_XMAC) {
  754. /* Take external Phy out of reset */
  755. r = skge_read32(hw, B2_GP_IO);
  756. if (port == 0)
  757. r |= GP_DIR_0|GP_IO_0;
  758. else
  759. r |= GP_DIR_2|GP_IO_2;
  760. skge_write32(hw, B2_GP_IO, r);
  761. /* Enable GMII interface */
  762. xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
  763. }
  764. switch(hw->phy_type) {
  765. case SK_PHY_XMAC:
  766. xm_phy_init(skge);
  767. break;
  768. case SK_PHY_BCOM:
  769. bcom_phy_init(skge);
  770. bcom_check_link(hw, port);
  771. }
  772. /* Set Station Address */
  773. xm_outaddr(hw, port, XM_SA, dev->ll_addr);
  774. /* We don't use match addresses so clear */
  775. for (i = 1; i < 16; i++)
  776. xm_outaddr(hw, port, XM_EXM(i), zero);
  777. /* Clear MIB counters */
  778. xm_write16(hw, port, XM_STAT_CMD,
  779. XM_SC_CLR_RXC | XM_SC_CLR_TXC);
  780. /* Clear two times according to Errata #3 */
  781. xm_write16(hw, port, XM_STAT_CMD,
  782. XM_SC_CLR_RXC | XM_SC_CLR_TXC);
  783. /* configure Rx High Water Mark (XM_RX_HI_WM) */
  784. xm_write16(hw, port, XM_RX_HI_WM, 1450);
  785. /* We don't need the FCS appended to the packet. */
  786. r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
  787. if (skge->duplex == DUPLEX_HALF) {
  788. /*
  789. * If in manual half duplex mode the other side might be in
  790. * full duplex mode, so ignore if a carrier extension is not seen
  791. * on frames received
  792. */
  793. r |= XM_RX_DIS_CEXT;
  794. }
  795. xm_write16(hw, port, XM_RX_CMD, r);
  796. /* We want short frames padded to 60 bytes. */
  797. xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
  798. xm_write16(hw, port, XM_TX_THR, 512);
  799. /*
  800. * Enable the reception of all error frames. This is is
  801. * a necessary evil due to the design of the XMAC. The
  802. * XMAC's receive FIFO is only 8K in size, however jumbo
  803. * frames can be up to 9000 bytes in length. When bad
  804. * frame filtering is enabled, the XMAC's RX FIFO operates
  805. * in 'store and forward' mode. For this to work, the
  806. * entire frame has to fit into the FIFO, but that means
  807. * that jumbo frames larger than 8192 bytes will be
  808. * truncated. Disabling all bad frame filtering causes
  809. * the RX FIFO to operate in streaming mode, in which
  810. * case the XMAC will start transferring frames out of the
  811. * RX FIFO as soon as the FIFO threshold is reached.
  812. */
  813. xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
  814. /*
  815. * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
  816. * - Enable all bits excepting 'Octets Rx OK Low CntOv'
  817. * and 'Octets Rx OK Hi Cnt Ov'.
  818. */
  819. xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
  820. /*
  821. * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
  822. * - Enable all bits excepting 'Octets Tx OK Low CntOv'
  823. * and 'Octets Tx OK Hi Cnt Ov'.
  824. */
  825. xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
  826. /* Configure MAC arbiter */
  827. skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
  828. /* configure timeout values */
  829. skge_write8(hw, B3_MA_TOINI_RX1, 72);
  830. skge_write8(hw, B3_MA_TOINI_RX2, 72);
  831. skge_write8(hw, B3_MA_TOINI_TX1, 72);
  832. skge_write8(hw, B3_MA_TOINI_TX2, 72);
  833. skge_write8(hw, B3_MA_RCINI_RX1, 0);
  834. skge_write8(hw, B3_MA_RCINI_RX2, 0);
  835. skge_write8(hw, B3_MA_RCINI_TX1, 0);
  836. skge_write8(hw, B3_MA_RCINI_TX2, 0);
  837. /* Configure Rx MAC FIFO */
  838. skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
  839. skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
  840. skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
  841. /* Configure Tx MAC FIFO */
  842. skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
  843. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
  844. skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
  845. /* enable timeout timers */
  846. skge_write16(hw, B3_PA_CTRL,
  847. (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
  848. }
  849. static void genesis_stop(struct skge_port *skge)
  850. {
  851. struct skge_hw *hw = skge->hw;
  852. int port = skge->port;
  853. unsigned retries = 1000;
  854. u16 cmd;
  855. /* Disable Tx and Rx */
  856. cmd = xm_read16(hw, port, XM_MMU_CMD);
  857. cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
  858. xm_write16(hw, port, XM_MMU_CMD, cmd);
  859. genesis_reset(hw, port);
  860. /* Clear Tx packet arbiter timeout IRQ */
  861. skge_write16(hw, B3_PA_CTRL,
  862. port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
  863. /* Reset the MAC */
  864. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
  865. do {
  866. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
  867. if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
  868. break;
  869. } while (--retries > 0);
  870. /* For external PHYs there must be special handling */
  871. if (hw->phy_type != SK_PHY_XMAC) {
  872. u32 reg = skge_read32(hw, B2_GP_IO);
  873. if (port == 0) {
  874. reg |= GP_DIR_0;
  875. reg &= ~GP_IO_0;
  876. } else {
  877. reg |= GP_DIR_2;
  878. reg &= ~GP_IO_2;
  879. }
  880. skge_write32(hw, B2_GP_IO, reg);
  881. skge_read32(hw, B2_GP_IO);
  882. }
  883. xm_write16(hw, port, XM_MMU_CMD,
  884. xm_read16(hw, port, XM_MMU_CMD)
  885. & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
  886. xm_read16(hw, port, XM_MMU_CMD);
  887. }
  888. static void genesis_link_up(struct skge_port *skge)
  889. {
  890. struct skge_hw *hw = skge->hw;
  891. int port = skge->port;
  892. u16 cmd, msk;
  893. u32 mode;
  894. cmd = xm_read16(hw, port, XM_MMU_CMD);
  895. /*
  896. * enabling pause frame reception is required for 1000BT
  897. * because the XMAC is not reset if the link is going down
  898. */
  899. if (skge->flow_status == FLOW_STAT_NONE ||
  900. skge->flow_status == FLOW_STAT_LOC_SEND)
  901. /* Disable Pause Frame Reception */
  902. cmd |= XM_MMU_IGN_PF;
  903. else
  904. /* Enable Pause Frame Reception */
  905. cmd &= ~XM_MMU_IGN_PF;
  906. xm_write16(hw, port, XM_MMU_CMD, cmd);
  907. mode = xm_read32(hw, port, XM_MODE);
  908. if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
  909. skge->flow_status == FLOW_STAT_LOC_SEND) {
  910. /*
  911. * Configure Pause Frame Generation
  912. * Use internal and external Pause Frame Generation.
  913. * Sending pause frames is edge triggered.
  914. * Send a Pause frame with the maximum pause time if
  915. * internal oder external FIFO full condition occurs.
  916. * Send a zero pause time frame to re-start transmission.
  917. */
  918. /* XM_PAUSE_DA = '010000C28001' (default) */
  919. /* XM_MAC_PTIME = 0xffff (maximum) */
  920. /* remember this value is defined in big endian (!) */
  921. xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
  922. mode |= XM_PAUSE_MODE;
  923. skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
  924. } else {
  925. /*
  926. * disable pause frame generation is required for 1000BT
  927. * because the XMAC is not reset if the link is going down
  928. */
  929. /* Disable Pause Mode in Mode Register */
  930. mode &= ~XM_PAUSE_MODE;
  931. skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
  932. }
  933. xm_write32(hw, port, XM_MODE, mode);
  934. /* Turn on detection of Tx underrun */
  935. msk = xm_read16(hw, port, XM_IMSK);
  936. msk &= ~XM_IS_TXF_UR;
  937. xm_write16(hw, port, XM_IMSK, msk);
  938. xm_read16(hw, port, XM_ISRC);
  939. /* get MMU Command Reg. */
  940. cmd = xm_read16(hw, port, XM_MMU_CMD);
  941. if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
  942. cmd |= XM_MMU_GMII_FD;
  943. /*
  944. * Workaround BCOM Errata (#10523) for all BCom Phys
  945. * Enable Power Management after link up
  946. */
  947. if (hw->phy_type == SK_PHY_BCOM) {
  948. xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
  949. xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
  950. & ~PHY_B_AC_DIS_PM);
  951. xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
  952. }
  953. /* enable Rx/Tx */
  954. xm_write16(hw, port, XM_MMU_CMD,
  955. cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
  956. skge_link_up(skge);
  957. }
  958. static inline void bcom_phy_intr(struct skge_port *skge)
  959. {
  960. struct skge_hw *hw = skge->hw;
  961. int port = skge->port;
  962. u16 isrc;
  963. isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
  964. DBGIO(PFX "%s: phy interrupt status 0x%x\n",
  965. skge->netdev->name, isrc);
  966. if (isrc & PHY_B_IS_PSE)
  967. DBG(PFX "%s: uncorrectable pair swap error\n",
  968. hw->dev[port]->name);
  969. /* Workaround BCom Errata:
  970. * enable and disable loopback mode if "NO HCD" occurs.
  971. */
  972. if (isrc & PHY_B_IS_NO_HDCL) {
  973. u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
  974. xm_phy_write(hw, port, PHY_BCOM_CTRL,
  975. ctrl | PHY_CT_LOOP);
  976. xm_phy_write(hw, port, PHY_BCOM_CTRL,
  977. ctrl & ~PHY_CT_LOOP);
  978. }
  979. if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
  980. bcom_check_link(hw, port);
  981. }
  982. static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
  983. {
  984. int i;
  985. gma_write16(hw, port, GM_SMI_DATA, val);
  986. gma_write16(hw, port, GM_SMI_CTRL,
  987. GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
  988. for (i = 0; i < PHY_RETRIES; i++) {
  989. udelay(1);
  990. if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
  991. return 0;
  992. }
  993. DBG(PFX "%s: phy write timeout port %x reg %x val %x\n",
  994. hw->dev[port]->name,
  995. port, reg, val);
  996. return -EIO;
  997. }
  998. static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
  999. {
  1000. int i;
  1001. gma_write16(hw, port, GM_SMI_CTRL,
  1002. GM_SMI_CT_PHY_AD(hw->phy_addr)
  1003. | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
  1004. for (i = 0; i < PHY_RETRIES; i++) {
  1005. udelay(1);
  1006. if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
  1007. goto ready;
  1008. }
  1009. return -ETIMEDOUT;
  1010. ready:
  1011. *val = gma_read16(hw, port, GM_SMI_DATA);
  1012. return 0;
  1013. }
  1014. static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
  1015. {
  1016. u16 v = 0;
  1017. if (__gm_phy_read(hw, port, reg, &v))
  1018. DBG(PFX "%s: phy read timeout port %x reg %x val %x\n",
  1019. hw->dev[port]->name,
  1020. port, reg, v);
  1021. return v;
  1022. }
  1023. /* Marvell Phy Initialization */
  1024. static void yukon_init(struct skge_hw *hw, int port)
  1025. {
  1026. struct skge_port *skge = netdev_priv(hw->dev[port]);
  1027. u16 ctrl, ct1000, adv;
  1028. if (skge->autoneg == AUTONEG_ENABLE) {
  1029. u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
  1030. ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
  1031. PHY_M_EC_MAC_S_MSK);
  1032. ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
  1033. ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
  1034. gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
  1035. }
  1036. ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
  1037. if (skge->autoneg == AUTONEG_DISABLE)
  1038. ctrl &= ~PHY_CT_ANE;
  1039. ctrl |= PHY_CT_RESET;
  1040. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1041. ctrl = 0;
  1042. ct1000 = 0;
  1043. adv = PHY_AN_CSMA;
  1044. if (skge->autoneg == AUTONEG_ENABLE) {
  1045. if (hw->copper) {
  1046. if (skge->advertising & ADVERTISED_1000baseT_Full)
  1047. ct1000 |= PHY_M_1000C_AFD;
  1048. if (skge->advertising & ADVERTISED_1000baseT_Half)
  1049. ct1000 |= PHY_M_1000C_AHD;
  1050. if (skge->advertising & ADVERTISED_100baseT_Full)
  1051. adv |= PHY_M_AN_100_FD;
  1052. if (skge->advertising & ADVERTISED_100baseT_Half)
  1053. adv |= PHY_M_AN_100_HD;
  1054. if (skge->advertising & ADVERTISED_10baseT_Full)
  1055. adv |= PHY_M_AN_10_FD;
  1056. if (skge->advertising & ADVERTISED_10baseT_Half)
  1057. adv |= PHY_M_AN_10_HD;
  1058. /* Set Flow-control capabilities */
  1059. adv |= phy_pause_map[skge->flow_control];
  1060. } else {
  1061. if (skge->advertising & ADVERTISED_1000baseT_Full)
  1062. adv |= PHY_M_AN_1000X_AFD;
  1063. if (skge->advertising & ADVERTISED_1000baseT_Half)
  1064. adv |= PHY_M_AN_1000X_AHD;
  1065. adv |= fiber_pause_map[skge->flow_control];
  1066. }
  1067. /* Restart Auto-negotiation */
  1068. ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
  1069. } else {
  1070. /* forced speed/duplex settings */
  1071. ct1000 = PHY_M_1000C_MSE;
  1072. if (skge->duplex == DUPLEX_FULL)
  1073. ctrl |= PHY_CT_DUP_MD;
  1074. switch (skge->speed) {
  1075. case SPEED_1000:
  1076. ctrl |= PHY_CT_SP1000;
  1077. break;
  1078. case SPEED_100:
  1079. ctrl |= PHY_CT_SP100;
  1080. break;
  1081. }
  1082. ctrl |= PHY_CT_RESET;
  1083. }
  1084. gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
  1085. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
  1086. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1087. /* Enable phy interrupt on autonegotiation complete (or link up) */
  1088. if (skge->autoneg == AUTONEG_ENABLE)
  1089. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
  1090. else
  1091. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
  1092. }
  1093. static void yukon_reset(struct skge_hw *hw, int port)
  1094. {
  1095. gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
  1096. gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
  1097. gma_write16(hw, port, GM_MC_ADDR_H2, 0);
  1098. gma_write16(hw, port, GM_MC_ADDR_H3, 0);
  1099. gma_write16(hw, port, GM_MC_ADDR_H4, 0);
  1100. gma_write16(hw, port, GM_RX_CTRL,
  1101. gma_read16(hw, port, GM_RX_CTRL)
  1102. | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  1103. }
  1104. /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
  1105. static int is_yukon_lite_a0(struct skge_hw *hw)
  1106. {
  1107. u32 reg;
  1108. int ret;
  1109. if (hw->chip_id != CHIP_ID_YUKON)
  1110. return 0;
  1111. reg = skge_read32(hw, B2_FAR);
  1112. skge_write8(hw, B2_FAR + 3, 0xff);
  1113. ret = (skge_read8(hw, B2_FAR + 3) != 0);
  1114. skge_write32(hw, B2_FAR, reg);
  1115. return ret;
  1116. }
  1117. static void yukon_mac_init(struct skge_hw *hw, int port)
  1118. {
  1119. struct skge_port *skge = netdev_priv(hw->dev[port]);
  1120. int i;
  1121. u32 reg;
  1122. const u8 *addr = hw->dev[port]->ll_addr;
  1123. /* WA code for COMA mode -- set PHY reset */
  1124. if (hw->chip_id == CHIP_ID_YUKON_LITE &&
  1125. hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
  1126. reg = skge_read32(hw, B2_GP_IO);
  1127. reg |= GP_DIR_9 | GP_IO_9;
  1128. skge_write32(hw, B2_GP_IO, reg);
  1129. }
  1130. /* hard reset */
  1131. skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  1132. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
  1133. /* WA code for COMA mode -- clear PHY reset */
  1134. if (hw->chip_id == CHIP_ID_YUKON_LITE &&
  1135. hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
  1136. reg = skge_read32(hw, B2_GP_IO);
  1137. reg |= GP_DIR_9;
  1138. reg &= ~GP_IO_9;
  1139. skge_write32(hw, B2_GP_IO, reg);
  1140. }
  1141. /* Set hardware config mode */
  1142. reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
  1143. GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
  1144. reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
  1145. /* Clear GMC reset */
  1146. skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
  1147. skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
  1148. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
  1149. if (skge->autoneg == AUTONEG_DISABLE) {
  1150. reg = GM_GPCR_AU_ALL_DIS;
  1151. gma_write16(hw, port, GM_GP_CTRL,
  1152. gma_read16(hw, port, GM_GP_CTRL) | reg);
  1153. switch (skge->speed) {
  1154. case SPEED_1000:
  1155. reg &= ~GM_GPCR_SPEED_100;
  1156. reg |= GM_GPCR_SPEED_1000;
  1157. break;
  1158. case SPEED_100:
  1159. reg &= ~GM_GPCR_SPEED_1000;
  1160. reg |= GM_GPCR_SPEED_100;
  1161. break;
  1162. case SPEED_10:
  1163. reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
  1164. break;
  1165. }
  1166. if (skge->duplex == DUPLEX_FULL)
  1167. reg |= GM_GPCR_DUP_FULL;
  1168. } else
  1169. reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
  1170. switch (skge->flow_control) {
  1171. case FLOW_MODE_NONE:
  1172. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1173. reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
  1174. break;
  1175. case FLOW_MODE_LOC_SEND:
  1176. /* disable Rx flow-control */
  1177. reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
  1178. break;
  1179. case FLOW_MODE_SYMMETRIC:
  1180. case FLOW_MODE_SYM_OR_REM:
  1181. /* enable Tx & Rx flow-control */
  1182. break;
  1183. }
  1184. gma_write16(hw, port, GM_GP_CTRL, reg);
  1185. skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
  1186. yukon_init(hw, port);
  1187. /* MIB clear */
  1188. reg = gma_read16(hw, port, GM_PHY_ADDR);
  1189. gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
  1190. for (i = 0; i < GM_MIB_CNT_SIZE; i++)
  1191. gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
  1192. gma_write16(hw, port, GM_PHY_ADDR, reg);
  1193. /* transmit control */
  1194. gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
  1195. /* receive control reg: unicast + multicast + no FCS */
  1196. gma_write16(hw, port, GM_RX_CTRL,
  1197. GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
  1198. /* transmit flow control */
  1199. gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
  1200. /* transmit parameter */
  1201. gma_write16(hw, port, GM_TX_PARAM,
  1202. TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
  1203. TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
  1204. TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
  1205. /* configure the Serial Mode Register */
  1206. reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
  1207. | GM_SMOD_VLAN_ENA
  1208. | IPG_DATA_VAL(IPG_DATA_DEF);
  1209. gma_write16(hw, port, GM_SERIAL_MODE, reg);
  1210. /* physical address: used for pause frames */
  1211. gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
  1212. /* virtual address for data */
  1213. gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
  1214. /* enable interrupt mask for counter overflows */
  1215. gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
  1216. gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
  1217. gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
  1218. /* Initialize Mac Fifo */
  1219. /* Configure Rx MAC FIFO */
  1220. skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
  1221. reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
  1222. /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
  1223. if (is_yukon_lite_a0(hw))
  1224. reg &= ~GMF_RX_F_FL_ON;
  1225. skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
  1226. skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
  1227. /*
  1228. * because Pause Packet Truncation in GMAC is not working
  1229. * we have to increase the Flush Threshold to 64 bytes
  1230. * in order to flush pause packets in Rx FIFO on Yukon-1
  1231. */
  1232. skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
  1233. /* Configure Tx MAC FIFO */
  1234. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
  1235. skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
  1236. }
  1237. /* Go into power down mode */
  1238. static void yukon_suspend(struct skge_hw *hw, int port)
  1239. {
  1240. u16 ctrl;
  1241. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  1242. ctrl |= PHY_M_PC_POL_R_DIS;
  1243. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  1244. ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
  1245. ctrl |= PHY_CT_RESET;
  1246. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1247. /* switch IEEE compatible power down mode on */
  1248. ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
  1249. ctrl |= PHY_CT_PDOWN;
  1250. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1251. }
  1252. static void yukon_stop(struct skge_port *skge)
  1253. {
  1254. struct skge_hw *hw = skge->hw;
  1255. int port = skge->port;
  1256. skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
  1257. yukon_reset(hw, port);
  1258. gma_write16(hw, port, GM_GP_CTRL,
  1259. gma_read16(hw, port, GM_GP_CTRL)
  1260. & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
  1261. gma_read16(hw, port, GM_GP_CTRL);
  1262. yukon_suspend(hw, port);
  1263. /* set GPHY Control reset */
  1264. skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  1265. skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
  1266. }
  1267. static u16 yukon_speed(const struct skge_hw *hw __unused, u16 aux)
  1268. {
  1269. switch (aux & PHY_M_PS_SPEED_MSK) {
  1270. case PHY_M_PS_SPEED_1000:
  1271. return SPEED_1000;
  1272. case PHY_M_PS_SPEED_100:
  1273. return SPEED_100;
  1274. default:
  1275. return SPEED_10;
  1276. }
  1277. }
  1278. static void yukon_link_up(struct skge_port *skge)
  1279. {
  1280. struct skge_hw *hw = skge->hw;
  1281. int port = skge->port;
  1282. u16 reg;
  1283. /* Enable Transmit FIFO Underrun */
  1284. skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
  1285. reg = gma_read16(hw, port, GM_GP_CTRL);
  1286. if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
  1287. reg |= GM_GPCR_DUP_FULL;
  1288. /* enable Rx/Tx */
  1289. reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
  1290. gma_write16(hw, port, GM_GP_CTRL, reg);
  1291. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
  1292. skge_link_up(skge);
  1293. }
  1294. static void yukon_link_down(struct skge_port *skge)
  1295. {
  1296. struct skge_hw *hw = skge->hw;
  1297. int port = skge->port;
  1298. u16 ctrl;
  1299. ctrl = gma_read16(hw, port, GM_GP_CTRL);
  1300. ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  1301. gma_write16(hw, port, GM_GP_CTRL, ctrl);
  1302. if (skge->flow_status == FLOW_STAT_REM_SEND) {
  1303. ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
  1304. ctrl |= PHY_M_AN_ASP;
  1305. /* restore Asymmetric Pause bit */
  1306. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
  1307. }
  1308. skge_link_down(skge);
  1309. yukon_init(hw, port);
  1310. }
  1311. static void yukon_phy_intr(struct skge_port *skge)
  1312. {
  1313. struct skge_hw *hw = skge->hw;
  1314. int port = skge->port;
  1315. const char *reason = NULL;
  1316. u16 istatus, phystat;
  1317. istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
  1318. phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
  1319. DBGIO(PFX "%s: phy interrupt status 0x%x 0x%x\n",
  1320. skge->netdev->name, istatus, phystat);
  1321. if (istatus & PHY_M_IS_AN_COMPL) {
  1322. if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
  1323. & PHY_M_AN_RF) {
  1324. reason = "remote fault";
  1325. goto failed;
  1326. }
  1327. if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
  1328. reason = "master/slave fault";
  1329. goto failed;
  1330. }
  1331. if (!(phystat & PHY_M_PS_SPDUP_RES)) {
  1332. reason = "speed/duplex";
  1333. goto failed;
  1334. }
  1335. skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
  1336. ? DUPLEX_FULL : DUPLEX_HALF;
  1337. skge->speed = yukon_speed(hw, phystat);
  1338. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  1339. switch (phystat & PHY_M_PS_PAUSE_MSK) {
  1340. case PHY_M_PS_PAUSE_MSK:
  1341. skge->flow_status = FLOW_STAT_SYMMETRIC;
  1342. break;
  1343. case PHY_M_PS_RX_P_EN:
  1344. skge->flow_status = FLOW_STAT_REM_SEND;
  1345. break;
  1346. case PHY_M_PS_TX_P_EN:
  1347. skge->flow_status = FLOW_STAT_LOC_SEND;
  1348. break;
  1349. default:
  1350. skge->flow_status = FLOW_STAT_NONE;
  1351. }
  1352. if (skge->flow_status == FLOW_STAT_NONE ||
  1353. (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
  1354. skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1355. else
  1356. skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
  1357. yukon_link_up(skge);
  1358. return;
  1359. }
  1360. if (istatus & PHY_M_IS_LSP_CHANGE)
  1361. skge->speed = yukon_speed(hw, phystat);
  1362. if (istatus & PHY_M_IS_DUP_CHANGE)
  1363. skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
  1364. if (istatus & PHY_M_IS_LST_CHANGE) {
  1365. if (phystat & PHY_M_PS_LINK_UP)
  1366. yukon_link_up(skge);
  1367. else
  1368. yukon_link_down(skge);
  1369. }
  1370. return;
  1371. failed:
  1372. DBG(PFX "%s: autonegotiation failed (%s)\n",
  1373. skge->netdev->name, reason);
  1374. /* XXX restart autonegotiation? */
  1375. }
  1376. static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
  1377. {
  1378. u32 end;
  1379. start /= 8;
  1380. len /= 8;
  1381. end = start + len - 1;
  1382. skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
  1383. skge_write32(hw, RB_ADDR(q, RB_START), start);
  1384. skge_write32(hw, RB_ADDR(q, RB_WP), start);
  1385. skge_write32(hw, RB_ADDR(q, RB_RP), start);
  1386. skge_write32(hw, RB_ADDR(q, RB_END), end);
  1387. if (q == Q_R1 || q == Q_R2) {
  1388. /* Set thresholds on receive queue's */
  1389. skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
  1390. start + (2*len)/3);
  1391. skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
  1392. start + (len/3));
  1393. } else {
  1394. /* Enable store & forward on Tx queue's because
  1395. * Tx FIFO is only 4K on Genesis and 1K on Yukon
  1396. */
  1397. skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
  1398. }
  1399. skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
  1400. }
  1401. /* Setup Bus Memory Interface */
  1402. static void skge_qset(struct skge_port *skge, u16 q,
  1403. const struct skge_element *e)
  1404. {
  1405. struct skge_hw *hw = skge->hw;
  1406. u32 watermark = 0x600;
  1407. u64 base = skge->dma + (e->desc - skge->mem);
  1408. /* optimization to reduce window on 32bit/33mhz */
  1409. if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
  1410. watermark /= 2;
  1411. skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
  1412. skge_write32(hw, Q_ADDR(q, Q_F), watermark);
  1413. skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
  1414. skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
  1415. }
  1416. void skge_free(struct net_device *dev)
  1417. {
  1418. struct skge_port *skge = netdev_priv(dev);
  1419. free(skge->rx_ring.start);
  1420. skge->rx_ring.start = NULL;
  1421. free(skge->tx_ring.start);
  1422. skge->tx_ring.start = NULL;
  1423. free_dma(skge->mem, RING_SIZE);
  1424. skge->mem = NULL;
  1425. skge->dma = 0;
  1426. }
  1427. static int skge_up(struct net_device *dev)
  1428. {
  1429. struct skge_port *skge = netdev_priv(dev);
  1430. struct skge_hw *hw = skge->hw;
  1431. int port = skge->port;
  1432. u32 chunk, ram_addr;
  1433. int err;
  1434. DBG2(PFX "%s: enabling interface\n", dev->name);
  1435. skge->mem = malloc_dma(RING_SIZE, SKGE_RING_ALIGN);
  1436. skge->dma = virt_to_bus(skge->mem);
  1437. if (!skge->mem)
  1438. return -ENOMEM;
  1439. memset(skge->mem, 0, RING_SIZE);
  1440. assert(!(skge->dma & 7));
  1441. /* FIXME: find out whether 64 bit iPXE will be loaded > 4GB */
  1442. if ((u64)skge->dma >> 32 != ((u64) skge->dma + RING_SIZE) >> 32) {
  1443. DBG(PFX "pci_alloc_consistent region crosses 4G boundary\n");
  1444. err = -EINVAL;
  1445. goto err;
  1446. }
  1447. err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma, NUM_RX_DESC);
  1448. if (err)
  1449. goto err;
  1450. /* this call relies on e->iob and d->control to be 0
  1451. * This is assured by calling memset() on skge->mem and using zalloc()
  1452. * for the skge_element structures.
  1453. */
  1454. skge_rx_refill(dev);
  1455. err = skge_ring_alloc(&skge->tx_ring, skge->mem + RX_RING_SIZE,
  1456. skge->dma + RX_RING_SIZE, NUM_TX_DESC);
  1457. if (err)
  1458. goto err;
  1459. /* Initialize MAC */
  1460. if (hw->chip_id == CHIP_ID_GENESIS)
  1461. genesis_mac_init(hw, port);
  1462. else
  1463. yukon_mac_init(hw, port);
  1464. /* Configure RAMbuffers - equally between ports and tx/rx */
  1465. chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
  1466. ram_addr = hw->ram_offset + 2 * chunk * port;
  1467. skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
  1468. skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
  1469. assert(!(skge->tx_ring.to_use != skge->tx_ring.to_clean));
  1470. skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
  1471. skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
  1472. /* Start receiver BMU */
  1473. wmb();
  1474. skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
  1475. skge_led(skge, LED_MODE_ON);
  1476. hw->intr_mask |= portmask[port];
  1477. skge_write32(hw, B0_IMSK, hw->intr_mask);
  1478. return 0;
  1479. err:
  1480. skge_rx_clean(skge);
  1481. skge_free(dev);
  1482. return err;
  1483. }
  1484. /* stop receiver */
  1485. static void skge_rx_stop(struct skge_hw *hw, int port)
  1486. {
  1487. skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
  1488. skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
  1489. RB_RST_SET|RB_DIS_OP_MD);
  1490. skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
  1491. }
  1492. static void skge_down(struct net_device *dev)
  1493. {
  1494. struct skge_port *skge = netdev_priv(dev);
  1495. struct skge_hw *hw = skge->hw;
  1496. int port = skge->port;
  1497. if (skge->mem == NULL)
  1498. return;
  1499. DBG2(PFX "%s: disabling interface\n", dev->name);
  1500. if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
  1501. skge->use_xm_link_timer = 0;
  1502. netdev_link_down(dev);
  1503. hw->intr_mask &= ~portmask[port];
  1504. skge_write32(hw, B0_IMSK, hw->intr_mask);
  1505. skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
  1506. if (hw->chip_id == CHIP_ID_GENESIS)
  1507. genesis_stop(skge);
  1508. else
  1509. yukon_stop(skge);
  1510. /* Stop transmitter */
  1511. skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
  1512. skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
  1513. RB_RST_SET|RB_DIS_OP_MD);
  1514. /* Disable Force Sync bit and Enable Alloc bit */
  1515. skge_write8(hw, SK_REG(port, TXA_CTRL),
  1516. TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
  1517. /* Stop Interval Timer and Limit Counter of Tx Arbiter */
  1518. skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
  1519. skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
  1520. /* Reset PCI FIFO */
  1521. skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
  1522. skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
  1523. /* Reset the RAM Buffer async Tx queue */
  1524. skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
  1525. skge_rx_stop(hw, port);
  1526. if (hw->chip_id == CHIP_ID_GENESIS) {
  1527. skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
  1528. skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
  1529. } else {
  1530. skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
  1531. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  1532. }
  1533. skge_led(skge, LED_MODE_OFF);
  1534. skge_tx_clean(dev);
  1535. skge_rx_clean(skge);
  1536. skge_free(dev);
  1537. return;
  1538. }
  1539. static inline int skge_tx_avail(const struct skge_ring *ring)
  1540. {
  1541. mb();
  1542. return ((ring->to_clean > ring->to_use) ? 0 : NUM_TX_DESC)
  1543. + (ring->to_clean - ring->to_use) - 1;
  1544. }
  1545. static int skge_xmit_frame(struct net_device *dev, struct io_buffer *iob)
  1546. {
  1547. struct skge_port *skge = netdev_priv(dev);
  1548. struct skge_hw *hw = skge->hw;
  1549. struct skge_element *e;
  1550. struct skge_tx_desc *td;
  1551. u32 control, len;
  1552. u64 map;
  1553. if (skge_tx_avail(&skge->tx_ring) < 1)
  1554. return -EBUSY;
  1555. e = skge->tx_ring.to_use;
  1556. td = e->desc;
  1557. assert(!(td->control & BMU_OWN));
  1558. e->iob = iob;
  1559. len = iob_len(iob);
  1560. map = virt_to_bus(iob->data);
  1561. td->dma_lo = map;
  1562. td->dma_hi = map >> 32;
  1563. control = BMU_CHECK;
  1564. control |= BMU_EOF| BMU_IRQ_EOF;
  1565. /* Make sure all the descriptors written */
  1566. wmb();
  1567. td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
  1568. wmb();
  1569. skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
  1570. DBGIO(PFX "%s: tx queued, slot %td, len %d\n",
  1571. dev->name, e - skge->tx_ring.start, (unsigned int)len);
  1572. skge->tx_ring.to_use = e->next;
  1573. wmb();
  1574. if (skge_tx_avail(&skge->tx_ring) <= 1) {
  1575. DBG(PFX "%s: transmit queue full\n", dev->name);
  1576. }
  1577. return 0;
  1578. }
  1579. /* Free all buffers in transmit ring */
  1580. static void skge_tx_clean(struct net_device *dev)
  1581. {
  1582. struct skge_port *skge = netdev_priv(dev);
  1583. struct skge_element *e;
  1584. for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
  1585. struct skge_tx_desc *td = e->desc;
  1586. td->control = 0;
  1587. }
  1588. skge->tx_ring.to_clean = e;
  1589. }
  1590. static inline u16 phy_length(const struct skge_hw *hw, u32 status)
  1591. {
  1592. if (hw->chip_id == CHIP_ID_GENESIS)
  1593. return status >> XMR_FS_LEN_SHIFT;
  1594. else
  1595. return status >> GMR_FS_LEN_SHIFT;
  1596. }
  1597. static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
  1598. {
  1599. if (hw->chip_id == CHIP_ID_GENESIS)
  1600. return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
  1601. else
  1602. return (status & GMR_FS_ANY_ERR) ||
  1603. (status & GMR_FS_RX_OK) == 0;
  1604. }
  1605. /* Free all buffers in Tx ring which are no longer owned by device */
  1606. static void skge_tx_done(struct net_device *dev)
  1607. {
  1608. struct skge_port *skge = netdev_priv(dev);
  1609. struct skge_ring *ring = &skge->tx_ring;
  1610. struct skge_element *e;
  1611. skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
  1612. for (e = ring->to_clean; e != ring->to_use; e = e->next) {
  1613. u32 control = ((const struct skge_tx_desc *) e->desc)->control;
  1614. if (control & BMU_OWN)
  1615. break;
  1616. netdev_tx_complete(dev, e->iob);
  1617. }
  1618. skge->tx_ring.to_clean = e;
  1619. /* Can run lockless until we need to synchronize to restart queue. */
  1620. mb();
  1621. }
  1622. static void skge_rx_refill(struct net_device *dev)
  1623. {
  1624. struct skge_port *skge = netdev_priv(dev);
  1625. struct skge_ring *ring = &skge->rx_ring;
  1626. struct skge_element *e;
  1627. struct io_buffer *iob;
  1628. struct skge_rx_desc *rd;
  1629. u32 control;
  1630. int i;
  1631. for (i = 0; i < NUM_RX_DESC; i++) {
  1632. e = ring->to_clean;
  1633. rd = e->desc;
  1634. iob = e->iob;
  1635. control = rd->control;
  1636. /* nothing to do here */
  1637. if (iob || (control & BMU_OWN))
  1638. continue;
  1639. DBG2("refilling rx desc %zd: ", (ring->to_clean - ring->start));
  1640. iob = alloc_iob(RX_BUF_SIZE);
  1641. if (iob) {
  1642. skge_rx_setup(skge, e, iob, RX_BUF_SIZE);
  1643. } else {
  1644. DBG("descr %zd: alloc_iob() failed\n",
  1645. (ring->to_clean - ring->start));
  1646. /* We pass the descriptor to the NIC even if the
  1647. * allocation failed. The card will stop as soon as it
  1648. * encounters a descriptor with the OWN bit set to 0,
  1649. * thus never getting to the next descriptor that might
  1650. * contain a valid io_buffer. This would effectively
  1651. * stall the receive.
  1652. */
  1653. skge_rx_setup(skge, e, NULL, 0);
  1654. }
  1655. ring->to_clean = e->next;
  1656. }
  1657. }
  1658. static void skge_rx_done(struct net_device *dev)
  1659. {
  1660. struct skge_port *skge = netdev_priv(dev);
  1661. struct skge_ring *ring = &skge->rx_ring;
  1662. struct skge_rx_desc *rd;
  1663. struct skge_element *e;
  1664. struct io_buffer *iob;
  1665. u32 control;
  1666. u16 len;
  1667. int i;
  1668. e = ring->to_clean;
  1669. for (i = 0; i < NUM_RX_DESC; i++) {
  1670. iob = e->iob;
  1671. rd = e->desc;
  1672. rmb();
  1673. control = rd->control;
  1674. if ((control & BMU_OWN))
  1675. break;
  1676. if (!iob)
  1677. continue;
  1678. len = control & BMU_BBC;
  1679. /* catch RX errors */
  1680. if ((bad_phy_status(skge->hw, rd->status)) ||
  1681. (phy_length(skge->hw, rd->status) != len)) {
  1682. /* report receive errors */
  1683. DBG("rx error\n");
  1684. netdev_rx_err(dev, iob, -EIO);
  1685. } else {
  1686. DBG2("received packet, len %d\n", len);
  1687. iob_put(iob, len);
  1688. netdev_rx(dev, iob);
  1689. }
  1690. /* io_buffer passed to core, make sure we don't reuse it */
  1691. e->iob = NULL;
  1692. e = e->next;
  1693. }
  1694. skge_rx_refill(dev);
  1695. }
  1696. static void skge_poll(struct net_device *dev)
  1697. {
  1698. struct skge_port *skge = netdev_priv(dev);
  1699. struct skge_hw *hw = skge->hw;
  1700. u32 status;
  1701. /* reading this register ACKs interrupts */
  1702. status = skge_read32(hw, B0_SP_ISRC);
  1703. /* Link event? */
  1704. if (status & IS_EXT_REG) {
  1705. skge_phyirq(hw);
  1706. if (skge->use_xm_link_timer)
  1707. xm_link_timer(skge);
  1708. }
  1709. skge_tx_done(dev);
  1710. skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
  1711. skge_rx_done(dev);
  1712. /* restart receiver */
  1713. wmb();
  1714. skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
  1715. skge_read32(hw, B0_IMSK);
  1716. return;
  1717. }
  1718. static void skge_phyirq(struct skge_hw *hw)
  1719. {
  1720. int port;
  1721. for (port = 0; port < hw->ports; port++) {
  1722. struct net_device *dev = hw->dev[port];
  1723. struct skge_port *skge = netdev_priv(dev);
  1724. if (hw->chip_id != CHIP_ID_GENESIS)
  1725. yukon_phy_intr(skge);
  1726. else if (hw->phy_type == SK_PHY_BCOM)
  1727. bcom_phy_intr(skge);
  1728. }
  1729. hw->intr_mask |= IS_EXT_REG;
  1730. skge_write32(hw, B0_IMSK, hw->intr_mask);
  1731. skge_read32(hw, B0_IMSK);
  1732. }
  1733. static const struct {
  1734. u8 id;
  1735. const char *name;
  1736. } skge_chips[] = {
  1737. { CHIP_ID_GENESIS, "Genesis" },
  1738. { CHIP_ID_YUKON, "Yukon" },
  1739. { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
  1740. { CHIP_ID_YUKON_LP, "Yukon-LP"},
  1741. };
  1742. static const char *skge_board_name(const struct skge_hw *hw)
  1743. {
  1744. unsigned int i;
  1745. static char buf[16];
  1746. for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
  1747. if (skge_chips[i].id == hw->chip_id)
  1748. return skge_chips[i].name;
  1749. snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
  1750. return buf;
  1751. }
  1752. /*
  1753. * Setup the board data structure, but don't bring up
  1754. * the port(s)
  1755. */
  1756. static int skge_reset(struct skge_hw *hw)
  1757. {
  1758. u32 reg;
  1759. u16 ctst, pci_status;
  1760. u8 t8, mac_cfg, pmd_type;
  1761. int i;
  1762. ctst = skge_read16(hw, B0_CTST);
  1763. /* do a SW reset */
  1764. skge_write8(hw, B0_CTST, CS_RST_SET);
  1765. skge_write8(hw, B0_CTST, CS_RST_CLR);
  1766. /* clear PCI errors, if any */
  1767. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1768. skge_write8(hw, B2_TST_CTRL2, 0);
  1769. pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
  1770. pci_write_config_word(hw->pdev, PCI_STATUS,
  1771. pci_status | PCI_STATUS_ERROR_BITS);
  1772. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1773. skge_write8(hw, B0_CTST, CS_MRST_CLR);
  1774. /* restore CLK_RUN bits (for Yukon-Lite) */
  1775. skge_write16(hw, B0_CTST,
  1776. ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
  1777. hw->chip_id = skge_read8(hw, B2_CHIP_ID);
  1778. hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
  1779. pmd_type = skge_read8(hw, B2_PMD_TYP);
  1780. hw->copper = (pmd_type == 'T' || pmd_type == '1');
  1781. switch (hw->chip_id) {
  1782. case CHIP_ID_GENESIS:
  1783. switch (hw->phy_type) {
  1784. case SK_PHY_XMAC:
  1785. hw->phy_addr = PHY_ADDR_XMAC;
  1786. break;
  1787. case SK_PHY_BCOM:
  1788. hw->phy_addr = PHY_ADDR_BCOM;
  1789. break;
  1790. default:
  1791. DBG(PFX "unsupported phy type 0x%x\n",
  1792. hw->phy_type);
  1793. return -EOPNOTSUPP;
  1794. }
  1795. break;
  1796. case CHIP_ID_YUKON:
  1797. case CHIP_ID_YUKON_LITE:
  1798. case CHIP_ID_YUKON_LP:
  1799. if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
  1800. hw->copper = 1;
  1801. hw->phy_addr = PHY_ADDR_MARV;
  1802. break;
  1803. default:
  1804. DBG(PFX "unsupported chip type 0x%x\n",
  1805. hw->chip_id);
  1806. return -EOPNOTSUPP;
  1807. }
  1808. mac_cfg = skge_read8(hw, B2_MAC_CFG);
  1809. hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
  1810. hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
  1811. /* read the adapters RAM size */
  1812. t8 = skge_read8(hw, B2_E_0);
  1813. if (hw->chip_id == CHIP_ID_GENESIS) {
  1814. if (t8 == 3) {
  1815. /* special case: 4 x 64k x 36, offset = 0x80000 */
  1816. hw->ram_size = 0x100000;
  1817. hw->ram_offset = 0x80000;
  1818. } else
  1819. hw->ram_size = t8 * 512;
  1820. }
  1821. else if (t8 == 0)
  1822. hw->ram_size = 0x20000;
  1823. else
  1824. hw->ram_size = t8 * 4096;
  1825. hw->intr_mask = IS_HW_ERR;
  1826. /* Use PHY IRQ for all but fiber based Genesis board */
  1827. if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
  1828. hw->intr_mask |= IS_EXT_REG;
  1829. if (hw->chip_id == CHIP_ID_GENESIS)
  1830. genesis_init(hw);
  1831. else {
  1832. /* switch power to VCC (WA for VAUX problem) */
  1833. skge_write8(hw, B0_POWER_CTRL,
  1834. PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
  1835. /* avoid boards with stuck Hardware error bits */
  1836. if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
  1837. (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
  1838. DBG(PFX "stuck hardware sensor bit\n");
  1839. hw->intr_mask &= ~IS_HW_ERR;
  1840. }
  1841. /* Clear PHY COMA */
  1842. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1843. pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
  1844. reg &= ~PCI_PHY_COMA;
  1845. pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
  1846. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1847. for (i = 0; i < hw->ports; i++) {
  1848. skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
  1849. skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
  1850. }
  1851. }
  1852. /* turn off hardware timer (unused) */
  1853. skge_write8(hw, B2_TI_CTRL, TIM_STOP);
  1854. skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
  1855. skge_write8(hw, B0_LED, LED_STAT_ON);
  1856. /* enable the Tx Arbiters */
  1857. for (i = 0; i < hw->ports; i++)
  1858. skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
  1859. /* Initialize ram interface */
  1860. skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
  1861. skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
  1862. skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
  1863. skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
  1864. skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
  1865. skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
  1866. skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
  1867. skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
  1868. skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
  1869. skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
  1870. skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
  1871. skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
  1872. skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
  1873. skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
  1874. /* Set interrupt moderation for Transmit only
  1875. * Receive interrupts avoided by NAPI
  1876. */
  1877. skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
  1878. skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
  1879. skge_write32(hw, B2_IRQM_CTRL, TIM_START);
  1880. skge_write32(hw, B0_IMSK, hw->intr_mask);
  1881. for (i = 0; i < hw->ports; i++) {
  1882. if (hw->chip_id == CHIP_ID_GENESIS)
  1883. genesis_reset(hw, i);
  1884. else
  1885. yukon_reset(hw, i);
  1886. }
  1887. return 0;
  1888. }
  1889. /* Initialize network device */
  1890. static struct net_device *skge_devinit(struct skge_hw *hw, int port,
  1891. int highmem __unused)
  1892. {
  1893. struct skge_port *skge;
  1894. struct net_device *dev = alloc_etherdev(sizeof(*skge));
  1895. if (!dev) {
  1896. DBG(PFX "etherdev alloc failed\n");
  1897. return NULL;
  1898. }
  1899. dev->dev = &hw->pdev->dev;
  1900. skge = netdev_priv(dev);
  1901. skge->netdev = dev;
  1902. skge->hw = hw;
  1903. /* Auto speed and flow control */
  1904. skge->autoneg = AUTONEG_ENABLE;
  1905. skge->flow_control = FLOW_MODE_SYM_OR_REM;
  1906. skge->duplex = -1;
  1907. skge->speed = -1;
  1908. skge->advertising = skge_supported_modes(hw);
  1909. hw->dev[port] = dev;
  1910. skge->port = port;
  1911. /* read the mac address */
  1912. memcpy(dev->hw_addr, (void *) (hw->regs + B2_MAC_1 + port*8), ETH_ALEN);
  1913. return dev;
  1914. }
  1915. static void skge_show_addr(struct net_device *dev)
  1916. {
  1917. DBG2(PFX "%s: addr %s\n",
  1918. dev->name, netdev_addr(dev));
  1919. }
  1920. static int skge_probe(struct pci_device *pdev)
  1921. {
  1922. struct net_device *dev, *dev1;
  1923. struct skge_hw *hw;
  1924. int err, using_dac = 0;
  1925. adjust_pci_device(pdev);
  1926. err = -ENOMEM;
  1927. hw = zalloc(sizeof(*hw));
  1928. if (!hw) {
  1929. DBG(PFX "cannot allocate hardware struct\n");
  1930. goto err_out_free_regions;
  1931. }
  1932. hw->pdev = pdev;
  1933. hw->regs = (unsigned long)ioremap(pci_bar_start(pdev, PCI_BASE_ADDRESS_0),
  1934. SKGE_REG_SIZE);
  1935. if (!hw->regs) {
  1936. DBG(PFX "cannot map device registers\n");
  1937. goto err_out_free_hw;
  1938. }
  1939. err = skge_reset(hw);
  1940. if (err)
  1941. goto err_out_iounmap;
  1942. DBG(PFX " addr 0x%llx irq %d chip %s rev %d\n",
  1943. (unsigned long long)pdev->ioaddr, pdev->irq,
  1944. skge_board_name(hw), hw->chip_rev);
  1945. dev = skge_devinit(hw, 0, using_dac);
  1946. if (!dev)
  1947. goto err_out_led_off;
  1948. netdev_init ( dev, &skge_operations );
  1949. err = register_netdev(dev);
  1950. if (err) {
  1951. DBG(PFX "cannot register net device\n");
  1952. goto err_out_free_netdev;
  1953. }
  1954. skge_show_addr(dev);
  1955. if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
  1956. if (register_netdev(dev1) == 0)
  1957. skge_show_addr(dev1);
  1958. else {
  1959. /* Failure to register second port need not be fatal */
  1960. DBG(PFX "register of second port failed\n");
  1961. hw->dev[1] = NULL;
  1962. netdev_nullify(dev1);
  1963. netdev_put(dev1);
  1964. }
  1965. }
  1966. pci_set_drvdata(pdev, hw);
  1967. return 0;
  1968. err_out_free_netdev:
  1969. netdev_nullify(dev);
  1970. netdev_put(dev);
  1971. err_out_led_off:
  1972. skge_write16(hw, B0_LED, LED_STAT_OFF);
  1973. err_out_iounmap:
  1974. iounmap((void*)hw->regs);
  1975. err_out_free_hw:
  1976. free(hw);
  1977. err_out_free_regions:
  1978. pci_set_drvdata(pdev, NULL);
  1979. return err;
  1980. }
  1981. static void skge_remove(struct pci_device *pdev)
  1982. {
  1983. struct skge_hw *hw = pci_get_drvdata(pdev);
  1984. struct net_device *dev0, *dev1;
  1985. if (!hw)
  1986. return;
  1987. if ((dev1 = hw->dev[1]))
  1988. unregister_netdev(dev1);
  1989. dev0 = hw->dev[0];
  1990. unregister_netdev(dev0);
  1991. hw->intr_mask = 0;
  1992. skge_write32(hw, B0_IMSK, 0);
  1993. skge_read32(hw, B0_IMSK);
  1994. skge_write16(hw, B0_LED, LED_STAT_OFF);
  1995. skge_write8(hw, B0_CTST, CS_RST_SET);
  1996. if (dev1) {
  1997. netdev_nullify(dev1);
  1998. netdev_put(dev1);
  1999. }
  2000. netdev_nullify(dev0);
  2001. netdev_put(dev0);
  2002. iounmap((void*)hw->regs);
  2003. free(hw);
  2004. pci_set_drvdata(pdev, NULL);
  2005. }
  2006. /*
  2007. * Enable or disable IRQ masking.
  2008. *
  2009. * @v netdev Device to control.
  2010. * @v enable Zero to mask off IRQ, non-zero to enable IRQ.
  2011. *
  2012. * This is a iPXE Network Driver API function.
  2013. */
  2014. static void skge_net_irq ( struct net_device *dev, int enable ) {
  2015. struct skge_port *skge = netdev_priv(dev);
  2016. struct skge_hw *hw = skge->hw;
  2017. if (enable)
  2018. hw->intr_mask |= portmask[skge->port];
  2019. else
  2020. hw->intr_mask &= ~portmask[skge->port];
  2021. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2022. }
  2023. struct pci_driver skge_driver __pci_driver = {
  2024. .ids = skge_id_table,
  2025. .id_count = ( sizeof (skge_id_table) / sizeof (skge_id_table[0]) ),
  2026. .probe = skge_probe,
  2027. .remove = skge_remove
  2028. };