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amd8111e.c 17KB

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  1. /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
  2. * Copyright (C) 2004 Advanced Micro Devices
  3. * Copyright (C) 2005 Liu Tao <liutao1980@gmail.com> [etherboot port]
  4. *
  5. * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
  6. * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
  7. * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
  8. * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
  9. * Copyright 1993 United States Government as represented by the
  10. * Director, National Security Agency.[ pcnet32.c ]
  11. * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
  12. * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
  13. *
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  28. * USA
  29. */
  30. FILE_LICENCE ( GPL2_OR_LATER );
  31. #include "etherboot.h"
  32. #include "nic.h"
  33. #include "mii.h"
  34. #include <ipxe/pci.h>
  35. #include <ipxe/ethernet.h>
  36. #include "string.h"
  37. #include "stdint.h"
  38. #include "amd8111e.h"
  39. /* driver definitions */
  40. #define NUM_TX_SLOTS 2
  41. #define NUM_RX_SLOTS 4
  42. #define TX_SLOTS_MASK 1
  43. #define RX_SLOTS_MASK 3
  44. #define TX_BUF_LEN 1536
  45. #define RX_BUF_LEN 1536
  46. #define TX_PKT_LEN_MAX (ETH_FRAME_LEN - ETH_HLEN)
  47. #define RX_PKT_LEN_MIN 60
  48. #define RX_PKT_LEN_MAX ETH_FRAME_LEN
  49. #define TX_TIMEOUT 3000
  50. #define TX_PROCESS_TIME 10
  51. #define TX_RETRY (TX_TIMEOUT / TX_PROCESS_TIME)
  52. #define PHY_RW_RETRY 10
  53. struct amd8111e_tx_desc {
  54. u16 buf_len;
  55. u16 tx_flags;
  56. u16 tag_ctrl_info;
  57. u16 tag_ctrl_cmd;
  58. u32 buf_phy_addr;
  59. u32 reserved;
  60. };
  61. struct amd8111e_rx_desc {
  62. u32 reserved;
  63. u16 msg_len;
  64. u16 tag_ctrl_info;
  65. u16 buf_len;
  66. u16 rx_flags;
  67. u32 buf_phy_addr;
  68. };
  69. struct eth_frame {
  70. u8 dst_addr[ETH_ALEN];
  71. u8 src_addr[ETH_ALEN];
  72. u16 type;
  73. u8 data[ETH_FRAME_LEN - ETH_HLEN];
  74. } __attribute__((packed));
  75. struct amd8111e_priv {
  76. struct amd8111e_tx_desc tx_ring[NUM_TX_SLOTS];
  77. struct amd8111e_rx_desc rx_ring[NUM_RX_SLOTS];
  78. unsigned char tx_buf[NUM_TX_SLOTS][TX_BUF_LEN];
  79. unsigned char rx_buf[NUM_RX_SLOTS][RX_BUF_LEN];
  80. unsigned long tx_idx, rx_idx;
  81. int tx_consistent;
  82. char opened;
  83. char link;
  84. char speed;
  85. char duplex;
  86. int ext_phy_addr;
  87. u32 ext_phy_id;
  88. struct pci_device *pdev;
  89. struct nic *nic;
  90. void *mmio;
  91. };
  92. static struct amd8111e_priv amd8111e;
  93. /********************************************************
  94. * locale functions *
  95. ********************************************************/
  96. static void amd8111e_init_hw_default(struct amd8111e_priv *lp);
  97. static int amd8111e_start(struct amd8111e_priv *lp);
  98. static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val);
  99. #if 0
  100. static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val);
  101. #endif
  102. static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp);
  103. static void amd8111e_disable_interrupt(struct amd8111e_priv *lp);
  104. static void amd8111e_enable_interrupt(struct amd8111e_priv *lp);
  105. static void amd8111e_force_interrupt(struct amd8111e_priv *lp);
  106. static int amd8111e_get_mac_address(struct amd8111e_priv *lp);
  107. static int amd8111e_init_rx_ring(struct amd8111e_priv *lp);
  108. static int amd8111e_init_tx_ring(struct amd8111e_priv *lp);
  109. static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index);
  110. static void amd8111e_wait_link(struct amd8111e_priv *lp);
  111. static void amd8111e_poll_link(struct amd8111e_priv *lp);
  112. static void amd8111e_restart(struct amd8111e_priv *lp);
  113. /*
  114. * This function clears necessary the device registers.
  115. */
  116. static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
  117. {
  118. unsigned int reg_val;
  119. void *mmio = lp->mmio;
  120. /* stop the chip */
  121. writel(RUN, mmio + CMD0);
  122. /* Clear RCV_RING_BASE_ADDR */
  123. writel(0, mmio + RCV_RING_BASE_ADDR0);
  124. /* Clear XMT_RING_BASE_ADDR */
  125. writel(0, mmio + XMT_RING_BASE_ADDR0);
  126. writel(0, mmio + XMT_RING_BASE_ADDR1);
  127. writel(0, mmio + XMT_RING_BASE_ADDR2);
  128. writel(0, mmio + XMT_RING_BASE_ADDR3);
  129. /* Clear CMD0 */
  130. writel(CMD0_CLEAR, mmio + CMD0);
  131. /* Clear CMD2 */
  132. writel(CMD2_CLEAR, mmio + CMD2);
  133. /* Clear CMD7 */
  134. writel(CMD7_CLEAR, mmio + CMD7);
  135. /* Clear DLY_INT_A and DLY_INT_B */
  136. writel(0x0, mmio + DLY_INT_A);
  137. writel(0x0, mmio + DLY_INT_B);
  138. /* Clear FLOW_CONTROL */
  139. writel(0x0, mmio + FLOW_CONTROL);
  140. /* Clear INT0 write 1 to clear register */
  141. reg_val = readl(mmio + INT0);
  142. writel(reg_val, mmio + INT0);
  143. /* Clear STVAL */
  144. writel(0x0, mmio + STVAL);
  145. /* Clear INTEN0 */
  146. writel(INTEN0_CLEAR, mmio + INTEN0);
  147. /* Clear LADRF */
  148. writel(0x0, mmio + LADRF);
  149. /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
  150. writel(0x80010, mmio + SRAM_SIZE);
  151. /* Clear RCV_RING0_LEN */
  152. writel(0x0, mmio + RCV_RING_LEN0);
  153. /* Clear XMT_RING0/1/2/3_LEN */
  154. writel(0x0, mmio + XMT_RING_LEN0);
  155. writel(0x0, mmio + XMT_RING_LEN1);
  156. writel(0x0, mmio + XMT_RING_LEN2);
  157. writel(0x0, mmio + XMT_RING_LEN3);
  158. /* Clear XMT_RING_LIMIT */
  159. writel(0x0, mmio + XMT_RING_LIMIT);
  160. /* Clear MIB */
  161. writew(MIB_CLEAR, mmio + MIB_ADDR);
  162. /* Clear LARF */
  163. writel( 0, mmio + LADRF);
  164. writel( 0, mmio + LADRF + 4);
  165. /* SRAM_SIZE register */
  166. reg_val = readl(mmio + SRAM_SIZE);
  167. /* Set default value to CTRL1 Register */
  168. writel(CTRL1_DEFAULT, mmio + CTRL1);
  169. /* To avoid PCI posting bug */
  170. readl(mmio + CMD2);
  171. }
  172. /*
  173. * This function initializes the device registers and starts the device.
  174. */
  175. static int amd8111e_start(struct amd8111e_priv *lp)
  176. {
  177. struct nic *nic = lp->nic;
  178. void *mmio = lp->mmio;
  179. int i, reg_val;
  180. /* stop the chip */
  181. writel(RUN, mmio + CMD0);
  182. /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
  183. writew(0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
  184. /* enable the port manager and set auto negotiation always */
  185. writel(VAL1 | EN_PMGR, mmio + CMD3 );
  186. writel(XPHYANE | XPHYRST, mmio + CTRL2);
  187. /* set control registers */
  188. reg_val = readl(mmio + CTRL1);
  189. reg_val &= ~XMTSP_MASK;
  190. writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
  191. /* initialize tx and rx ring base addresses */
  192. amd8111e_init_tx_ring(lp);
  193. amd8111e_init_rx_ring(lp);
  194. writel(virt_to_bus(lp->tx_ring), mmio + XMT_RING_BASE_ADDR0);
  195. writel(virt_to_bus(lp->rx_ring), mmio + RCV_RING_BASE_ADDR0);
  196. writew(NUM_TX_SLOTS, mmio + XMT_RING_LEN0);
  197. writew(NUM_RX_SLOTS, mmio + RCV_RING_LEN0);
  198. /* set default IPG to 96 */
  199. writew(DEFAULT_IPG, mmio + IPG);
  200. writew(DEFAULT_IPG - IFS1_DELTA, mmio + IFS1);
  201. /* AutoPAD transmit, Retransmit on Underflow */
  202. writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
  203. /* JUMBO disabled */
  204. writel(JUMBO, mmio + CMD3);
  205. /* Setting the MAC address to the device */
  206. for(i = 0; i < ETH_ALEN; i++)
  207. writeb(nic->node_addr[i], mmio + PADR + i);
  208. /* set RUN bit to start the chip, interrupt not enabled */
  209. writel(VAL2 | RDMD0 | VAL0 | RUN, mmio + CMD0);
  210. /* To avoid PCI posting bug */
  211. readl(mmio + CMD0);
  212. return 0;
  213. }
  214. /*
  215. This function will read the PHY registers.
  216. */
  217. static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val)
  218. {
  219. void *mmio = lp->mmio;
  220. unsigned int reg_val;
  221. unsigned int retry = PHY_RW_RETRY;
  222. reg_val = readl(mmio + PHY_ACCESS);
  223. while (reg_val & PHY_CMD_ACTIVE)
  224. reg_val = readl(mmio + PHY_ACCESS);
  225. writel(PHY_RD_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16),
  226. mmio + PHY_ACCESS);
  227. do {
  228. reg_val = readl(mmio + PHY_ACCESS);
  229. udelay(30); /* It takes 30 us to read/write data */
  230. } while (--retry && (reg_val & PHY_CMD_ACTIVE));
  231. if (reg_val & PHY_RD_ERR) {
  232. *val = 0;
  233. return -1;
  234. }
  235. *val = reg_val & 0xffff;
  236. return 0;
  237. }
  238. /*
  239. This function will write into PHY registers.
  240. */
  241. #if 0
  242. static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val)
  243. {
  244. void *mmio = lp->mmio;
  245. unsigned int reg_val;
  246. unsigned int retry = PHY_RW_RETRY;
  247. reg_val = readl(mmio + PHY_ACCESS);
  248. while (reg_val & PHY_CMD_ACTIVE)
  249. reg_val = readl(mmio + PHY_ACCESS);
  250. writel(PHY_WR_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16) | val,
  251. mmio + PHY_ACCESS);
  252. do {
  253. reg_val = readl(mmio + PHY_ACCESS);
  254. udelay(30); /* It takes 30 us to read/write the data */
  255. } while (--retry && (reg_val & PHY_CMD_ACTIVE));
  256. if(reg_val & PHY_RD_ERR)
  257. return -1;
  258. return 0;
  259. }
  260. #endif
  261. static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp)
  262. {
  263. int i;
  264. lp->ext_phy_id = 0;
  265. lp->ext_phy_addr = 1;
  266. for (i = 0x1e; i >= 0; i--) {
  267. u32 id1, id2;
  268. if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
  269. continue;
  270. if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
  271. continue;
  272. lp->ext_phy_id = (id1 << 16) | id2;
  273. lp->ext_phy_addr = i;
  274. break;
  275. }
  276. if (lp->ext_phy_id)
  277. printf("Found MII PHY ID 0x%08x at address 0x%02x\n",
  278. (unsigned int) lp->ext_phy_id, lp->ext_phy_addr);
  279. else
  280. printf("Couldn't detect MII PHY, assuming address 0x01\n");
  281. }
  282. static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
  283. {
  284. void *mmio = lp->mmio;
  285. unsigned int int0;
  286. writel(INTREN, mmio + CMD0);
  287. writel(INTEN0_CLEAR, mmio + INTEN0);
  288. int0 = readl(mmio + INT0);
  289. writel(int0, mmio + INT0);
  290. readl(mmio + INT0);
  291. }
  292. static void amd8111e_enable_interrupt(struct amd8111e_priv *lp)
  293. {
  294. void *mmio = lp->mmio;
  295. writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
  296. writel(VAL0 | INTREN, mmio + CMD0);
  297. readl(mmio + CMD0);
  298. }
  299. static void amd8111e_force_interrupt(struct amd8111e_priv *lp)
  300. {
  301. void *mmio = lp->mmio;
  302. writel(VAL0 | UINTCMD, mmio + CMD0);
  303. readl(mmio + CMD0);
  304. }
  305. static int amd8111e_get_mac_address(struct amd8111e_priv *lp)
  306. {
  307. struct nic *nic = lp->nic;
  308. void *mmio = lp->mmio;
  309. int i;
  310. /* BIOS should have set mac address to PADR register,
  311. * so we read PADR to get it.
  312. */
  313. for (i = 0; i < ETH_ALEN; i++)
  314. nic->node_addr[i] = readb(mmio + PADR + i);
  315. DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) );
  316. return 0;
  317. }
  318. static int amd8111e_init_rx_ring(struct amd8111e_priv *lp)
  319. {
  320. int i;
  321. lp->rx_idx = 0;
  322. /* Initilaizing receive descriptors */
  323. for (i = 0; i < NUM_RX_SLOTS; i++) {
  324. lp->rx_ring[i].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[i]));
  325. lp->rx_ring[i].buf_len = cpu_to_le16(RX_BUF_LEN);
  326. wmb();
  327. lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
  328. }
  329. return 0;
  330. }
  331. static int amd8111e_init_tx_ring(struct amd8111e_priv *lp)
  332. {
  333. int i;
  334. lp->tx_idx = 0;
  335. lp->tx_consistent = 1;
  336. /* Initializing transmit descriptors */
  337. for (i = 0; i < NUM_TX_SLOTS; i++) {
  338. lp->tx_ring[i].tx_flags = 0;
  339. lp->tx_ring[i].buf_phy_addr = 0;
  340. lp->tx_ring[i].buf_len = 0;
  341. }
  342. return 0;
  343. }
  344. static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index)
  345. {
  346. volatile u16 status;
  347. int retry = TX_RETRY;
  348. status = le16_to_cpu(lp->tx_ring[index].tx_flags);
  349. while (--retry && (status & OWN_BIT)) {
  350. mdelay(TX_PROCESS_TIME);
  351. status = le16_to_cpu(lp->tx_ring[index].tx_flags);
  352. }
  353. if (status & OWN_BIT) {
  354. printf("Error: tx slot %d timeout, stat = 0x%x\n", index, status);
  355. amd8111e_restart(lp);
  356. return -1;
  357. }
  358. return 0;
  359. }
  360. static void amd8111e_wait_link(struct amd8111e_priv *lp)
  361. {
  362. unsigned int status;
  363. u32 reg_val;
  364. do {
  365. /* read phy to update STAT0 register */
  366. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
  367. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
  368. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
  369. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
  370. status = readl(lp->mmio + STAT0);
  371. } while (!(status & AUTONEG_COMPLETE) || !(status & LINK_STATS));
  372. }
  373. static void amd8111e_poll_link(struct amd8111e_priv *lp)
  374. {
  375. unsigned int status, speed;
  376. u32 reg_val;
  377. if (!lp->link) {
  378. /* read phy to update STAT0 register */
  379. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
  380. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
  381. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
  382. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
  383. status = readl(lp->mmio + STAT0);
  384. if (status & LINK_STATS) {
  385. lp->link = 1;
  386. speed = (status & SPEED_MASK) >> 7;
  387. if (speed == PHY_SPEED_100)
  388. lp->speed = 1;
  389. else
  390. lp->speed = 0;
  391. if (status & FULL_DPLX)
  392. lp->duplex = 1;
  393. else
  394. lp->duplex = 0;
  395. printf("Link is up: %s Mbps %s duplex\n",
  396. lp->speed ? "100" : "10", lp->duplex ? "full" : "half");
  397. }
  398. } else {
  399. status = readl(lp->mmio + STAT0);
  400. if (!(status & LINK_STATS)) {
  401. lp->link = 0;
  402. printf("Link is down\n");
  403. }
  404. }
  405. }
  406. static void amd8111e_restart(struct amd8111e_priv *lp)
  407. {
  408. printf("\nStarting nic...\n");
  409. amd8111e_disable_interrupt(lp);
  410. amd8111e_init_hw_default(lp);
  411. amd8111e_probe_ext_phy(lp);
  412. amd8111e_get_mac_address(lp);
  413. amd8111e_start(lp);
  414. printf("Waiting link up...\n");
  415. lp->link = 0;
  416. amd8111e_wait_link(lp);
  417. amd8111e_poll_link(lp);
  418. }
  419. /********************************************************
  420. * Interface Functions *
  421. ********************************************************/
  422. static void amd8111e_transmit(struct nic *nic, const char *dst_addr,
  423. unsigned int type, unsigned int size, const char *packet)
  424. {
  425. struct amd8111e_priv *lp = nic->priv_data;
  426. struct eth_frame *frame;
  427. unsigned int index;
  428. /* check packet size */
  429. if (size > TX_PKT_LEN_MAX) {
  430. printf("amd8111e_transmit(): too large packet, drop\n");
  431. return;
  432. }
  433. /* get tx slot */
  434. index = lp->tx_idx;
  435. if (amd8111e_wait_tx_ring(lp, index))
  436. return;
  437. /* fill frame */
  438. frame = (struct eth_frame *)lp->tx_buf[index];
  439. memset(frame->data, 0, TX_PKT_LEN_MAX);
  440. memcpy(frame->dst_addr, dst_addr, ETH_ALEN);
  441. memcpy(frame->src_addr, nic->node_addr, ETH_ALEN);
  442. frame->type = htons(type);
  443. memcpy(frame->data, packet, size);
  444. /* start xmit */
  445. lp->tx_ring[index].buf_len = cpu_to_le16(ETH_HLEN + size);
  446. lp->tx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(frame));
  447. wmb();
  448. lp->tx_ring[index].tx_flags =
  449. cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT | ADD_FCS_BIT | LTINT_BIT);
  450. writel(VAL1 | TDMD0, lp->mmio + CMD0);
  451. readl(lp->mmio + CMD0);
  452. /* update slot pointer */
  453. lp->tx_idx = (lp->tx_idx + 1) & TX_SLOTS_MASK;
  454. }
  455. static int amd8111e_poll(struct nic *nic, int retrieve)
  456. {
  457. /* return true if there's an ethernet packet ready to read */
  458. /* nic->packet should contain data on return */
  459. /* nic->packetlen should contain length of data */
  460. struct amd8111e_priv *lp = nic->priv_data;
  461. u16 status, pkt_len;
  462. unsigned int index, pkt_ok;
  463. amd8111e_poll_link(lp);
  464. index = lp->rx_idx;
  465. status = le16_to_cpu(lp->rx_ring[index].rx_flags);
  466. pkt_len = le16_to_cpu(lp->rx_ring[index].msg_len) - 4; /* remove 4bytes FCS */
  467. if (status & OWN_BIT)
  468. return 0;
  469. if (status & ERR_BIT)
  470. pkt_ok = 0;
  471. else if (!(status & STP_BIT))
  472. pkt_ok = 0;
  473. else if (!(status & ENP_BIT))
  474. pkt_ok = 0;
  475. else if (pkt_len < RX_PKT_LEN_MIN)
  476. pkt_ok = 0;
  477. else if (pkt_len > RX_PKT_LEN_MAX)
  478. pkt_ok = 0;
  479. else
  480. pkt_ok = 1;
  481. if (pkt_ok) {
  482. if (!retrieve)
  483. return 1;
  484. nic->packetlen = pkt_len;
  485. memcpy(nic->packet, lp->rx_buf[index], nic->packetlen);
  486. }
  487. lp->rx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[index]));
  488. lp->rx_ring[index].buf_len = cpu_to_le16(RX_BUF_LEN);
  489. wmb();
  490. lp->rx_ring[index].rx_flags = cpu_to_le16(OWN_BIT);
  491. writel(VAL2 | RDMD0, lp->mmio + CMD0);
  492. readl(lp->mmio + CMD0);
  493. lp->rx_idx = (lp->rx_idx + 1) & RX_SLOTS_MASK;
  494. return pkt_ok;
  495. }
  496. static void amd8111e_disable(struct nic *nic)
  497. {
  498. struct amd8111e_priv *lp = nic->priv_data;
  499. /* disable interrupt */
  500. amd8111e_disable_interrupt(lp);
  501. /* stop chip */
  502. amd8111e_init_hw_default(lp);
  503. /* unmap mmio */
  504. iounmap(lp->mmio);
  505. /* update status */
  506. lp->opened = 0;
  507. }
  508. static void amd8111e_irq(struct nic *nic, irq_action_t action)
  509. {
  510. struct amd8111e_priv *lp = nic->priv_data;
  511. switch (action) {
  512. case DISABLE:
  513. amd8111e_disable_interrupt(lp);
  514. break;
  515. case ENABLE:
  516. amd8111e_enable_interrupt(lp);
  517. break;
  518. case FORCE:
  519. amd8111e_force_interrupt(lp);
  520. break;
  521. }
  522. }
  523. static struct nic_operations amd8111e_operations = {
  524. .connect = dummy_connect,
  525. .poll = amd8111e_poll,
  526. .transmit = amd8111e_transmit,
  527. .irq = amd8111e_irq,
  528. };
  529. static int amd8111e_probe(struct nic *nic, struct pci_device *pdev)
  530. {
  531. struct amd8111e_priv *lp = &amd8111e;
  532. unsigned long mmio_start, mmio_len;
  533. nic->ioaddr = pdev->ioaddr;
  534. nic->irqno = pdev->irq;
  535. mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
  536. mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_0);
  537. memset(lp, 0, sizeof(*lp));
  538. lp->pdev = pdev;
  539. lp->nic = nic;
  540. lp->mmio = ioremap(mmio_start, mmio_len);
  541. lp->opened = 1;
  542. adjust_pci_device(pdev);
  543. nic->priv_data = lp;
  544. amd8111e_restart(lp);
  545. nic->nic_op = &amd8111e_operations;
  546. return 1;
  547. }
  548. static struct pci_device_id amd8111e_nics[] = {
  549. PCI_ROM(0x1022, 0x7462, "amd8111e", "AMD8111E", 0),
  550. };
  551. PCI_DRIVER ( amd8111e_driver, amd8111e_nics, PCI_NO_CLASS );
  552. DRIVER ( "AMD8111E", nic_driver, pci_driver, amd8111e_driver,
  553. amd8111e_probe, amd8111e_disable );
  554. /*
  555. * Local variables:
  556. * c-basic-offset: 8
  557. * c-indent-level: 8
  558. * tab-width: 8
  559. * End:
  560. */