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cs89x0.h 16KB

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  1. /**
  2. Per an email message from Russ Nelson <nelson@crynwr.com> on
  3. 18 March 2008 this file is now licensed under GPL Version 2.
  4. From: Russ Nelson <nelson@crynwr.com>
  5. Date: Tue, 18 Mar 2008 12:42:00 -0400
  6. Subject: Re: [Etherboot-developers] cs89x0 driver in etherboot
  7. -- quote from email
  8. As copyright holder, if I say it doesn't conflict with the GPL,
  9. then it doesn't conflict with the GPL.
  10. However, there's no point in causing people's brains to overheat,
  11. so yes, I grant permission for the code to be relicensed under the
  12. GPLv2. Please make sure that this change in licensing makes its
  13. way upstream. -russ
  14. -- quote from email
  15. **/
  16. /* Copyright, 1988-1992, Russell Nelson, Crynwr Software
  17. This program is free software; you can redistribute it and/or modify
  18. it under the terms of the GNU General Public License as published by
  19. the Free Software Foundation, version 1.
  20. This program is distributed in the hope that it will be useful,
  21. but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. GNU General Public License for more details.
  24. You should have received a copy of the GNU General Public License
  25. along with this program; if not, write to the Free Software
  26. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
  27. #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
  28. /* offset 2h -> Model/Product Number */
  29. /* offset 3h -> Chip Revision Number */
  30. #define PP_ISAIOB 0x0020 /* IO base address */
  31. #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
  32. #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
  33. #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
  34. #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
  35. #define PP_ISASOF 0x0026 /* ISA DMA offset */
  36. #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
  37. #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
  38. #define PP_CS8900_ISAMemB 0x002C /* Memory base */
  39. #define PP_CS8920_ISAMemB 0x0348 /* */
  40. #define PP_ISABootBase 0x0030 /* Boot Prom base */
  41. #define PP_ISABootMask 0x0034 /* Boot Prom Mask */
  42. /* EEPROM data and command registers */
  43. #define PP_EECMD 0x0040 /* NVR Interface Command register */
  44. #define PP_EEData 0x0042 /* NVR Interface Data Register */
  45. #define PP_DebugReg 0x0044 /* Debug Register */
  46. #define PP_RxCFG 0x0102 /* Rx Bus config */
  47. #define PP_RxCTL 0x0104 /* Receive Control Register */
  48. #define PP_TxCFG 0x0106 /* Transmit Config Register */
  49. #define PP_TxCMD 0x0108 /* Transmit Command Register */
  50. #define PP_BufCFG 0x010A /* Bus configuration Register */
  51. #define PP_LineCTL 0x0112 /* Line Config Register */
  52. #define PP_SelfCTL 0x0114 /* Self Command Register */
  53. #define PP_BusCTL 0x0116 /* ISA bus control Register */
  54. #define PP_TestCTL 0x0118 /* Test Register */
  55. #define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */
  56. #define PP_ISQ 0x0120 /* Interrupt Status */
  57. #define PP_RxEvent 0x0124 /* Rx Event Register */
  58. #define PP_TxEvent 0x0128 /* Tx Event Register */
  59. #define PP_BufEvent 0x012C /* Bus Event Register */
  60. #define PP_RxMiss 0x0130 /* Receive Miss Count */
  61. #define PP_TxCol 0x0132 /* Transmit Collision Count */
  62. #define PP_LineST 0x0134 /* Line State Register */
  63. #define PP_SelfST 0x0136 /* Self State register */
  64. #define PP_BusST 0x0138 /* Bus Status */
  65. #define PP_TDR 0x013C /* Time Domain Reflectometry */
  66. #define PP_AutoNegST 0x013E /* Auto Neg Status */
  67. #define PP_TxCommand 0x0144 /* Tx Command */
  68. #define PP_TxLength 0x0146 /* Tx Length */
  69. #define PP_LAF 0x0150 /* Hash Table */
  70. #define PP_IA 0x0158 /* Physical Address Register */
  71. #define PP_RxStatus 0x0400 /* Receive start of frame */
  72. #define PP_RxLength 0x0402 /* Receive Length of frame */
  73. #define PP_RxFrame 0x0404 /* Receive frame pointer */
  74. #define PP_TxFrame 0x0A00 /* Transmit frame pointer */
  75. /* Primary I/O Base Address. If no I/O base is supplied by the user, then this */
  76. /* can be used as the default I/O base to access the PacketPage Area. */
  77. #define DEFAULTIOBASE 0x0300
  78. #define FIRST_IO 0x020C /* First I/O port to check */
  79. #define LAST_IO 0x037C /* Last I/O port to check (+10h) */
  80. #define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */
  81. #define ADD_SIG 0x3000 /* Expected ID signature */
  82. #define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */
  83. #ifdef IBMEIPKT
  84. #define EISA_ID_SIG 0x4D24 /* IBM */
  85. #define PART_NO_SIG 0x1010 /* IBM */
  86. #define MONGOOSE_BIT 0x0000 /* IBM */
  87. #else
  88. #define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */
  89. #define PART_NO_SIG 0x4000 /* ID code CS8920 board (PnP Vendor Product code) */
  90. #define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */
  91. #endif
  92. #define PRODUCT_ID_ADD 0x0002 /* Address of product ID */
  93. /* Mask to find out the types of registers */
  94. #define REG_TYPE_MASK 0x001F
  95. /* Eeprom Commands */
  96. #define ERSE_WR_ENBL 0x00F0
  97. #define ERSE_WR_DISABLE 0x0000
  98. /* Defines Control/Config register quintuplet numbers */
  99. #define RX_BUF_CFG 0x0003
  100. #define RX_CONTROL 0x0005
  101. #define TX_CFG 0x0007
  102. #define TX_COMMAND 0x0009
  103. #define BUF_CFG 0x000B
  104. #define LINE_CONTROL 0x0013
  105. #define SELF_CONTROL 0x0015
  106. #define BUS_CONTROL 0x0017
  107. #define TEST_CONTROL 0x0019
  108. /* Defines Status/Count registers quintuplet numbers */
  109. #define RX_EVENT 0x0004
  110. #define TX_EVENT 0x0008
  111. #define BUF_EVENT 0x000C
  112. #define RX_MISS_COUNT 0x0010
  113. #define TX_COL_COUNT 0x0012
  114. #define LINE_STATUS 0x0014
  115. #define SELF_STATUS 0x0016
  116. #define BUS_STATUS 0x0018
  117. #define TDR 0x001C
  118. /* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */
  119. #define SKIP_1 0x0040
  120. #define RX_STREAM_ENBL 0x0080
  121. #define RX_OK_ENBL 0x0100
  122. #define RX_DMA_ONLY 0x0200
  123. #define AUTO_RX_DMA 0x0400
  124. #define BUFFER_CRC 0x0800
  125. #define RX_CRC_ERROR_ENBL 0x1000
  126. #define RX_RUNT_ENBL 0x2000
  127. #define RX_EXTRA_DATA_ENBL 0x4000
  128. /* PP_RxCTL - Receive Control bit definition - Read/write */
  129. #define RX_IA_HASH_ACCEPT 0x0040
  130. #define RX_PROM_ACCEPT 0x0080
  131. #define RX_OK_ACCEPT 0x0100
  132. #define RX_MULTCAST_ACCEPT 0x0200
  133. #define RX_IA_ACCEPT 0x0400
  134. #define RX_BROADCAST_ACCEPT 0x0800
  135. #define RX_BAD_CRC_ACCEPT 0x1000
  136. #define RX_RUNT_ACCEPT 0x2000
  137. #define RX_EXTRA_DATA_ACCEPT 0x4000
  138. #define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
  139. /* Default receive mode - individually addressed, broadcast, and error free */
  140. #define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
  141. /* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
  142. #define TX_LOST_CRS_ENBL 0x0040
  143. #define TX_SQE_ERROR_ENBL 0x0080
  144. #define TX_OK_ENBL 0x0100
  145. #define TX_LATE_COL_ENBL 0x0200
  146. #define TX_JBR_ENBL 0x0400
  147. #define TX_ANY_COL_ENBL 0x0800
  148. #define TX_16_COL_ENBL 0x8000
  149. /* PP_TxCMD - Transmit Command bit definition - Read-only */
  150. #define TX_START_4_BYTES 0x0000
  151. #define TX_START_64_BYTES 0x0040
  152. #define TX_START_128_BYTES 0x0080
  153. #define TX_START_ALL_BYTES 0x00C0
  154. #define TX_FORCE 0x0100
  155. #define TX_ONE_COL 0x0200
  156. #define TX_TWO_PART_DEFF_DISABLE 0x0400
  157. #define TX_NO_CRC 0x1000
  158. #define TX_RUNT 0x2000
  159. /* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
  160. #define GENERATE_SW_INTERRUPT 0x0040
  161. #define RX_DMA_ENBL 0x0080
  162. #define READY_FOR_TX_ENBL 0x0100
  163. #define TX_UNDERRUN_ENBL 0x0200
  164. #define RX_MISS_ENBL 0x0400
  165. #define RX_128_BYTE_ENBL 0x0800
  166. #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
  167. #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
  168. #define RX_DEST_MATCH_ENBL 0x8000
  169. /* PP_LineCTL - Line Control bit definition - Read/write */
  170. #define SERIAL_RX_ON 0x0040
  171. #define SERIAL_TX_ON 0x0080
  172. #define AUI_ONLY 0x0100
  173. #define AUTO_AUI_10BASET 0x0200
  174. #define MODIFIED_BACKOFF 0x0800
  175. #define NO_AUTO_POLARITY 0x1000
  176. #define TWO_PART_DEFDIS 0x2000
  177. #define LOW_RX_SQUELCH 0x4000
  178. /* PP_SelfCTL - Software Self Control bit definition - Read/write */
  179. #define POWER_ON_RESET 0x0040
  180. #define SW_STOP 0x0100
  181. #define SLEEP_ON 0x0200
  182. #define AUTO_WAKEUP 0x0400
  183. #define HCB0_ENBL 0x1000
  184. #define HCB1_ENBL 0x2000
  185. #define HCB0 0x4000
  186. #define HCB1 0x8000
  187. /* PP_BusCTL - ISA Bus Control bit definition - Read/write */
  188. #define RESET_RX_DMA 0x0040
  189. #define MEMORY_ON 0x0400
  190. #define DMA_BURST_MODE 0x0800
  191. #define IO_CHANNEL_READY_ON 0x1000
  192. #define RX_DMA_SIZE_64K 0x2000
  193. #define ENABLE_IRQ 0x8000
  194. /* PP_TestCTL - Test Control bit definition - Read/write */
  195. #define LINK_OFF 0x0080
  196. #define ENDEC_LOOPBACK 0x0200
  197. #define AUI_LOOPBACK 0x0400
  198. #define BACKOFF_OFF 0x0800
  199. #define FAST_TEST 0x8000
  200. /* PP_RxEvent - Receive Event Bit definition - Read-only */
  201. #define RX_IA_HASHED 0x0040
  202. #define RX_DRIBBLE 0x0080
  203. #define RX_OK 0x0100
  204. #define RX_HASHED 0x0200
  205. #define RX_IA 0x0400
  206. #define RX_BROADCAST 0x0800
  207. #define RX_CRC_ERROR 0x1000
  208. #define RX_RUNT 0x2000
  209. #define RX_EXTRA_DATA 0x4000
  210. #define HASH_INDEX_MASK 0x0FC00
  211. /* PP_TxEvent - Transmit Event Bit definition - Read-only */
  212. #define TX_LOST_CRS 0x0040
  213. #define TX_SQE_ERROR 0x0080
  214. #define TX_OK 0x0100
  215. #define TX_LATE_COL 0x0200
  216. #define TX_JBR 0x0400
  217. #define TX_16_COL 0x8000
  218. #define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS)
  219. #define TX_COL_COUNT_MASK 0x7800
  220. /* PP_BufEvent - Buffer Event Bit definition - Read-only */
  221. #define SW_INTERRUPT 0x0040
  222. #define RX_DMA 0x0080
  223. #define READY_FOR_TX 0x0100
  224. #define TX_UNDERRUN 0x0200
  225. #define RX_MISS 0x0400
  226. #define RX_128_BYTE 0x0800
  227. #define TX_COL_OVRFLW 0x1000
  228. #define RX_MISS_OVRFLW 0x2000
  229. #define RX_DEST_MATCH 0x8000
  230. /* PP_LineST - Ethernet Line Status bit definition - Read-only */
  231. #define LINK_OK 0x0080
  232. #define AUI_ON 0x0100
  233. #define TENBASET_ON 0x0200
  234. #define POLARITY_OK 0x1000
  235. #define CRS_OK 0x4000
  236. /* PP_SelfST - Chip Software Status bit definition */
  237. #define ACTIVE_33V 0x0040
  238. #define INIT_DONE 0x0080
  239. #define SI_BUSY 0x0100
  240. #define EEPROM_PRESENT 0x0200
  241. #define EEPROM_OK 0x0400
  242. #define EL_PRESENT 0x0800
  243. #define EE_SIZE_64 0x1000
  244. /* PP_BusST - ISA Bus Status bit definition */
  245. #define TX_BID_ERROR 0x0080
  246. #define READY_FOR_TX_NOW 0x0100
  247. /* PP_AutoNegCTL - Auto Negotiation Control bit definition */
  248. #define RE_NEG_NOW 0x0040
  249. #define ALLOW_FDX 0x0080
  250. #define AUTO_NEG_ENABLE 0x0100
  251. #define NLP_ENABLE 0x0200
  252. #define FORCE_FDX 0x8000
  253. #define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
  254. #define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)
  255. /* PP_AutoNegST - Auto Negotiation Status bit definition */
  256. #define AUTO_NEG_BUSY 0x0080
  257. #define FLP_LINK 0x0100
  258. #define FLP_LINK_GOOD 0x0800
  259. #define LINK_FAULT 0x1000
  260. #define HDX_ACTIVE 0x4000
  261. #define FDX_ACTIVE 0x8000
  262. /* The following block defines the ISQ event types */
  263. #define ISQ_RECEIVER_EVENT 0x04
  264. #define ISQ_TRANSMITTER_EVENT 0x08
  265. #define ISQ_BUFFER_EVENT 0x0c
  266. #define ISQ_RX_MISS_EVENT 0x10
  267. #define ISQ_TX_COL_EVENT 0x12
  268. #define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */
  269. #define ISQ_HIST 16 /* small history buffer */
  270. #define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */
  271. #define TXRXBUFSIZE 0x0600
  272. #define RXDMABUFSIZE 0x8000
  273. #define RXDMASIZE 0x4000
  274. #define TXRX_LENGTH_MASK 0x07FF
  275. /* rx options bits */
  276. #define RCV_WITH_RXON 1 /* Set SerRx ON */
  277. #define RCV_COUNTS 2 /* Use Framecnt1 */
  278. #define RCV_PONG 4 /* Pong respondent */
  279. #define RCV_DONG 8 /* Dong operation */
  280. #define RCV_POLLING 0x10 /* Poll RxEvent */
  281. #define RCV_ISQ 0x20 /* Use ISQ, int */
  282. #define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */
  283. #define RCV_DMA 0x200 /* Set RxDMA only */
  284. #define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */
  285. #define RCV_FIXED_DATA 0x800 /* Every frame same */
  286. #define RCV_IO 0x1000 /* Use ISA IO only */
  287. #define RCV_MEMORY 0x2000 /* Use ISA Memory */
  288. #define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */
  289. #define PKT_START PP_TxFrame /* Start of packet RAM */
  290. #define RX_FRAME_PORT 0x0000
  291. #define TX_FRAME_PORT RX_FRAME_PORT
  292. #define TX_CMD_PORT 0x0004
  293. #define TX_NOW 0x0000 /* Tx packet after 5 bytes copied */
  294. #define TX_AFTER_381 0x0020 /* Tx packet after 381 bytes copied */
  295. #define TX_AFTER_ALL 0x00C0 /* Tx packet after all bytes copied */
  296. #define TX_LEN_PORT 0x0006
  297. #define ISQ_PORT 0x0008
  298. #define ADD_PORT 0x000A
  299. #define DATA_PORT 0x000C
  300. #define EEPROM_WRITE_EN 0x00F0
  301. #define EEPROM_WRITE_DIS 0x0000
  302. #define EEPROM_WRITE_CMD 0x0100
  303. #define EEPROM_READ_CMD 0x0200
  304. /* Receive Header */
  305. /* Description of header of each packet in receive area of memory */
  306. #define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */
  307. #define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */
  308. #define RBUF_LEN_LOW 2 /* Length of received data - low byte */
  309. #define RBUF_LEN_HI 3 /* Length of received data - high byte */
  310. #define RBUF_HEAD_LEN 4 /* Length of this header */
  311. #define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */
  312. #define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */
  313. /* for bios scan */
  314. /* */
  315. #ifdef CSDEBUG
  316. /* use these values for debugging bios scan */
  317. #define BIOS_START_SEG 0x00000
  318. #define BIOS_OFFSET_INC 0x0010
  319. #else
  320. #define BIOS_START_SEG 0x0c000
  321. #define BIOS_OFFSET_INC 0x0200
  322. #endif
  323. #define BIOS_LAST_OFFSET 0x0fc00
  324. /* Byte offsets into the EEPROM configuration buffer */
  325. #define ISA_CNF_OFFSET 0x6
  326. #define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */
  327. #define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */
  328. /* the assumption here is that the bits in the eeprom are generally */
  329. /* in the same position as those in the autonegctl register. */
  330. /* Of course the IMM bit is not in that register so it must be */
  331. /* masked out */
  332. #define EE_FORCE_FDX 0x8000
  333. #define EE_NLP_ENABLE 0x0200
  334. #define EE_AUTO_NEG_ENABLE 0x0100
  335. #define EE_ALLOW_FDX 0x0080
  336. #define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX)
  337. #define IMM_BIT 0x0040 /* ignore missing media */
  338. #define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
  339. #define A_CNF_10B_T 0x0001
  340. #define A_CNF_AUI 0x0002
  341. #define A_CNF_10B_2 0x0004
  342. #define A_CNF_MEDIA_TYPE 0x0060
  343. #define A_CNF_MEDIA_AUTO 0x0000
  344. #define A_CNF_MEDIA_10B_T 0x0020
  345. #define A_CNF_MEDIA_AUI 0x0040
  346. #define A_CNF_MEDIA_10B_2 0x0060
  347. #define A_CNF_DC_DC_POLARITY 0x0080
  348. #define A_CNF_NO_AUTO_POLARITY 0x2000
  349. #define A_CNF_LOW_RX_SQUELCH 0x4000
  350. #define A_CNF_EXTND_10B_2 0x8000
  351. #define PACKET_PAGE_OFFSET 0x8
  352. /* Bit definitions for the ISA configuration word from the EEPROM */
  353. #define INT_NO_MASK 0x000F
  354. #define DMA_NO_MASK 0x0070
  355. #define ISA_DMA_SIZE 0x0200
  356. #define ISA_AUTO_RxDMA 0x0400
  357. #define ISA_RxDMA 0x0800
  358. #define DMA_BURST 0x1000
  359. #define STREAM_TRANSFER 0x2000
  360. #define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
  361. /* DMA controller registers */
  362. #define DMA_BASE 0x00 /* DMA controller base */
  363. #define DMA_BASE_2 0x0C0 /* DMA controller base */
  364. #define DMA_STAT 0x0D0 /* DMA controller status register */
  365. #define DMA_MASK 0x0D4 /* DMA controller mask register */
  366. #define DMA_MODE 0x0D6 /* DMA controller mode register */
  367. #define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */
  368. /* DMA data */
  369. #define DMA_DISABLE 0x04 /* Disable channel n */
  370. #define DMA_ENABLE 0x00 /* Enable channel n */
  371. /* Demand transfers, incr. address, auto init, writes, ch. n */
  372. #define DMA_RX_MODE 0x14
  373. /* Demand transfers, incr. address, auto init, reads, ch. n */
  374. #define DMA_TX_MODE 0x18
  375. #define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */
  376. #define CS8900 0x0000
  377. #define CS8920 0x4000
  378. #define CS8920M 0x6000
  379. #define REVISON_BITS 0x1F00
  380. #define EEVER_NUMBER 0x12
  381. #define CHKSUM_LEN 0x14
  382. #define CHKSUM_VAL 0x0000
  383. #define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */
  384. #define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */
  385. #define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */
  386. #define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */
  387. #define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */
  388. #define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */
  389. #define PNP_ADD_PORT 0x0279
  390. #define PNP_WRITE_PORT 0x0A79
  391. #define GET_PNP_ISA_STRUCT 0x40
  392. #define PNP_ISA_STRUCT_LEN 0x06
  393. #define PNP_CSN_CNT_OFF 0x01
  394. #define PNP_RD_PORT_OFF 0x02
  395. #define PNP_FUNCTION_OK 0x00
  396. #define PNP_WAKE 0x03
  397. #define PNP_RSRC_DATA 0x04
  398. #define PNP_RSRC_READY 0x01
  399. #define PNP_STATUS 0x05
  400. #define PNP_ACTIVATE 0x30
  401. #define PNP_CNF_IO_H 0x60
  402. #define PNP_CNF_IO_L 0x61
  403. #define PNP_CNF_INT 0x70
  404. #define PNP_CNF_DMA 0x74
  405. #define PNP_CNF_MEM 0x48
  406. #define BIT0 1
  407. #define BIT15 0x8000
  408. /*
  409. * Local variables:
  410. * c-basic-offset: 8
  411. * End:
  412. */