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hermon.c 68KB

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  1. /*
  2. * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
  3. * Copyright (C) 2008 Mellanox Technologies Ltd.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of the
  8. * License, or any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <stdint.h>
  20. #include <stdlib.h>
  21. #include <stdio.h>
  22. #include <string.h>
  23. #include <strings.h>
  24. #include <unistd.h>
  25. #include <errno.h>
  26. #include <byteswap.h>
  27. #include <gpxe/pci.h>
  28. #include <gpxe/malloc.h>
  29. #include <gpxe/umalloc.h>
  30. #include <gpxe/iobuf.h>
  31. #include <gpxe/netdevice.h>
  32. #include <gpxe/process.h>
  33. #include <gpxe/infiniband.h>
  34. #include "hermon.h"
  35. /**
  36. * @file
  37. *
  38. * Mellanox Hermon Infiniband HCA
  39. *
  40. */
  41. /***************************************************************************
  42. *
  43. * Queue number allocation
  44. *
  45. ***************************************************************************
  46. */
  47. /**
  48. * Allocate offsets within usage bitmask
  49. *
  50. * @v bits Usage bitmask
  51. * @v bits_len Length of usage bitmask
  52. * @v num_bits Number of contiguous bits to allocate within bitmask
  53. * @ret bit First free bit within bitmask, or negative error
  54. */
  55. static int hermon_bitmask_alloc ( hermon_bitmask_t *bits,
  56. unsigned int bits_len,
  57. unsigned int num_bits ) {
  58. unsigned int bit = 0;
  59. hermon_bitmask_t mask = 1;
  60. unsigned int found = 0;
  61. /* Search bits for num_bits contiguous free bits */
  62. while ( bit < bits_len ) {
  63. if ( ( mask & *bits ) == 0 ) {
  64. if ( ++found == num_bits )
  65. goto found;
  66. } else {
  67. found = 0;
  68. }
  69. bit++;
  70. mask = ( mask << 1 ) | ( mask >> ( 8 * sizeof ( mask ) - 1 ) );
  71. if ( mask == 1 )
  72. bits++;
  73. }
  74. return -ENFILE;
  75. found:
  76. /* Mark bits as in-use */
  77. do {
  78. *bits |= mask;
  79. if ( mask == 1 )
  80. bits--;
  81. mask = ( mask >> 1 ) | ( mask << ( 8 * sizeof ( mask ) - 1 ) );
  82. } while ( --found );
  83. return ( bit - num_bits + 1 );
  84. }
  85. /**
  86. * Free offsets within usage bitmask
  87. *
  88. * @v bits Usage bitmask
  89. * @v bit Starting bit within bitmask
  90. * @v num_bits Number of contiguous bits to free within bitmask
  91. */
  92. static void hermon_bitmask_free ( hermon_bitmask_t *bits,
  93. int bit, unsigned int num_bits ) {
  94. hermon_bitmask_t mask;
  95. for ( ; num_bits ; bit++, num_bits-- ) {
  96. mask = ( 1 << ( bit % ( 8 * sizeof ( mask ) ) ) );
  97. bits[ ( bit / ( 8 * sizeof ( mask ) ) ) ] &= ~mask;
  98. }
  99. }
  100. /***************************************************************************
  101. *
  102. * HCA commands
  103. *
  104. ***************************************************************************
  105. */
  106. /**
  107. * Wait for Hermon command completion
  108. *
  109. * @v hermon Hermon device
  110. * @v hcr HCA command registers
  111. * @ret rc Return status code
  112. */
  113. static int hermon_cmd_wait ( struct hermon *hermon,
  114. struct hermonprm_hca_command_register *hcr ) {
  115. unsigned int wait;
  116. for ( wait = HERMON_HCR_MAX_WAIT_MS ; wait ; wait-- ) {
  117. hcr->u.dwords[6] =
  118. readl ( hermon->config + HERMON_HCR_REG ( 6 ) );
  119. if ( ( MLX_GET ( hcr, go ) == 0 ) &&
  120. ( MLX_GET ( hcr, t ) == hermon->toggle ) )
  121. return 0;
  122. mdelay ( 1 );
  123. }
  124. return -EBUSY;
  125. }
  126. /**
  127. * Issue HCA command
  128. *
  129. * @v hermon Hermon device
  130. * @v command Command opcode, flags and input/output lengths
  131. * @v op_mod Opcode modifier (0 if no modifier applicable)
  132. * @v in Input parameters
  133. * @v in_mod Input modifier (0 if no modifier applicable)
  134. * @v out Output parameters
  135. * @ret rc Return status code
  136. */
  137. static int hermon_cmd ( struct hermon *hermon, unsigned long command,
  138. unsigned int op_mod, const void *in,
  139. unsigned int in_mod, void *out ) {
  140. struct hermonprm_hca_command_register hcr;
  141. unsigned int opcode = HERMON_HCR_OPCODE ( command );
  142. size_t in_len = HERMON_HCR_IN_LEN ( command );
  143. size_t out_len = HERMON_HCR_OUT_LEN ( command );
  144. void *in_buffer;
  145. void *out_buffer;
  146. unsigned int status;
  147. unsigned int i;
  148. int rc;
  149. assert ( in_len <= HERMON_MBOX_SIZE );
  150. assert ( out_len <= HERMON_MBOX_SIZE );
  151. DBGC2 ( hermon, "Hermon %p command %02x in %zx%s out %zx%s\n",
  152. hermon, opcode, in_len,
  153. ( ( command & HERMON_HCR_IN_MBOX ) ? "(mbox)" : "" ), out_len,
  154. ( ( command & HERMON_HCR_OUT_MBOX ) ? "(mbox)" : "" ) );
  155. /* Check that HCR is free */
  156. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  157. DBGC ( hermon, "Hermon %p command interface locked\n",
  158. hermon );
  159. return rc;
  160. }
  161. /* Flip HCR toggle */
  162. hermon->toggle = ( 1 - hermon->toggle );
  163. /* Prepare HCR */
  164. memset ( &hcr, 0, sizeof ( hcr ) );
  165. in_buffer = &hcr.u.dwords[0];
  166. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  167. in_buffer = hermon->mailbox_in;
  168. MLX_FILL_1 ( &hcr, 1, in_param_l, virt_to_bus ( in_buffer ) );
  169. }
  170. memcpy ( in_buffer, in, in_len );
  171. MLX_FILL_1 ( &hcr, 2, input_modifier, in_mod );
  172. out_buffer = &hcr.u.dwords[3];
  173. if ( out_len && ( command & HERMON_HCR_OUT_MBOX ) ) {
  174. out_buffer = hermon->mailbox_out;
  175. MLX_FILL_1 ( &hcr, 4, out_param_l,
  176. virt_to_bus ( out_buffer ) );
  177. }
  178. MLX_FILL_4 ( &hcr, 6,
  179. opcode, opcode,
  180. opcode_modifier, op_mod,
  181. go, 1,
  182. t, hermon->toggle );
  183. DBGC ( hermon, "Hermon %p issuing command:\n", hermon );
  184. DBGC_HDA ( hermon, virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  185. &hcr, sizeof ( hcr ) );
  186. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  187. DBGC2 ( hermon, "Input mailbox:\n" );
  188. DBGC2_HDA ( hermon, virt_to_phys ( in_buffer ), in_buffer,
  189. ( ( in_len < 512 ) ? in_len : 512 ) );
  190. }
  191. /* Issue command */
  192. for ( i = 0 ; i < ( sizeof ( hcr ) / sizeof ( hcr.u.dwords[0] ) ) ;
  193. i++ ) {
  194. writel ( hcr.u.dwords[i],
  195. hermon->config + HERMON_HCR_REG ( i ) );
  196. barrier();
  197. }
  198. /* Wait for command completion */
  199. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  200. DBGC ( hermon, "Hermon %p timed out waiting for command:\n",
  201. hermon );
  202. DBGC_HDA ( hermon,
  203. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  204. &hcr, sizeof ( hcr ) );
  205. return rc;
  206. }
  207. /* Check command status */
  208. status = MLX_GET ( &hcr, status );
  209. if ( status != 0 ) {
  210. DBGC ( hermon, "Hermon %p command failed with status %02x:\n",
  211. hermon, status );
  212. DBGC_HDA ( hermon,
  213. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  214. &hcr, sizeof ( hcr ) );
  215. return -EIO;
  216. }
  217. /* Read output parameters, if any */
  218. hcr.u.dwords[3] = readl ( hermon->config + HERMON_HCR_REG ( 3 ) );
  219. hcr.u.dwords[4] = readl ( hermon->config + HERMON_HCR_REG ( 4 ) );
  220. memcpy ( out, out_buffer, out_len );
  221. if ( out_len ) {
  222. DBGC2 ( hermon, "Output%s:\n",
  223. ( command & HERMON_HCR_OUT_MBOX ) ? " mailbox" : "" );
  224. DBGC2_HDA ( hermon, virt_to_phys ( out_buffer ), out_buffer,
  225. ( ( out_len < 512 ) ? out_len : 512 ) );
  226. }
  227. return 0;
  228. }
  229. static inline int
  230. hermon_cmd_query_dev_cap ( struct hermon *hermon,
  231. struct hermonprm_query_dev_cap *dev_cap ) {
  232. return hermon_cmd ( hermon,
  233. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_DEV_CAP,
  234. 1, sizeof ( *dev_cap ) ),
  235. 0, NULL, 0, dev_cap );
  236. }
  237. static inline int
  238. hermon_cmd_query_fw ( struct hermon *hermon, struct hermonprm_query_fw *fw ) {
  239. return hermon_cmd ( hermon,
  240. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_FW,
  241. 1, sizeof ( *fw ) ),
  242. 0, NULL, 0, fw );
  243. }
  244. static inline int
  245. hermon_cmd_init_hca ( struct hermon *hermon,
  246. const struct hermonprm_init_hca *init_hca ) {
  247. return hermon_cmd ( hermon,
  248. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_HCA,
  249. 1, sizeof ( *init_hca ) ),
  250. 0, init_hca, 0, NULL );
  251. }
  252. static inline int
  253. hermon_cmd_close_hca ( struct hermon *hermon ) {
  254. return hermon_cmd ( hermon,
  255. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_HCA ),
  256. 0, NULL, 0, NULL );
  257. }
  258. static inline int
  259. hermon_cmd_init_port ( struct hermon *hermon, unsigned int port,
  260. const struct hermonprm_init_port *init_port ) {
  261. return hermon_cmd ( hermon,
  262. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_PORT,
  263. 1, sizeof ( *init_port ) ),
  264. 0, init_port, port, NULL );
  265. }
  266. static inline int
  267. hermon_cmd_close_port ( struct hermon *hermon, unsigned int port ) {
  268. return hermon_cmd ( hermon,
  269. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_PORT ),
  270. 0, NULL, port, NULL );
  271. }
  272. static inline int
  273. hermon_cmd_sw2hw_mpt ( struct hermon *hermon, unsigned int index,
  274. const struct hermonprm_mpt *mpt ) {
  275. return hermon_cmd ( hermon,
  276. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_MPT,
  277. 1, sizeof ( *mpt ) ),
  278. 0, mpt, index, NULL );
  279. }
  280. static inline int
  281. hermon_cmd_write_mtt ( struct hermon *hermon,
  282. const struct hermonprm_write_mtt *write_mtt ) {
  283. return hermon_cmd ( hermon,
  284. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MTT,
  285. 1, sizeof ( *write_mtt ) ),
  286. 0, write_mtt, 1, NULL );
  287. }
  288. static inline int
  289. hermon_cmd_map_eq ( struct hermon *hermon, unsigned long index_map,
  290. const struct hermonprm_event_mask *mask ) {
  291. return hermon_cmd ( hermon,
  292. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_EQ,
  293. 0, sizeof ( *mask ) ),
  294. 0, mask, index_map, NULL );
  295. }
  296. static inline int
  297. hermon_cmd_sw2hw_eq ( struct hermon *hermon, unsigned int index,
  298. const struct hermonprm_eqc *eqctx ) {
  299. return hermon_cmd ( hermon,
  300. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_EQ,
  301. 1, sizeof ( *eqctx ) ),
  302. 0, eqctx, index, NULL );
  303. }
  304. static inline int
  305. hermon_cmd_hw2sw_eq ( struct hermon *hermon, unsigned int index,
  306. struct hermonprm_eqc *eqctx ) {
  307. return hermon_cmd ( hermon,
  308. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_EQ,
  309. 1, sizeof ( *eqctx ) ),
  310. 1, NULL, index, eqctx );
  311. }
  312. static inline int
  313. hermon_cmd_query_eq ( struct hermon *hermon, unsigned int index,
  314. struct hermonprm_eqc *eqctx ) {
  315. return hermon_cmd ( hermon,
  316. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_EQ,
  317. 1, sizeof ( *eqctx ) ),
  318. 0, NULL, index, eqctx );
  319. }
  320. static inline int
  321. hermon_cmd_sw2hw_cq ( struct hermon *hermon, unsigned long cqn,
  322. const struct hermonprm_completion_queue_context *cqctx ){
  323. return hermon_cmd ( hermon,
  324. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_CQ,
  325. 1, sizeof ( *cqctx ) ),
  326. 0, cqctx, cqn, NULL );
  327. }
  328. static inline int
  329. hermon_cmd_hw2sw_cq ( struct hermon *hermon, unsigned long cqn,
  330. struct hermonprm_completion_queue_context *cqctx) {
  331. return hermon_cmd ( hermon,
  332. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_CQ,
  333. 1, sizeof ( *cqctx ) ),
  334. 0, NULL, cqn, cqctx );
  335. }
  336. static inline int
  337. hermon_cmd_rst2init_qp ( struct hermon *hermon, unsigned long qpn,
  338. const struct hermonprm_qp_ee_state_transitions *ctx ){
  339. return hermon_cmd ( hermon,
  340. HERMON_HCR_IN_CMD ( HERMON_HCR_RST2INIT_QP,
  341. 1, sizeof ( *ctx ) ),
  342. 0, ctx, qpn, NULL );
  343. }
  344. static inline int
  345. hermon_cmd_init2rtr_qp ( struct hermon *hermon, unsigned long qpn,
  346. const struct hermonprm_qp_ee_state_transitions *ctx ){
  347. return hermon_cmd ( hermon,
  348. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT2RTR_QP,
  349. 1, sizeof ( *ctx ) ),
  350. 0, ctx, qpn, NULL );
  351. }
  352. static inline int
  353. hermon_cmd_rtr2rts_qp ( struct hermon *hermon, unsigned long qpn,
  354. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  355. return hermon_cmd ( hermon,
  356. HERMON_HCR_IN_CMD ( HERMON_HCR_RTR2RTS_QP,
  357. 1, sizeof ( *ctx ) ),
  358. 0, ctx, qpn, NULL );
  359. }
  360. static inline int
  361. hermon_cmd_rts2rts_qp ( struct hermon *hermon, unsigned long qpn,
  362. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  363. return hermon_cmd ( hermon,
  364. HERMON_HCR_IN_CMD ( HERMON_HCR_RTS2RTS_QP,
  365. 1, sizeof ( *ctx ) ),
  366. 0, ctx, qpn, NULL );
  367. }
  368. static inline int
  369. hermon_cmd_2rst_qp ( struct hermon *hermon, unsigned long qpn ) {
  370. return hermon_cmd ( hermon,
  371. HERMON_HCR_VOID_CMD ( HERMON_HCR_2RST_QP ),
  372. 0x03, NULL, qpn, NULL );
  373. }
  374. static inline int
  375. hermon_cmd_mad_ifc ( struct hermon *hermon, unsigned int port,
  376. union hermonprm_mad *mad ) {
  377. return hermon_cmd ( hermon,
  378. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MAD_IFC,
  379. 1, sizeof ( *mad ),
  380. 1, sizeof ( *mad ) ),
  381. 0x03, mad, port, mad );
  382. }
  383. static inline int
  384. hermon_cmd_read_mcg ( struct hermon *hermon, unsigned int index,
  385. struct hermonprm_mcg_entry *mcg ) {
  386. return hermon_cmd ( hermon,
  387. HERMON_HCR_OUT_CMD ( HERMON_HCR_READ_MCG,
  388. 1, sizeof ( *mcg ) ),
  389. 0, NULL, index, mcg );
  390. }
  391. static inline int
  392. hermon_cmd_write_mcg ( struct hermon *hermon, unsigned int index,
  393. const struct hermonprm_mcg_entry *mcg ) {
  394. return hermon_cmd ( hermon,
  395. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MCG,
  396. 1, sizeof ( *mcg ) ),
  397. 0, mcg, index, NULL );
  398. }
  399. static inline int
  400. hermon_cmd_mgid_hash ( struct hermon *hermon, const struct ib_gid *gid,
  401. struct hermonprm_mgm_hash *hash ) {
  402. return hermon_cmd ( hermon,
  403. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MGID_HASH,
  404. 1, sizeof ( *gid ),
  405. 0, sizeof ( *hash ) ),
  406. 0, gid, 0, hash );
  407. }
  408. static inline int
  409. hermon_cmd_run_fw ( struct hermon *hermon ) {
  410. return hermon_cmd ( hermon,
  411. HERMON_HCR_VOID_CMD ( HERMON_HCR_RUN_FW ),
  412. 0, NULL, 0, NULL );
  413. }
  414. static inline int
  415. hermon_cmd_unmap_icm ( struct hermon *hermon, unsigned int page_count,
  416. const struct hermonprm_scalar_parameter *offset ) {
  417. return hermon_cmd ( hermon,
  418. HERMON_HCR_IN_CMD ( HERMON_HCR_UNMAP_ICM,
  419. 0, sizeof ( *offset ) ),
  420. 0, offset, page_count, NULL );
  421. }
  422. static inline int
  423. hermon_cmd_map_icm ( struct hermon *hermon,
  424. const struct hermonprm_virtual_physical_mapping *map ) {
  425. return hermon_cmd ( hermon,
  426. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM,
  427. 1, sizeof ( *map ) ),
  428. 0, map, 1, NULL );
  429. }
  430. static inline int
  431. hermon_cmd_unmap_icm_aux ( struct hermon *hermon ) {
  432. return hermon_cmd ( hermon,
  433. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_ICM_AUX ),
  434. 0, NULL, 0, NULL );
  435. }
  436. static inline int
  437. hermon_cmd_map_icm_aux ( struct hermon *hermon,
  438. const struct hermonprm_virtual_physical_mapping *map ) {
  439. return hermon_cmd ( hermon,
  440. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM_AUX,
  441. 1, sizeof ( *map ) ),
  442. 0, map, 1, NULL );
  443. }
  444. static inline int
  445. hermon_cmd_set_icm_size ( struct hermon *hermon,
  446. const struct hermonprm_scalar_parameter *icm_size,
  447. struct hermonprm_scalar_parameter *icm_aux_size ) {
  448. return hermon_cmd ( hermon,
  449. HERMON_HCR_INOUT_CMD ( HERMON_HCR_SET_ICM_SIZE,
  450. 0, sizeof ( *icm_size ),
  451. 0, sizeof (*icm_aux_size) ),
  452. 0, icm_size, 0, icm_aux_size );
  453. }
  454. static inline int
  455. hermon_cmd_unmap_fa ( struct hermon *hermon ) {
  456. return hermon_cmd ( hermon,
  457. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_FA ),
  458. 0, NULL, 0, NULL );
  459. }
  460. static inline int
  461. hermon_cmd_map_fa ( struct hermon *hermon,
  462. const struct hermonprm_virtual_physical_mapping *map ) {
  463. return hermon_cmd ( hermon,
  464. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_FA,
  465. 1, sizeof ( *map ) ),
  466. 0, map, 1, NULL );
  467. }
  468. /***************************************************************************
  469. *
  470. * Memory translation table operations
  471. *
  472. ***************************************************************************
  473. */
  474. /**
  475. * Allocate MTT entries
  476. *
  477. * @v hermon Hermon device
  478. * @v memory Memory to map into MTT
  479. * @v len Length of memory to map
  480. * @v mtt MTT descriptor to fill in
  481. * @ret rc Return status code
  482. */
  483. static int hermon_alloc_mtt ( struct hermon *hermon,
  484. const void *memory, size_t len,
  485. struct hermon_mtt *mtt ) {
  486. struct hermonprm_write_mtt write_mtt;
  487. physaddr_t start;
  488. unsigned int page_offset;
  489. unsigned int num_pages;
  490. int mtt_offset;
  491. unsigned int mtt_base_addr;
  492. unsigned int i;
  493. int rc;
  494. /* Find available MTT entries */
  495. start = virt_to_phys ( memory );
  496. page_offset = ( start & ( HERMON_PAGE_SIZE - 1 ) );
  497. start -= page_offset;
  498. len += page_offset;
  499. num_pages = ( ( len + HERMON_PAGE_SIZE - 1 ) / HERMON_PAGE_SIZE );
  500. mtt_offset = hermon_bitmask_alloc ( hermon->mtt_inuse, HERMON_MAX_MTTS,
  501. num_pages );
  502. if ( mtt_offset < 0 ) {
  503. DBGC ( hermon, "Hermon %p could not allocate %d MTT entries\n",
  504. hermon, num_pages );
  505. rc = mtt_offset;
  506. goto err_mtt_offset;
  507. }
  508. mtt_base_addr = ( ( hermon->cap.reserved_mtts + mtt_offset ) *
  509. hermon->cap.mtt_entry_size );
  510. /* Fill in MTT structure */
  511. mtt->mtt_offset = mtt_offset;
  512. mtt->num_pages = num_pages;
  513. mtt->mtt_base_addr = mtt_base_addr;
  514. mtt->page_offset = page_offset;
  515. /* Construct and issue WRITE_MTT commands */
  516. for ( i = 0 ; i < num_pages ; i++ ) {
  517. memset ( &write_mtt, 0, sizeof ( write_mtt ) );
  518. MLX_FILL_1 ( &write_mtt.mtt_base_addr, 1,
  519. value, mtt_base_addr );
  520. MLX_FILL_2 ( &write_mtt.mtt, 1,
  521. p, 1,
  522. ptag_l, ( start >> 3 ) );
  523. if ( ( rc = hermon_cmd_write_mtt ( hermon,
  524. &write_mtt ) ) != 0 ) {
  525. DBGC ( hermon, "Hermon %p could not write MTT at %x\n",
  526. hermon, mtt_base_addr );
  527. goto err_write_mtt;
  528. }
  529. start += HERMON_PAGE_SIZE;
  530. mtt_base_addr += hermon->cap.mtt_entry_size;
  531. }
  532. return 0;
  533. err_write_mtt:
  534. hermon_bitmask_free ( hermon->mtt_inuse, mtt_offset, num_pages );
  535. err_mtt_offset:
  536. return rc;
  537. }
  538. /**
  539. * Free MTT entries
  540. *
  541. * @v hermon Hermon device
  542. * @v mtt MTT descriptor
  543. */
  544. static void hermon_free_mtt ( struct hermon *hermon,
  545. struct hermon_mtt *mtt ) {
  546. hermon_bitmask_free ( hermon->mtt_inuse, mtt->mtt_offset,
  547. mtt->num_pages );
  548. }
  549. /***************************************************************************
  550. *
  551. * Completion queue operations
  552. *
  553. ***************************************************************************
  554. */
  555. /**
  556. * Create completion queue
  557. *
  558. * @v ibdev Infiniband device
  559. * @v cq Completion queue
  560. * @ret rc Return status code
  561. */
  562. static int hermon_create_cq ( struct ib_device *ibdev,
  563. struct ib_completion_queue *cq ) {
  564. struct hermon *hermon = ib_get_drvdata ( ibdev );
  565. struct hermon_completion_queue *hermon_cq;
  566. struct hermonprm_completion_queue_context cqctx;
  567. int cqn_offset;
  568. unsigned int i;
  569. int rc;
  570. /* Find a free completion queue number */
  571. cqn_offset = hermon_bitmask_alloc ( hermon->cq_inuse,
  572. HERMON_MAX_CQS, 1 );
  573. if ( cqn_offset < 0 ) {
  574. DBGC ( hermon, "Hermon %p out of completion queues\n",
  575. hermon );
  576. rc = cqn_offset;
  577. goto err_cqn_offset;
  578. }
  579. cq->cqn = ( hermon->cap.reserved_cqs + cqn_offset );
  580. /* Allocate control structures */
  581. hermon_cq = zalloc ( sizeof ( *hermon_cq ) );
  582. if ( ! hermon_cq ) {
  583. rc = -ENOMEM;
  584. goto err_hermon_cq;
  585. }
  586. /* Allocate completion queue itself */
  587. hermon_cq->cqe_size = ( cq->num_cqes * sizeof ( hermon_cq->cqe[0] ) );
  588. hermon_cq->cqe = malloc_dma ( hermon_cq->cqe_size,
  589. sizeof ( hermon_cq->cqe[0] ) );
  590. if ( ! hermon_cq->cqe ) {
  591. rc = -ENOMEM;
  592. goto err_cqe;
  593. }
  594. memset ( hermon_cq->cqe, 0, hermon_cq->cqe_size );
  595. for ( i = 0 ; i < cq->num_cqes ; i++ ) {
  596. MLX_FILL_1 ( &hermon_cq->cqe[i].normal, 7, owner, 1 );
  597. }
  598. barrier();
  599. /* Allocate MTT entries */
  600. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_cq->cqe,
  601. hermon_cq->cqe_size,
  602. &hermon_cq->mtt ) ) != 0 )
  603. goto err_alloc_mtt;
  604. /* Hand queue over to hardware */
  605. memset ( &cqctx, 0, sizeof ( cqctx ) );
  606. MLX_FILL_1 ( &cqctx, 0, st, 0xa /* "Event fired" */ );
  607. MLX_FILL_1 ( &cqctx, 2,
  608. page_offset, ( hermon_cq->mtt.page_offset >> 5 ) );
  609. MLX_FILL_2 ( &cqctx, 3,
  610. usr_page, HERMON_UAR_NON_EQ_PAGE,
  611. log_cq_size, fls ( cq->num_cqes - 1 ) );
  612. MLX_FILL_1 ( &cqctx, 7, mtt_base_addr_l,
  613. ( hermon_cq->mtt.mtt_base_addr >> 3 ) );
  614. MLX_FILL_1 ( &cqctx, 15, db_record_addr_l,
  615. ( virt_to_phys ( &hermon_cq->doorbell ) >> 3 ) );
  616. if ( ( rc = hermon_cmd_sw2hw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  617. DBGC ( hermon, "Hermon %p SW2HW_CQ failed: %s\n",
  618. hermon, strerror ( rc ) );
  619. goto err_sw2hw_cq;
  620. }
  621. DBGC ( hermon, "Hermon %p CQN %#lx ring at [%p,%p)\n",
  622. hermon, cq->cqn, hermon_cq->cqe,
  623. ( ( ( void * ) hermon_cq->cqe ) + hermon_cq->cqe_size ) );
  624. ib_cq_set_drvdata ( cq, hermon_cq );
  625. return 0;
  626. err_sw2hw_cq:
  627. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  628. err_alloc_mtt:
  629. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  630. err_cqe:
  631. free ( hermon_cq );
  632. err_hermon_cq:
  633. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  634. err_cqn_offset:
  635. return rc;
  636. }
  637. /**
  638. * Destroy completion queue
  639. *
  640. * @v ibdev Infiniband device
  641. * @v cq Completion queue
  642. */
  643. static void hermon_destroy_cq ( struct ib_device *ibdev,
  644. struct ib_completion_queue *cq ) {
  645. struct hermon *hermon = ib_get_drvdata ( ibdev );
  646. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  647. struct hermonprm_completion_queue_context cqctx;
  648. int cqn_offset;
  649. int rc;
  650. /* Take ownership back from hardware */
  651. if ( ( rc = hermon_cmd_hw2sw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  652. DBGC ( hermon, "Hermon %p FATAL HW2SW_CQ failed on CQN %#lx: "
  653. "%s\n", hermon, cq->cqn, strerror ( rc ) );
  654. /* Leak memory and return; at least we avoid corruption */
  655. return;
  656. }
  657. /* Free MTT entries */
  658. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  659. /* Free memory */
  660. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  661. free ( hermon_cq );
  662. /* Mark queue number as free */
  663. cqn_offset = ( cq->cqn - hermon->cap.reserved_cqs );
  664. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  665. ib_cq_set_drvdata ( cq, NULL );
  666. }
  667. /***************************************************************************
  668. *
  669. * Queue pair operations
  670. *
  671. ***************************************************************************
  672. */
  673. /**
  674. * Create queue pair
  675. *
  676. * @v ibdev Infiniband device
  677. * @v qp Queue pair
  678. * @ret rc Return status code
  679. */
  680. static int hermon_create_qp ( struct ib_device *ibdev,
  681. struct ib_queue_pair *qp ) {
  682. struct hermon *hermon = ib_get_drvdata ( ibdev );
  683. struct hermon_queue_pair *hermon_qp;
  684. struct hermonprm_qp_ee_state_transitions qpctx;
  685. int qpn_offset;
  686. int rc;
  687. /* Find a free queue pair number */
  688. qpn_offset = hermon_bitmask_alloc ( hermon->qp_inuse,
  689. HERMON_MAX_QPS, 1 );
  690. if ( qpn_offset < 0 ) {
  691. DBGC ( hermon, "Hermon %p out of queue pairs\n", hermon );
  692. rc = qpn_offset;
  693. goto err_qpn_offset;
  694. }
  695. qp->qpn = ( HERMON_QPN_BASE + hermon->cap.reserved_qps +
  696. qpn_offset );
  697. /* Allocate control structures */
  698. hermon_qp = zalloc ( sizeof ( *hermon_qp ) );
  699. if ( ! hermon_qp ) {
  700. rc = -ENOMEM;
  701. goto err_hermon_qp;
  702. }
  703. /* Calculate doorbell address */
  704. hermon_qp->send.doorbell =
  705. ( hermon->uar + HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE +
  706. HERMON_DB_POST_SND_OFFSET );
  707. /* Allocate work queue buffer */
  708. hermon_qp->send.num_wqes = ( qp->send.num_wqes /* headroom */ + 1 +
  709. ( 2048 / sizeof ( hermon_qp->send.wqe[0] ) ) );
  710. hermon_qp->send.num_wqes =
  711. ( 1 << fls ( hermon_qp->send.num_wqes - 1 ) ); /* round up */
  712. hermon_qp->send.wqe_size = ( hermon_qp->send.num_wqes *
  713. sizeof ( hermon_qp->send.wqe[0] ) );
  714. hermon_qp->recv.wqe_size = ( qp->recv.num_wqes *
  715. sizeof ( hermon_qp->recv.wqe[0] ) );
  716. hermon_qp->wqe_size = ( hermon_qp->send.wqe_size +
  717. hermon_qp->recv.wqe_size );
  718. hermon_qp->wqe = malloc_dma ( hermon_qp->wqe_size,
  719. sizeof ( hermon_qp->send.wqe[0] ) );
  720. if ( ! hermon_qp->wqe ) {
  721. rc = -ENOMEM;
  722. goto err_alloc_wqe;
  723. }
  724. hermon_qp->send.wqe = hermon_qp->wqe;
  725. memset ( hermon_qp->send.wqe, 0xff, hermon_qp->send.wqe_size );
  726. hermon_qp->recv.wqe = ( hermon_qp->wqe + hermon_qp->send.wqe_size );
  727. memset ( hermon_qp->recv.wqe, 0, hermon_qp->recv.wqe_size );
  728. /* Allocate MTT entries */
  729. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_qp->wqe,
  730. hermon_qp->wqe_size,
  731. &hermon_qp->mtt ) ) != 0 ) {
  732. goto err_alloc_mtt;
  733. }
  734. /* Transition queue to INIT state */
  735. memset ( &qpctx, 0, sizeof ( qpctx ) );
  736. MLX_FILL_2 ( &qpctx, 2,
  737. qpc_eec_data.pm_state, 0x03 /* Always 0x03 for UD */,
  738. qpc_eec_data.st, HERMON_ST_UD );
  739. MLX_FILL_1 ( &qpctx, 3, qpc_eec_data.pd, HERMON_GLOBAL_PD );
  740. MLX_FILL_4 ( &qpctx, 4,
  741. qpc_eec_data.log_rq_size, fls ( qp->recv.num_wqes - 1 ),
  742. qpc_eec_data.log_rq_stride,
  743. ( fls ( sizeof ( hermon_qp->recv.wqe[0] ) - 1 ) - 4 ),
  744. qpc_eec_data.log_sq_size,
  745. fls ( hermon_qp->send.num_wqes - 1 ),
  746. qpc_eec_data.log_sq_stride,
  747. ( fls ( sizeof ( hermon_qp->send.wqe[0] ) - 1 ) - 4 ) );
  748. MLX_FILL_1 ( &qpctx, 5,
  749. qpc_eec_data.usr_page, HERMON_UAR_NON_EQ_PAGE );
  750. MLX_FILL_1 ( &qpctx, 33, qpc_eec_data.cqn_snd, qp->send.cq->cqn );
  751. MLX_FILL_1 ( &qpctx, 38, qpc_eec_data.page_offset,
  752. ( hermon_qp->mtt.page_offset >> 6 ) );
  753. MLX_FILL_1 ( &qpctx, 41, qpc_eec_data.cqn_rcv, qp->recv.cq->cqn );
  754. MLX_FILL_1 ( &qpctx, 43, qpc_eec_data.db_record_addr_l,
  755. ( virt_to_phys ( &hermon_qp->recv.doorbell ) >> 2 ) );
  756. MLX_FILL_1 ( &qpctx, 44, qpc_eec_data.q_key, qp->qkey );
  757. MLX_FILL_1 ( &qpctx, 53, qpc_eec_data.mtt_base_addr_l,
  758. ( hermon_qp->mtt.mtt_base_addr >> 3 ) );
  759. if ( ( rc = hermon_cmd_rst2init_qp ( hermon, qp->qpn,
  760. &qpctx ) ) != 0 ) {
  761. DBGC ( hermon, "Hermon %p RST2INIT_QP failed: %s\n",
  762. hermon, strerror ( rc ) );
  763. goto err_rst2init_qp;
  764. }
  765. /* Transition queue to RTR state */
  766. memset ( &qpctx, 0, sizeof ( qpctx ) );
  767. MLX_FILL_2 ( &qpctx, 4,
  768. qpc_eec_data.mtu, HERMON_MTU_2048,
  769. qpc_eec_data.msg_max, 11 /* 2^11 = 2048 */ );
  770. MLX_FILL_1 ( &qpctx, 16,
  771. qpc_eec_data.primary_address_path.sched_queue,
  772. ( 0x83 /* default policy */ |
  773. ( ( ibdev->port - 1 ) << 6 ) ) );
  774. if ( ( rc = hermon_cmd_init2rtr_qp ( hermon, qp->qpn,
  775. &qpctx ) ) != 0 ) {
  776. DBGC ( hermon, "Hermon %p INIT2RTR_QP failed: %s\n",
  777. hermon, strerror ( rc ) );
  778. goto err_init2rtr_qp;
  779. }
  780. memset ( &qpctx, 0, sizeof ( qpctx ) );
  781. if ( ( rc = hermon_cmd_rtr2rts_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ){
  782. DBGC ( hermon, "Hermon %p RTR2RTS_QP failed: %s\n",
  783. hermon, strerror ( rc ) );
  784. goto err_rtr2rts_qp;
  785. }
  786. DBGC ( hermon, "Hermon %p QPN %#lx send ring at [%p,%p)\n",
  787. hermon, qp->qpn, hermon_qp->send.wqe,
  788. ( ((void *)hermon_qp->send.wqe ) + hermon_qp->send.wqe_size ) );
  789. DBGC ( hermon, "Hermon %p QPN %#lx receive ring at [%p,%p)\n",
  790. hermon, qp->qpn, hermon_qp->recv.wqe,
  791. ( ((void *)hermon_qp->recv.wqe ) + hermon_qp->recv.wqe_size ) );
  792. ib_qp_set_drvdata ( qp, hermon_qp );
  793. return 0;
  794. err_rtr2rts_qp:
  795. err_init2rtr_qp:
  796. hermon_cmd_2rst_qp ( hermon, qp->qpn );
  797. err_rst2init_qp:
  798. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  799. err_alloc_mtt:
  800. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  801. err_alloc_wqe:
  802. free ( hermon_qp );
  803. err_hermon_qp:
  804. hermon_bitmask_free ( hermon->qp_inuse, qpn_offset, 1 );
  805. err_qpn_offset:
  806. return rc;
  807. }
  808. /**
  809. * Modify queue pair
  810. *
  811. * @v ibdev Infiniband device
  812. * @v qp Queue pair
  813. * @v mod_list Modification list
  814. * @ret rc Return status code
  815. */
  816. static int hermon_modify_qp ( struct ib_device *ibdev,
  817. struct ib_queue_pair *qp,
  818. unsigned long mod_list ) {
  819. struct hermon *hermon = ib_get_drvdata ( ibdev );
  820. struct hermonprm_qp_ee_state_transitions qpctx;
  821. unsigned long optparammask = 0;
  822. int rc;
  823. /* Construct optparammask */
  824. if ( mod_list & IB_MODIFY_QKEY )
  825. optparammask |= HERMON_QP_OPT_PARAM_QKEY;
  826. /* Issue RTS2RTS_QP */
  827. memset ( &qpctx, 0, sizeof ( qpctx ) );
  828. MLX_FILL_1 ( &qpctx, 0, opt_param_mask, optparammask );
  829. MLX_FILL_1 ( &qpctx, 44, qpc_eec_data.q_key, qp->qkey );
  830. if ( ( rc = hermon_cmd_rts2rts_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ){
  831. DBGC ( hermon, "Hermon %p RTS2RTS_QP failed: %s\n",
  832. hermon, strerror ( rc ) );
  833. return rc;
  834. }
  835. return 0;
  836. }
  837. /**
  838. * Destroy queue pair
  839. *
  840. * @v ibdev Infiniband device
  841. * @v qp Queue pair
  842. */
  843. static void hermon_destroy_qp ( struct ib_device *ibdev,
  844. struct ib_queue_pair *qp ) {
  845. struct hermon *hermon = ib_get_drvdata ( ibdev );
  846. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  847. int qpn_offset;
  848. int rc;
  849. /* Take ownership back from hardware */
  850. if ( ( rc = hermon_cmd_2rst_qp ( hermon, qp->qpn ) ) != 0 ) {
  851. DBGC ( hermon, "Hermon %p FATAL 2RST_QP failed on QPN %#lx: "
  852. "%s\n", hermon, qp->qpn, strerror ( rc ) );
  853. /* Leak memory and return; at least we avoid corruption */
  854. return;
  855. }
  856. /* Free MTT entries */
  857. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  858. /* Free memory */
  859. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  860. free ( hermon_qp );
  861. /* Mark queue number as free */
  862. qpn_offset = ( qp->qpn - HERMON_QPN_BASE -
  863. hermon->cap.reserved_qps );
  864. hermon_bitmask_free ( hermon->qp_inuse, qpn_offset, 1 );
  865. ib_qp_set_drvdata ( qp, NULL );
  866. }
  867. /***************************************************************************
  868. *
  869. * Work request operations
  870. *
  871. ***************************************************************************
  872. */
  873. /** GID used for GID-less send work queue entries */
  874. static const struct ib_gid hermon_no_gid = {
  875. { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  876. };
  877. /**
  878. * Post send work queue entry
  879. *
  880. * @v ibdev Infiniband device
  881. * @v qp Queue pair
  882. * @v av Address vector
  883. * @v iobuf I/O buffer
  884. * @ret rc Return status code
  885. */
  886. static int hermon_post_send ( struct ib_device *ibdev,
  887. struct ib_queue_pair *qp,
  888. struct ib_address_vector *av,
  889. struct io_buffer *iobuf ) {
  890. struct hermon *hermon = ib_get_drvdata ( ibdev );
  891. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  892. struct ib_work_queue *wq = &qp->send;
  893. struct hermon_send_work_queue *hermon_send_wq = &hermon_qp->send;
  894. struct hermonprm_ud_send_wqe *wqe;
  895. const struct ib_gid *gid;
  896. union hermonprm_doorbell_register db_reg;
  897. unsigned int wqe_idx_mask;
  898. /* Allocate work queue entry */
  899. wqe_idx_mask = ( wq->num_wqes - 1 );
  900. if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) {
  901. DBGC ( hermon, "Hermon %p send queue full", hermon );
  902. return -ENOBUFS;
  903. }
  904. wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf;
  905. wqe = &hermon_send_wq->wqe[ wq->next_idx &
  906. ( hermon_send_wq->num_wqes - 1 ) ].ud;
  907. /* Construct work queue entry */
  908. memset ( ( ( ( void * ) wqe ) + 4 /* avoid ctrl.owner */ ), 0,
  909. ( sizeof ( *wqe ) - 4 ) );
  910. MLX_FILL_1 ( &wqe->ctrl, 1, ds, ( sizeof ( *wqe ) / 16 ) );
  911. MLX_FILL_1 ( &wqe->ctrl, 2, c, 0x03 /* generate completion */ );
  912. MLX_FILL_2 ( &wqe->ud, 0,
  913. ud_address_vector.pd, HERMON_GLOBAL_PD,
  914. ud_address_vector.port_number, ibdev->port );
  915. MLX_FILL_2 ( &wqe->ud, 1,
  916. ud_address_vector.rlid, av->dlid,
  917. ud_address_vector.g, av->gid_present );
  918. MLX_FILL_1 ( &wqe->ud, 2,
  919. ud_address_vector.max_stat_rate,
  920. ( ( ( av->rate < 2 ) || ( av->rate > 10 ) ) ?
  921. 8 : ( av->rate + 5 ) ) );
  922. MLX_FILL_1 ( &wqe->ud, 3, ud_address_vector.sl, av->sl );
  923. gid = ( av->gid_present ? &av->gid : &hermon_no_gid );
  924. memcpy ( &wqe->ud.u.dwords[4], gid, sizeof ( *gid ) );
  925. MLX_FILL_1 ( &wqe->ud, 8, destination_qp, av->dest_qp );
  926. MLX_FILL_1 ( &wqe->ud, 9, q_key, av->qkey );
  927. MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_len ( iobuf ) );
  928. MLX_FILL_1 ( &wqe->data[0], 1, l_key, hermon->reserved_lkey );
  929. MLX_FILL_1 ( &wqe->data[0], 3,
  930. local_address_l, virt_to_bus ( iobuf->data ) );
  931. barrier();
  932. MLX_FILL_2 ( &wqe->ctrl, 0,
  933. opcode, HERMON_OPCODE_SEND,
  934. owner,
  935. ( ( wq->next_idx & hermon_send_wq->num_wqes ) ? 1 : 0 ) );
  936. DBGCP ( hermon, "Hermon %p posting send WQE:\n", hermon );
  937. DBGCP_HD ( hermon, wqe, sizeof ( *wqe ) );
  938. barrier();
  939. /* Ring doorbell register */
  940. MLX_FILL_1 ( &db_reg.send, 0, qn, qp->qpn );
  941. DBGCP ( hermon, "Ringing doorbell %08lx with %08lx\n",
  942. virt_to_phys ( hermon_send_wq->doorbell ), db_reg.dword[0] );
  943. writel ( db_reg.dword[0], ( hermon_send_wq->doorbell ) );
  944. /* Update work queue's index */
  945. wq->next_idx++;
  946. return 0;
  947. }
  948. /**
  949. * Post receive work queue entry
  950. *
  951. * @v ibdev Infiniband device
  952. * @v qp Queue pair
  953. * @v iobuf I/O buffer
  954. * @ret rc Return status code
  955. */
  956. static int hermon_post_recv ( struct ib_device *ibdev,
  957. struct ib_queue_pair *qp,
  958. struct io_buffer *iobuf ) {
  959. struct hermon *hermon = ib_get_drvdata ( ibdev );
  960. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  961. struct ib_work_queue *wq = &qp->recv;
  962. struct hermon_recv_work_queue *hermon_recv_wq = &hermon_qp->recv;
  963. struct hermonprm_recv_wqe *wqe;
  964. unsigned int wqe_idx_mask;
  965. /* Allocate work queue entry */
  966. wqe_idx_mask = ( wq->num_wqes - 1 );
  967. if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) {
  968. DBGC ( hermon, "Hermon %p receive queue full", hermon );
  969. return -ENOBUFS;
  970. }
  971. wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf;
  972. wqe = &hermon_recv_wq->wqe[wq->next_idx & wqe_idx_mask].recv;
  973. /* Construct work queue entry */
  974. MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_tailroom ( iobuf ) );
  975. MLX_FILL_1 ( &wqe->data[0], 1, l_key, hermon->reserved_lkey );
  976. MLX_FILL_1 ( &wqe->data[0], 3,
  977. local_address_l, virt_to_bus ( iobuf->data ) );
  978. /* Update work queue's index */
  979. wq->next_idx++;
  980. /* Update doorbell record */
  981. barrier();
  982. MLX_FILL_1 ( &hermon_recv_wq->doorbell, 0, receive_wqe_counter,
  983. ( wq->next_idx & 0xffff ) );
  984. return 0;
  985. }
  986. /**
  987. * Handle completion
  988. *
  989. * @v ibdev Infiniband device
  990. * @v cq Completion queue
  991. * @v cqe Hardware completion queue entry
  992. * @v complete_send Send completion handler
  993. * @v complete_recv Receive completion handler
  994. * @ret rc Return status code
  995. */
  996. static int hermon_complete ( struct ib_device *ibdev,
  997. struct ib_completion_queue *cq,
  998. union hermonprm_completion_entry *cqe,
  999. ib_completer_t complete_send,
  1000. ib_completer_t complete_recv ) {
  1001. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1002. struct ib_completion completion;
  1003. struct ib_work_queue *wq;
  1004. struct ib_queue_pair *qp;
  1005. struct hermon_queue_pair *hermon_qp;
  1006. struct io_buffer *iobuf;
  1007. ib_completer_t complete;
  1008. unsigned int opcode;
  1009. unsigned long qpn;
  1010. int is_send;
  1011. unsigned int wqe_idx;
  1012. int rc = 0;
  1013. /* Parse completion */
  1014. memset ( &completion, 0, sizeof ( completion ) );
  1015. qpn = MLX_GET ( &cqe->normal, qpn );
  1016. is_send = MLX_GET ( &cqe->normal, s_r );
  1017. opcode = MLX_GET ( &cqe->normal, opcode );
  1018. if ( opcode >= HERMON_OPCODE_RECV_ERROR ) {
  1019. /* "s" field is not valid for error opcodes */
  1020. is_send = ( opcode == HERMON_OPCODE_SEND_ERROR );
  1021. completion.syndrome = MLX_GET ( &cqe->error, syndrome );
  1022. DBGC ( hermon, "Hermon %p CQN %lx syndrome %x vendor %lx\n",
  1023. hermon, cq->cqn, completion.syndrome,
  1024. MLX_GET ( &cqe->error, vendor_error_syndrome ) );
  1025. rc = -EIO;
  1026. /* Don't return immediately; propagate error to completer */
  1027. }
  1028. /* Identify work queue */
  1029. wq = ib_find_wq ( cq, qpn, is_send );
  1030. if ( ! wq ) {
  1031. DBGC ( hermon, "Hermon %p CQN %lx unknown %s QPN %lx\n",
  1032. hermon, cq->cqn, ( is_send ? "send" : "recv" ), qpn );
  1033. return -EIO;
  1034. }
  1035. qp = wq->qp;
  1036. hermon_qp = ib_qp_get_drvdata ( qp );
  1037. /* Identify I/O buffer */
  1038. wqe_idx = ( MLX_GET ( &cqe->normal, wqe_counter ) &
  1039. ( wq->num_wqes - 1 ) );
  1040. iobuf = wq->iobufs[wqe_idx];
  1041. if ( ! iobuf ) {
  1042. DBGC ( hermon, "Hermon %p CQN %lx QPN %lx empty WQE %x\n",
  1043. hermon, cq->cqn, qpn, wqe_idx );
  1044. return -EIO;
  1045. }
  1046. wq->iobufs[wqe_idx] = NULL;
  1047. /* Fill in length for received packets */
  1048. if ( ! is_send ) {
  1049. completion.len = MLX_GET ( &cqe->normal, byte_cnt );
  1050. if ( completion.len > iob_tailroom ( iobuf ) ) {
  1051. DBGC ( hermon, "Hermon %p CQN %lx QPN %lx IDX %x "
  1052. "overlength received packet length %zd\n",
  1053. hermon, cq->cqn, qpn, wqe_idx, completion.len );
  1054. return -EIO;
  1055. }
  1056. }
  1057. /* Pass off to caller's completion handler */
  1058. complete = ( is_send ? complete_send : complete_recv );
  1059. complete ( ibdev, qp, &completion, iobuf );
  1060. return rc;
  1061. }
  1062. /**
  1063. * Poll completion queue
  1064. *
  1065. * @v ibdev Infiniband device
  1066. * @v cq Completion queue
  1067. * @v complete_send Send completion handler
  1068. * @v complete_recv Receive completion handler
  1069. */
  1070. static void hermon_poll_cq ( struct ib_device *ibdev,
  1071. struct ib_completion_queue *cq,
  1072. ib_completer_t complete_send,
  1073. ib_completer_t complete_recv ) {
  1074. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1075. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  1076. union hermonprm_completion_entry *cqe;
  1077. unsigned int cqe_idx_mask;
  1078. int rc;
  1079. while ( 1 ) {
  1080. /* Look for completion entry */
  1081. cqe_idx_mask = ( cq->num_cqes - 1 );
  1082. cqe = &hermon_cq->cqe[cq->next_idx & cqe_idx_mask];
  1083. if ( MLX_GET ( &cqe->normal, owner ) ^
  1084. ( ( cq->next_idx & cq->num_cqes ) ? 1 : 0 ) ) {
  1085. /* Entry still owned by hardware; end of poll */
  1086. break;
  1087. }
  1088. DBGCP ( hermon, "Hermon %p completion:\n", hermon );
  1089. DBGCP_HD ( hermon, cqe, sizeof ( *cqe ) );
  1090. /* Handle completion */
  1091. if ( ( rc = hermon_complete ( ibdev, cq, cqe, complete_send,
  1092. complete_recv ) ) != 0 ) {
  1093. DBGC ( hermon, "Hermon %p failed to complete: %s\n",
  1094. hermon, strerror ( rc ) );
  1095. DBGC_HD ( hermon, cqe, sizeof ( *cqe ) );
  1096. }
  1097. /* Update completion queue's index */
  1098. cq->next_idx++;
  1099. /* Update doorbell record */
  1100. MLX_FILL_1 ( &hermon_cq->doorbell, 0, update_ci,
  1101. ( cq->next_idx & 0x00ffffffUL ) );
  1102. }
  1103. }
  1104. /***************************************************************************
  1105. *
  1106. * Infiniband link-layer operations
  1107. *
  1108. ***************************************************************************
  1109. */
  1110. /**
  1111. * Initialise Infiniband link
  1112. *
  1113. * @v ibdev Infiniband device
  1114. * @ret rc Return status code
  1115. */
  1116. static int hermon_open ( struct ib_device *ibdev ) {
  1117. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1118. struct hermonprm_init_port init_port;
  1119. int rc;
  1120. memset ( &init_port, 0, sizeof ( init_port ) );
  1121. MLX_FILL_2 ( &init_port, 0,
  1122. port_width_cap, 3,
  1123. vl_cap, 1 );
  1124. MLX_FILL_2 ( &init_port, 1,
  1125. mtu, HERMON_MTU_2048,
  1126. max_gid, 1 );
  1127. MLX_FILL_1 ( &init_port, 2, max_pkey, 64 );
  1128. if ( ( rc = hermon_cmd_init_port ( hermon, ibdev->port,
  1129. &init_port ) ) != 0 ) {
  1130. DBGC ( hermon, "Hermon %p could not intialise port: %s\n",
  1131. hermon, strerror ( rc ) );
  1132. return rc;
  1133. }
  1134. return 0;
  1135. }
  1136. /**
  1137. * Close Infiniband link
  1138. *
  1139. * @v ibdev Infiniband device
  1140. */
  1141. static void hermon_close ( struct ib_device *ibdev ) {
  1142. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1143. int rc;
  1144. if ( ( rc = hermon_cmd_close_port ( hermon, ibdev->port ) ) != 0 ) {
  1145. DBGC ( hermon, "Hermon %p could not close port: %s\n",
  1146. hermon, strerror ( rc ) );
  1147. /* Nothing we can do about this */
  1148. }
  1149. }
  1150. /***************************************************************************
  1151. *
  1152. * Multicast group operations
  1153. *
  1154. ***************************************************************************
  1155. */
  1156. /**
  1157. * Attach to multicast group
  1158. *
  1159. * @v ibdev Infiniband device
  1160. * @v qp Queue pair
  1161. * @v gid Multicast GID
  1162. * @ret rc Return status code
  1163. */
  1164. static int hermon_mcast_attach ( struct ib_device *ibdev,
  1165. struct ib_queue_pair *qp,
  1166. struct ib_gid *gid ) {
  1167. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1168. struct hermonprm_mgm_hash hash;
  1169. struct hermonprm_mcg_entry mcg;
  1170. unsigned int index;
  1171. int rc;
  1172. /* Generate hash table index */
  1173. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1174. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1175. hermon, strerror ( rc ) );
  1176. return rc;
  1177. }
  1178. index = MLX_GET ( &hash, hash );
  1179. /* Check for existing hash table entry */
  1180. if ( ( rc = hermon_cmd_read_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1181. DBGC ( hermon, "Hermon %p could not read MCG %#x: %s\n",
  1182. hermon, index, strerror ( rc ) );
  1183. return rc;
  1184. }
  1185. if ( MLX_GET ( &mcg, hdr.members_count ) != 0 ) {
  1186. /* FIXME: this implementation allows only a single QP
  1187. * per multicast group, and doesn't handle hash
  1188. * collisions. Sufficient for IPoIB but may need to
  1189. * be extended in future.
  1190. */
  1191. DBGC ( hermon, "Hermon %p MGID index %#x already in use\n",
  1192. hermon, index );
  1193. return -EBUSY;
  1194. }
  1195. /* Update hash table entry */
  1196. MLX_FILL_1 ( &mcg, 1, hdr.members_count, 1 );
  1197. MLX_FILL_1 ( &mcg, 8, qp[0].qpn, qp->qpn );
  1198. memcpy ( &mcg.u.dwords[4], gid, sizeof ( *gid ) );
  1199. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1200. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1201. hermon, index, strerror ( rc ) );
  1202. return rc;
  1203. }
  1204. return 0;
  1205. }
  1206. /**
  1207. * Detach from multicast group
  1208. *
  1209. * @v ibdev Infiniband device
  1210. * @v qp Queue pair
  1211. * @v gid Multicast GID
  1212. */
  1213. static void hermon_mcast_detach ( struct ib_device *ibdev,
  1214. struct ib_queue_pair *qp __unused,
  1215. struct ib_gid *gid ) {
  1216. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1217. struct hermonprm_mgm_hash hash;
  1218. struct hermonprm_mcg_entry mcg;
  1219. unsigned int index;
  1220. int rc;
  1221. /* Generate hash table index */
  1222. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1223. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1224. hermon, strerror ( rc ) );
  1225. return;
  1226. }
  1227. index = MLX_GET ( &hash, hash );
  1228. /* Clear hash table entry */
  1229. memset ( &mcg, 0, sizeof ( mcg ) );
  1230. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1231. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1232. hermon, index, strerror ( rc ) );
  1233. return;
  1234. }
  1235. }
  1236. /***************************************************************************
  1237. *
  1238. * MAD operations
  1239. *
  1240. ***************************************************************************
  1241. */
  1242. /**
  1243. * Issue management datagram
  1244. *
  1245. * @v ibdev Infiniband device
  1246. * @v mad Management datagram
  1247. * @v len Length of management datagram
  1248. * @ret rc Return status code
  1249. */
  1250. static int hermon_mad ( struct ib_device *ibdev, struct ib_mad_hdr *mad,
  1251. size_t len ) {
  1252. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1253. union hermonprm_mad mad_ifc;
  1254. int rc;
  1255. /* Copy in request packet */
  1256. memset ( &mad_ifc, 0, sizeof ( mad_ifc ) );
  1257. assert ( len <= sizeof ( mad_ifc.mad ) );
  1258. memcpy ( &mad_ifc.mad, mad, len );
  1259. /* Issue MAD */
  1260. if ( ( rc = hermon_cmd_mad_ifc ( hermon, ibdev->port,
  1261. &mad_ifc ) ) != 0 ) {
  1262. DBGC ( hermon, "Hermon %p could not issue MAD IFC: %s\n",
  1263. hermon, strerror ( rc ) );
  1264. return rc;
  1265. }
  1266. /* Copy out reply packet */
  1267. memcpy ( mad, &mad_ifc.mad, len );
  1268. if ( mad->status != 0 ) {
  1269. DBGC ( hermon, "Hermon %p MAD IFC status %04x\n",
  1270. hermon, ntohs ( mad->status ) );
  1271. return -EIO;
  1272. }
  1273. return 0;
  1274. }
  1275. /** Hermon Infiniband operations */
  1276. static struct ib_device_operations hermon_ib_operations = {
  1277. .create_cq = hermon_create_cq,
  1278. .destroy_cq = hermon_destroy_cq,
  1279. .create_qp = hermon_create_qp,
  1280. .modify_qp = hermon_modify_qp,
  1281. .destroy_qp = hermon_destroy_qp,
  1282. .post_send = hermon_post_send,
  1283. .post_recv = hermon_post_recv,
  1284. .poll_cq = hermon_poll_cq,
  1285. .open = hermon_open,
  1286. .close = hermon_close,
  1287. .mcast_attach = hermon_mcast_attach,
  1288. .mcast_detach = hermon_mcast_detach,
  1289. .mad = hermon_mad,
  1290. };
  1291. /***************************************************************************
  1292. *
  1293. * Event queues
  1294. *
  1295. ***************************************************************************
  1296. */
  1297. /**
  1298. * Create event queue
  1299. *
  1300. * @v hermon Hermon device
  1301. * @ret rc Return status code
  1302. */
  1303. static int hermon_create_eq ( struct hermon *hermon ) {
  1304. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1305. struct hermonprm_eqc eqctx;
  1306. struct hermonprm_event_mask mask;
  1307. unsigned int i;
  1308. int rc;
  1309. /* Select event queue number */
  1310. hermon_eq->eqn = ( 4 * hermon->cap.reserved_uars );
  1311. if ( hermon_eq->eqn < hermon->cap.reserved_eqs )
  1312. hermon_eq->eqn = hermon->cap.reserved_eqs;
  1313. /* Calculate doorbell address */
  1314. hermon_eq->doorbell =
  1315. ( hermon->uar + HERMON_DB_EQ_OFFSET ( hermon_eq->eqn ) );
  1316. /* Allocate event queue itself */
  1317. hermon_eq->eqe_size =
  1318. ( HERMON_NUM_EQES * sizeof ( hermon_eq->eqe[0] ) );
  1319. hermon_eq->eqe = malloc_dma ( hermon_eq->eqe_size,
  1320. sizeof ( hermon_eq->eqe[0] ) );
  1321. if ( ! hermon_eq->eqe ) {
  1322. rc = -ENOMEM;
  1323. goto err_eqe;
  1324. }
  1325. memset ( hermon_eq->eqe, 0, hermon_eq->eqe_size );
  1326. for ( i = 0 ; i < HERMON_NUM_EQES ; i++ ) {
  1327. MLX_FILL_1 ( &hermon_eq->eqe[i].generic, 7, owner, 1 );
  1328. }
  1329. barrier();
  1330. /* Allocate MTT entries */
  1331. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_eq->eqe,
  1332. hermon_eq->eqe_size,
  1333. &hermon_eq->mtt ) ) != 0 )
  1334. goto err_alloc_mtt;
  1335. /* Hand queue over to hardware */
  1336. memset ( &eqctx, 0, sizeof ( eqctx ) );
  1337. MLX_FILL_1 ( &eqctx, 0, st, 0xa /* "Fired" */ );
  1338. MLX_FILL_1 ( &eqctx, 2,
  1339. page_offset, ( hermon_eq->mtt.page_offset >> 5 ) );
  1340. MLX_FILL_1 ( &eqctx, 3, log_eq_size, fls ( HERMON_NUM_EQES - 1 ) );
  1341. MLX_FILL_1 ( &eqctx, 7, mtt_base_addr_l,
  1342. ( hermon_eq->mtt.mtt_base_addr >> 3 ) );
  1343. if ( ( rc = hermon_cmd_sw2hw_eq ( hermon, hermon_eq->eqn,
  1344. &eqctx ) ) != 0 ) {
  1345. DBGC ( hermon, "Hermon %p SW2HW_EQ failed: %s\n",
  1346. hermon, strerror ( rc ) );
  1347. goto err_sw2hw_eq;
  1348. }
  1349. /* Map events to this event queue */
  1350. memset ( &mask, 0, sizeof ( mask ) );
  1351. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1352. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1353. ( HERMON_MAP_EQ | hermon_eq->eqn ),
  1354. &mask ) ) != 0 ) {
  1355. DBGC ( hermon, "Hermon %p MAP_EQ failed: %s\n",
  1356. hermon, strerror ( rc ) );
  1357. goto err_map_eq;
  1358. }
  1359. DBGC ( hermon, "Hermon %p EQN %#lx ring at [%p,%p])\n",
  1360. hermon, hermon_eq->eqn, hermon_eq->eqe,
  1361. ( ( ( void * ) hermon_eq->eqe ) + hermon_eq->eqe_size ) );
  1362. return 0;
  1363. err_map_eq:
  1364. hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn, &eqctx );
  1365. err_sw2hw_eq:
  1366. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1367. err_alloc_mtt:
  1368. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1369. err_eqe:
  1370. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1371. return rc;
  1372. }
  1373. /**
  1374. * Destroy event queue
  1375. *
  1376. * @v hermon Hermon device
  1377. */
  1378. static void hermon_destroy_eq ( struct hermon *hermon ) {
  1379. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1380. struct hermonprm_eqc eqctx;
  1381. struct hermonprm_event_mask mask;
  1382. int rc;
  1383. /* Unmap events from event queue */
  1384. memset ( &mask, 0, sizeof ( mask ) );
  1385. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1386. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1387. ( HERMON_UNMAP_EQ | hermon_eq->eqn ),
  1388. &mask ) ) != 0 ) {
  1389. DBGC ( hermon, "Hermon %p FATAL MAP_EQ failed to unmap: %s\n",
  1390. hermon, strerror ( rc ) );
  1391. /* Continue; HCA may die but system should survive */
  1392. }
  1393. /* Take ownership back from hardware */
  1394. if ( ( rc = hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn,
  1395. &eqctx ) ) != 0 ) {
  1396. DBGC ( hermon, "Hermon %p FATAL HW2SW_EQ failed: %s\n",
  1397. hermon, strerror ( rc ) );
  1398. /* Leak memory and return; at least we avoid corruption */
  1399. return;
  1400. }
  1401. /* Free MTT entries */
  1402. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1403. /* Free memory */
  1404. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1405. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1406. }
  1407. /**
  1408. * Handle port state event
  1409. *
  1410. * @v hermon Hermon device
  1411. * @v eqe Port state change event queue entry
  1412. */
  1413. static void hermon_event_port_state_change ( struct hermon *hermon,
  1414. union hermonprm_event_entry *eqe){
  1415. unsigned int port;
  1416. int link_up;
  1417. /* Get port and link status */
  1418. port = ( MLX_GET ( &eqe->port_state_change, data.p ) - 1 );
  1419. link_up = ( MLX_GET ( &eqe->generic, event_sub_type ) & 0x04 );
  1420. DBGC ( hermon, "Hermon %p port %d link %s\n", hermon, ( port + 1 ),
  1421. ( link_up ? "up" : "down" ) );
  1422. /* Sanity check */
  1423. if ( port >= HERMON_NUM_PORTS ) {
  1424. DBGC ( hermon, "Hermon %p port %d does not exist!\n",
  1425. hermon, ( port + 1 ) );
  1426. return;
  1427. }
  1428. /* Notify Infiniband core of link state change */
  1429. ib_link_state_changed ( hermon->ibdev[port] );
  1430. }
  1431. /**
  1432. * Poll event queue
  1433. *
  1434. * @v hermon Hermon device
  1435. */
  1436. static void hermon_poll_eq ( struct hermon *hermon ) {
  1437. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1438. union hermonprm_event_entry *eqe;
  1439. union hermonprm_doorbell_register db_reg;
  1440. unsigned int eqe_idx_mask;
  1441. unsigned int event_type;
  1442. while ( 1 ) {
  1443. /* Look for event entry */
  1444. eqe_idx_mask = ( HERMON_NUM_EQES - 1 );
  1445. eqe = &hermon_eq->eqe[hermon_eq->next_idx & eqe_idx_mask];
  1446. if ( MLX_GET ( &eqe->generic, owner ) ^
  1447. ( ( hermon_eq->next_idx & HERMON_NUM_EQES ) ? 1 : 0 ) ) {
  1448. /* Entry still owned by hardware; end of poll */
  1449. break;
  1450. }
  1451. DBGCP ( hermon, "Hermon %p event:\n", hermon );
  1452. DBGCP_HD ( hermon, eqe, sizeof ( *eqe ) );
  1453. /* Handle event */
  1454. event_type = MLX_GET ( &eqe->generic, event_type );
  1455. switch ( event_type ) {
  1456. case HERMON_EV_PORT_STATE_CHANGE:
  1457. hermon_event_port_state_change ( hermon, eqe );
  1458. break;
  1459. default:
  1460. DBGC ( hermon, "Hermon %p unrecognised event type "
  1461. "%#x:\n", hermon, event_type );
  1462. DBGC_HD ( hermon, eqe, sizeof ( *eqe ) );
  1463. break;
  1464. }
  1465. /* Update event queue's index */
  1466. hermon_eq->next_idx++;
  1467. /* Ring doorbell */
  1468. MLX_FILL_1 ( &db_reg.event, 0,
  1469. ci, ( hermon_eq->next_idx & 0x00ffffffUL ) );
  1470. DBGCP ( hermon, "Ringing doorbell %08lx with %08lx\n",
  1471. virt_to_phys ( hermon_eq->doorbell ),
  1472. db_reg.dword[0] );
  1473. writel ( db_reg.dword[0], hermon_eq->doorbell );
  1474. }
  1475. }
  1476. /**
  1477. * Event queue poll processor
  1478. *
  1479. * @v process Hermon event queue process
  1480. */
  1481. static void hermon_step ( struct process *process ) {
  1482. struct hermon *hermon =
  1483. container_of ( process, struct hermon, event_process );
  1484. hermon_poll_eq ( hermon );
  1485. }
  1486. /***************************************************************************
  1487. *
  1488. * Firmware control
  1489. *
  1490. ***************************************************************************
  1491. */
  1492. /**
  1493. * Start firmware running
  1494. *
  1495. * @v hermon Hermon device
  1496. * @ret rc Return status code
  1497. */
  1498. static int hermon_start_firmware ( struct hermon *hermon ) {
  1499. struct hermonprm_query_fw fw;
  1500. struct hermonprm_virtual_physical_mapping map_fa;
  1501. unsigned int fw_pages;
  1502. unsigned int log2_fw_pages;
  1503. size_t fw_size;
  1504. physaddr_t fw_base;
  1505. int rc;
  1506. /* Get firmware parameters */
  1507. if ( ( rc = hermon_cmd_query_fw ( hermon, &fw ) ) != 0 ) {
  1508. DBGC ( hermon, "Hermon %p could not query firmware: %s\n",
  1509. hermon, strerror ( rc ) );
  1510. goto err_query_fw;
  1511. }
  1512. DBGC ( hermon, "Hermon %p firmware version %ld.%ld.%ld\n", hermon,
  1513. MLX_GET ( &fw, fw_rev_major ), MLX_GET ( &fw, fw_rev_minor ),
  1514. MLX_GET ( &fw, fw_rev_subminor ) );
  1515. fw_pages = MLX_GET ( &fw, fw_pages );
  1516. log2_fw_pages = fls ( fw_pages - 1 );
  1517. fw_pages = ( 1 << log2_fw_pages );
  1518. DBGC ( hermon, "Hermon %p requires %d kB for firmware\n",
  1519. hermon, ( fw_pages * 4 ) );
  1520. /* Allocate firmware pages and map firmware area */
  1521. fw_size = ( fw_pages * HERMON_PAGE_SIZE );
  1522. hermon->firmware_area = umalloc ( fw_size );
  1523. if ( ! hermon->firmware_area ) {
  1524. rc = -ENOMEM;
  1525. goto err_alloc_fa;
  1526. }
  1527. fw_base = ( user_to_phys ( hermon->firmware_area, fw_size ) &
  1528. ~( fw_size - 1 ) );
  1529. DBGC ( hermon, "Hermon %p firmware area at physical [%lx,%lx)\n",
  1530. hermon, fw_base, ( fw_base + fw_size ) );
  1531. memset ( &map_fa, 0, sizeof ( map_fa ) );
  1532. MLX_FILL_2 ( &map_fa, 3,
  1533. log2size, log2_fw_pages,
  1534. pa_l, ( fw_base >> 12 ) );
  1535. if ( ( rc = hermon_cmd_map_fa ( hermon, &map_fa ) ) != 0 ) {
  1536. DBGC ( hermon, "Hermon %p could not map firmware: %s\n",
  1537. hermon, strerror ( rc ) );
  1538. goto err_map_fa;
  1539. }
  1540. /* Start firmware */
  1541. if ( ( rc = hermon_cmd_run_fw ( hermon ) ) != 0 ) {
  1542. DBGC ( hermon, "Hermon %p could not run firmware: %s\n",
  1543. hermon, strerror ( rc ) );
  1544. goto err_run_fw;
  1545. }
  1546. DBGC ( hermon, "Hermon %p firmware started\n", hermon );
  1547. return 0;
  1548. err_run_fw:
  1549. hermon_cmd_unmap_fa ( hermon );
  1550. err_map_fa:
  1551. ufree ( hermon->firmware_area );
  1552. hermon->firmware_area = UNULL;
  1553. err_alloc_fa:
  1554. err_query_fw:
  1555. return rc;
  1556. }
  1557. /**
  1558. * Stop firmware running
  1559. *
  1560. * @v hermon Hermon device
  1561. */
  1562. static void hermon_stop_firmware ( struct hermon *hermon ) {
  1563. int rc;
  1564. if ( ( rc = hermon_cmd_unmap_fa ( hermon ) ) != 0 ) {
  1565. DBGC ( hermon, "Hermon %p FATAL could not stop firmware: %s\n",
  1566. hermon, strerror ( rc ) );
  1567. /* Leak memory and return; at least we avoid corruption */
  1568. return;
  1569. }
  1570. ufree ( hermon->firmware_area );
  1571. hermon->firmware_area = UNULL;
  1572. }
  1573. /***************************************************************************
  1574. *
  1575. * Infinihost Context Memory management
  1576. *
  1577. ***************************************************************************
  1578. */
  1579. /**
  1580. * Get device limits
  1581. *
  1582. * @v hermon Hermon device
  1583. * @ret rc Return status code
  1584. */
  1585. static int hermon_get_cap ( struct hermon *hermon ) {
  1586. struct hermonprm_query_dev_cap dev_cap;
  1587. int rc;
  1588. if ( ( rc = hermon_cmd_query_dev_cap ( hermon, &dev_cap ) ) != 0 ) {
  1589. DBGC ( hermon, "Hermon %p could not get device limits: %s\n",
  1590. hermon, strerror ( rc ) );
  1591. return rc;
  1592. }
  1593. hermon->cap.cmpt_entry_size = MLX_GET ( &dev_cap, c_mpt_entry_sz );
  1594. hermon->cap.reserved_qps =
  1595. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_qps ) );
  1596. hermon->cap.qpc_entry_size = MLX_GET ( &dev_cap, qpc_entry_sz );
  1597. hermon->cap.altc_entry_size = MLX_GET ( &dev_cap, altc_entry_sz );
  1598. hermon->cap.auxc_entry_size = MLX_GET ( &dev_cap, aux_entry_sz );
  1599. hermon->cap.reserved_srqs =
  1600. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_srqs ) );
  1601. hermon->cap.srqc_entry_size = MLX_GET ( &dev_cap, srq_entry_sz );
  1602. hermon->cap.reserved_cqs =
  1603. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_cqs ) );
  1604. hermon->cap.cqc_entry_size = MLX_GET ( &dev_cap, cqc_entry_sz );
  1605. hermon->cap.reserved_eqs = MLX_GET ( &dev_cap, num_rsvd_eqs );
  1606. hermon->cap.eqc_entry_size = MLX_GET ( &dev_cap, eqc_entry_sz );
  1607. hermon->cap.reserved_mtts =
  1608. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mtts ) );
  1609. hermon->cap.mtt_entry_size = MLX_GET ( &dev_cap, mtt_entry_sz );
  1610. hermon->cap.reserved_mrws =
  1611. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mrws ) );
  1612. hermon->cap.dmpt_entry_size = MLX_GET ( &dev_cap, d_mpt_entry_sz );
  1613. hermon->cap.reserved_uars = MLX_GET ( &dev_cap, num_rsvd_uars );
  1614. return 0;
  1615. }
  1616. /**
  1617. * Get ICM usage
  1618. *
  1619. * @v log_num_entries Log2 of the number of entries
  1620. * @v entry_size Entry size
  1621. * @ret usage Usage size in ICM
  1622. */
  1623. static size_t icm_usage ( unsigned int log_num_entries, size_t entry_size ) {
  1624. size_t usage;
  1625. usage = ( ( 1 << log_num_entries ) * entry_size );
  1626. usage = ( ( usage + HERMON_PAGE_SIZE - 1 ) &
  1627. ~( HERMON_PAGE_SIZE - 1 ) );
  1628. return usage;
  1629. }
  1630. /**
  1631. * Allocate ICM
  1632. *
  1633. * @v hermon Hermon device
  1634. * @v init_hca INIT_HCA structure to fill in
  1635. * @ret rc Return status code
  1636. */
  1637. static int hermon_alloc_icm ( struct hermon *hermon,
  1638. struct hermonprm_init_hca *init_hca ) {
  1639. struct hermonprm_scalar_parameter icm_size;
  1640. struct hermonprm_scalar_parameter icm_aux_size;
  1641. struct hermonprm_virtual_physical_mapping map_icm_aux;
  1642. struct hermonprm_virtual_physical_mapping map_icm;
  1643. uint64_t icm_offset = 0;
  1644. unsigned int log_num_qps, log_num_srqs, log_num_cqs, log_num_eqs;
  1645. unsigned int log_num_mtts, log_num_mpts;
  1646. size_t cmpt_max_len;
  1647. size_t qp_cmpt_len, srq_cmpt_len, cq_cmpt_len, eq_cmpt_len;
  1648. size_t icm_len, icm_aux_len;
  1649. physaddr_t icm_phys;
  1650. int i;
  1651. int rc;
  1652. /*
  1653. * Start by carving up the ICM virtual address space
  1654. *
  1655. */
  1656. /* Calculate number of each object type within ICM */
  1657. log_num_qps = fls ( hermon->cap.reserved_qps + HERMON_MAX_QPS - 1 );
  1658. log_num_srqs = fls ( hermon->cap.reserved_srqs - 1 );
  1659. log_num_cqs = fls ( hermon->cap.reserved_cqs + HERMON_MAX_CQS - 1 );
  1660. log_num_eqs = fls ( hermon->cap.reserved_eqs + HERMON_MAX_EQS - 1 );
  1661. log_num_mtts = fls ( hermon->cap.reserved_mtts + HERMON_MAX_MTTS - 1 );
  1662. /* ICM starts with the cMPT tables, which are sparse */
  1663. cmpt_max_len = ( HERMON_CMPT_MAX_ENTRIES *
  1664. ( ( uint64_t ) hermon->cap.cmpt_entry_size ) );
  1665. qp_cmpt_len = icm_usage ( log_num_qps, hermon->cap.cmpt_entry_size );
  1666. hermon->icm_map[HERMON_ICM_QP_CMPT].offset = icm_offset;
  1667. hermon->icm_map[HERMON_ICM_QP_CMPT].len = qp_cmpt_len;
  1668. icm_offset += cmpt_max_len;
  1669. srq_cmpt_len = icm_usage ( log_num_srqs, hermon->cap.cmpt_entry_size );
  1670. hermon->icm_map[HERMON_ICM_SRQ_CMPT].offset = icm_offset;
  1671. hermon->icm_map[HERMON_ICM_SRQ_CMPT].len = srq_cmpt_len;
  1672. icm_offset += cmpt_max_len;
  1673. cq_cmpt_len = icm_usage ( log_num_cqs, hermon->cap.cmpt_entry_size );
  1674. hermon->icm_map[HERMON_ICM_CQ_CMPT].offset = icm_offset;
  1675. hermon->icm_map[HERMON_ICM_CQ_CMPT].len = cq_cmpt_len;
  1676. icm_offset += cmpt_max_len;
  1677. eq_cmpt_len = icm_usage ( log_num_eqs, hermon->cap.cmpt_entry_size );
  1678. hermon->icm_map[HERMON_ICM_EQ_CMPT].offset = icm_offset;
  1679. hermon->icm_map[HERMON_ICM_EQ_CMPT].len = eq_cmpt_len;
  1680. icm_offset += cmpt_max_len;
  1681. hermon->icm_map[HERMON_ICM_OTHER].offset = icm_offset;
  1682. /* Queue pair contexts */
  1683. MLX_FILL_1 ( init_hca, 12,
  1684. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_h,
  1685. ( icm_offset >> 32 ) );
  1686. MLX_FILL_2 ( init_hca, 13,
  1687. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_l,
  1688. ( icm_offset >> 5 ),
  1689. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp,
  1690. log_num_qps );
  1691. DBGC ( hermon, "Hermon %p ICM QPC base = %llx\n", hermon, icm_offset );
  1692. icm_offset += icm_usage ( log_num_qps, hermon->cap.qpc_entry_size );
  1693. /* Extended alternate path contexts */
  1694. MLX_FILL_1 ( init_hca, 24,
  1695. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_h,
  1696. ( icm_offset >> 32 ) );
  1697. MLX_FILL_1 ( init_hca, 25,
  1698. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_l,
  1699. icm_offset );
  1700. DBGC ( hermon, "Hermon %p ICM ALTC base = %llx\n", hermon, icm_offset);
  1701. icm_offset += icm_usage ( log_num_qps,
  1702. hermon->cap.altc_entry_size );
  1703. /* Extended auxiliary contexts */
  1704. MLX_FILL_1 ( init_hca, 28,
  1705. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_h,
  1706. ( icm_offset >> 32 ) );
  1707. MLX_FILL_1 ( init_hca, 29,
  1708. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_l,
  1709. icm_offset );
  1710. DBGC ( hermon, "Hermon %p ICM AUXC base = %llx\n", hermon, icm_offset);
  1711. icm_offset += icm_usage ( log_num_qps,
  1712. hermon->cap.auxc_entry_size );
  1713. /* Shared receive queue contexts */
  1714. MLX_FILL_1 ( init_hca, 18,
  1715. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_h,
  1716. ( icm_offset >> 32 ) );
  1717. MLX_FILL_2 ( init_hca, 19,
  1718. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_l,
  1719. ( icm_offset >> 5 ),
  1720. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_srq,
  1721. log_num_srqs );
  1722. DBGC ( hermon, "Hermon %p ICM SRQC base = %llx\n", hermon, icm_offset);
  1723. icm_offset += icm_usage ( log_num_srqs,
  1724. hermon->cap.srqc_entry_size );
  1725. /* Completion queue contexts */
  1726. MLX_FILL_1 ( init_hca, 20,
  1727. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_h,
  1728. ( icm_offset >> 32 ) );
  1729. MLX_FILL_2 ( init_hca, 21,
  1730. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_l,
  1731. ( icm_offset >> 5 ),
  1732. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq,
  1733. log_num_cqs );
  1734. DBGC ( hermon, "Hermon %p ICM CQC base = %llx\n", hermon, icm_offset );
  1735. icm_offset += icm_usage ( log_num_cqs, hermon->cap.cqc_entry_size );
  1736. /* Event queue contexts */
  1737. MLX_FILL_1 ( init_hca, 32,
  1738. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_h,
  1739. ( icm_offset >> 32 ) );
  1740. MLX_FILL_2 ( init_hca, 33,
  1741. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_l,
  1742. ( icm_offset >> 5 ),
  1743. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_eq,
  1744. log_num_eqs );
  1745. DBGC ( hermon, "Hermon %p ICM EQC base = %llx\n", hermon, icm_offset );
  1746. icm_offset += icm_usage ( log_num_eqs, hermon->cap.eqc_entry_size );
  1747. /* Memory translation table */
  1748. MLX_FILL_1 ( init_hca, 64,
  1749. tpt_parameters.mtt_base_addr_h, ( icm_offset >> 32 ) );
  1750. MLX_FILL_1 ( init_hca, 65,
  1751. tpt_parameters.mtt_base_addr_l, icm_offset );
  1752. DBGC ( hermon, "Hermon %p ICM MTT base = %llx\n", hermon, icm_offset );
  1753. icm_offset += icm_usage ( log_num_mtts,
  1754. hermon->cap.mtt_entry_size );
  1755. /* Memory protection table */
  1756. log_num_mpts = fls ( hermon->cap.reserved_mrws + 1 - 1 );
  1757. MLX_FILL_1 ( init_hca, 60,
  1758. tpt_parameters.dmpt_base_adr_h, ( icm_offset >> 32 ) );
  1759. MLX_FILL_1 ( init_hca, 61,
  1760. tpt_parameters.dmpt_base_adr_l, icm_offset );
  1761. MLX_FILL_1 ( init_hca, 62,
  1762. tpt_parameters.log_dmpt_sz, log_num_mpts );
  1763. DBGC ( hermon, "Hermon %p ICM DMPT base = %llx\n", hermon, icm_offset);
  1764. icm_offset += icm_usage ( log_num_mpts,
  1765. hermon->cap.dmpt_entry_size );
  1766. /* Multicast table */
  1767. MLX_FILL_1 ( init_hca, 48,
  1768. multicast_parameters.mc_base_addr_h,
  1769. ( icm_offset >> 32 ) );
  1770. MLX_FILL_1 ( init_hca, 49,
  1771. multicast_parameters.mc_base_addr_l, icm_offset );
  1772. MLX_FILL_1 ( init_hca, 52,
  1773. multicast_parameters.log_mc_table_entry_sz,
  1774. fls ( sizeof ( struct hermonprm_mcg_entry ) - 1 ) );
  1775. MLX_FILL_1 ( init_hca, 53,
  1776. multicast_parameters.log_mc_table_hash_sz, 3 );
  1777. MLX_FILL_1 ( init_hca, 54,
  1778. multicast_parameters.log_mc_table_sz, 3 );
  1779. DBGC ( hermon, "Hermon %p ICM MC base = %llx\n", hermon, icm_offset );
  1780. icm_offset += ( ( 8 * sizeof ( struct hermonprm_mcg_entry ) +
  1781. HERMON_PAGE_SIZE - 1 ) & ~( HERMON_PAGE_SIZE - 1 ) );
  1782. hermon->icm_map[HERMON_ICM_OTHER].len =
  1783. ( icm_offset - hermon->icm_map[HERMON_ICM_OTHER].offset );
  1784. /*
  1785. * Allocate and map physical memory for (portions of) ICM
  1786. *
  1787. * Map is:
  1788. * ICM AUX area (aligned to its own size)
  1789. * cMPT areas
  1790. * Other areas
  1791. */
  1792. /* Calculate physical memory required for ICM */
  1793. icm_len = 0;
  1794. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  1795. icm_len += hermon->icm_map[i].len;
  1796. }
  1797. /* Get ICM auxiliary area size */
  1798. memset ( &icm_size, 0, sizeof ( icm_size ) );
  1799. MLX_FILL_1 ( &icm_size, 0, value_hi, ( icm_offset >> 32 ) );
  1800. MLX_FILL_1 ( &icm_size, 1, value, icm_offset );
  1801. if ( ( rc = hermon_cmd_set_icm_size ( hermon, &icm_size,
  1802. &icm_aux_size ) ) != 0 ) {
  1803. DBGC ( hermon, "Hermon %p could not set ICM size: %s\n",
  1804. hermon, strerror ( rc ) );
  1805. goto err_set_icm_size;
  1806. }
  1807. icm_aux_len = ( MLX_GET ( &icm_aux_size, value ) * HERMON_PAGE_SIZE );
  1808. /* Must round up to nearest power of two :( */
  1809. icm_aux_len = ( 1 << fls ( icm_aux_len - 1 ) );
  1810. /* Allocate ICM data and auxiliary area */
  1811. DBGC ( hermon, "Hermon %p requires %zd kB ICM and %zd kB AUX ICM\n",
  1812. hermon, ( icm_len / 1024 ), ( icm_aux_len / 1024 ) );
  1813. hermon->icm = umalloc ( 2 * icm_aux_len + icm_len );
  1814. if ( ! hermon->icm ) {
  1815. rc = -ENOMEM;
  1816. goto err_alloc;
  1817. }
  1818. icm_phys = user_to_phys ( hermon->icm, 0 );
  1819. /* Map ICM auxiliary area */
  1820. icm_phys = ( ( icm_phys + icm_aux_len - 1 ) & ~( icm_aux_len - 1 ) );
  1821. memset ( &map_icm_aux, 0, sizeof ( map_icm_aux ) );
  1822. MLX_FILL_2 ( &map_icm_aux, 3,
  1823. log2size, fls ( ( icm_aux_len / HERMON_PAGE_SIZE ) - 1 ),
  1824. pa_l, ( icm_phys >> 12 ) );
  1825. DBGC ( hermon, "Hermon %p mapping ICM AUX (2^%d pages) => %08lx\n",
  1826. hermon, fls ( ( icm_aux_len / HERMON_PAGE_SIZE ) - 1 ),
  1827. icm_phys );
  1828. if ( ( rc = hermon_cmd_map_icm_aux ( hermon, &map_icm_aux ) ) != 0 ) {
  1829. DBGC ( hermon, "Hermon %p could not map AUX ICM: %s\n",
  1830. hermon, strerror ( rc ) );
  1831. goto err_map_icm_aux;
  1832. }
  1833. icm_phys += icm_aux_len;
  1834. /* MAP ICM area */
  1835. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  1836. memset ( &map_icm, 0, sizeof ( map_icm ) );
  1837. MLX_FILL_1 ( &map_icm, 0,
  1838. va_h, ( hermon->icm_map[i].offset >> 32 ) );
  1839. MLX_FILL_1 ( &map_icm, 1,
  1840. va_l, ( hermon->icm_map[i].offset >> 12 ) );
  1841. MLX_FILL_2 ( &map_icm, 3,
  1842. log2size,
  1843. fls ( ( hermon->icm_map[i].len /
  1844. HERMON_PAGE_SIZE ) - 1 ),
  1845. pa_l, ( icm_phys >> 12 ) );
  1846. DBGC ( hermon, "Hermon %p mapping ICM %llx+%zx (2^%d pages) "
  1847. "=> %08lx\n", hermon, hermon->icm_map[i].offset,
  1848. hermon->icm_map[i].len,
  1849. fls ( ( hermon->icm_map[i].len /
  1850. HERMON_PAGE_SIZE ) - 1 ), icm_phys );
  1851. if ( ( rc = hermon_cmd_map_icm ( hermon, &map_icm ) ) != 0 ) {
  1852. DBGC ( hermon, "Hermon %p could not map ICM: %s\n",
  1853. hermon, strerror ( rc ) );
  1854. goto err_map_icm;
  1855. }
  1856. icm_phys += hermon->icm_map[i].len;
  1857. }
  1858. return 0;
  1859. err_map_icm:
  1860. assert ( i == 0 ); /* We don't handle partial failure at present */
  1861. hermon_cmd_unmap_icm_aux ( hermon );
  1862. err_map_icm_aux:
  1863. ufree ( hermon->icm );
  1864. hermon->icm = UNULL;
  1865. err_alloc:
  1866. err_set_icm_size:
  1867. return rc;
  1868. }
  1869. /**
  1870. * Free ICM
  1871. *
  1872. * @v hermon Hermon device
  1873. */
  1874. static void hermon_free_icm ( struct hermon *hermon ) {
  1875. struct hermonprm_scalar_parameter unmap_icm;
  1876. int i;
  1877. for ( i = ( HERMON_ICM_NUM_REGIONS - 1 ) ; i >= 0 ; i-- ) {
  1878. memset ( &unmap_icm, 0, sizeof ( unmap_icm ) );
  1879. MLX_FILL_1 ( &unmap_icm, 0, value_hi,
  1880. ( hermon->icm_map[i].offset >> 32 ) );
  1881. MLX_FILL_1 ( &unmap_icm, 1, value,
  1882. hermon->icm_map[i].offset );
  1883. hermon_cmd_unmap_icm ( hermon,
  1884. ( 1 << fls ( ( hermon->icm_map[i].len /
  1885. HERMON_PAGE_SIZE ) - 1)),
  1886. &unmap_icm );
  1887. }
  1888. hermon_cmd_unmap_icm_aux ( hermon );
  1889. ufree ( hermon->icm );
  1890. hermon->icm = UNULL;
  1891. }
  1892. /***************************************************************************
  1893. *
  1894. * PCI interface
  1895. *
  1896. ***************************************************************************
  1897. */
  1898. /**
  1899. * Set up memory protection table
  1900. *
  1901. * @v hermon Hermon device
  1902. * @ret rc Return status code
  1903. */
  1904. static int hermon_setup_mpt ( struct hermon *hermon ) {
  1905. struct hermonprm_mpt mpt;
  1906. uint32_t key;
  1907. int rc;
  1908. /* Derive key */
  1909. key = ( hermon->cap.reserved_mrws | HERMON_MKEY_PREFIX );
  1910. hermon->reserved_lkey = ( ( key << 8 ) | ( key >> 24 ) );
  1911. /* Initialise memory protection table */
  1912. memset ( &mpt, 0, sizeof ( mpt ) );
  1913. MLX_FILL_4 ( &mpt, 0,
  1914. r_w, 1,
  1915. pa, 1,
  1916. lr, 1,
  1917. lw, 1 );
  1918. MLX_FILL_1 ( &mpt, 2, mem_key, key );
  1919. MLX_FILL_1 ( &mpt, 3, pd, HERMON_GLOBAL_PD );
  1920. MLX_FILL_1 ( &mpt, 10, len64, 1 );
  1921. if ( ( rc = hermon_cmd_sw2hw_mpt ( hermon,
  1922. hermon->cap.reserved_mrws,
  1923. &mpt ) ) != 0 ) {
  1924. DBGC ( hermon, "Hermon %p could not set up MPT: %s\n",
  1925. hermon, strerror ( rc ) );
  1926. return rc;
  1927. }
  1928. return 0;
  1929. }
  1930. /**
  1931. * Probe PCI device
  1932. *
  1933. * @v pci PCI device
  1934. * @v id PCI ID
  1935. * @ret rc Return status code
  1936. */
  1937. static int hermon_probe ( struct pci_device *pci,
  1938. const struct pci_device_id *id __unused ) {
  1939. struct hermon *hermon;
  1940. struct ib_device *ibdev;
  1941. struct hermonprm_init_hca init_hca;
  1942. int i;
  1943. int rc;
  1944. /* Allocate Hermon device */
  1945. hermon = zalloc ( sizeof ( *hermon ) );
  1946. if ( ! hermon ) {
  1947. rc = -ENOMEM;
  1948. goto err_alloc_hermon;
  1949. }
  1950. pci_set_drvdata ( pci, hermon );
  1951. process_init ( &hermon->event_process, hermon_step, NULL );
  1952. /* Allocate Infiniband devices */
  1953. for ( i = 0 ; i < HERMON_NUM_PORTS ; i++ ) {
  1954. ibdev = alloc_ibdev ( 0 );
  1955. if ( ! ibdev ) {
  1956. rc = -ENOMEM;
  1957. goto err_alloc_ibdev;
  1958. }
  1959. hermon->ibdev[i] = ibdev;
  1960. ibdev->op = &hermon_ib_operations;
  1961. ibdev->dev = &pci->dev;
  1962. ibdev->port = ( HERMON_PORT_BASE + i );
  1963. ib_set_drvdata ( ibdev, hermon );
  1964. }
  1965. /* Fix up PCI device */
  1966. adjust_pci_device ( pci );
  1967. /* Get PCI BARs */
  1968. hermon->config = ioremap ( pci_bar_start ( pci, HERMON_PCI_CONFIG_BAR),
  1969. HERMON_PCI_CONFIG_BAR_SIZE );
  1970. hermon->uar = ioremap ( pci_bar_start ( pci, HERMON_PCI_UAR_BAR ),
  1971. HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE );
  1972. /* Allocate space for mailboxes */
  1973. hermon->mailbox_in = malloc_dma ( HERMON_MBOX_SIZE,
  1974. HERMON_MBOX_ALIGN );
  1975. if ( ! hermon->mailbox_in ) {
  1976. rc = -ENOMEM;
  1977. goto err_mailbox_in;
  1978. }
  1979. hermon->mailbox_out = malloc_dma ( HERMON_MBOX_SIZE,
  1980. HERMON_MBOX_ALIGN );
  1981. if ( ! hermon->mailbox_out ) {
  1982. rc = -ENOMEM;
  1983. goto err_mailbox_out;
  1984. }
  1985. /* Start firmware */
  1986. if ( ( rc = hermon_start_firmware ( hermon ) ) != 0 )
  1987. goto err_start_firmware;
  1988. /* Get device limits */
  1989. if ( ( rc = hermon_get_cap ( hermon ) ) != 0 )
  1990. goto err_get_cap;
  1991. /* Allocate ICM */
  1992. memset ( &init_hca, 0, sizeof ( init_hca ) );
  1993. if ( ( rc = hermon_alloc_icm ( hermon, &init_hca ) ) != 0 )
  1994. goto err_alloc_icm;
  1995. /* Initialise HCA */
  1996. MLX_FILL_1 ( &init_hca, 0, version, 0x02 /* "Must be 0x02" */ );
  1997. MLX_FILL_1 ( &init_hca, 5, udp, 1 );
  1998. MLX_FILL_1 ( &init_hca, 74, uar_parameters.log_max_uars, 8 );
  1999. if ( ( rc = hermon_cmd_init_hca ( hermon, &init_hca ) ) != 0 ) {
  2000. DBGC ( hermon, "Hermon %p could not initialise HCA: %s\n",
  2001. hermon, strerror ( rc ) );
  2002. goto err_init_hca;
  2003. }
  2004. /* Set up memory protection */
  2005. if ( ( rc = hermon_setup_mpt ( hermon ) ) != 0 )
  2006. goto err_setup_mpt;
  2007. /* Set up event queue */
  2008. if ( ( rc = hermon_create_eq ( hermon ) ) != 0 )
  2009. goto err_create_eq;
  2010. /* Register Infiniband devices */
  2011. for ( i = 0 ; i < HERMON_NUM_PORTS ; i++ ) {
  2012. if ( ( rc = register_ibdev ( hermon->ibdev[i] ) ) != 0 ) {
  2013. DBGC ( hermon, "Hermon %p could not register IB "
  2014. "device: %s\n", hermon, strerror ( rc ) );
  2015. goto err_register_ibdev;
  2016. }
  2017. }
  2018. return 0;
  2019. i = ( HERMON_NUM_PORTS - 1 );
  2020. err_register_ibdev:
  2021. for ( ; i >= 0 ; i-- )
  2022. unregister_ibdev ( hermon->ibdev[i] );
  2023. hermon_destroy_eq ( hermon );
  2024. err_create_eq:
  2025. err_setup_mpt:
  2026. hermon_cmd_close_hca ( hermon );
  2027. err_init_hca:
  2028. hermon_free_icm ( hermon );
  2029. err_alloc_icm:
  2030. err_get_cap:
  2031. hermon_stop_firmware ( hermon );
  2032. err_start_firmware:
  2033. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2034. err_mailbox_out:
  2035. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2036. err_mailbox_in:
  2037. i = ( HERMON_NUM_PORTS - 1 );
  2038. err_alloc_ibdev:
  2039. for ( ; i >= 0 ; i-- )
  2040. free_ibdev ( hermon->ibdev[i] );
  2041. process_del ( &hermon->event_process );
  2042. free ( hermon );
  2043. err_alloc_hermon:
  2044. return rc;
  2045. }
  2046. /**
  2047. * Remove PCI device
  2048. *
  2049. * @v pci PCI device
  2050. */
  2051. static void hermon_remove ( struct pci_device *pci ) {
  2052. struct hermon *hermon = pci_get_drvdata ( pci );
  2053. int i;
  2054. for ( i = ( HERMON_NUM_PORTS - 1 ) ; i >= 0 ; i-- )
  2055. unregister_ibdev ( hermon->ibdev[i] );
  2056. hermon_destroy_eq ( hermon );
  2057. hermon_cmd_close_hca ( hermon );
  2058. hermon_free_icm ( hermon );
  2059. hermon_stop_firmware ( hermon );
  2060. hermon_stop_firmware ( hermon );
  2061. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2062. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2063. for ( i = ( HERMON_NUM_PORTS - 1 ) ; i >= 0 ; i-- )
  2064. free_ibdev ( hermon->ibdev[i] );
  2065. process_del ( &hermon->event_process );
  2066. free ( hermon );
  2067. }
  2068. static struct pci_device_id hermon_nics[] = {
  2069. PCI_ROM ( 0x15b3, 0x6340, "mt25408", "MT25408 HCA driver" ),
  2070. PCI_ROM ( 0x15b3, 0x634a, "mt25418", "MT25418 HCA driver" ),
  2071. };
  2072. struct pci_driver hermon_driver __pci_driver = {
  2073. .ids = hermon_nics,
  2074. .id_count = ( sizeof ( hermon_nics ) / sizeof ( hermon_nics[0] ) ),
  2075. .probe = hermon_probe,
  2076. .remove = hermon_remove,
  2077. };