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davicom.c 21KB

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  1. #ifdef ALLMULTI
  2. #error multicast support is not yet implemented
  3. #endif
  4. /*
  5. DAVICOM DM9009/DM9102/DM9102A Etherboot Driver V1.00
  6. This driver was ported from Marty Connor's Tulip Etherboot driver.
  7. Thanks Marty Connor (mdc@etherboot.org)
  8. This davicom etherboot driver supports DM9009/DM9102/DM9102A/
  9. DM9102A+DM9801/DM9102A+DM9802 NICs.
  10. This software may be used and distributed according to the terms
  11. of the GNU Public License, incorporated herein by reference.
  12. */
  13. /*********************************************************************/
  14. /* Revision History */
  15. /*********************************************************************/
  16. /*
  17. 19 OCT 2000 Sten 1.00
  18. Different half and full duplex mode
  19. Do the different programming for DM9801/DM9802
  20. 12 OCT 2000 Sten 0.90
  21. This driver was ported from tulip driver and it
  22. has the following difference.
  23. Changed symbol tulip/TULIP to davicom/DAVICOM
  24. Deleted some code that did not use in this driver.
  25. Used chain-strcture to replace ring structure
  26. for both TX/RX descriptor.
  27. Allocated two tx descriptor.
  28. According current media mode to set operating
  29. register(CR6)
  30. */
  31. /*********************************************************************/
  32. /* Declarations */
  33. /*********************************************************************/
  34. #include "etherboot.h"
  35. #include "nic.h"
  36. #include <gpxe/pci.h>
  37. #include <gpxe/ethernet.h>
  38. #undef DAVICOM_DEBUG
  39. #undef DAVICOM_DEBUG_WHERE
  40. #define TX_TIME_OUT 2*TICKS_PER_SEC
  41. /* Register offsets for davicom device */
  42. enum davicom_offsets {
  43. CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
  44. CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58,
  45. CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0
  46. };
  47. /* EEPROM Address width definitions */
  48. #define EEPROM_ADDRLEN 6
  49. #define EEPROM_SIZE 32 /* 1 << EEPROM_ADDRLEN */
  50. /* Used to be 128, but we only need to read enough to get the MAC
  51. address at bytes 20..25 */
  52. /* Data Read from the EEPROM */
  53. static unsigned char ee_data[EEPROM_SIZE];
  54. /* The EEPROM commands include the alway-set leading bit. */
  55. #define EE_WRITE_CMD (5 << addr_len)
  56. #define EE_READ_CMD (6 << addr_len)
  57. #define EE_ERASE_CMD (7 << addr_len)
  58. /* EEPROM_Ctrl bits. */
  59. #define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */
  60. #define EE_CS 0x01 /* EEPROM chip select. */
  61. #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
  62. #define EE_WRITE_0 0x01
  63. #define EE_WRITE_1 0x05
  64. #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
  65. #define EE_ENB (0x4800 | EE_CS)
  66. /* Sten 10/11 for phyxcer */
  67. #define PHY_DATA_0 0x0
  68. #define PHY_DATA_1 0x20000
  69. #define MDCLKH 0x10000
  70. /* Delay between EEPROM clock transitions. Even at 33Mhz current PCI
  71. implementations don't overrun the EEPROM clock. We add a bus
  72. turn-around to insure that this remains true. */
  73. #define eeprom_delay() inl(ee_addr)
  74. /* helpful macro if on a big_endian machine for changing byte order.
  75. not strictly needed on Intel
  76. Already defined in Etherboot includes
  77. #define le16_to_cpu(val) (val)
  78. */
  79. /* transmit and receive descriptor format */
  80. struct txdesc {
  81. volatile unsigned long status; /* owner, status */
  82. unsigned long buf1sz:11, /* size of buffer 1 */
  83. buf2sz:11, /* size of buffer 2 */
  84. control:10; /* control bits */
  85. const unsigned char *buf1addr; /* buffer 1 address */
  86. const unsigned char *buf2addr; /* buffer 2 address */
  87. };
  88. struct rxdesc {
  89. volatile unsigned long status; /* owner, status */
  90. unsigned long buf1sz:11, /* size of buffer 1 */
  91. buf2sz:11, /* size of buffer 2 */
  92. control:10; /* control bits */
  93. unsigned char *buf1addr; /* buffer 1 address */
  94. unsigned char *buf2addr; /* buffer 2 address */
  95. };
  96. /* Size of transmit and receive buffers */
  97. #define BUFLEN 1536
  98. /*********************************************************************/
  99. /* Global Storage */
  100. /*********************************************************************/
  101. static struct nic_operations davicom_operations;
  102. /* PCI Bus parameters */
  103. static unsigned short vendor, dev_id;
  104. static unsigned long ioaddr;
  105. /* Note: transmit and receive buffers must be longword aligned and
  106. longword divisable */
  107. /* transmit descriptor and buffer */
  108. #define NTXD 2
  109. #define NRXD 4
  110. struct {
  111. struct txdesc txd[NTXD] __attribute__ ((aligned(4)));
  112. unsigned char txb[BUFLEN] __attribute__ ((aligned(4)));
  113. struct rxdesc rxd[NRXD] __attribute__ ((aligned(4)));
  114. unsigned char rxb[NRXD * BUFLEN] __attribute__ ((aligned(4)));
  115. } davicom_bufs __shared;
  116. #define txd davicom_bufs.txd
  117. #define txb davicom_bufs.txb
  118. #define rxd davicom_bufs.rxd
  119. #define rxb davicom_bufs.rxb
  120. static int rxd_tail;
  121. static int TxPtr;
  122. /*********************************************************************/
  123. /* Function Prototypes */
  124. /*********************************************************************/
  125. static void whereami(const char *str);
  126. static int read_eeprom(unsigned long ioaddr, int location, int addr_len);
  127. static int davicom_probe(struct nic *nic,struct pci_device *pci);
  128. static void davicom_init_chain(struct nic *nic); /* Sten 10/9 */
  129. static void davicom_reset(struct nic *nic);
  130. static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
  131. unsigned int s, const char *p);
  132. static int davicom_poll(struct nic *nic, int retrieve);
  133. static void davicom_disable(struct nic *nic);
  134. #ifdef DAVICOM_DEBUG
  135. static void davicom_more(void);
  136. #endif /* DAVICOM_DEBUG */
  137. static void davicom_wait(unsigned int nticks);
  138. static int phy_read(int);
  139. static void phy_write(int, u16);
  140. static void phy_write_1bit(u32, u32);
  141. static int phy_read_1bit(u32);
  142. static void davicom_media_chk(struct nic *);
  143. /*********************************************************************/
  144. /* Utility Routines */
  145. /*********************************************************************/
  146. static inline void whereami(const char *str)
  147. {
  148. printf("%s\n", str);
  149. /* sleep(2); */
  150. }
  151. #ifdef DAVICOM_DEBUG
  152. static void davicom_more()
  153. {
  154. printf("\n\n-- more --");
  155. while (!iskey())
  156. /* wait */;
  157. getchar();
  158. printf("\n\n");
  159. }
  160. #endif /* DAVICOM_DEBUG */
  161. static void davicom_wait(unsigned int nticks)
  162. {
  163. unsigned int to = currticks() + nticks;
  164. while (currticks() < to)
  165. /* wait */ ;
  166. }
  167. /*********************************************************************/
  168. /* For DAVICOM phyxcer register by MII interface */
  169. /*********************************************************************/
  170. /*
  171. Read a word data from phy register
  172. */
  173. static int phy_read(int location)
  174. {
  175. int i, phy_addr=1;
  176. u16 phy_data;
  177. u32 io_dcr9;
  178. whereami("phy_read\n");
  179. io_dcr9 = ioaddr + CSR9;
  180. /* Send 33 synchronization clock to Phy controller */
  181. for (i=0; i<34; i++)
  182. phy_write_1bit(io_dcr9, PHY_DATA_1);
  183. /* Send start command(01) to Phy */
  184. phy_write_1bit(io_dcr9, PHY_DATA_0);
  185. phy_write_1bit(io_dcr9, PHY_DATA_1);
  186. /* Send read command(10) to Phy */
  187. phy_write_1bit(io_dcr9, PHY_DATA_1);
  188. phy_write_1bit(io_dcr9, PHY_DATA_0);
  189. /* Send Phy addres */
  190. for (i=0x10; i>0; i=i>>1)
  191. phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
  192. /* Send register addres */
  193. for (i=0x10; i>0; i=i>>1)
  194. phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
  195. /* Skip transition state */
  196. phy_read_1bit(io_dcr9);
  197. /* read 16bit data */
  198. for (phy_data=0, i=0; i<16; i++) {
  199. phy_data<<=1;
  200. phy_data|=phy_read_1bit(io_dcr9);
  201. }
  202. return phy_data;
  203. }
  204. /*
  205. Write a word to Phy register
  206. */
  207. static void phy_write(int location, u16 phy_data)
  208. {
  209. u16 i, phy_addr=1;
  210. u32 io_dcr9;
  211. whereami("phy_write\n");
  212. io_dcr9 = ioaddr + CSR9;
  213. /* Send 33 synchronization clock to Phy controller */
  214. for (i=0; i<34; i++)
  215. phy_write_1bit(io_dcr9, PHY_DATA_1);
  216. /* Send start command(01) to Phy */
  217. phy_write_1bit(io_dcr9, PHY_DATA_0);
  218. phy_write_1bit(io_dcr9, PHY_DATA_1);
  219. /* Send write command(01) to Phy */
  220. phy_write_1bit(io_dcr9, PHY_DATA_0);
  221. phy_write_1bit(io_dcr9, PHY_DATA_1);
  222. /* Send Phy addres */
  223. for (i=0x10; i>0; i=i>>1)
  224. phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
  225. /* Send register addres */
  226. for (i=0x10; i>0; i=i>>1)
  227. phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
  228. /* written trasnition */
  229. phy_write_1bit(io_dcr9, PHY_DATA_1);
  230. phy_write_1bit(io_dcr9, PHY_DATA_0);
  231. /* Write a word data to PHY controller */
  232. for (i=0x8000; i>0; i>>=1)
  233. phy_write_1bit(io_dcr9, phy_data&i ? PHY_DATA_1: PHY_DATA_0);
  234. }
  235. /*
  236. Write one bit data to Phy Controller
  237. */
  238. static void phy_write_1bit(u32 ee_addr, u32 phy_data)
  239. {
  240. whereami("phy_write_1bit\n");
  241. outl(phy_data, ee_addr); /* MII Clock Low */
  242. eeprom_delay();
  243. outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */
  244. eeprom_delay();
  245. outl(phy_data, ee_addr); /* MII Clock Low */
  246. eeprom_delay();
  247. }
  248. /*
  249. Read one bit phy data from PHY controller
  250. */
  251. static int phy_read_1bit(u32 ee_addr)
  252. {
  253. int phy_data;
  254. whereami("phy_read_1bit\n");
  255. outl(0x50000, ee_addr);
  256. eeprom_delay();
  257. phy_data=(inl(ee_addr)>>19) & 0x1;
  258. outl(0x40000, ee_addr);
  259. eeprom_delay();
  260. return phy_data;
  261. }
  262. /*
  263. DM9801/DM9802 present check and program
  264. */
  265. static void HPNA_process(void)
  266. {
  267. if ( (phy_read(3) & 0xfff0) == 0xb900 ) {
  268. if ( phy_read(31) == 0x4404 ) {
  269. /* DM9801 present */
  270. if (phy_read(3) == 0xb901)
  271. phy_write(16, 0x5); /* DM9801 E4 */
  272. else
  273. phy_write(16, 0x1005); /* DM9801 E3 and others */
  274. phy_write(25, ((phy_read(24) + 3) & 0xff) | 0xf000);
  275. } else {
  276. /* DM9802 present */
  277. phy_write(16, 0x5);
  278. phy_write(25, (phy_read(25) & 0xff00) + 2);
  279. }
  280. }
  281. }
  282. /*
  283. Sense media mode and set CR6
  284. */
  285. static void davicom_media_chk(struct nic * nic __unused)
  286. {
  287. unsigned long to, csr6;
  288. csr6 = 0x00200000; /* SF */
  289. outl(csr6, ioaddr + CSR6);
  290. #define PCI_DEVICE_ID_DM9009 0x9009
  291. if (vendor == PCI_VENDOR_ID_DAVICOM && dev_id == PCI_DEVICE_ID_DM9009) {
  292. /* Set to 10BaseT mode for DM9009 */
  293. phy_write(0, 0);
  294. } else {
  295. /* For DM9102/DM9102A */
  296. to = currticks() + 2 * TICKS_PER_SEC;
  297. while ( ((phy_read(1) & 0x24)!=0x24) && (currticks() < to))
  298. /* wait */ ;
  299. if ( (phy_read(1) & 0x24) == 0x24 ) {
  300. if (phy_read(17) & 0xa000)
  301. csr6 |= 0x00000200; /* Full Duplex mode */
  302. } else
  303. csr6 |= 0x00040000; /* Select DM9801/DM9802 when Ethernet link failed */
  304. }
  305. /* set the chip's operating mode */
  306. outl(csr6, ioaddr + CSR6);
  307. /* DM9801/DM9802 present check & program */
  308. if (csr6 & 0x40000)
  309. HPNA_process();
  310. }
  311. /*********************************************************************/
  312. /* EEPROM Reading Code */
  313. /*********************************************************************/
  314. /* EEPROM routines adapted from the Linux Tulip Code */
  315. /* Reading a serial EEPROM is a "bit" grungy, but we work our way
  316. through:->.
  317. */
  318. static int read_eeprom(unsigned long ioaddr, int location, int addr_len)
  319. {
  320. int i;
  321. unsigned short retval = 0;
  322. long ee_addr = ioaddr + CSR9;
  323. int read_cmd = location | EE_READ_CMD;
  324. whereami("read_eeprom\n");
  325. outl(EE_ENB & ~EE_CS, ee_addr);
  326. outl(EE_ENB, ee_addr);
  327. /* Shift the read command bits out. */
  328. for (i = 4 + addr_len; i >= 0; i--) {
  329. short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  330. outl(EE_ENB | dataval, ee_addr);
  331. eeprom_delay();
  332. outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
  333. eeprom_delay();
  334. }
  335. outl(EE_ENB, ee_addr);
  336. for (i = 16; i > 0; i--) {
  337. outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
  338. eeprom_delay();
  339. retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
  340. outl(EE_ENB, ee_addr);
  341. eeprom_delay();
  342. }
  343. /* Terminate the EEPROM access. */
  344. outl(EE_ENB & ~EE_CS, ee_addr);
  345. return retval;
  346. }
  347. /*********************************************************************/
  348. /* davicom_init_chain - setup the tx and rx descriptors */
  349. /* Sten 10/9 */
  350. /*********************************************************************/
  351. static void davicom_init_chain(struct nic *nic)
  352. {
  353. int i;
  354. /* setup the transmit descriptor */
  355. /* Sten: Set 2 TX descriptor but use one TX buffer because
  356. it transmit a packet and wait complete every time. */
  357. for (i=0; i<NTXD; i++) {
  358. txd[i].buf1addr = (void *)virt_to_bus(&txb[0]); /* Used same TX buffer */
  359. txd[i].buf2addr = (void *)virt_to_bus(&txd[i+1]); /* Point to Next TX desc */
  360. txd[i].buf1sz = 0;
  361. txd[i].buf2sz = 0;
  362. txd[i].control = 0x184; /* Begin/End/Chain */
  363. txd[i].status = 0x00000000; /* give ownership to Host */
  364. }
  365. /* construct perfect filter frame with mac address as first match
  366. and broadcast address for all others */
  367. for (i=0; i<192; i++) txb[i] = 0xFF;
  368. txb[0] = nic->node_addr[0];
  369. txb[1] = nic->node_addr[1];
  370. txb[4] = nic->node_addr[2];
  371. txb[5] = nic->node_addr[3];
  372. txb[8] = nic->node_addr[4];
  373. txb[9] = nic->node_addr[5];
  374. /* setup receive descriptor */
  375. for (i=0; i<NRXD; i++) {
  376. rxd[i].buf1addr = (void *)virt_to_bus(&rxb[i * BUFLEN]);
  377. rxd[i].buf2addr = (void *)virt_to_bus(&rxd[i+1]); /* Point to Next RX desc */
  378. rxd[i].buf1sz = BUFLEN;
  379. rxd[i].buf2sz = 0; /* not used */
  380. rxd[i].control = 0x4; /* Chain Structure */
  381. rxd[i].status = 0x80000000; /* give ownership to device */
  382. }
  383. /* Chain the last descriptor to first */
  384. txd[NTXD - 1].buf2addr = (void *)virt_to_bus(&txd[0]);
  385. rxd[NRXD - 1].buf2addr = (void *)virt_to_bus(&rxd[0]);
  386. TxPtr = 0;
  387. rxd_tail = 0;
  388. }
  389. /*********************************************************************/
  390. /* davicom_reset - Reset adapter */
  391. /*********************************************************************/
  392. static void davicom_reset(struct nic *nic)
  393. {
  394. unsigned long to;
  395. whereami("davicom_reset\n");
  396. /* Stop Tx and RX */
  397. outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
  398. /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
  399. outl(0x00000001, ioaddr + CSR0);
  400. davicom_wait(TICKS_PER_SEC);
  401. /* TX/RX descriptor burst */
  402. outl(0x0C00000, ioaddr + CSR0); /* Sten 10/9 */
  403. /* set up transmit and receive descriptors */
  404. davicom_init_chain(nic); /* Sten 10/9 */
  405. /* Point to receive descriptor */
  406. outl(virt_to_bus(&rxd[0]), ioaddr + CSR3);
  407. outl(virt_to_bus(&txd[0]), ioaddr + CSR4); /* Sten 10/9 */
  408. /* According phyxcer media mode to set CR6,
  409. DM9102/A phyxcer can auto-detect media mode */
  410. davicom_media_chk(nic);
  411. /* Prepare Setup Frame Sten 10/9 */
  412. txd[TxPtr].buf1sz = 192;
  413. txd[TxPtr].control = 0x024; /* SF/CE */
  414. txd[TxPtr].status = 0x80000000; /* Give ownership to device */
  415. /* Start Tx */
  416. outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6);
  417. /* immediate transmit demand */
  418. outl(0, ioaddr + CSR1);
  419. to = currticks() + TX_TIME_OUT;
  420. while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) /* Sten 10/9 */
  421. /* wait */ ;
  422. if (currticks() >= to) {
  423. printf ("TX Setup Timeout!\n");
  424. }
  425. /* Point to next TX descriptor */
  426. TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */
  427. #ifdef DAVICOM_DEBUG
  428. printf("txd.status = %X\n", txd.status);
  429. printf("ticks = %d\n", currticks() - (to - TX_TIME_OUT));
  430. davicom_more();
  431. #endif
  432. /* enable RX */
  433. outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6);
  434. /* immediate poll demand */
  435. outl(0, ioaddr + CSR2);
  436. }
  437. /*********************************************************************/
  438. /* eth_transmit - Transmit a frame */
  439. /*********************************************************************/
  440. static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
  441. unsigned int s, const char *p)
  442. {
  443. unsigned long to;
  444. whereami("davicom_transmit\n");
  445. /* Stop Tx */
  446. /* outl(inl(ioaddr + CSR6) & ~0x00002000, ioaddr + CSR6); */
  447. /* setup ethernet header */
  448. memcpy(&txb[0], d, ETH_ALEN); /* DA 6byte */
  449. memcpy(&txb[ETH_ALEN], nic->node_addr, ETH_ALEN); /* SA 6byte*/
  450. txb[ETH_ALEN*2] = (t >> 8) & 0xFF; /* Frame type: 2byte */
  451. txb[ETH_ALEN*2+1] = t & 0xFF;
  452. memcpy(&txb[ETH_HLEN], p, s); /* Frame data */
  453. /* setup the transmit descriptor */
  454. txd[TxPtr].buf1sz = ETH_HLEN+s;
  455. txd[TxPtr].control = 0x00000184; /* LS+FS+CE */
  456. txd[TxPtr].status = 0x80000000; /* give ownership to device */
  457. /* immediate transmit demand */
  458. outl(0, ioaddr + CSR1);
  459. to = currticks() + TX_TIME_OUT;
  460. while ((txd[TxPtr].status & 0x80000000) && (currticks() < to))
  461. /* wait */ ;
  462. if (currticks() >= to) {
  463. printf ("TX Timeout!\n");
  464. }
  465. /* Point to next TX descriptor */
  466. TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */
  467. }
  468. /*********************************************************************/
  469. /* eth_poll - Wait for a frame */
  470. /*********************************************************************/
  471. static int davicom_poll(struct nic *nic, int retrieve)
  472. {
  473. whereami("davicom_poll\n");
  474. if (rxd[rxd_tail].status & 0x80000000)
  475. return 0;
  476. if ( ! retrieve ) return 1;
  477. whereami("davicom_poll got one\n");
  478. nic->packetlen = (rxd[rxd_tail].status & 0x3FFF0000) >> 16;
  479. if( rxd[rxd_tail].status & 0x00008000){
  480. rxd[rxd_tail].status = 0x80000000;
  481. rxd_tail++;
  482. if (rxd_tail == NRXD) rxd_tail = 0;
  483. return 0;
  484. }
  485. /* copy packet to working buffer */
  486. /* XXX - this copy could be avoided with a little more work
  487. but for now we are content with it because the optimised
  488. memcpy is quite fast */
  489. memcpy(nic->packet, rxb + rxd_tail * BUFLEN, nic->packetlen);
  490. /* return the descriptor and buffer to receive ring */
  491. rxd[rxd_tail].status = 0x80000000;
  492. rxd_tail++;
  493. if (rxd_tail == NRXD) rxd_tail = 0;
  494. return 1;
  495. }
  496. /*********************************************************************/
  497. /* eth_disable - Disable the interface */
  498. /*********************************************************************/
  499. static void davicom_disable ( struct nic *nic ) {
  500. whereami("davicom_disable\n");
  501. davicom_reset(nic);
  502. /* disable interrupts */
  503. outl(0x00000000, ioaddr + CSR7);
  504. /* Stop the chip's Tx and Rx processes. */
  505. outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
  506. /* Clear the missed-packet counter. */
  507. (volatile unsigned long)inl(ioaddr + CSR8);
  508. }
  509. /*********************************************************************/
  510. /* eth_irq - enable, disable and force interrupts */
  511. /*********************************************************************/
  512. static void davicom_irq(struct nic *nic __unused, irq_action_t action __unused)
  513. {
  514. switch ( action ) {
  515. case DISABLE :
  516. break;
  517. case ENABLE :
  518. break;
  519. case FORCE :
  520. break;
  521. }
  522. }
  523. /*********************************************************************/
  524. /* eth_probe - Look for an adapter */
  525. /*********************************************************************/
  526. static int davicom_probe ( struct nic *nic, struct pci_device *pci ) {
  527. unsigned int i;
  528. whereami("davicom_probe\n");
  529. if (pci->ioaddr == 0)
  530. return 0;
  531. vendor = pci->vendor;
  532. dev_id = pci->device;
  533. ioaddr = pci->ioaddr;
  534. pci_fill_nic ( nic, pci );
  535. /* wakeup chip */
  536. pci_write_config_dword(pci, 0x40, 0x00000000);
  537. /* Stop the chip's Tx and Rx processes. */
  538. outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
  539. /* Clear the missed-packet counter. */
  540. (volatile unsigned long)inl(ioaddr + CSR8);
  541. /* Get MAC Address */
  542. /* read EEPROM data */
  543. for (i = 0; i < sizeof(ee_data)/2; i++)
  544. ((unsigned short *)ee_data)[i] =
  545. le16_to_cpu(read_eeprom(ioaddr, i, EEPROM_ADDRLEN));
  546. /* extract MAC address from EEPROM buffer */
  547. for (i=0; i<ETH_ALEN; i++)
  548. nic->node_addr[i] = ee_data[20+i];
  549. DBG ( "Davicom %s at IOADDR %4.4lx\n", eth_ntoa ( nic->node_addr ), ioaddr );
  550. /* initialize device */
  551. davicom_reset(nic);
  552. nic->nic_op = &davicom_operations;
  553. return 1;
  554. }
  555. static struct nic_operations davicom_operations = {
  556. .connect = dummy_connect,
  557. .poll = davicom_poll,
  558. .transmit = davicom_transmit,
  559. .irq = davicom_irq,
  560. };
  561. static struct pci_device_id davicom_nics[] = {
  562. PCI_ROM(0x1282, 0x9100, "davicom9100", "Davicom 9100"),
  563. PCI_ROM(0x1282, 0x9102, "davicom9102", "Davicom 9102"),
  564. PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009"),
  565. PCI_ROM(0x1282, 0x9132, "davicom9132", "Davicom 9132"), /* Needs probably some fixing */
  566. };
  567. PCI_DRIVER ( davicom_driver, davicom_nics, PCI_NO_CLASS );
  568. DRIVER ( "DAVICOM", nic_driver, pci_driver, davicom_driver,
  569. davicom_probe, davicom_disable );