Ви не можете вибрати більше 25 тем Теми мають розпочинатися з літери або цифри, можуть містити дефіси (-) і не повинні перевищувати 35 символів.

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311
  1. /*
  2. * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
  3. * Copyright (C) 2008 Mellanox Technologies Ltd.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of the
  8. * License, or any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. FILE_LICENCE ( GPL2_OR_LATER );
  20. #include <stdint.h>
  21. #include <stdlib.h>
  22. #include <stdio.h>
  23. #include <string.h>
  24. #include <strings.h>
  25. #include <unistd.h>
  26. #include <errno.h>
  27. #include <byteswap.h>
  28. #include <gpxe/io.h>
  29. #include <gpxe/pci.h>
  30. #include <gpxe/malloc.h>
  31. #include <gpxe/umalloc.h>
  32. #include <gpxe/iobuf.h>
  33. #include <gpxe/netdevice.h>
  34. #include <gpxe/infiniband.h>
  35. #include <gpxe/ib_smc.h>
  36. #include "hermon.h"
  37. /**
  38. * @file
  39. *
  40. * Mellanox Hermon Infiniband HCA
  41. *
  42. */
  43. /***************************************************************************
  44. *
  45. * Queue number allocation
  46. *
  47. ***************************************************************************
  48. */
  49. /**
  50. * Allocate offsets within usage bitmask
  51. *
  52. * @v bits Usage bitmask
  53. * @v bits_len Length of usage bitmask
  54. * @v num_bits Number of contiguous bits to allocate within bitmask
  55. * @ret bit First free bit within bitmask, or negative error
  56. */
  57. static int hermon_bitmask_alloc ( hermon_bitmask_t *bits,
  58. unsigned int bits_len,
  59. unsigned int num_bits ) {
  60. unsigned int bit = 0;
  61. hermon_bitmask_t mask = 1;
  62. unsigned int found = 0;
  63. /* Search bits for num_bits contiguous free bits */
  64. while ( bit < bits_len ) {
  65. if ( ( mask & *bits ) == 0 ) {
  66. if ( ++found == num_bits )
  67. goto found;
  68. } else {
  69. found = 0;
  70. }
  71. bit++;
  72. mask = ( mask << 1 ) | ( mask >> ( 8 * sizeof ( mask ) - 1 ) );
  73. if ( mask == 1 )
  74. bits++;
  75. }
  76. return -ENFILE;
  77. found:
  78. /* Mark bits as in-use */
  79. do {
  80. *bits |= mask;
  81. if ( mask == 1 )
  82. bits--;
  83. mask = ( mask >> 1 ) | ( mask << ( 8 * sizeof ( mask ) - 1 ) );
  84. } while ( --found );
  85. return ( bit - num_bits + 1 );
  86. }
  87. /**
  88. * Free offsets within usage bitmask
  89. *
  90. * @v bits Usage bitmask
  91. * @v bit Starting bit within bitmask
  92. * @v num_bits Number of contiguous bits to free within bitmask
  93. */
  94. static void hermon_bitmask_free ( hermon_bitmask_t *bits,
  95. int bit, unsigned int num_bits ) {
  96. hermon_bitmask_t mask;
  97. for ( ; num_bits ; bit++, num_bits-- ) {
  98. mask = ( 1 << ( bit % ( 8 * sizeof ( mask ) ) ) );
  99. bits[ ( bit / ( 8 * sizeof ( mask ) ) ) ] &= ~mask;
  100. }
  101. }
  102. /***************************************************************************
  103. *
  104. * HCA commands
  105. *
  106. ***************************************************************************
  107. */
  108. /**
  109. * Wait for Hermon command completion
  110. *
  111. * @v hermon Hermon device
  112. * @v hcr HCA command registers
  113. * @ret rc Return status code
  114. */
  115. static int hermon_cmd_wait ( struct hermon *hermon,
  116. struct hermonprm_hca_command_register *hcr ) {
  117. unsigned int wait;
  118. for ( wait = HERMON_HCR_MAX_WAIT_MS ; wait ; wait-- ) {
  119. hcr->u.dwords[6] =
  120. readl ( hermon->config + HERMON_HCR_REG ( 6 ) );
  121. if ( ( MLX_GET ( hcr, go ) == 0 ) &&
  122. ( MLX_GET ( hcr, t ) == hermon->toggle ) )
  123. return 0;
  124. mdelay ( 1 );
  125. }
  126. return -EBUSY;
  127. }
  128. /**
  129. * Issue HCA command
  130. *
  131. * @v hermon Hermon device
  132. * @v command Command opcode, flags and input/output lengths
  133. * @v op_mod Opcode modifier (0 if no modifier applicable)
  134. * @v in Input parameters
  135. * @v in_mod Input modifier (0 if no modifier applicable)
  136. * @v out Output parameters
  137. * @ret rc Return status code
  138. */
  139. static int hermon_cmd ( struct hermon *hermon, unsigned long command,
  140. unsigned int op_mod, const void *in,
  141. unsigned int in_mod, void *out ) {
  142. struct hermonprm_hca_command_register hcr;
  143. unsigned int opcode = HERMON_HCR_OPCODE ( command );
  144. size_t in_len = HERMON_HCR_IN_LEN ( command );
  145. size_t out_len = HERMON_HCR_OUT_LEN ( command );
  146. void *in_buffer;
  147. void *out_buffer;
  148. unsigned int status;
  149. unsigned int i;
  150. int rc;
  151. assert ( in_len <= HERMON_MBOX_SIZE );
  152. assert ( out_len <= HERMON_MBOX_SIZE );
  153. DBGC2 ( hermon, "Hermon %p command %02x in %zx%s out %zx%s\n",
  154. hermon, opcode, in_len,
  155. ( ( command & HERMON_HCR_IN_MBOX ) ? "(mbox)" : "" ), out_len,
  156. ( ( command & HERMON_HCR_OUT_MBOX ) ? "(mbox)" : "" ) );
  157. /* Check that HCR is free */
  158. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  159. DBGC ( hermon, "Hermon %p command interface locked\n",
  160. hermon );
  161. return rc;
  162. }
  163. /* Flip HCR toggle */
  164. hermon->toggle = ( 1 - hermon->toggle );
  165. /* Prepare HCR */
  166. memset ( &hcr, 0, sizeof ( hcr ) );
  167. in_buffer = &hcr.u.dwords[0];
  168. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  169. in_buffer = hermon->mailbox_in;
  170. MLX_FILL_1 ( &hcr, 1, in_param_l, virt_to_bus ( in_buffer ) );
  171. }
  172. memcpy ( in_buffer, in, in_len );
  173. MLX_FILL_1 ( &hcr, 2, input_modifier, in_mod );
  174. out_buffer = &hcr.u.dwords[3];
  175. if ( out_len && ( command & HERMON_HCR_OUT_MBOX ) ) {
  176. out_buffer = hermon->mailbox_out;
  177. MLX_FILL_1 ( &hcr, 4, out_param_l,
  178. virt_to_bus ( out_buffer ) );
  179. }
  180. MLX_FILL_4 ( &hcr, 6,
  181. opcode, opcode,
  182. opcode_modifier, op_mod,
  183. go, 1,
  184. t, hermon->toggle );
  185. DBGC ( hermon, "Hermon %p issuing command:\n", hermon );
  186. DBGC_HDA ( hermon, virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  187. &hcr, sizeof ( hcr ) );
  188. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  189. DBGC2 ( hermon, "Input mailbox:\n" );
  190. DBGC2_HDA ( hermon, virt_to_phys ( in_buffer ), in_buffer,
  191. ( ( in_len < 512 ) ? in_len : 512 ) );
  192. }
  193. /* Issue command */
  194. for ( i = 0 ; i < ( sizeof ( hcr ) / sizeof ( hcr.u.dwords[0] ) ) ;
  195. i++ ) {
  196. writel ( hcr.u.dwords[i],
  197. hermon->config + HERMON_HCR_REG ( i ) );
  198. barrier();
  199. }
  200. /* Wait for command completion */
  201. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  202. DBGC ( hermon, "Hermon %p timed out waiting for command:\n",
  203. hermon );
  204. DBGC_HDA ( hermon,
  205. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  206. &hcr, sizeof ( hcr ) );
  207. return rc;
  208. }
  209. /* Check command status */
  210. status = MLX_GET ( &hcr, status );
  211. if ( status != 0 ) {
  212. DBGC ( hermon, "Hermon %p command failed with status %02x:\n",
  213. hermon, status );
  214. DBGC_HDA ( hermon,
  215. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  216. &hcr, sizeof ( hcr ) );
  217. return -EIO;
  218. }
  219. /* Read output parameters, if any */
  220. hcr.u.dwords[3] = readl ( hermon->config + HERMON_HCR_REG ( 3 ) );
  221. hcr.u.dwords[4] = readl ( hermon->config + HERMON_HCR_REG ( 4 ) );
  222. memcpy ( out, out_buffer, out_len );
  223. if ( out_len ) {
  224. DBGC2 ( hermon, "Output%s:\n",
  225. ( command & HERMON_HCR_OUT_MBOX ) ? " mailbox" : "" );
  226. DBGC2_HDA ( hermon, virt_to_phys ( out_buffer ), out_buffer,
  227. ( ( out_len < 512 ) ? out_len : 512 ) );
  228. }
  229. return 0;
  230. }
  231. static inline int
  232. hermon_cmd_query_dev_cap ( struct hermon *hermon,
  233. struct hermonprm_query_dev_cap *dev_cap ) {
  234. return hermon_cmd ( hermon,
  235. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_DEV_CAP,
  236. 1, sizeof ( *dev_cap ) ),
  237. 0, NULL, 0, dev_cap );
  238. }
  239. static inline int
  240. hermon_cmd_query_fw ( struct hermon *hermon, struct hermonprm_query_fw *fw ) {
  241. return hermon_cmd ( hermon,
  242. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_FW,
  243. 1, sizeof ( *fw ) ),
  244. 0, NULL, 0, fw );
  245. }
  246. static inline int
  247. hermon_cmd_init_hca ( struct hermon *hermon,
  248. const struct hermonprm_init_hca *init_hca ) {
  249. return hermon_cmd ( hermon,
  250. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_HCA,
  251. 1, sizeof ( *init_hca ) ),
  252. 0, init_hca, 0, NULL );
  253. }
  254. static inline int
  255. hermon_cmd_close_hca ( struct hermon *hermon ) {
  256. return hermon_cmd ( hermon,
  257. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_HCA ),
  258. 0, NULL, 0, NULL );
  259. }
  260. static inline int
  261. hermon_cmd_init_port ( struct hermon *hermon, unsigned int port,
  262. const struct hermonprm_init_port *init_port ) {
  263. return hermon_cmd ( hermon,
  264. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_PORT,
  265. 1, sizeof ( *init_port ) ),
  266. 0, init_port, port, NULL );
  267. }
  268. static inline int
  269. hermon_cmd_close_port ( struct hermon *hermon, unsigned int port ) {
  270. return hermon_cmd ( hermon,
  271. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_PORT ),
  272. 0, NULL, port, NULL );
  273. }
  274. static inline int
  275. hermon_cmd_sw2hw_mpt ( struct hermon *hermon, unsigned int index,
  276. const struct hermonprm_mpt *mpt ) {
  277. return hermon_cmd ( hermon,
  278. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_MPT,
  279. 1, sizeof ( *mpt ) ),
  280. 0, mpt, index, NULL );
  281. }
  282. static inline int
  283. hermon_cmd_write_mtt ( struct hermon *hermon,
  284. const struct hermonprm_write_mtt *write_mtt ) {
  285. return hermon_cmd ( hermon,
  286. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MTT,
  287. 1, sizeof ( *write_mtt ) ),
  288. 0, write_mtt, 1, NULL );
  289. }
  290. static inline int
  291. hermon_cmd_map_eq ( struct hermon *hermon, unsigned long index_map,
  292. const struct hermonprm_event_mask *mask ) {
  293. return hermon_cmd ( hermon,
  294. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_EQ,
  295. 0, sizeof ( *mask ) ),
  296. 0, mask, index_map, NULL );
  297. }
  298. static inline int
  299. hermon_cmd_sw2hw_eq ( struct hermon *hermon, unsigned int index,
  300. const struct hermonprm_eqc *eqctx ) {
  301. return hermon_cmd ( hermon,
  302. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_EQ,
  303. 1, sizeof ( *eqctx ) ),
  304. 0, eqctx, index, NULL );
  305. }
  306. static inline int
  307. hermon_cmd_hw2sw_eq ( struct hermon *hermon, unsigned int index,
  308. struct hermonprm_eqc *eqctx ) {
  309. return hermon_cmd ( hermon,
  310. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_EQ,
  311. 1, sizeof ( *eqctx ) ),
  312. 1, NULL, index, eqctx );
  313. }
  314. static inline int
  315. hermon_cmd_query_eq ( struct hermon *hermon, unsigned int index,
  316. struct hermonprm_eqc *eqctx ) {
  317. return hermon_cmd ( hermon,
  318. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_EQ,
  319. 1, sizeof ( *eqctx ) ),
  320. 0, NULL, index, eqctx );
  321. }
  322. static inline int
  323. hermon_cmd_sw2hw_cq ( struct hermon *hermon, unsigned long cqn,
  324. const struct hermonprm_completion_queue_context *cqctx ){
  325. return hermon_cmd ( hermon,
  326. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_CQ,
  327. 1, sizeof ( *cqctx ) ),
  328. 0, cqctx, cqn, NULL );
  329. }
  330. static inline int
  331. hermon_cmd_hw2sw_cq ( struct hermon *hermon, unsigned long cqn,
  332. struct hermonprm_completion_queue_context *cqctx) {
  333. return hermon_cmd ( hermon,
  334. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_CQ,
  335. 1, sizeof ( *cqctx ) ),
  336. 0, NULL, cqn, cqctx );
  337. }
  338. static inline int
  339. hermon_cmd_rst2init_qp ( struct hermon *hermon, unsigned long qpn,
  340. const struct hermonprm_qp_ee_state_transitions *ctx ){
  341. return hermon_cmd ( hermon,
  342. HERMON_HCR_IN_CMD ( HERMON_HCR_RST2INIT_QP,
  343. 1, sizeof ( *ctx ) ),
  344. 0, ctx, qpn, NULL );
  345. }
  346. static inline int
  347. hermon_cmd_init2rtr_qp ( struct hermon *hermon, unsigned long qpn,
  348. const struct hermonprm_qp_ee_state_transitions *ctx ){
  349. return hermon_cmd ( hermon,
  350. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT2RTR_QP,
  351. 1, sizeof ( *ctx ) ),
  352. 0, ctx, qpn, NULL );
  353. }
  354. static inline int
  355. hermon_cmd_rtr2rts_qp ( struct hermon *hermon, unsigned long qpn,
  356. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  357. return hermon_cmd ( hermon,
  358. HERMON_HCR_IN_CMD ( HERMON_HCR_RTR2RTS_QP,
  359. 1, sizeof ( *ctx ) ),
  360. 0, ctx, qpn, NULL );
  361. }
  362. static inline int
  363. hermon_cmd_rts2rts_qp ( struct hermon *hermon, unsigned long qpn,
  364. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  365. return hermon_cmd ( hermon,
  366. HERMON_HCR_IN_CMD ( HERMON_HCR_RTS2RTS_QP,
  367. 1, sizeof ( *ctx ) ),
  368. 0, ctx, qpn, NULL );
  369. }
  370. static inline int
  371. hermon_cmd_2rst_qp ( struct hermon *hermon, unsigned long qpn ) {
  372. return hermon_cmd ( hermon,
  373. HERMON_HCR_VOID_CMD ( HERMON_HCR_2RST_QP ),
  374. 0x03, NULL, qpn, NULL );
  375. }
  376. static inline int
  377. hermon_cmd_mad_ifc ( struct hermon *hermon, unsigned int port,
  378. union hermonprm_mad *mad ) {
  379. return hermon_cmd ( hermon,
  380. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MAD_IFC,
  381. 1, sizeof ( *mad ),
  382. 1, sizeof ( *mad ) ),
  383. 0x03, mad, port, mad );
  384. }
  385. static inline int
  386. hermon_cmd_read_mcg ( struct hermon *hermon, unsigned int index,
  387. struct hermonprm_mcg_entry *mcg ) {
  388. return hermon_cmd ( hermon,
  389. HERMON_HCR_OUT_CMD ( HERMON_HCR_READ_MCG,
  390. 1, sizeof ( *mcg ) ),
  391. 0, NULL, index, mcg );
  392. }
  393. static inline int
  394. hermon_cmd_write_mcg ( struct hermon *hermon, unsigned int index,
  395. const struct hermonprm_mcg_entry *mcg ) {
  396. return hermon_cmd ( hermon,
  397. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MCG,
  398. 1, sizeof ( *mcg ) ),
  399. 0, mcg, index, NULL );
  400. }
  401. static inline int
  402. hermon_cmd_mgid_hash ( struct hermon *hermon, const struct ib_gid *gid,
  403. struct hermonprm_mgm_hash *hash ) {
  404. return hermon_cmd ( hermon,
  405. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MGID_HASH,
  406. 1, sizeof ( *gid ),
  407. 0, sizeof ( *hash ) ),
  408. 0, gid, 0, hash );
  409. }
  410. static inline int
  411. hermon_cmd_run_fw ( struct hermon *hermon ) {
  412. return hermon_cmd ( hermon,
  413. HERMON_HCR_VOID_CMD ( HERMON_HCR_RUN_FW ),
  414. 0, NULL, 0, NULL );
  415. }
  416. static inline int
  417. hermon_cmd_unmap_icm ( struct hermon *hermon, unsigned int page_count,
  418. const struct hermonprm_scalar_parameter *offset ) {
  419. return hermon_cmd ( hermon,
  420. HERMON_HCR_IN_CMD ( HERMON_HCR_UNMAP_ICM,
  421. 0, sizeof ( *offset ) ),
  422. 0, offset, page_count, NULL );
  423. }
  424. static inline int
  425. hermon_cmd_map_icm ( struct hermon *hermon,
  426. const struct hermonprm_virtual_physical_mapping *map ) {
  427. return hermon_cmd ( hermon,
  428. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM,
  429. 1, sizeof ( *map ) ),
  430. 0, map, 1, NULL );
  431. }
  432. static inline int
  433. hermon_cmd_unmap_icm_aux ( struct hermon *hermon ) {
  434. return hermon_cmd ( hermon,
  435. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_ICM_AUX ),
  436. 0, NULL, 0, NULL );
  437. }
  438. static inline int
  439. hermon_cmd_map_icm_aux ( struct hermon *hermon,
  440. const struct hermonprm_virtual_physical_mapping *map ) {
  441. return hermon_cmd ( hermon,
  442. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM_AUX,
  443. 1, sizeof ( *map ) ),
  444. 0, map, 1, NULL );
  445. }
  446. static inline int
  447. hermon_cmd_set_icm_size ( struct hermon *hermon,
  448. const struct hermonprm_scalar_parameter *icm_size,
  449. struct hermonprm_scalar_parameter *icm_aux_size ) {
  450. return hermon_cmd ( hermon,
  451. HERMON_HCR_INOUT_CMD ( HERMON_HCR_SET_ICM_SIZE,
  452. 0, sizeof ( *icm_size ),
  453. 0, sizeof (*icm_aux_size) ),
  454. 0, icm_size, 0, icm_aux_size );
  455. }
  456. static inline int
  457. hermon_cmd_unmap_fa ( struct hermon *hermon ) {
  458. return hermon_cmd ( hermon,
  459. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_FA ),
  460. 0, NULL, 0, NULL );
  461. }
  462. static inline int
  463. hermon_cmd_map_fa ( struct hermon *hermon,
  464. const struct hermonprm_virtual_physical_mapping *map ) {
  465. return hermon_cmd ( hermon,
  466. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_FA,
  467. 1, sizeof ( *map ) ),
  468. 0, map, 1, NULL );
  469. }
  470. /***************************************************************************
  471. *
  472. * Memory translation table operations
  473. *
  474. ***************************************************************************
  475. */
  476. /**
  477. * Allocate MTT entries
  478. *
  479. * @v hermon Hermon device
  480. * @v memory Memory to map into MTT
  481. * @v len Length of memory to map
  482. * @v mtt MTT descriptor to fill in
  483. * @ret rc Return status code
  484. */
  485. static int hermon_alloc_mtt ( struct hermon *hermon,
  486. const void *memory, size_t len,
  487. struct hermon_mtt *mtt ) {
  488. struct hermonprm_write_mtt write_mtt;
  489. physaddr_t start;
  490. unsigned int page_offset;
  491. unsigned int num_pages;
  492. int mtt_offset;
  493. unsigned int mtt_base_addr;
  494. unsigned int i;
  495. int rc;
  496. /* Find available MTT entries */
  497. start = virt_to_phys ( memory );
  498. page_offset = ( start & ( HERMON_PAGE_SIZE - 1 ) );
  499. start -= page_offset;
  500. len += page_offset;
  501. num_pages = ( ( len + HERMON_PAGE_SIZE - 1 ) / HERMON_PAGE_SIZE );
  502. mtt_offset = hermon_bitmask_alloc ( hermon->mtt_inuse, HERMON_MAX_MTTS,
  503. num_pages );
  504. if ( mtt_offset < 0 ) {
  505. DBGC ( hermon, "Hermon %p could not allocate %d MTT entries\n",
  506. hermon, num_pages );
  507. rc = mtt_offset;
  508. goto err_mtt_offset;
  509. }
  510. mtt_base_addr = ( ( hermon->cap.reserved_mtts + mtt_offset ) *
  511. hermon->cap.mtt_entry_size );
  512. /* Fill in MTT structure */
  513. mtt->mtt_offset = mtt_offset;
  514. mtt->num_pages = num_pages;
  515. mtt->mtt_base_addr = mtt_base_addr;
  516. mtt->page_offset = page_offset;
  517. /* Construct and issue WRITE_MTT commands */
  518. for ( i = 0 ; i < num_pages ; i++ ) {
  519. memset ( &write_mtt, 0, sizeof ( write_mtt ) );
  520. MLX_FILL_1 ( &write_mtt.mtt_base_addr, 1,
  521. value, mtt_base_addr );
  522. MLX_FILL_2 ( &write_mtt.mtt, 1,
  523. p, 1,
  524. ptag_l, ( start >> 3 ) );
  525. if ( ( rc = hermon_cmd_write_mtt ( hermon,
  526. &write_mtt ) ) != 0 ) {
  527. DBGC ( hermon, "Hermon %p could not write MTT at %x\n",
  528. hermon, mtt_base_addr );
  529. goto err_write_mtt;
  530. }
  531. start += HERMON_PAGE_SIZE;
  532. mtt_base_addr += hermon->cap.mtt_entry_size;
  533. }
  534. return 0;
  535. err_write_mtt:
  536. hermon_bitmask_free ( hermon->mtt_inuse, mtt_offset, num_pages );
  537. err_mtt_offset:
  538. return rc;
  539. }
  540. /**
  541. * Free MTT entries
  542. *
  543. * @v hermon Hermon device
  544. * @v mtt MTT descriptor
  545. */
  546. static void hermon_free_mtt ( struct hermon *hermon,
  547. struct hermon_mtt *mtt ) {
  548. hermon_bitmask_free ( hermon->mtt_inuse, mtt->mtt_offset,
  549. mtt->num_pages );
  550. }
  551. /***************************************************************************
  552. *
  553. * MAD operations
  554. *
  555. ***************************************************************************
  556. */
  557. /**
  558. * Issue management datagram
  559. *
  560. * @v ibdev Infiniband device
  561. * @v mad Management datagram
  562. * @ret rc Return status code
  563. */
  564. static int hermon_mad ( struct ib_device *ibdev, union ib_mad *mad ) {
  565. struct hermon *hermon = ib_get_drvdata ( ibdev );
  566. union hermonprm_mad mad_ifc;
  567. int rc;
  568. linker_assert ( sizeof ( *mad ) == sizeof ( mad_ifc.mad ),
  569. mad_size_mismatch );
  570. /* Copy in request packet */
  571. memcpy ( &mad_ifc.mad, mad, sizeof ( mad_ifc.mad ) );
  572. /* Issue MAD */
  573. if ( ( rc = hermon_cmd_mad_ifc ( hermon, ibdev->port,
  574. &mad_ifc ) ) != 0 ) {
  575. DBGC ( hermon, "Hermon %p could not issue MAD IFC: %s\n",
  576. hermon, strerror ( rc ) );
  577. return rc;
  578. }
  579. /* Copy out reply packet */
  580. memcpy ( mad, &mad_ifc.mad, sizeof ( *mad ) );
  581. if ( mad->hdr.status != 0 ) {
  582. DBGC ( hermon, "Hermon %p MAD IFC status %04x\n",
  583. hermon, ntohs ( mad->hdr.status ) );
  584. return -EIO;
  585. }
  586. return 0;
  587. }
  588. /***************************************************************************
  589. *
  590. * Completion queue operations
  591. *
  592. ***************************************************************************
  593. */
  594. /**
  595. * Create completion queue
  596. *
  597. * @v ibdev Infiniband device
  598. * @v cq Completion queue
  599. * @ret rc Return status code
  600. */
  601. static int hermon_create_cq ( struct ib_device *ibdev,
  602. struct ib_completion_queue *cq ) {
  603. struct hermon *hermon = ib_get_drvdata ( ibdev );
  604. struct hermon_completion_queue *hermon_cq;
  605. struct hermonprm_completion_queue_context cqctx;
  606. int cqn_offset;
  607. unsigned int i;
  608. int rc;
  609. /* Find a free completion queue number */
  610. cqn_offset = hermon_bitmask_alloc ( hermon->cq_inuse,
  611. HERMON_MAX_CQS, 1 );
  612. if ( cqn_offset < 0 ) {
  613. DBGC ( hermon, "Hermon %p out of completion queues\n",
  614. hermon );
  615. rc = cqn_offset;
  616. goto err_cqn_offset;
  617. }
  618. cq->cqn = ( hermon->cap.reserved_cqs + cqn_offset );
  619. /* Allocate control structures */
  620. hermon_cq = zalloc ( sizeof ( *hermon_cq ) );
  621. if ( ! hermon_cq ) {
  622. rc = -ENOMEM;
  623. goto err_hermon_cq;
  624. }
  625. /* Allocate completion queue itself */
  626. hermon_cq->cqe_size = ( cq->num_cqes * sizeof ( hermon_cq->cqe[0] ) );
  627. hermon_cq->cqe = malloc_dma ( hermon_cq->cqe_size,
  628. sizeof ( hermon_cq->cqe[0] ) );
  629. if ( ! hermon_cq->cqe ) {
  630. rc = -ENOMEM;
  631. goto err_cqe;
  632. }
  633. memset ( hermon_cq->cqe, 0, hermon_cq->cqe_size );
  634. for ( i = 0 ; i < cq->num_cqes ; i++ ) {
  635. MLX_FILL_1 ( &hermon_cq->cqe[i].normal, 7, owner, 1 );
  636. }
  637. barrier();
  638. /* Allocate MTT entries */
  639. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_cq->cqe,
  640. hermon_cq->cqe_size,
  641. &hermon_cq->mtt ) ) != 0 )
  642. goto err_alloc_mtt;
  643. /* Hand queue over to hardware */
  644. memset ( &cqctx, 0, sizeof ( cqctx ) );
  645. MLX_FILL_1 ( &cqctx, 0, st, 0xa /* "Event fired" */ );
  646. MLX_FILL_1 ( &cqctx, 2,
  647. page_offset, ( hermon_cq->mtt.page_offset >> 5 ) );
  648. MLX_FILL_2 ( &cqctx, 3,
  649. usr_page, HERMON_UAR_NON_EQ_PAGE,
  650. log_cq_size, fls ( cq->num_cqes - 1 ) );
  651. MLX_FILL_1 ( &cqctx, 7, mtt_base_addr_l,
  652. ( hermon_cq->mtt.mtt_base_addr >> 3 ) );
  653. MLX_FILL_1 ( &cqctx, 15, db_record_addr_l,
  654. ( virt_to_phys ( &hermon_cq->doorbell ) >> 3 ) );
  655. if ( ( rc = hermon_cmd_sw2hw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  656. DBGC ( hermon, "Hermon %p SW2HW_CQ failed: %s\n",
  657. hermon, strerror ( rc ) );
  658. goto err_sw2hw_cq;
  659. }
  660. DBGC ( hermon, "Hermon %p CQN %#lx ring at [%p,%p)\n",
  661. hermon, cq->cqn, hermon_cq->cqe,
  662. ( ( ( void * ) hermon_cq->cqe ) + hermon_cq->cqe_size ) );
  663. ib_cq_set_drvdata ( cq, hermon_cq );
  664. return 0;
  665. err_sw2hw_cq:
  666. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  667. err_alloc_mtt:
  668. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  669. err_cqe:
  670. free ( hermon_cq );
  671. err_hermon_cq:
  672. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  673. err_cqn_offset:
  674. return rc;
  675. }
  676. /**
  677. * Destroy completion queue
  678. *
  679. * @v ibdev Infiniband device
  680. * @v cq Completion queue
  681. */
  682. static void hermon_destroy_cq ( struct ib_device *ibdev,
  683. struct ib_completion_queue *cq ) {
  684. struct hermon *hermon = ib_get_drvdata ( ibdev );
  685. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  686. struct hermonprm_completion_queue_context cqctx;
  687. int cqn_offset;
  688. int rc;
  689. /* Take ownership back from hardware */
  690. if ( ( rc = hermon_cmd_hw2sw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  691. DBGC ( hermon, "Hermon %p FATAL HW2SW_CQ failed on CQN %#lx: "
  692. "%s\n", hermon, cq->cqn, strerror ( rc ) );
  693. /* Leak memory and return; at least we avoid corruption */
  694. return;
  695. }
  696. /* Free MTT entries */
  697. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  698. /* Free memory */
  699. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  700. free ( hermon_cq );
  701. /* Mark queue number as free */
  702. cqn_offset = ( cq->cqn - hermon->cap.reserved_cqs );
  703. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  704. ib_cq_set_drvdata ( cq, NULL );
  705. }
  706. /***************************************************************************
  707. *
  708. * Queue pair operations
  709. *
  710. ***************************************************************************
  711. */
  712. /**
  713. * Create queue pair
  714. *
  715. * @v ibdev Infiniband device
  716. * @v qp Queue pair
  717. * @ret rc Return status code
  718. */
  719. static int hermon_create_qp ( struct ib_device *ibdev,
  720. struct ib_queue_pair *qp ) {
  721. struct hermon *hermon = ib_get_drvdata ( ibdev );
  722. struct hermon_queue_pair *hermon_qp;
  723. struct hermonprm_qp_ee_state_transitions qpctx;
  724. int qpn_offset;
  725. int rc;
  726. /* Find a free queue pair number */
  727. qpn_offset = hermon_bitmask_alloc ( hermon->qp_inuse,
  728. HERMON_MAX_QPS, 1 );
  729. if ( qpn_offset < 0 ) {
  730. DBGC ( hermon, "Hermon %p out of queue pairs\n", hermon );
  731. rc = qpn_offset;
  732. goto err_qpn_offset;
  733. }
  734. qp->qpn = ( HERMON_QPN_BASE + hermon->cap.reserved_qps +
  735. qpn_offset );
  736. /* Allocate control structures */
  737. hermon_qp = zalloc ( sizeof ( *hermon_qp ) );
  738. if ( ! hermon_qp ) {
  739. rc = -ENOMEM;
  740. goto err_hermon_qp;
  741. }
  742. /* Calculate doorbell address */
  743. hermon_qp->send.doorbell =
  744. ( hermon->uar + HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE +
  745. HERMON_DB_POST_SND_OFFSET );
  746. /* Allocate work queue buffer */
  747. hermon_qp->send.num_wqes = ( qp->send.num_wqes /* headroom */ + 1 +
  748. ( 2048 / sizeof ( hermon_qp->send.wqe[0] ) ) );
  749. hermon_qp->send.num_wqes =
  750. ( 1 << fls ( hermon_qp->send.num_wqes - 1 ) ); /* round up */
  751. hermon_qp->send.wqe_size = ( hermon_qp->send.num_wqes *
  752. sizeof ( hermon_qp->send.wqe[0] ) );
  753. hermon_qp->recv.wqe_size = ( qp->recv.num_wqes *
  754. sizeof ( hermon_qp->recv.wqe[0] ) );
  755. hermon_qp->wqe_size = ( hermon_qp->send.wqe_size +
  756. hermon_qp->recv.wqe_size );
  757. hermon_qp->wqe = malloc_dma ( hermon_qp->wqe_size,
  758. sizeof ( hermon_qp->send.wqe[0] ) );
  759. if ( ! hermon_qp->wqe ) {
  760. rc = -ENOMEM;
  761. goto err_alloc_wqe;
  762. }
  763. hermon_qp->send.wqe = hermon_qp->wqe;
  764. memset ( hermon_qp->send.wqe, 0xff, hermon_qp->send.wqe_size );
  765. hermon_qp->recv.wqe = ( hermon_qp->wqe + hermon_qp->send.wqe_size );
  766. memset ( hermon_qp->recv.wqe, 0, hermon_qp->recv.wqe_size );
  767. /* Allocate MTT entries */
  768. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_qp->wqe,
  769. hermon_qp->wqe_size,
  770. &hermon_qp->mtt ) ) != 0 ) {
  771. goto err_alloc_mtt;
  772. }
  773. /* Transition queue to INIT state */
  774. memset ( &qpctx, 0, sizeof ( qpctx ) );
  775. MLX_FILL_2 ( &qpctx, 2,
  776. qpc_eec_data.pm_state, 0x03 /* Always 0x03 for UD */,
  777. qpc_eec_data.st, HERMON_ST_UD );
  778. MLX_FILL_1 ( &qpctx, 3, qpc_eec_data.pd, HERMON_GLOBAL_PD );
  779. MLX_FILL_4 ( &qpctx, 4,
  780. qpc_eec_data.log_rq_size, fls ( qp->recv.num_wqes - 1 ),
  781. qpc_eec_data.log_rq_stride,
  782. ( fls ( sizeof ( hermon_qp->recv.wqe[0] ) - 1 ) - 4 ),
  783. qpc_eec_data.log_sq_size,
  784. fls ( hermon_qp->send.num_wqes - 1 ),
  785. qpc_eec_data.log_sq_stride,
  786. ( fls ( sizeof ( hermon_qp->send.wqe[0] ) - 1 ) - 4 ) );
  787. MLX_FILL_1 ( &qpctx, 5,
  788. qpc_eec_data.usr_page, HERMON_UAR_NON_EQ_PAGE );
  789. MLX_FILL_1 ( &qpctx, 33, qpc_eec_data.cqn_snd, qp->send.cq->cqn );
  790. MLX_FILL_1 ( &qpctx, 38, qpc_eec_data.page_offset,
  791. ( hermon_qp->mtt.page_offset >> 6 ) );
  792. MLX_FILL_1 ( &qpctx, 41, qpc_eec_data.cqn_rcv, qp->recv.cq->cqn );
  793. MLX_FILL_1 ( &qpctx, 43, qpc_eec_data.db_record_addr_l,
  794. ( virt_to_phys ( &hermon_qp->recv.doorbell ) >> 2 ) );
  795. MLX_FILL_1 ( &qpctx, 53, qpc_eec_data.mtt_base_addr_l,
  796. ( hermon_qp->mtt.mtt_base_addr >> 3 ) );
  797. if ( ( rc = hermon_cmd_rst2init_qp ( hermon, qp->qpn,
  798. &qpctx ) ) != 0 ) {
  799. DBGC ( hermon, "Hermon %p RST2INIT_QP failed: %s\n",
  800. hermon, strerror ( rc ) );
  801. goto err_rst2init_qp;
  802. }
  803. /* Transition queue to RTR state */
  804. memset ( &qpctx, 0, sizeof ( qpctx ) );
  805. MLX_FILL_2 ( &qpctx, 4,
  806. qpc_eec_data.mtu, HERMON_MTU_2048,
  807. qpc_eec_data.msg_max, 11 /* 2^11 = 2048 */ );
  808. MLX_FILL_1 ( &qpctx, 16,
  809. qpc_eec_data.primary_address_path.sched_queue,
  810. ( 0x83 /* default policy */ |
  811. ( ( ibdev->port - 1 ) << 6 ) ) );
  812. if ( ( rc = hermon_cmd_init2rtr_qp ( hermon, qp->qpn,
  813. &qpctx ) ) != 0 ) {
  814. DBGC ( hermon, "Hermon %p INIT2RTR_QP failed: %s\n",
  815. hermon, strerror ( rc ) );
  816. goto err_init2rtr_qp;
  817. }
  818. memset ( &qpctx, 0, sizeof ( qpctx ) );
  819. if ( ( rc = hermon_cmd_rtr2rts_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ){
  820. DBGC ( hermon, "Hermon %p RTR2RTS_QP failed: %s\n",
  821. hermon, strerror ( rc ) );
  822. goto err_rtr2rts_qp;
  823. }
  824. DBGC ( hermon, "Hermon %p QPN %#lx send ring at [%p,%p)\n",
  825. hermon, qp->qpn, hermon_qp->send.wqe,
  826. ( ((void *)hermon_qp->send.wqe ) + hermon_qp->send.wqe_size ) );
  827. DBGC ( hermon, "Hermon %p QPN %#lx receive ring at [%p,%p)\n",
  828. hermon, qp->qpn, hermon_qp->recv.wqe,
  829. ( ((void *)hermon_qp->recv.wqe ) + hermon_qp->recv.wqe_size ) );
  830. ib_qp_set_drvdata ( qp, hermon_qp );
  831. return 0;
  832. err_rtr2rts_qp:
  833. err_init2rtr_qp:
  834. hermon_cmd_2rst_qp ( hermon, qp->qpn );
  835. err_rst2init_qp:
  836. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  837. err_alloc_mtt:
  838. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  839. err_alloc_wqe:
  840. free ( hermon_qp );
  841. err_hermon_qp:
  842. hermon_bitmask_free ( hermon->qp_inuse, qpn_offset, 1 );
  843. err_qpn_offset:
  844. return rc;
  845. }
  846. /**
  847. * Modify queue pair
  848. *
  849. * @v ibdev Infiniband device
  850. * @v qp Queue pair
  851. * @ret rc Return status code
  852. */
  853. static int hermon_modify_qp ( struct ib_device *ibdev,
  854. struct ib_queue_pair *qp ) {
  855. struct hermon *hermon = ib_get_drvdata ( ibdev );
  856. struct hermonprm_qp_ee_state_transitions qpctx;
  857. int rc;
  858. /* Issue RTS2RTS_QP */
  859. memset ( &qpctx, 0, sizeof ( qpctx ) );
  860. MLX_FILL_1 ( &qpctx, 0, opt_param_mask, HERMON_QP_OPT_PARAM_QKEY );
  861. MLX_FILL_1 ( &qpctx, 44, qpc_eec_data.q_key, qp->qkey );
  862. if ( ( rc = hermon_cmd_rts2rts_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ){
  863. DBGC ( hermon, "Hermon %p RTS2RTS_QP failed: %s\n",
  864. hermon, strerror ( rc ) );
  865. return rc;
  866. }
  867. return 0;
  868. }
  869. /**
  870. * Destroy queue pair
  871. *
  872. * @v ibdev Infiniband device
  873. * @v qp Queue pair
  874. */
  875. static void hermon_destroy_qp ( struct ib_device *ibdev,
  876. struct ib_queue_pair *qp ) {
  877. struct hermon *hermon = ib_get_drvdata ( ibdev );
  878. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  879. int qpn_offset;
  880. int rc;
  881. /* Take ownership back from hardware */
  882. if ( ( rc = hermon_cmd_2rst_qp ( hermon, qp->qpn ) ) != 0 ) {
  883. DBGC ( hermon, "Hermon %p FATAL 2RST_QP failed on QPN %#lx: "
  884. "%s\n", hermon, qp->qpn, strerror ( rc ) );
  885. /* Leak memory and return; at least we avoid corruption */
  886. return;
  887. }
  888. /* Free MTT entries */
  889. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  890. /* Free memory */
  891. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  892. free ( hermon_qp );
  893. /* Mark queue number as free */
  894. qpn_offset = ( qp->qpn - HERMON_QPN_BASE -
  895. hermon->cap.reserved_qps );
  896. hermon_bitmask_free ( hermon->qp_inuse, qpn_offset, 1 );
  897. ib_qp_set_drvdata ( qp, NULL );
  898. }
  899. /***************************************************************************
  900. *
  901. * Work request operations
  902. *
  903. ***************************************************************************
  904. */
  905. /**
  906. * Post send work queue entry
  907. *
  908. * @v ibdev Infiniband device
  909. * @v qp Queue pair
  910. * @v av Address vector
  911. * @v iobuf I/O buffer
  912. * @ret rc Return status code
  913. */
  914. static int hermon_post_send ( struct ib_device *ibdev,
  915. struct ib_queue_pair *qp,
  916. struct ib_address_vector *av,
  917. struct io_buffer *iobuf ) {
  918. struct hermon *hermon = ib_get_drvdata ( ibdev );
  919. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  920. struct ib_work_queue *wq = &qp->send;
  921. struct hermon_send_work_queue *hermon_send_wq = &hermon_qp->send;
  922. struct hermonprm_ud_send_wqe *wqe;
  923. union hermonprm_doorbell_register db_reg;
  924. unsigned int wqe_idx_mask;
  925. /* Allocate work queue entry */
  926. wqe_idx_mask = ( wq->num_wqes - 1 );
  927. if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) {
  928. DBGC ( hermon, "Hermon %p send queue full", hermon );
  929. return -ENOBUFS;
  930. }
  931. wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf;
  932. wqe = &hermon_send_wq->wqe[ wq->next_idx &
  933. ( hermon_send_wq->num_wqes - 1 ) ].ud;
  934. /* Construct work queue entry */
  935. memset ( ( ( ( void * ) wqe ) + 4 /* avoid ctrl.owner */ ), 0,
  936. ( sizeof ( *wqe ) - 4 ) );
  937. MLX_FILL_1 ( &wqe->ctrl, 1, ds, ( sizeof ( *wqe ) / 16 ) );
  938. MLX_FILL_1 ( &wqe->ctrl, 2, c, 0x03 /* generate completion */ );
  939. MLX_FILL_2 ( &wqe->ud, 0,
  940. ud_address_vector.pd, HERMON_GLOBAL_PD,
  941. ud_address_vector.port_number, ibdev->port );
  942. MLX_FILL_2 ( &wqe->ud, 1,
  943. ud_address_vector.rlid, av->lid,
  944. ud_address_vector.g, av->gid_present );
  945. MLX_FILL_1 ( &wqe->ud, 2,
  946. ud_address_vector.max_stat_rate,
  947. ( ( ( av->rate < 2 ) || ( av->rate > 10 ) ) ?
  948. 8 : ( av->rate + 5 ) ) );
  949. MLX_FILL_1 ( &wqe->ud, 3, ud_address_vector.sl, av->sl );
  950. memcpy ( &wqe->ud.u.dwords[4], &av->gid, sizeof ( av->gid ) );
  951. MLX_FILL_1 ( &wqe->ud, 8, destination_qp, av->qpn );
  952. MLX_FILL_1 ( &wqe->ud, 9, q_key, av->qkey );
  953. MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_len ( iobuf ) );
  954. MLX_FILL_1 ( &wqe->data[0], 1, l_key, hermon->reserved_lkey );
  955. MLX_FILL_1 ( &wqe->data[0], 3,
  956. local_address_l, virt_to_bus ( iobuf->data ) );
  957. barrier();
  958. MLX_FILL_2 ( &wqe->ctrl, 0,
  959. opcode, HERMON_OPCODE_SEND,
  960. owner,
  961. ( ( wq->next_idx & hermon_send_wq->num_wqes ) ? 1 : 0 ) );
  962. DBGCP ( hermon, "Hermon %p posting send WQE:\n", hermon );
  963. DBGCP_HD ( hermon, wqe, sizeof ( *wqe ) );
  964. barrier();
  965. /* Ring doorbell register */
  966. MLX_FILL_1 ( &db_reg.send, 0, qn, qp->qpn );
  967. DBGCP ( hermon, "Ringing doorbell %08lx with %08x\n",
  968. virt_to_phys ( hermon_send_wq->doorbell ), db_reg.dword[0] );
  969. writel ( db_reg.dword[0], ( hermon_send_wq->doorbell ) );
  970. /* Update work queue's index */
  971. wq->next_idx++;
  972. return 0;
  973. }
  974. /**
  975. * Post receive work queue entry
  976. *
  977. * @v ibdev Infiniband device
  978. * @v qp Queue pair
  979. * @v iobuf I/O buffer
  980. * @ret rc Return status code
  981. */
  982. static int hermon_post_recv ( struct ib_device *ibdev,
  983. struct ib_queue_pair *qp,
  984. struct io_buffer *iobuf ) {
  985. struct hermon *hermon = ib_get_drvdata ( ibdev );
  986. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  987. struct ib_work_queue *wq = &qp->recv;
  988. struct hermon_recv_work_queue *hermon_recv_wq = &hermon_qp->recv;
  989. struct hermonprm_recv_wqe *wqe;
  990. unsigned int wqe_idx_mask;
  991. /* Allocate work queue entry */
  992. wqe_idx_mask = ( wq->num_wqes - 1 );
  993. if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) {
  994. DBGC ( hermon, "Hermon %p receive queue full", hermon );
  995. return -ENOBUFS;
  996. }
  997. wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf;
  998. wqe = &hermon_recv_wq->wqe[wq->next_idx & wqe_idx_mask].recv;
  999. /* Construct work queue entry */
  1000. MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_tailroom ( iobuf ) );
  1001. MLX_FILL_1 ( &wqe->data[0], 1, l_key, hermon->reserved_lkey );
  1002. MLX_FILL_1 ( &wqe->data[0], 3,
  1003. local_address_l, virt_to_bus ( iobuf->data ) );
  1004. /* Update work queue's index */
  1005. wq->next_idx++;
  1006. /* Update doorbell record */
  1007. barrier();
  1008. MLX_FILL_1 ( &hermon_recv_wq->doorbell, 0, receive_wqe_counter,
  1009. ( wq->next_idx & 0xffff ) );
  1010. return 0;
  1011. }
  1012. /**
  1013. * Handle completion
  1014. *
  1015. * @v ibdev Infiniband device
  1016. * @v cq Completion queue
  1017. * @v cqe Hardware completion queue entry
  1018. * @ret rc Return status code
  1019. */
  1020. static int hermon_complete ( struct ib_device *ibdev,
  1021. struct ib_completion_queue *cq,
  1022. union hermonprm_completion_entry *cqe ) {
  1023. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1024. struct ib_work_queue *wq;
  1025. struct ib_queue_pair *qp;
  1026. struct hermon_queue_pair *hermon_qp;
  1027. struct io_buffer *iobuf;
  1028. struct ib_address_vector av;
  1029. struct ib_global_route_header *grh;
  1030. unsigned int opcode;
  1031. unsigned long qpn;
  1032. int is_send;
  1033. unsigned int wqe_idx;
  1034. size_t len;
  1035. int rc = 0;
  1036. /* Parse completion */
  1037. qpn = MLX_GET ( &cqe->normal, qpn );
  1038. is_send = MLX_GET ( &cqe->normal, s_r );
  1039. opcode = MLX_GET ( &cqe->normal, opcode );
  1040. if ( opcode >= HERMON_OPCODE_RECV_ERROR ) {
  1041. /* "s" field is not valid for error opcodes */
  1042. is_send = ( opcode == HERMON_OPCODE_SEND_ERROR );
  1043. DBGC ( hermon, "Hermon %p CQN %lx syndrome %x vendor %x\n",
  1044. hermon, cq->cqn, MLX_GET ( &cqe->error, syndrome ),
  1045. MLX_GET ( &cqe->error, vendor_error_syndrome ) );
  1046. rc = -EIO;
  1047. /* Don't return immediately; propagate error to completer */
  1048. }
  1049. /* Identify work queue */
  1050. wq = ib_find_wq ( cq, qpn, is_send );
  1051. if ( ! wq ) {
  1052. DBGC ( hermon, "Hermon %p CQN %lx unknown %s QPN %lx\n",
  1053. hermon, cq->cqn, ( is_send ? "send" : "recv" ), qpn );
  1054. return -EIO;
  1055. }
  1056. qp = wq->qp;
  1057. hermon_qp = ib_qp_get_drvdata ( qp );
  1058. /* Identify I/O buffer */
  1059. wqe_idx = ( MLX_GET ( &cqe->normal, wqe_counter ) &
  1060. ( wq->num_wqes - 1 ) );
  1061. iobuf = wq->iobufs[wqe_idx];
  1062. if ( ! iobuf ) {
  1063. DBGC ( hermon, "Hermon %p CQN %lx QPN %lx empty WQE %x\n",
  1064. hermon, cq->cqn, qpn, wqe_idx );
  1065. return -EIO;
  1066. }
  1067. wq->iobufs[wqe_idx] = NULL;
  1068. if ( is_send ) {
  1069. /* Hand off to completion handler */
  1070. ib_complete_send ( ibdev, qp, iobuf, rc );
  1071. } else {
  1072. /* Set received length */
  1073. len = MLX_GET ( &cqe->normal, byte_cnt );
  1074. assert ( len <= iob_tailroom ( iobuf ) );
  1075. iob_put ( iobuf, len );
  1076. assert ( iob_len ( iobuf ) >= sizeof ( *grh ) );
  1077. grh = iobuf->data;
  1078. iob_pull ( iobuf, sizeof ( *grh ) );
  1079. /* Construct address vector */
  1080. memset ( &av, 0, sizeof ( av ) );
  1081. av.qpn = MLX_GET ( &cqe->normal, srq_rqpn );
  1082. av.lid = MLX_GET ( &cqe->normal, slid_smac47_32 );
  1083. av.sl = MLX_GET ( &cqe->normal, sl );
  1084. av.gid_present = MLX_GET ( &cqe->normal, g );
  1085. memcpy ( &av.gid, &grh->sgid, sizeof ( av.gid ) );
  1086. /* Hand off to completion handler */
  1087. ib_complete_recv ( ibdev, qp, &av, iobuf, rc );
  1088. }
  1089. return rc;
  1090. }
  1091. /**
  1092. * Poll completion queue
  1093. *
  1094. * @v ibdev Infiniband device
  1095. * @v cq Completion queue
  1096. */
  1097. static void hermon_poll_cq ( struct ib_device *ibdev,
  1098. struct ib_completion_queue *cq ) {
  1099. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1100. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  1101. union hermonprm_completion_entry *cqe;
  1102. unsigned int cqe_idx_mask;
  1103. int rc;
  1104. while ( 1 ) {
  1105. /* Look for completion entry */
  1106. cqe_idx_mask = ( cq->num_cqes - 1 );
  1107. cqe = &hermon_cq->cqe[cq->next_idx & cqe_idx_mask];
  1108. if ( MLX_GET ( &cqe->normal, owner ) ^
  1109. ( ( cq->next_idx & cq->num_cqes ) ? 1 : 0 ) ) {
  1110. /* Entry still owned by hardware; end of poll */
  1111. break;
  1112. }
  1113. DBGCP ( hermon, "Hermon %p completion:\n", hermon );
  1114. DBGCP_HD ( hermon, cqe, sizeof ( *cqe ) );
  1115. /* Handle completion */
  1116. if ( ( rc = hermon_complete ( ibdev, cq, cqe ) ) != 0 ) {
  1117. DBGC ( hermon, "Hermon %p failed to complete: %s\n",
  1118. hermon, strerror ( rc ) );
  1119. DBGC_HD ( hermon, cqe, sizeof ( *cqe ) );
  1120. }
  1121. /* Update completion queue's index */
  1122. cq->next_idx++;
  1123. /* Update doorbell record */
  1124. MLX_FILL_1 ( &hermon_cq->doorbell, 0, update_ci,
  1125. ( cq->next_idx & 0x00ffffffUL ) );
  1126. }
  1127. }
  1128. /***************************************************************************
  1129. *
  1130. * Event queues
  1131. *
  1132. ***************************************************************************
  1133. */
  1134. /**
  1135. * Create event queue
  1136. *
  1137. * @v hermon Hermon device
  1138. * @ret rc Return status code
  1139. */
  1140. static int hermon_create_eq ( struct hermon *hermon ) {
  1141. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1142. struct hermonprm_eqc eqctx;
  1143. struct hermonprm_event_mask mask;
  1144. unsigned int i;
  1145. int rc;
  1146. /* Select event queue number */
  1147. hermon_eq->eqn = ( 4 * hermon->cap.reserved_uars );
  1148. if ( hermon_eq->eqn < hermon->cap.reserved_eqs )
  1149. hermon_eq->eqn = hermon->cap.reserved_eqs;
  1150. /* Calculate doorbell address */
  1151. hermon_eq->doorbell =
  1152. ( hermon->uar + HERMON_DB_EQ_OFFSET ( hermon_eq->eqn ) );
  1153. /* Allocate event queue itself */
  1154. hermon_eq->eqe_size =
  1155. ( HERMON_NUM_EQES * sizeof ( hermon_eq->eqe[0] ) );
  1156. hermon_eq->eqe = malloc_dma ( hermon_eq->eqe_size,
  1157. sizeof ( hermon_eq->eqe[0] ) );
  1158. if ( ! hermon_eq->eqe ) {
  1159. rc = -ENOMEM;
  1160. goto err_eqe;
  1161. }
  1162. memset ( hermon_eq->eqe, 0, hermon_eq->eqe_size );
  1163. for ( i = 0 ; i < HERMON_NUM_EQES ; i++ ) {
  1164. MLX_FILL_1 ( &hermon_eq->eqe[i].generic, 7, owner, 1 );
  1165. }
  1166. barrier();
  1167. /* Allocate MTT entries */
  1168. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_eq->eqe,
  1169. hermon_eq->eqe_size,
  1170. &hermon_eq->mtt ) ) != 0 )
  1171. goto err_alloc_mtt;
  1172. /* Hand queue over to hardware */
  1173. memset ( &eqctx, 0, sizeof ( eqctx ) );
  1174. MLX_FILL_1 ( &eqctx, 0, st, 0xa /* "Fired" */ );
  1175. MLX_FILL_1 ( &eqctx, 2,
  1176. page_offset, ( hermon_eq->mtt.page_offset >> 5 ) );
  1177. MLX_FILL_1 ( &eqctx, 3, log_eq_size, fls ( HERMON_NUM_EQES - 1 ) );
  1178. MLX_FILL_1 ( &eqctx, 7, mtt_base_addr_l,
  1179. ( hermon_eq->mtt.mtt_base_addr >> 3 ) );
  1180. if ( ( rc = hermon_cmd_sw2hw_eq ( hermon, hermon_eq->eqn,
  1181. &eqctx ) ) != 0 ) {
  1182. DBGC ( hermon, "Hermon %p SW2HW_EQ failed: %s\n",
  1183. hermon, strerror ( rc ) );
  1184. goto err_sw2hw_eq;
  1185. }
  1186. /* Map events to this event queue */
  1187. memset ( &mask, 0, sizeof ( mask ) );
  1188. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1189. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1190. ( HERMON_MAP_EQ | hermon_eq->eqn ),
  1191. &mask ) ) != 0 ) {
  1192. DBGC ( hermon, "Hermon %p MAP_EQ failed: %s\n",
  1193. hermon, strerror ( rc ) );
  1194. goto err_map_eq;
  1195. }
  1196. DBGC ( hermon, "Hermon %p EQN %#lx ring at [%p,%p])\n",
  1197. hermon, hermon_eq->eqn, hermon_eq->eqe,
  1198. ( ( ( void * ) hermon_eq->eqe ) + hermon_eq->eqe_size ) );
  1199. return 0;
  1200. err_map_eq:
  1201. hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn, &eqctx );
  1202. err_sw2hw_eq:
  1203. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1204. err_alloc_mtt:
  1205. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1206. err_eqe:
  1207. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1208. return rc;
  1209. }
  1210. /**
  1211. * Destroy event queue
  1212. *
  1213. * @v hermon Hermon device
  1214. */
  1215. static void hermon_destroy_eq ( struct hermon *hermon ) {
  1216. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1217. struct hermonprm_eqc eqctx;
  1218. struct hermonprm_event_mask mask;
  1219. int rc;
  1220. /* Unmap events from event queue */
  1221. memset ( &mask, 0, sizeof ( mask ) );
  1222. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1223. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1224. ( HERMON_UNMAP_EQ | hermon_eq->eqn ),
  1225. &mask ) ) != 0 ) {
  1226. DBGC ( hermon, "Hermon %p FATAL MAP_EQ failed to unmap: %s\n",
  1227. hermon, strerror ( rc ) );
  1228. /* Continue; HCA may die but system should survive */
  1229. }
  1230. /* Take ownership back from hardware */
  1231. if ( ( rc = hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn,
  1232. &eqctx ) ) != 0 ) {
  1233. DBGC ( hermon, "Hermon %p FATAL HW2SW_EQ failed: %s\n",
  1234. hermon, strerror ( rc ) );
  1235. /* Leak memory and return; at least we avoid corruption */
  1236. return;
  1237. }
  1238. /* Free MTT entries */
  1239. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1240. /* Free memory */
  1241. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1242. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1243. }
  1244. /**
  1245. * Handle port state event
  1246. *
  1247. * @v hermon Hermon device
  1248. * @v eqe Port state change event queue entry
  1249. */
  1250. static void hermon_event_port_state_change ( struct hermon *hermon,
  1251. union hermonprm_event_entry *eqe){
  1252. unsigned int port;
  1253. int link_up;
  1254. /* Get port and link status */
  1255. port = ( MLX_GET ( &eqe->port_state_change, data.p ) - 1 );
  1256. link_up = ( MLX_GET ( &eqe->generic, event_sub_type ) & 0x04 );
  1257. DBGC ( hermon, "Hermon %p port %d link %s\n", hermon, ( port + 1 ),
  1258. ( link_up ? "up" : "down" ) );
  1259. /* Sanity check */
  1260. if ( port >= HERMON_NUM_PORTS ) {
  1261. DBGC ( hermon, "Hermon %p port %d does not exist!\n",
  1262. hermon, ( port + 1 ) );
  1263. return;
  1264. }
  1265. /* Update MAD parameters */
  1266. ib_smc_update ( hermon->ibdev[port], hermon_mad );
  1267. /* Notify Infiniband core of link state change */
  1268. ib_link_state_changed ( hermon->ibdev[port] );
  1269. }
  1270. /**
  1271. * Poll event queue
  1272. *
  1273. * @v ibdev Infiniband device
  1274. */
  1275. static void hermon_poll_eq ( struct ib_device *ibdev ) {
  1276. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1277. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1278. union hermonprm_event_entry *eqe;
  1279. union hermonprm_doorbell_register db_reg;
  1280. unsigned int eqe_idx_mask;
  1281. unsigned int event_type;
  1282. while ( 1 ) {
  1283. /* Look for event entry */
  1284. eqe_idx_mask = ( HERMON_NUM_EQES - 1 );
  1285. eqe = &hermon_eq->eqe[hermon_eq->next_idx & eqe_idx_mask];
  1286. if ( MLX_GET ( &eqe->generic, owner ) ^
  1287. ( ( hermon_eq->next_idx & HERMON_NUM_EQES ) ? 1 : 0 ) ) {
  1288. /* Entry still owned by hardware; end of poll */
  1289. break;
  1290. }
  1291. DBGCP ( hermon, "Hermon %p event:\n", hermon );
  1292. DBGCP_HD ( hermon, eqe, sizeof ( *eqe ) );
  1293. /* Handle event */
  1294. event_type = MLX_GET ( &eqe->generic, event_type );
  1295. switch ( event_type ) {
  1296. case HERMON_EV_PORT_STATE_CHANGE:
  1297. hermon_event_port_state_change ( hermon, eqe );
  1298. break;
  1299. default:
  1300. DBGC ( hermon, "Hermon %p unrecognised event type "
  1301. "%#x:\n", hermon, event_type );
  1302. DBGC_HD ( hermon, eqe, sizeof ( *eqe ) );
  1303. break;
  1304. }
  1305. /* Update event queue's index */
  1306. hermon_eq->next_idx++;
  1307. /* Ring doorbell */
  1308. MLX_FILL_1 ( &db_reg.event, 0,
  1309. ci, ( hermon_eq->next_idx & 0x00ffffffUL ) );
  1310. DBGCP ( hermon, "Ringing doorbell %08lx with %08x\n",
  1311. virt_to_phys ( hermon_eq->doorbell ),
  1312. db_reg.dword[0] );
  1313. writel ( db_reg.dword[0], hermon_eq->doorbell );
  1314. }
  1315. }
  1316. /***************************************************************************
  1317. *
  1318. * Infiniband link-layer operations
  1319. *
  1320. ***************************************************************************
  1321. */
  1322. /**
  1323. * Initialise Infiniband link
  1324. *
  1325. * @v ibdev Infiniband device
  1326. * @ret rc Return status code
  1327. */
  1328. static int hermon_open ( struct ib_device *ibdev ) {
  1329. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1330. struct hermonprm_init_port init_port;
  1331. int rc;
  1332. memset ( &init_port, 0, sizeof ( init_port ) );
  1333. MLX_FILL_2 ( &init_port, 0,
  1334. port_width_cap, 3,
  1335. vl_cap, 1 );
  1336. MLX_FILL_2 ( &init_port, 1,
  1337. mtu, HERMON_MTU_2048,
  1338. max_gid, 1 );
  1339. MLX_FILL_1 ( &init_port, 2, max_pkey, 64 );
  1340. if ( ( rc = hermon_cmd_init_port ( hermon, ibdev->port,
  1341. &init_port ) ) != 0 ) {
  1342. DBGC ( hermon, "Hermon %p could not intialise port: %s\n",
  1343. hermon, strerror ( rc ) );
  1344. return rc;
  1345. }
  1346. /* Update MAD parameters */
  1347. ib_smc_update ( ibdev, hermon_mad );
  1348. return 0;
  1349. }
  1350. /**
  1351. * Close Infiniband link
  1352. *
  1353. * @v ibdev Infiniband device
  1354. */
  1355. static void hermon_close ( struct ib_device *ibdev ) {
  1356. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1357. int rc;
  1358. if ( ( rc = hermon_cmd_close_port ( hermon, ibdev->port ) ) != 0 ) {
  1359. DBGC ( hermon, "Hermon %p could not close port: %s\n",
  1360. hermon, strerror ( rc ) );
  1361. /* Nothing we can do about this */
  1362. }
  1363. }
  1364. /***************************************************************************
  1365. *
  1366. * Multicast group operations
  1367. *
  1368. ***************************************************************************
  1369. */
  1370. /**
  1371. * Attach to multicast group
  1372. *
  1373. * @v ibdev Infiniband device
  1374. * @v qp Queue pair
  1375. * @v gid Multicast GID
  1376. * @ret rc Return status code
  1377. */
  1378. static int hermon_mcast_attach ( struct ib_device *ibdev,
  1379. struct ib_queue_pair *qp,
  1380. struct ib_gid *gid ) {
  1381. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1382. struct hermonprm_mgm_hash hash;
  1383. struct hermonprm_mcg_entry mcg;
  1384. unsigned int index;
  1385. int rc;
  1386. /* Generate hash table index */
  1387. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1388. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1389. hermon, strerror ( rc ) );
  1390. return rc;
  1391. }
  1392. index = MLX_GET ( &hash, hash );
  1393. /* Check for existing hash table entry */
  1394. if ( ( rc = hermon_cmd_read_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1395. DBGC ( hermon, "Hermon %p could not read MCG %#x: %s\n",
  1396. hermon, index, strerror ( rc ) );
  1397. return rc;
  1398. }
  1399. if ( MLX_GET ( &mcg, hdr.members_count ) != 0 ) {
  1400. /* FIXME: this implementation allows only a single QP
  1401. * per multicast group, and doesn't handle hash
  1402. * collisions. Sufficient for IPoIB but may need to
  1403. * be extended in future.
  1404. */
  1405. DBGC ( hermon, "Hermon %p MGID index %#x already in use\n",
  1406. hermon, index );
  1407. return -EBUSY;
  1408. }
  1409. /* Update hash table entry */
  1410. MLX_FILL_1 ( &mcg, 1, hdr.members_count, 1 );
  1411. MLX_FILL_1 ( &mcg, 8, qp[0].qpn, qp->qpn );
  1412. memcpy ( &mcg.u.dwords[4], gid, sizeof ( *gid ) );
  1413. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1414. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1415. hermon, index, strerror ( rc ) );
  1416. return rc;
  1417. }
  1418. return 0;
  1419. }
  1420. /**
  1421. * Detach from multicast group
  1422. *
  1423. * @v ibdev Infiniband device
  1424. * @v qp Queue pair
  1425. * @v gid Multicast GID
  1426. */
  1427. static void hermon_mcast_detach ( struct ib_device *ibdev,
  1428. struct ib_queue_pair *qp __unused,
  1429. struct ib_gid *gid ) {
  1430. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1431. struct hermonprm_mgm_hash hash;
  1432. struct hermonprm_mcg_entry mcg;
  1433. unsigned int index;
  1434. int rc;
  1435. /* Generate hash table index */
  1436. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1437. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1438. hermon, strerror ( rc ) );
  1439. return;
  1440. }
  1441. index = MLX_GET ( &hash, hash );
  1442. /* Clear hash table entry */
  1443. memset ( &mcg, 0, sizeof ( mcg ) );
  1444. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1445. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1446. hermon, index, strerror ( rc ) );
  1447. return;
  1448. }
  1449. }
  1450. /** Hermon Infiniband operations */
  1451. static struct ib_device_operations hermon_ib_operations = {
  1452. .create_cq = hermon_create_cq,
  1453. .destroy_cq = hermon_destroy_cq,
  1454. .create_qp = hermon_create_qp,
  1455. .modify_qp = hermon_modify_qp,
  1456. .destroy_qp = hermon_destroy_qp,
  1457. .post_send = hermon_post_send,
  1458. .post_recv = hermon_post_recv,
  1459. .poll_cq = hermon_poll_cq,
  1460. .poll_eq = hermon_poll_eq,
  1461. .open = hermon_open,
  1462. .close = hermon_close,
  1463. .mcast_attach = hermon_mcast_attach,
  1464. .mcast_detach = hermon_mcast_detach,
  1465. };
  1466. /***************************************************************************
  1467. *
  1468. * Firmware control
  1469. *
  1470. ***************************************************************************
  1471. */
  1472. /**
  1473. * Map virtual to physical address for firmware usage
  1474. *
  1475. * @v hermon Hermon device
  1476. * @v map Mapping function
  1477. * @v va Virtual address
  1478. * @v pa Physical address
  1479. * @v len Length of region
  1480. * @ret rc Return status code
  1481. */
  1482. static int hermon_map_vpm ( struct hermon *hermon,
  1483. int ( *map ) ( struct hermon *hermon,
  1484. const struct hermonprm_virtual_physical_mapping* ),
  1485. uint64_t va, physaddr_t pa, size_t len ) {
  1486. struct hermonprm_virtual_physical_mapping mapping;
  1487. int rc;
  1488. assert ( ( va & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1489. assert ( ( pa & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1490. assert ( ( len & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1491. while ( len ) {
  1492. memset ( &mapping, 0, sizeof ( mapping ) );
  1493. MLX_FILL_1 ( &mapping, 0, va_h, ( va >> 32 ) );
  1494. MLX_FILL_1 ( &mapping, 1, va_l, ( va >> 12 ) );
  1495. MLX_FILL_2 ( &mapping, 3,
  1496. log2size, 0,
  1497. pa_l, ( pa >> 12 ) );
  1498. if ( ( rc = map ( hermon, &mapping ) ) != 0 ) {
  1499. DBGC ( hermon, "Hermon %p could not map %llx => %lx: "
  1500. "%s\n", hermon, va, pa, strerror ( rc ) );
  1501. return rc;
  1502. }
  1503. pa += HERMON_PAGE_SIZE;
  1504. va += HERMON_PAGE_SIZE;
  1505. len -= HERMON_PAGE_SIZE;
  1506. }
  1507. return 0;
  1508. }
  1509. /**
  1510. * Start firmware running
  1511. *
  1512. * @v hermon Hermon device
  1513. * @ret rc Return status code
  1514. */
  1515. static int hermon_start_firmware ( struct hermon *hermon ) {
  1516. struct hermonprm_query_fw fw;
  1517. unsigned int fw_pages;
  1518. size_t fw_size;
  1519. physaddr_t fw_base;
  1520. int rc;
  1521. /* Get firmware parameters */
  1522. if ( ( rc = hermon_cmd_query_fw ( hermon, &fw ) ) != 0 ) {
  1523. DBGC ( hermon, "Hermon %p could not query firmware: %s\n",
  1524. hermon, strerror ( rc ) );
  1525. goto err_query_fw;
  1526. }
  1527. DBGC ( hermon, "Hermon %p firmware version %d.%d.%d\n", hermon,
  1528. MLX_GET ( &fw, fw_rev_major ), MLX_GET ( &fw, fw_rev_minor ),
  1529. MLX_GET ( &fw, fw_rev_subminor ) );
  1530. fw_pages = MLX_GET ( &fw, fw_pages );
  1531. DBGC ( hermon, "Hermon %p requires %d pages (%d kB) for firmware\n",
  1532. hermon, fw_pages, ( fw_pages * ( HERMON_PAGE_SIZE / 1024 ) ) );
  1533. /* Allocate firmware pages and map firmware area */
  1534. fw_size = ( fw_pages * HERMON_PAGE_SIZE );
  1535. hermon->firmware_area = umalloc ( fw_size );
  1536. if ( ! hermon->firmware_area ) {
  1537. rc = -ENOMEM;
  1538. goto err_alloc_fa;
  1539. }
  1540. fw_base = user_to_phys ( hermon->firmware_area, 0 );
  1541. DBGC ( hermon, "Hermon %p firmware area at physical [%lx,%lx)\n",
  1542. hermon, fw_base, ( fw_base + fw_size ) );
  1543. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_fa,
  1544. 0, fw_base, fw_size ) ) != 0 ) {
  1545. DBGC ( hermon, "Hermon %p could not map firmware: %s\n",
  1546. hermon, strerror ( rc ) );
  1547. goto err_map_fa;
  1548. }
  1549. /* Start firmware */
  1550. if ( ( rc = hermon_cmd_run_fw ( hermon ) ) != 0 ) {
  1551. DBGC ( hermon, "Hermon %p could not run firmware: %s\n",
  1552. hermon, strerror ( rc ) );
  1553. goto err_run_fw;
  1554. }
  1555. DBGC ( hermon, "Hermon %p firmware started\n", hermon );
  1556. return 0;
  1557. err_run_fw:
  1558. err_map_fa:
  1559. hermon_cmd_unmap_fa ( hermon );
  1560. ufree ( hermon->firmware_area );
  1561. hermon->firmware_area = UNULL;
  1562. err_alloc_fa:
  1563. err_query_fw:
  1564. return rc;
  1565. }
  1566. /**
  1567. * Stop firmware running
  1568. *
  1569. * @v hermon Hermon device
  1570. */
  1571. static void hermon_stop_firmware ( struct hermon *hermon ) {
  1572. int rc;
  1573. if ( ( rc = hermon_cmd_unmap_fa ( hermon ) ) != 0 ) {
  1574. DBGC ( hermon, "Hermon %p FATAL could not stop firmware: %s\n",
  1575. hermon, strerror ( rc ) );
  1576. /* Leak memory and return; at least we avoid corruption */
  1577. return;
  1578. }
  1579. ufree ( hermon->firmware_area );
  1580. hermon->firmware_area = UNULL;
  1581. }
  1582. /***************************************************************************
  1583. *
  1584. * Infinihost Context Memory management
  1585. *
  1586. ***************************************************************************
  1587. */
  1588. /**
  1589. * Get device limits
  1590. *
  1591. * @v hermon Hermon device
  1592. * @ret rc Return status code
  1593. */
  1594. static int hermon_get_cap ( struct hermon *hermon ) {
  1595. struct hermonprm_query_dev_cap dev_cap;
  1596. int rc;
  1597. if ( ( rc = hermon_cmd_query_dev_cap ( hermon, &dev_cap ) ) != 0 ) {
  1598. DBGC ( hermon, "Hermon %p could not get device limits: %s\n",
  1599. hermon, strerror ( rc ) );
  1600. return rc;
  1601. }
  1602. hermon->cap.cmpt_entry_size = MLX_GET ( &dev_cap, c_mpt_entry_sz );
  1603. hermon->cap.reserved_qps =
  1604. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_qps ) );
  1605. hermon->cap.qpc_entry_size = MLX_GET ( &dev_cap, qpc_entry_sz );
  1606. hermon->cap.altc_entry_size = MLX_GET ( &dev_cap, altc_entry_sz );
  1607. hermon->cap.auxc_entry_size = MLX_GET ( &dev_cap, aux_entry_sz );
  1608. hermon->cap.reserved_srqs =
  1609. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_srqs ) );
  1610. hermon->cap.srqc_entry_size = MLX_GET ( &dev_cap, srq_entry_sz );
  1611. hermon->cap.reserved_cqs =
  1612. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_cqs ) );
  1613. hermon->cap.cqc_entry_size = MLX_GET ( &dev_cap, cqc_entry_sz );
  1614. hermon->cap.reserved_eqs = MLX_GET ( &dev_cap, num_rsvd_eqs );
  1615. hermon->cap.eqc_entry_size = MLX_GET ( &dev_cap, eqc_entry_sz );
  1616. hermon->cap.reserved_mtts =
  1617. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mtts ) );
  1618. hermon->cap.mtt_entry_size = MLX_GET ( &dev_cap, mtt_entry_sz );
  1619. hermon->cap.reserved_mrws =
  1620. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mrws ) );
  1621. hermon->cap.dmpt_entry_size = MLX_GET ( &dev_cap, d_mpt_entry_sz );
  1622. hermon->cap.reserved_uars = MLX_GET ( &dev_cap, num_rsvd_uars );
  1623. return 0;
  1624. }
  1625. /**
  1626. * Get ICM usage
  1627. *
  1628. * @v log_num_entries Log2 of the number of entries
  1629. * @v entry_size Entry size
  1630. * @ret usage Usage size in ICM
  1631. */
  1632. static size_t icm_usage ( unsigned int log_num_entries, size_t entry_size ) {
  1633. size_t usage;
  1634. usage = ( ( 1 << log_num_entries ) * entry_size );
  1635. usage = ( ( usage + HERMON_PAGE_SIZE - 1 ) &
  1636. ~( HERMON_PAGE_SIZE - 1 ) );
  1637. return usage;
  1638. }
  1639. /**
  1640. * Allocate ICM
  1641. *
  1642. * @v hermon Hermon device
  1643. * @v init_hca INIT_HCA structure to fill in
  1644. * @ret rc Return status code
  1645. */
  1646. static int hermon_alloc_icm ( struct hermon *hermon,
  1647. struct hermonprm_init_hca *init_hca ) {
  1648. struct hermonprm_scalar_parameter icm_size;
  1649. struct hermonprm_scalar_parameter icm_aux_size;
  1650. uint64_t icm_offset = 0;
  1651. unsigned int log_num_qps, log_num_srqs, log_num_cqs, log_num_eqs;
  1652. unsigned int log_num_mtts, log_num_mpts;
  1653. size_t cmpt_max_len;
  1654. size_t qp_cmpt_len, srq_cmpt_len, cq_cmpt_len, eq_cmpt_len;
  1655. size_t icm_len, icm_aux_len;
  1656. physaddr_t icm_phys;
  1657. int i;
  1658. int rc;
  1659. /*
  1660. * Start by carving up the ICM virtual address space
  1661. *
  1662. */
  1663. /* Calculate number of each object type within ICM */
  1664. log_num_qps = fls ( hermon->cap.reserved_qps + HERMON_MAX_QPS - 1 );
  1665. log_num_srqs = fls ( hermon->cap.reserved_srqs - 1 );
  1666. log_num_cqs = fls ( hermon->cap.reserved_cqs + HERMON_MAX_CQS - 1 );
  1667. log_num_eqs = fls ( hermon->cap.reserved_eqs + HERMON_MAX_EQS - 1 );
  1668. log_num_mtts = fls ( hermon->cap.reserved_mtts + HERMON_MAX_MTTS - 1 );
  1669. /* ICM starts with the cMPT tables, which are sparse */
  1670. cmpt_max_len = ( HERMON_CMPT_MAX_ENTRIES *
  1671. ( ( uint64_t ) hermon->cap.cmpt_entry_size ) );
  1672. qp_cmpt_len = icm_usage ( log_num_qps, hermon->cap.cmpt_entry_size );
  1673. hermon->icm_map[HERMON_ICM_QP_CMPT].offset = icm_offset;
  1674. hermon->icm_map[HERMON_ICM_QP_CMPT].len = qp_cmpt_len;
  1675. icm_offset += cmpt_max_len;
  1676. srq_cmpt_len = icm_usage ( log_num_srqs, hermon->cap.cmpt_entry_size );
  1677. hermon->icm_map[HERMON_ICM_SRQ_CMPT].offset = icm_offset;
  1678. hermon->icm_map[HERMON_ICM_SRQ_CMPT].len = srq_cmpt_len;
  1679. icm_offset += cmpt_max_len;
  1680. cq_cmpt_len = icm_usage ( log_num_cqs, hermon->cap.cmpt_entry_size );
  1681. hermon->icm_map[HERMON_ICM_CQ_CMPT].offset = icm_offset;
  1682. hermon->icm_map[HERMON_ICM_CQ_CMPT].len = cq_cmpt_len;
  1683. icm_offset += cmpt_max_len;
  1684. eq_cmpt_len = icm_usage ( log_num_eqs, hermon->cap.cmpt_entry_size );
  1685. hermon->icm_map[HERMON_ICM_EQ_CMPT].offset = icm_offset;
  1686. hermon->icm_map[HERMON_ICM_EQ_CMPT].len = eq_cmpt_len;
  1687. icm_offset += cmpt_max_len;
  1688. hermon->icm_map[HERMON_ICM_OTHER].offset = icm_offset;
  1689. /* Queue pair contexts */
  1690. MLX_FILL_1 ( init_hca, 12,
  1691. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_h,
  1692. ( icm_offset >> 32 ) );
  1693. MLX_FILL_2 ( init_hca, 13,
  1694. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_l,
  1695. ( icm_offset >> 5 ),
  1696. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp,
  1697. log_num_qps );
  1698. DBGC ( hermon, "Hermon %p ICM QPC base = %llx\n", hermon, icm_offset );
  1699. icm_offset += icm_usage ( log_num_qps, hermon->cap.qpc_entry_size );
  1700. /* Extended alternate path contexts */
  1701. MLX_FILL_1 ( init_hca, 24,
  1702. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_h,
  1703. ( icm_offset >> 32 ) );
  1704. MLX_FILL_1 ( init_hca, 25,
  1705. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_l,
  1706. icm_offset );
  1707. DBGC ( hermon, "Hermon %p ICM ALTC base = %llx\n", hermon, icm_offset);
  1708. icm_offset += icm_usage ( log_num_qps,
  1709. hermon->cap.altc_entry_size );
  1710. /* Extended auxiliary contexts */
  1711. MLX_FILL_1 ( init_hca, 28,
  1712. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_h,
  1713. ( icm_offset >> 32 ) );
  1714. MLX_FILL_1 ( init_hca, 29,
  1715. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_l,
  1716. icm_offset );
  1717. DBGC ( hermon, "Hermon %p ICM AUXC base = %llx\n", hermon, icm_offset);
  1718. icm_offset += icm_usage ( log_num_qps,
  1719. hermon->cap.auxc_entry_size );
  1720. /* Shared receive queue contexts */
  1721. MLX_FILL_1 ( init_hca, 18,
  1722. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_h,
  1723. ( icm_offset >> 32 ) );
  1724. MLX_FILL_2 ( init_hca, 19,
  1725. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_l,
  1726. ( icm_offset >> 5 ),
  1727. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_srq,
  1728. log_num_srqs );
  1729. DBGC ( hermon, "Hermon %p ICM SRQC base = %llx\n", hermon, icm_offset);
  1730. icm_offset += icm_usage ( log_num_srqs,
  1731. hermon->cap.srqc_entry_size );
  1732. /* Completion queue contexts */
  1733. MLX_FILL_1 ( init_hca, 20,
  1734. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_h,
  1735. ( icm_offset >> 32 ) );
  1736. MLX_FILL_2 ( init_hca, 21,
  1737. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_l,
  1738. ( icm_offset >> 5 ),
  1739. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq,
  1740. log_num_cqs );
  1741. DBGC ( hermon, "Hermon %p ICM CQC base = %llx\n", hermon, icm_offset );
  1742. icm_offset += icm_usage ( log_num_cqs, hermon->cap.cqc_entry_size );
  1743. /* Event queue contexts */
  1744. MLX_FILL_1 ( init_hca, 32,
  1745. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_h,
  1746. ( icm_offset >> 32 ) );
  1747. MLX_FILL_2 ( init_hca, 33,
  1748. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_l,
  1749. ( icm_offset >> 5 ),
  1750. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_eq,
  1751. log_num_eqs );
  1752. DBGC ( hermon, "Hermon %p ICM EQC base = %llx\n", hermon, icm_offset );
  1753. icm_offset += icm_usage ( log_num_eqs, hermon->cap.eqc_entry_size );
  1754. /* Memory translation table */
  1755. MLX_FILL_1 ( init_hca, 64,
  1756. tpt_parameters.mtt_base_addr_h, ( icm_offset >> 32 ) );
  1757. MLX_FILL_1 ( init_hca, 65,
  1758. tpt_parameters.mtt_base_addr_l, icm_offset );
  1759. DBGC ( hermon, "Hermon %p ICM MTT base = %llx\n", hermon, icm_offset );
  1760. icm_offset += icm_usage ( log_num_mtts,
  1761. hermon->cap.mtt_entry_size );
  1762. /* Memory protection table */
  1763. log_num_mpts = fls ( hermon->cap.reserved_mrws + 1 - 1 );
  1764. MLX_FILL_1 ( init_hca, 60,
  1765. tpt_parameters.dmpt_base_adr_h, ( icm_offset >> 32 ) );
  1766. MLX_FILL_1 ( init_hca, 61,
  1767. tpt_parameters.dmpt_base_adr_l, icm_offset );
  1768. MLX_FILL_1 ( init_hca, 62,
  1769. tpt_parameters.log_dmpt_sz, log_num_mpts );
  1770. DBGC ( hermon, "Hermon %p ICM DMPT base = %llx\n", hermon, icm_offset);
  1771. icm_offset += icm_usage ( log_num_mpts,
  1772. hermon->cap.dmpt_entry_size );
  1773. /* Multicast table */
  1774. MLX_FILL_1 ( init_hca, 48,
  1775. multicast_parameters.mc_base_addr_h,
  1776. ( icm_offset >> 32 ) );
  1777. MLX_FILL_1 ( init_hca, 49,
  1778. multicast_parameters.mc_base_addr_l, icm_offset );
  1779. MLX_FILL_1 ( init_hca, 52,
  1780. multicast_parameters.log_mc_table_entry_sz,
  1781. fls ( sizeof ( struct hermonprm_mcg_entry ) - 1 ) );
  1782. MLX_FILL_1 ( init_hca, 53,
  1783. multicast_parameters.log_mc_table_hash_sz, 3 );
  1784. MLX_FILL_1 ( init_hca, 54,
  1785. multicast_parameters.log_mc_table_sz, 3 );
  1786. DBGC ( hermon, "Hermon %p ICM MC base = %llx\n", hermon, icm_offset );
  1787. icm_offset += ( ( 8 * sizeof ( struct hermonprm_mcg_entry ) +
  1788. HERMON_PAGE_SIZE - 1 ) & ~( HERMON_PAGE_SIZE - 1 ) );
  1789. hermon->icm_map[HERMON_ICM_OTHER].len =
  1790. ( icm_offset - hermon->icm_map[HERMON_ICM_OTHER].offset );
  1791. /*
  1792. * Allocate and map physical memory for (portions of) ICM
  1793. *
  1794. * Map is:
  1795. * ICM AUX area (aligned to its own size)
  1796. * cMPT areas
  1797. * Other areas
  1798. */
  1799. /* Calculate physical memory required for ICM */
  1800. icm_len = 0;
  1801. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  1802. icm_len += hermon->icm_map[i].len;
  1803. }
  1804. /* Get ICM auxiliary area size */
  1805. memset ( &icm_size, 0, sizeof ( icm_size ) );
  1806. MLX_FILL_1 ( &icm_size, 0, value_hi, ( icm_offset >> 32 ) );
  1807. MLX_FILL_1 ( &icm_size, 1, value, icm_offset );
  1808. if ( ( rc = hermon_cmd_set_icm_size ( hermon, &icm_size,
  1809. &icm_aux_size ) ) != 0 ) {
  1810. DBGC ( hermon, "Hermon %p could not set ICM size: %s\n",
  1811. hermon, strerror ( rc ) );
  1812. goto err_set_icm_size;
  1813. }
  1814. icm_aux_len = ( MLX_GET ( &icm_aux_size, value ) * HERMON_PAGE_SIZE );
  1815. /* Allocate ICM data and auxiliary area */
  1816. DBGC ( hermon, "Hermon %p requires %zd kB ICM and %zd kB AUX ICM\n",
  1817. hermon, ( icm_len / 1024 ), ( icm_aux_len / 1024 ) );
  1818. hermon->icm = umalloc ( icm_aux_len + icm_len );
  1819. if ( ! hermon->icm ) {
  1820. rc = -ENOMEM;
  1821. goto err_alloc;
  1822. }
  1823. icm_phys = user_to_phys ( hermon->icm, 0 );
  1824. /* Map ICM auxiliary area */
  1825. DBGC ( hermon, "Hermon %p mapping ICM AUX => %08lx\n",
  1826. hermon, icm_phys );
  1827. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_icm_aux,
  1828. 0, icm_phys, icm_aux_len ) ) != 0 ) {
  1829. DBGC ( hermon, "Hermon %p could not map AUX ICM: %s\n",
  1830. hermon, strerror ( rc ) );
  1831. goto err_map_icm_aux;
  1832. }
  1833. icm_phys += icm_aux_len;
  1834. /* MAP ICM area */
  1835. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  1836. DBGC ( hermon, "Hermon %p mapping ICM %llx+%zx => %08lx\n",
  1837. hermon, hermon->icm_map[i].offset,
  1838. hermon->icm_map[i].len, icm_phys );
  1839. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_icm,
  1840. hermon->icm_map[i].offset,
  1841. icm_phys,
  1842. hermon->icm_map[i].len ) ) != 0 ){
  1843. DBGC ( hermon, "Hermon %p could not map ICM: %s\n",
  1844. hermon, strerror ( rc ) );
  1845. goto err_map_icm;
  1846. }
  1847. icm_phys += hermon->icm_map[i].len;
  1848. }
  1849. return 0;
  1850. err_map_icm:
  1851. assert ( i == 0 ); /* We don't handle partial failure at present */
  1852. err_map_icm_aux:
  1853. hermon_cmd_unmap_icm_aux ( hermon );
  1854. ufree ( hermon->icm );
  1855. hermon->icm = UNULL;
  1856. err_alloc:
  1857. err_set_icm_size:
  1858. return rc;
  1859. }
  1860. /**
  1861. * Free ICM
  1862. *
  1863. * @v hermon Hermon device
  1864. */
  1865. static void hermon_free_icm ( struct hermon *hermon ) {
  1866. struct hermonprm_scalar_parameter unmap_icm;
  1867. int i;
  1868. for ( i = ( HERMON_ICM_NUM_REGIONS - 1 ) ; i >= 0 ; i-- ) {
  1869. memset ( &unmap_icm, 0, sizeof ( unmap_icm ) );
  1870. MLX_FILL_1 ( &unmap_icm, 0, value_hi,
  1871. ( hermon->icm_map[i].offset >> 32 ) );
  1872. MLX_FILL_1 ( &unmap_icm, 1, value,
  1873. hermon->icm_map[i].offset );
  1874. hermon_cmd_unmap_icm ( hermon,
  1875. ( 1 << fls ( ( hermon->icm_map[i].len /
  1876. HERMON_PAGE_SIZE ) - 1)),
  1877. &unmap_icm );
  1878. }
  1879. hermon_cmd_unmap_icm_aux ( hermon );
  1880. ufree ( hermon->icm );
  1881. hermon->icm = UNULL;
  1882. }
  1883. /***************************************************************************
  1884. *
  1885. * PCI interface
  1886. *
  1887. ***************************************************************************
  1888. */
  1889. /**
  1890. * Set up memory protection table
  1891. *
  1892. * @v hermon Hermon device
  1893. * @ret rc Return status code
  1894. */
  1895. static int hermon_setup_mpt ( struct hermon *hermon ) {
  1896. struct hermonprm_mpt mpt;
  1897. uint32_t key;
  1898. int rc;
  1899. /* Derive key */
  1900. key = ( hermon->cap.reserved_mrws | HERMON_MKEY_PREFIX );
  1901. hermon->reserved_lkey = ( ( key << 8 ) | ( key >> 24 ) );
  1902. /* Initialise memory protection table */
  1903. memset ( &mpt, 0, sizeof ( mpt ) );
  1904. MLX_FILL_4 ( &mpt, 0,
  1905. r_w, 1,
  1906. pa, 1,
  1907. lr, 1,
  1908. lw, 1 );
  1909. MLX_FILL_1 ( &mpt, 2, mem_key, key );
  1910. MLX_FILL_1 ( &mpt, 3, pd, HERMON_GLOBAL_PD );
  1911. MLX_FILL_1 ( &mpt, 10, len64, 1 );
  1912. if ( ( rc = hermon_cmd_sw2hw_mpt ( hermon,
  1913. hermon->cap.reserved_mrws,
  1914. &mpt ) ) != 0 ) {
  1915. DBGC ( hermon, "Hermon %p could not set up MPT: %s\n",
  1916. hermon, strerror ( rc ) );
  1917. return rc;
  1918. }
  1919. return 0;
  1920. }
  1921. /**
  1922. * Probe PCI device
  1923. *
  1924. * @v pci PCI device
  1925. * @v id PCI ID
  1926. * @ret rc Return status code
  1927. */
  1928. static int hermon_probe ( struct pci_device *pci,
  1929. const struct pci_device_id *id __unused ) {
  1930. struct hermon *hermon;
  1931. struct ib_device *ibdev;
  1932. struct hermonprm_init_hca init_hca;
  1933. int i;
  1934. int rc;
  1935. /* Allocate Hermon device */
  1936. hermon = zalloc ( sizeof ( *hermon ) );
  1937. if ( ! hermon ) {
  1938. rc = -ENOMEM;
  1939. goto err_alloc_hermon;
  1940. }
  1941. pci_set_drvdata ( pci, hermon );
  1942. /* Allocate Infiniband devices */
  1943. for ( i = 0 ; i < HERMON_NUM_PORTS ; i++ ) {
  1944. ibdev = alloc_ibdev ( 0 );
  1945. if ( ! ibdev ) {
  1946. rc = -ENOMEM;
  1947. goto err_alloc_ibdev;
  1948. }
  1949. hermon->ibdev[i] = ibdev;
  1950. ibdev->op = &hermon_ib_operations;
  1951. ibdev->dev = &pci->dev;
  1952. ibdev->port = ( HERMON_PORT_BASE + i );
  1953. ib_set_drvdata ( ibdev, hermon );
  1954. }
  1955. /* Fix up PCI device */
  1956. adjust_pci_device ( pci );
  1957. /* Get PCI BARs */
  1958. hermon->config = ioremap ( pci_bar_start ( pci, HERMON_PCI_CONFIG_BAR),
  1959. HERMON_PCI_CONFIG_BAR_SIZE );
  1960. hermon->uar = ioremap ( pci_bar_start ( pci, HERMON_PCI_UAR_BAR ),
  1961. HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE );
  1962. /* Allocate space for mailboxes */
  1963. hermon->mailbox_in = malloc_dma ( HERMON_MBOX_SIZE,
  1964. HERMON_MBOX_ALIGN );
  1965. if ( ! hermon->mailbox_in ) {
  1966. rc = -ENOMEM;
  1967. goto err_mailbox_in;
  1968. }
  1969. hermon->mailbox_out = malloc_dma ( HERMON_MBOX_SIZE,
  1970. HERMON_MBOX_ALIGN );
  1971. if ( ! hermon->mailbox_out ) {
  1972. rc = -ENOMEM;
  1973. goto err_mailbox_out;
  1974. }
  1975. /* Start firmware */
  1976. if ( ( rc = hermon_start_firmware ( hermon ) ) != 0 )
  1977. goto err_start_firmware;
  1978. /* Get device limits */
  1979. if ( ( rc = hermon_get_cap ( hermon ) ) != 0 )
  1980. goto err_get_cap;
  1981. /* Allocate ICM */
  1982. memset ( &init_hca, 0, sizeof ( init_hca ) );
  1983. if ( ( rc = hermon_alloc_icm ( hermon, &init_hca ) ) != 0 )
  1984. goto err_alloc_icm;
  1985. /* Initialise HCA */
  1986. MLX_FILL_1 ( &init_hca, 0, version, 0x02 /* "Must be 0x02" */ );
  1987. MLX_FILL_1 ( &init_hca, 5, udp, 1 );
  1988. MLX_FILL_1 ( &init_hca, 74, uar_parameters.log_max_uars, 8 );
  1989. if ( ( rc = hermon_cmd_init_hca ( hermon, &init_hca ) ) != 0 ) {
  1990. DBGC ( hermon, "Hermon %p could not initialise HCA: %s\n",
  1991. hermon, strerror ( rc ) );
  1992. goto err_init_hca;
  1993. }
  1994. /* Set up memory protection */
  1995. if ( ( rc = hermon_setup_mpt ( hermon ) ) != 0 )
  1996. goto err_setup_mpt;
  1997. /* Set up event queue */
  1998. if ( ( rc = hermon_create_eq ( hermon ) ) != 0 )
  1999. goto err_create_eq;
  2000. /* Update MAD parameters */
  2001. for ( i = 0 ; i < HERMON_NUM_PORTS ; i++ )
  2002. ib_smc_update ( hermon->ibdev[i], hermon_mad );
  2003. /* Register Infiniband devices */
  2004. for ( i = 0 ; i < HERMON_NUM_PORTS ; i++ ) {
  2005. if ( ( rc = register_ibdev ( hermon->ibdev[i] ) ) != 0 ) {
  2006. DBGC ( hermon, "Hermon %p could not register IB "
  2007. "device: %s\n", hermon, strerror ( rc ) );
  2008. goto err_register_ibdev;
  2009. }
  2010. }
  2011. return 0;
  2012. i = HERMON_NUM_PORTS;
  2013. err_register_ibdev:
  2014. for ( i-- ; i >= 0 ; i-- )
  2015. unregister_ibdev ( hermon->ibdev[i] );
  2016. hermon_destroy_eq ( hermon );
  2017. err_create_eq:
  2018. err_setup_mpt:
  2019. hermon_cmd_close_hca ( hermon );
  2020. err_init_hca:
  2021. hermon_free_icm ( hermon );
  2022. err_alloc_icm:
  2023. err_get_cap:
  2024. hermon_stop_firmware ( hermon );
  2025. err_start_firmware:
  2026. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2027. err_mailbox_out:
  2028. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2029. err_mailbox_in:
  2030. i = HERMON_NUM_PORTS;
  2031. err_alloc_ibdev:
  2032. for ( i-- ; i >= 0 ; i-- )
  2033. ibdev_put ( hermon->ibdev[i] );
  2034. free ( hermon );
  2035. err_alloc_hermon:
  2036. return rc;
  2037. }
  2038. /**
  2039. * Remove PCI device
  2040. *
  2041. * @v pci PCI device
  2042. */
  2043. static void hermon_remove ( struct pci_device *pci ) {
  2044. struct hermon *hermon = pci_get_drvdata ( pci );
  2045. int i;
  2046. for ( i = ( HERMON_NUM_PORTS - 1 ) ; i >= 0 ; i-- )
  2047. unregister_ibdev ( hermon->ibdev[i] );
  2048. hermon_destroy_eq ( hermon );
  2049. hermon_cmd_close_hca ( hermon );
  2050. hermon_free_icm ( hermon );
  2051. hermon_stop_firmware ( hermon );
  2052. hermon_stop_firmware ( hermon );
  2053. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2054. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2055. for ( i = ( HERMON_NUM_PORTS - 1 ) ; i >= 0 ; i-- )
  2056. ibdev_put ( hermon->ibdev[i] );
  2057. free ( hermon );
  2058. }
  2059. static struct pci_device_id hermon_nics[] = {
  2060. PCI_ROM ( 0x15b3, 0x6340, "mt25408", "MT25408 HCA driver", 0 ),
  2061. PCI_ROM ( 0x15b3, 0x634a, "mt25418", "MT25418 HCA driver", 0 ),
  2062. PCI_ROM ( 0x15b3, 0x6732, "mt26418", "MT26418 HCA driver", 0 ),
  2063. PCI_ROM ( 0x15b3, 0x673c, "mt26428", "MT26428 HCA driver", 0 ),
  2064. };
  2065. struct pci_driver hermon_driver __pci_driver = {
  2066. .ids = hermon_nics,
  2067. .id_count = ( sizeof ( hermon_nics ) / sizeof ( hermon_nics[0] ) ),
  2068. .probe = hermon_probe,
  2069. .remove = hermon_remove,
  2070. };