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3c90x.c 34KB

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  1. /*
  2. * 3c90x.c -- This file implements the 3c90x driver for etherboot. Written
  3. * by Greg Beeley, Greg.Beeley@LightSys.org. Modified by Steve Smith,
  4. * Steve.Smith@Juno.Com. Alignment bug fix Neil Newell (nn@icenoir.net).
  5. *
  6. * This program Copyright (C) 1999 LightSys Technology Services, Inc.
  7. * Portions Copyright (C) 1999 Steve Smith
  8. *
  9. * This program may be re-distributed in source or binary form, modified,
  10. * sold, or copied for any purpose, provided that the above copyright message
  11. * and this text are included with all source copies or derivative works, and
  12. * provided that the above copyright message and this text are included in the
  13. * documentation of any binary-only distributions. This program is distributed
  14. * WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR
  15. * PURPOSE or MERCHANTABILITY. Please read the associated documentation
  16. * "3c90x.txt" before compiling and using this driver.
  17. *
  18. * --------
  19. *
  20. * Program written with the assistance of the 3com documentation for
  21. * the 3c905B-TX card, as well as with some assistance from the 3c59x
  22. * driver Donald Becker wrote for the Linux kernel, and with some assistance
  23. * from the remainder of the Etherboot distribution.
  24. *
  25. * REVISION HISTORY:
  26. *
  27. * v0.10 1-26-1998 GRB Initial implementation.
  28. * v0.90 1-27-1998 GRB System works.
  29. * v1.00pre1 2-11-1998 GRB Got prom boot issue fixed.
  30. * v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code)
  31. * Re-wrote poll and transmit for
  32. * better error recovery and heavy
  33. * network traffic operation
  34. * v2.01 5-26-2003 NN Fixed driver alignment issue which
  35. * caused system lockups if driver structures
  36. * not 8-byte aligned.
  37. *
  38. */
  39. #include "etherboot.h"
  40. #include "nic.h"
  41. #include <gpxe/pci.h>
  42. #include <gpxe/ethernet.h>
  43. #include "timer.h"
  44. static struct nic_operations a3c90x_operations;
  45. #define XCVR_MAGIC (0x5A00)
  46. /** any single transmission fails after 16 collisions or other errors
  47. ** this is the number of times to retry the transmission -- this should
  48. ** be plenty
  49. **/
  50. #define XMIT_RETRIES 250
  51. /*** Register definitions for the 3c905 ***/
  52. enum Registers
  53. {
  54. regPowerMgmtCtrl_w = 0x7c, /** 905B Revision Only **/
  55. regUpMaxBurst_w = 0x7a, /** 905B Revision Only **/
  56. regDnMaxBurst_w = 0x78, /** 905B Revision Only **/
  57. regDebugControl_w = 0x74, /** 905B Revision Only **/
  58. regDebugData_l = 0x70, /** 905B Revision Only **/
  59. regRealTimeCnt_l = 0x40, /** Universal **/
  60. regUpBurstThresh_b = 0x3e, /** 905B Revision Only **/
  61. regUpPoll_b = 0x3d, /** 905B Revision Only **/
  62. regUpPriorityThresh_b = 0x3c, /** 905B Revision Only **/
  63. regUpListPtr_l = 0x38, /** Universal **/
  64. regCountdown_w = 0x36, /** Universal **/
  65. regFreeTimer_w = 0x34, /** Universal **/
  66. regUpPktStatus_l = 0x30, /** Universal with Exception, pg 130 **/
  67. regTxFreeThresh_b = 0x2f, /** 90X Revision Only **/
  68. regDnPoll_b = 0x2d, /** 905B Revision Only **/
  69. regDnPriorityThresh_b = 0x2c, /** 905B Revision Only **/
  70. regDnBurstThresh_b = 0x2a, /** 905B Revision Only **/
  71. regDnListPtr_l = 0x24, /** Universal with Exception, pg 107 **/
  72. regDmaCtrl_l = 0x20, /** Universal with Exception, pg 106 **/
  73. /** **/
  74. regIntStatusAuto_w = 0x1e, /** 905B Revision Only **/
  75. regTxStatus_b = 0x1b, /** Universal with Exception, pg 113 **/
  76. regTimer_b = 0x1a, /** Universal **/
  77. regTxPktId_b = 0x18, /** 905B Revision Only **/
  78. regCommandIntStatus_w = 0x0e, /** Universal (Command Variations) **/
  79. };
  80. /** following are windowed registers **/
  81. enum Registers7
  82. {
  83. regPowerMgmtEvent_7_w = 0x0c, /** 905B Revision Only **/
  84. regVlanEtherType_7_w = 0x04, /** 905B Revision Only **/
  85. regVlanMask_7_w = 0x00, /** 905B Revision Only **/
  86. };
  87. enum Registers6
  88. {
  89. regBytesXmittedOk_6_w = 0x0c, /** Universal **/
  90. regBytesRcvdOk_6_w = 0x0a, /** Universal **/
  91. regUpperFramesOk_6_b = 0x09, /** Universal **/
  92. regFramesDeferred_6_b = 0x08, /** Universal **/
  93. regFramesRecdOk_6_b = 0x07, /** Universal with Exceptions, pg 142 **/
  94. regFramesXmittedOk_6_b = 0x06, /** Universal **/
  95. regRxOverruns_6_b = 0x05, /** Universal **/
  96. regLateCollisions_6_b = 0x04, /** Universal **/
  97. regSingleCollisions_6_b = 0x03, /** Universal **/
  98. regMultipleCollisions_6_b = 0x02, /** Universal **/
  99. regSqeErrors_6_b = 0x01, /** Universal **/
  100. regCarrierLost_6_b = 0x00, /** Universal **/
  101. };
  102. enum Registers5
  103. {
  104. regIndicationEnable_5_w = 0x0c, /** Universal **/
  105. regInterruptEnable_5_w = 0x0a, /** Universal **/
  106. regTxReclaimThresh_5_b = 0x09, /** 905B Revision Only **/
  107. regRxFilter_5_b = 0x08, /** Universal **/
  108. regRxEarlyThresh_5_w = 0x06, /** Universal **/
  109. regTxStartThresh_5_w = 0x00, /** Universal **/
  110. };
  111. enum Registers4
  112. {
  113. regUpperBytesOk_4_b = 0x0d, /** Universal **/
  114. regBadSSD_4_b = 0x0c, /** Universal **/
  115. regMediaStatus_4_w = 0x0a, /** Universal with Exceptions, pg 201 **/
  116. regPhysicalMgmt_4_w = 0x08, /** Universal **/
  117. regNetworkDiagnostic_4_w = 0x06, /** Universal with Exceptions, pg 203 **/
  118. regFifoDiagnostic_4_w = 0x04, /** Universal with Exceptions, pg 196 **/
  119. regVcoDiagnostic_4_w = 0x02, /** Undocumented? **/
  120. };
  121. enum Registers3
  122. {
  123. regTxFree_3_w = 0x0c, /** Universal **/
  124. regRxFree_3_w = 0x0a, /** Universal with Exceptions, pg 125 **/
  125. regResetMediaOptions_3_w = 0x08, /** Media Options on B Revision, **/
  126. /** Reset Options on Non-B Revision **/
  127. regMacControl_3_w = 0x06, /** Universal with Exceptions, pg 199 **/
  128. regMaxPktSize_3_w = 0x04, /** 905B Revision Only **/
  129. regInternalConfig_3_l = 0x00, /** Universal, different bit **/
  130. /** definitions, pg 59 **/
  131. };
  132. enum Registers2
  133. {
  134. regResetOptions_2_w = 0x0c, /** 905B Revision Only **/
  135. regStationMask_2_3w = 0x06, /** Universal with Exceptions, pg 127 **/
  136. regStationAddress_2_3w = 0x00, /** Universal with Exceptions, pg 127 **/
  137. };
  138. enum Registers1
  139. {
  140. regRxStatus_1_w = 0x0a, /** 90X Revision Only, Pg 126 **/
  141. };
  142. enum Registers0
  143. {
  144. regEepromData_0_w = 0x0c, /** Universal **/
  145. regEepromCommand_0_w = 0x0a, /** Universal **/
  146. regBiosRomData_0_b = 0x08, /** 905B Revision Only **/
  147. regBiosRomAddr_0_l = 0x04, /** 905B Revision Only **/
  148. };
  149. /*** The names for the eight register windows ***/
  150. enum Windows
  151. {
  152. winPowerVlan7 = 0x07,
  153. winStatistics6 = 0x06,
  154. winTxRxControl5 = 0x05,
  155. winDiagnostics4 = 0x04,
  156. winTxRxOptions3 = 0x03,
  157. winAddressing2 = 0x02,
  158. winUnused1 = 0x01,
  159. winEepromBios0 = 0x00,
  160. };
  161. /*** Command definitions for the 3c90X ***/
  162. enum Commands
  163. {
  164. cmdGlobalReset = 0x00, /** Universal with Exceptions, pg 151 **/
  165. cmdSelectRegisterWindow = 0x01, /** Universal **/
  166. cmdEnableDcConverter = 0x02, /** **/
  167. cmdRxDisable = 0x03, /** **/
  168. cmdRxEnable = 0x04, /** Universal **/
  169. cmdRxReset = 0x05, /** Universal **/
  170. cmdStallCtl = 0x06, /** Universal **/
  171. cmdTxEnable = 0x09, /** Universal **/
  172. cmdTxDisable = 0x0A, /** **/
  173. cmdTxReset = 0x0B, /** Universal **/
  174. cmdRequestInterrupt = 0x0C, /** **/
  175. cmdAcknowledgeInterrupt = 0x0D, /** Universal **/
  176. cmdSetInterruptEnable = 0x0E, /** Universal **/
  177. cmdSetIndicationEnable = 0x0F, /** Universal **/
  178. cmdSetRxFilter = 0x10, /** Universal **/
  179. cmdSetRxEarlyThresh = 0x11, /** **/
  180. cmdSetTxStartThresh = 0x13, /** **/
  181. cmdStatisticsEnable = 0x15, /** **/
  182. cmdStatisticsDisable = 0x16, /** **/
  183. cmdDisableDcConverter = 0x17, /** **/
  184. cmdSetTxReclaimThresh = 0x18, /** **/
  185. cmdSetHashFilterBit = 0x19, /** **/
  186. };
  187. /*** Values for int status register bitmask **/
  188. #define INT_INTERRUPTLATCH (1<<0)
  189. #define INT_HOSTERROR (1<<1)
  190. #define INT_TXCOMPLETE (1<<2)
  191. #define INT_RXCOMPLETE (1<<4)
  192. #define INT_RXEARLY (1<<5)
  193. #define INT_INTREQUESTED (1<<6)
  194. #define INT_UPDATESTATS (1<<7)
  195. #define INT_LINKEVENT (1<<8)
  196. #define INT_DNCOMPLETE (1<<9)
  197. #define INT_UPCOMPLETE (1<<10)
  198. #define INT_CMDINPROGRESS (1<<12)
  199. #define INT_WINDOWNUMBER (7<<13)
  200. /*** TX descriptor ***/
  201. typedef struct
  202. {
  203. unsigned int DnNextPtr;
  204. unsigned int FrameStartHeader;
  205. unsigned int HdrAddr;
  206. unsigned int HdrLength;
  207. unsigned int DataAddr;
  208. unsigned int DataLength;
  209. }
  210. TXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
  211. /*** RX descriptor ***/
  212. typedef struct
  213. {
  214. unsigned int UpNextPtr;
  215. unsigned int UpPktStatus;
  216. unsigned int DataAddr;
  217. unsigned int DataLength;
  218. }
  219. RXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
  220. /*** Global variables ***/
  221. static struct
  222. {
  223. unsigned int is3c556;
  224. unsigned char isBrev;
  225. unsigned char CurrentWindow;
  226. unsigned int IOAddr;
  227. unsigned char HWAddr[ETH_ALEN];
  228. TXD TransmitDPD;
  229. RXD ReceiveUPD;
  230. }
  231. INF_3C90X;
  232. /*** a3c90x_internal_IssueCommand: sends a command to the 3c90x card
  233. ***/
  234. static int
  235. a3c90x_internal_IssueCommand(int ioaddr, int cmd, int param)
  236. {
  237. unsigned int val;
  238. /** Build the cmd. **/
  239. val = cmd;
  240. val <<= 11;
  241. val |= param;
  242. /** Send the cmd to the cmd register **/
  243. outw(val, ioaddr + regCommandIntStatus_w);
  244. /** Wait for the cmd to complete, if necessary **/
  245. while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
  246. return 0;
  247. }
  248. /*** a3c90x_internal_SetWindow: selects a register window set.
  249. ***/
  250. static int
  251. a3c90x_internal_SetWindow(int ioaddr, int window)
  252. {
  253. /** Window already as set? **/
  254. if (INF_3C90X.CurrentWindow == window) return 0;
  255. /** Issue the window command. **/
  256. a3c90x_internal_IssueCommand(ioaddr, cmdSelectRegisterWindow, window);
  257. INF_3C90X.CurrentWindow = window;
  258. return 0;
  259. }
  260. /*** a3c90x_internal_ReadEeprom - read data from the serial eeprom.
  261. ***/
  262. static unsigned short
  263. a3c90x_internal_ReadEeprom(int ioaddr, int address)
  264. {
  265. unsigned short val;
  266. /** Select correct window **/
  267. a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winEepromBios0);
  268. /** Make sure the eeprom isn't busy **/
  269. while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
  270. /** Read the value. **/
  271. if (INF_3C90X.is3c556)
  272. {
  273. outw(address + (0x230), ioaddr + regEepromCommand_0_w);
  274. }
  275. else
  276. {
  277. outw(address + ((0x02)<<6), ioaddr + regEepromCommand_0_w);
  278. }
  279. while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
  280. val = inw(ioaddr + regEepromData_0_w);
  281. return val;
  282. }
  283. #if 0
  284. /*** a3c90x_internal_WriteEepromWord - write a physical word of
  285. *** data to the onboard serial eeprom (not the BIOS prom, but the
  286. *** nvram in the card that stores, among other things, the MAC
  287. *** address).
  288. ***/
  289. static int
  290. a3c90x_internal_WriteEepromWord(int ioaddr, int address, unsigned short value)
  291. {
  292. /** Select register window **/
  293. a3c90x_internal_SetWindow(ioaddr, winEepromBios0);
  294. /** Verify Eeprom not busy **/
  295. while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
  296. /** Issue WriteEnable, and wait for completion. **/
  297. outw(0x30, ioaddr + regEepromCommand_0_w);
  298. while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
  299. /** Issue EraseRegister, and wait for completion. **/
  300. outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w);
  301. while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
  302. /** Send the new data to the eeprom, and wait for completion. **/
  303. outw(value, ioaddr + regEepromData_0_w);
  304. outw(0x30, ioaddr + regEepromCommand_0_w);
  305. while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
  306. /** Burn the new data into the eeprom, and wait for completion. **/
  307. outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w);
  308. while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
  309. return 0;
  310. }
  311. #endif
  312. #if 0
  313. /*** a3c90x_internal_WriteEeprom - write data to the serial eeprom,
  314. *** and re-compute the eeprom checksum.
  315. ***/
  316. static int
  317. a3c90x_internal_WriteEeprom(int ioaddr, int address, unsigned short value)
  318. {
  319. int cksum = 0,v;
  320. int i;
  321. int maxAddress, cksumAddress;
  322. if (INF_3C90X.isBrev)
  323. {
  324. maxAddress=0x1f;
  325. cksumAddress=0x20;
  326. }
  327. else
  328. {
  329. maxAddress=0x16;
  330. cksumAddress=0x17;
  331. }
  332. /** Write the value. **/
  333. if (a3c90x_internal_WriteEepromWord(ioaddr, address, value) == -1)
  334. return -1;
  335. /** Recompute the checksum. **/
  336. for(i=0;i<=maxAddress;i++)
  337. {
  338. v = a3c90x_internal_ReadEeprom(ioaddr, i);
  339. cksum ^= (v & 0xFF);
  340. cksum ^= ((v>>8) & 0xFF);
  341. }
  342. /** Write the checksum to the location in the eeprom **/
  343. if (a3c90x_internal_WriteEepromWord(ioaddr, cksumAddress, cksum) == -1)
  344. return -1;
  345. return 0;
  346. }
  347. #endif
  348. /*** a3c90x_reset: exported function that resets the card to its default
  349. *** state. This is so the Linux driver can re-set the card up the way
  350. *** it wants to. If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will
  351. *** not alter the selected transceiver that we used to download the boot
  352. *** image.
  353. ***/
  354. static void a3c90x_reset(void)
  355. {
  356. #ifdef CFG_3C90X_PRESERVE_XCVR
  357. int cfg;
  358. /** Read the current InternalConfig value. **/
  359. a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
  360. cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
  361. #endif
  362. /** Send the reset command to the card **/
  363. printf("Issuing RESET:\n");
  364. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdGlobalReset, 0);
  365. /** wait for reset command to complete **/
  366. while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
  367. /** global reset command resets station mask, non-B revision cards
  368. ** require explicit reset of values
  369. **/
  370. a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
  371. outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
  372. outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
  373. outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
  374. #ifdef CFG_3C90X_PRESERVE_XCVR
  375. /** Re-set the original InternalConfig value from before reset **/
  376. a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
  377. outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
  378. /** enable DC converter for 10-Base-T **/
  379. if ((cfg&0x0300) == 0x0300)
  380. {
  381. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
  382. }
  383. #endif
  384. /** Issue transmit reset, wait for command completion **/
  385. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0);
  386. while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
  387. ;
  388. if (! INF_3C90X.isBrev)
  389. outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
  390. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
  391. /**
  392. ** reset of the receiver on B-revision cards re-negotiates the link
  393. ** takes several seconds (a computer eternity)
  394. **/
  395. if (INF_3C90X.isBrev)
  396. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04);
  397. else
  398. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00);
  399. while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
  400. ;
  401. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0);
  402. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
  403. cmdSetInterruptEnable, 0);
  404. /** enable rxComplete and txComplete **/
  405. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
  406. cmdSetIndicationEnable, 0x0014);
  407. /** acknowledge any pending status flags **/
  408. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
  409. cmdAcknowledgeInterrupt, 0x661);
  410. return;
  411. }
  412. /*** a3c90x_transmit: exported function that transmits a packet. Does not
  413. *** return any particular status. Parameters are:
  414. *** d[6] - destination address, ethernet;
  415. *** t - protocol type (ARP, IP, etc);
  416. *** s - size of the non-header part of the packet that needs transmitted;
  417. *** p - the pointer to the packet data itself.
  418. ***/
  419. static void
  420. a3c90x_transmit(struct nic *nic __unused, const char *d, unsigned int t,
  421. unsigned int s, const char *p)
  422. {
  423. struct eth_hdr
  424. {
  425. unsigned char dst_addr[ETH_ALEN];
  426. unsigned char src_addr[ETH_ALEN];
  427. unsigned short type;
  428. } hdr;
  429. unsigned char status;
  430. unsigned i, retries;
  431. for (retries=0; retries < XMIT_RETRIES ; retries++)
  432. {
  433. /** Stall the download engine **/
  434. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 2);
  435. /** Make sure the card is not waiting on us **/
  436. inw(INF_3C90X.IOAddr + regCommandIntStatus_w);
  437. inw(INF_3C90X.IOAddr + regCommandIntStatus_w);
  438. while (inw(INF_3C90X.IOAddr+regCommandIntStatus_w) &
  439. INT_CMDINPROGRESS)
  440. ;
  441. /** Set the ethernet packet type **/
  442. hdr.type = htons(t);
  443. /** Copy the destination address **/
  444. memcpy(hdr.dst_addr, d, ETH_ALEN);
  445. /** Copy our MAC address **/
  446. memcpy(hdr.src_addr, INF_3C90X.HWAddr, ETH_ALEN);
  447. /** Setup the DPD (download descriptor) **/
  448. INF_3C90X.TransmitDPD.DnNextPtr = 0;
  449. /** set notification for transmission completion (bit 15) **/
  450. INF_3C90X.TransmitDPD.FrameStartHeader = (s + sizeof(hdr)) | 0x8000;
  451. INF_3C90X.TransmitDPD.HdrAddr = virt_to_bus(&hdr);
  452. INF_3C90X.TransmitDPD.HdrLength = sizeof(hdr);
  453. INF_3C90X.TransmitDPD.DataAddr = virt_to_bus(p);
  454. INF_3C90X.TransmitDPD.DataLength = s + (1<<31);
  455. /** Send the packet **/
  456. outl(virt_to_bus(&(INF_3C90X.TransmitDPD)),
  457. INF_3C90X.IOAddr + regDnListPtr_l);
  458. /** End Stall and Wait for upload to complete. **/
  459. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 3);
  460. while(inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0)
  461. ;
  462. /** Wait for NIC Transmit to Complete **/
  463. load_timer2(10*TICKS_PER_MS); /* Give it 10 ms */
  464. while (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004) &&
  465. timer2_running())
  466. ;
  467. if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004))
  468. {
  469. printf("3C90X: Tx Timeout\n");
  470. continue;
  471. }
  472. status = inb(INF_3C90X.IOAddr + regTxStatus_b);
  473. /** acknowledge transmit interrupt by writing status **/
  474. outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
  475. /** successful completion (sans "interrupt Requested" bit) **/
  476. if ((status & 0xbf) == 0x80)
  477. return;
  478. printf("3C90X: Status (%hhX)\n", status);
  479. /** check error codes **/
  480. if (status & 0x02)
  481. {
  482. printf("3C90X: Tx Reclaim Error (%hhX)\n", status);
  483. a3c90x_reset();
  484. }
  485. else if (status & 0x04)
  486. {
  487. printf("3C90X: Tx Status Overflow (%hhX)\n", status);
  488. for (i=0; i<32; i++)
  489. outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
  490. /** must re-enable after max collisions before re-issuing tx **/
  491. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
  492. }
  493. else if (status & 0x08)
  494. {
  495. printf("3C90X: Tx Max Collisions (%hhX)\n", status);
  496. /** must re-enable after max collisions before re-issuing tx **/
  497. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
  498. }
  499. else if (status & 0x10)
  500. {
  501. printf("3C90X: Tx Underrun (%hhX)\n", status);
  502. a3c90x_reset();
  503. }
  504. else if (status & 0x20)
  505. {
  506. printf("3C90X: Tx Jabber (%hhX)\n", status);
  507. a3c90x_reset();
  508. }
  509. else if ((status & 0x80) != 0x80)
  510. {
  511. printf("3C90X: Internal Error - Incomplete Transmission (%hhX)\n",
  512. status);
  513. a3c90x_reset();
  514. }
  515. }
  516. /** failed after RETRY attempts **/
  517. printf("Failed to send after %d retries\n", retries);
  518. return;
  519. }
  520. /*** a3c90x_poll: exported routine that waits for a certain length of time
  521. *** for a packet, and if it sees none, returns 0. This routine should
  522. *** copy the packet to nic->packet if it gets a packet and set the size
  523. *** in nic->packetlen. Return 1 if a packet was found.
  524. ***/
  525. static int
  526. a3c90x_poll(struct nic *nic, int retrieve)
  527. {
  528. int i, errcode;
  529. if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0010))
  530. {
  531. return 0;
  532. }
  533. if ( ! retrieve ) return 1;
  534. /** we don't need to acknowledge rxComplete -- the upload engine
  535. ** does it for us.
  536. **/
  537. /** Build the up-load descriptor **/
  538. INF_3C90X.ReceiveUPD.UpNextPtr = 0;
  539. INF_3C90X.ReceiveUPD.UpPktStatus = 0;
  540. INF_3C90X.ReceiveUPD.DataAddr = virt_to_bus(nic->packet);
  541. INF_3C90X.ReceiveUPD.DataLength = 1536 + (1<<31);
  542. /** Submit the upload descriptor to the NIC **/
  543. outl(virt_to_bus(&(INF_3C90X.ReceiveUPD)),
  544. INF_3C90X.IOAddr + regUpListPtr_l);
  545. /** Wait for upload completion (upComplete(15) or upError (14)) **/
  546. for(i=0;i<40000;i++);
  547. while((INF_3C90X.ReceiveUPD.UpPktStatus & ((1<<14) | (1<<15))) == 0)
  548. for(i=0;i<40000;i++);
  549. /** Check for Error (else we have good packet) **/
  550. if (INF_3C90X.ReceiveUPD.UpPktStatus & (1<<14))
  551. {
  552. errcode = INF_3C90X.ReceiveUPD.UpPktStatus;
  553. if (errcode & (1<<16))
  554. printf("3C90X: Rx Overrun (%hX)\n",errcode>>16);
  555. else if (errcode & (1<<17))
  556. printf("3C90X: Runt Frame (%hX)\n",errcode>>16);
  557. else if (errcode & (1<<18))
  558. printf("3C90X: Alignment Error (%hX)\n",errcode>>16);
  559. else if (errcode & (1<<19))
  560. printf("3C90X: CRC Error (%hX)\n",errcode>>16);
  561. else if (errcode & (1<<20))
  562. printf("3C90X: Oversized Frame (%hX)\n",errcode>>16);
  563. else
  564. printf("3C90X: Packet error (%hX)\n",errcode>>16);
  565. return 0;
  566. }
  567. /** Ok, got packet. Set length in nic->packetlen. **/
  568. nic->packetlen = (INF_3C90X.ReceiveUPD.UpPktStatus & 0x1FFF);
  569. return 1;
  570. }
  571. /*** a3c90x_disable: exported routine to disable the card. What's this for?
  572. *** the eepro100.c driver didn't have one, so I just left this one empty too.
  573. *** Ideas anyone?
  574. *** Must turn off receiver at least so stray packets will not corrupt memory
  575. *** [Ken]
  576. ***/
  577. static void
  578. a3c90x_disable ( struct nic *nic __unused ) {
  579. a3c90x_reset();
  580. /* Disable the receiver and transmitter. */
  581. outw(cmdRxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
  582. outw(cmdTxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
  583. }
  584. static void a3c90x_irq(struct nic *nic __unused, irq_action_t action __unused)
  585. {
  586. switch ( action ) {
  587. case DISABLE :
  588. break;
  589. case ENABLE :
  590. break;
  591. case FORCE :
  592. break;
  593. }
  594. }
  595. /*** a3c90x_probe: exported routine to probe for the 3c905 card and perform
  596. *** initialization. If this routine is called, the pci functions did find the
  597. *** card. We just have to init it here.
  598. ***/
  599. static int a3c90x_probe ( struct nic *nic, struct pci_device *pci ) {
  600. int i, c;
  601. unsigned short eeprom[0x21];
  602. unsigned int cfg;
  603. unsigned int mopt;
  604. unsigned int mstat;
  605. unsigned short linktype;
  606. #define HWADDR_OFFSET 10
  607. if (pci->ioaddr == 0)
  608. return 0;
  609. adjust_pci_device(pci);
  610. pci_fill_nic ( nic, pci );
  611. nic->ioaddr = pci->ioaddr;
  612. nic->irqno = 0;
  613. INF_3C90X.is3c556 = (pci->device == 0x6055);
  614. INF_3C90X.IOAddr = pci->ioaddr & ~3;
  615. INF_3C90X.CurrentWindow = 255;
  616. switch (a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, 0x03))
  617. {
  618. case 0x9000: /** 10 Base TPO **/
  619. case 0x9001: /** 10/100 T4 **/
  620. case 0x9050: /** 10/100 TPO **/
  621. case 0x9051: /** 10 Base Combo **/
  622. INF_3C90X.isBrev = 0;
  623. break;
  624. case 0x9004: /** 10 Base TPO **/
  625. case 0x9005: /** 10 Base Combo **/
  626. case 0x9006: /** 10 Base TPO and Base2 **/
  627. case 0x900A: /** 10 Base FL **/
  628. case 0x9055: /** 10/100 TPO **/
  629. case 0x9056: /** 10/100 T4 **/
  630. case 0x905A: /** 10 Base FX **/
  631. default:
  632. INF_3C90X.isBrev = 1;
  633. break;
  634. }
  635. /** Load the EEPROM contents **/
  636. if (INF_3C90X.isBrev)
  637. {
  638. for(i=0;i<=0x20;i++)
  639. {
  640. eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
  641. }
  642. #ifdef CFG_3C90X_BOOTROM_FIX
  643. /** Set xcvrSelect in InternalConfig in eeprom. **/
  644. /* only necessary for 3c905b revision cards with boot PROM bug!!! */
  645. a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x13, 0x0160);
  646. #endif
  647. #ifdef CFG_3C90X_XCVR
  648. if (CFG_3C90X_XCVR == 255)
  649. {
  650. /** Clear the LanWorks register **/
  651. a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16, 0);
  652. }
  653. else
  654. {
  655. /** Set the selected permanent-xcvrSelect in the
  656. ** LanWorks register
  657. **/
  658. a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16,
  659. XCVR_MAGIC + ((CFG_3C90X_XCVR) & 0x000F));
  660. }
  661. #endif
  662. }
  663. else
  664. {
  665. for(i=0;i<=0x17;i++)
  666. {
  667. eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
  668. }
  669. }
  670. /** Print identification message **/
  671. printf("\n\n3C90X Driver 2.00 "
  672. "Copyright 1999 LightSys Technology Services, Inc.\n"
  673. "Portions Copyright 1999 Steve Smith\n");
  674. printf("Provided with ABSOLUTELY NO WARRANTY.\n");
  675. #ifdef CFG_3C90X_BOOTROM_FIX
  676. if (INF_3C90X.isBrev)
  677. {
  678. printf("NOTE: 3c905b bootrom fix enabled; has side "
  679. "effects. See 3c90x.txt for info.\n");
  680. }
  681. #endif
  682. printf("-------------------------------------------------------"
  683. "------------------------\n");
  684. /** Retrieve the Hardware address and print it on the screen. **/
  685. INF_3C90X.HWAddr[0] = eeprom[HWADDR_OFFSET + 0]>>8;
  686. INF_3C90X.HWAddr[1] = eeprom[HWADDR_OFFSET + 0]&0xFF;
  687. INF_3C90X.HWAddr[2] = eeprom[HWADDR_OFFSET + 1]>>8;
  688. INF_3C90X.HWAddr[3] = eeprom[HWADDR_OFFSET + 1]&0xFF;
  689. INF_3C90X.HWAddr[4] = eeprom[HWADDR_OFFSET + 2]>>8;
  690. INF_3C90X.HWAddr[5] = eeprom[HWADDR_OFFSET + 2]&0xFF;
  691. DBG ( "MAC Address = %s\n", eth_ntoa ( INF_3C90X.HWAddr ) );
  692. /** 3C556: Invert MII power **/
  693. if (INF_3C90X.is3c556) {
  694. unsigned int tmp;
  695. a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
  696. tmp = inw(INF_3C90X.IOAddr + regResetOptions_2_w);
  697. tmp |= 0x4000;
  698. outw(tmp, INF_3C90X.IOAddr + regResetOptions_2_w);
  699. }
  700. /* Test if the link is good, if not continue */
  701. a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winDiagnostics4);
  702. mstat = inw(INF_3C90X.IOAddr + regMediaStatus_4_w);
  703. if((mstat & (1<<11)) == 0) {
  704. printf("Valid link not established\n");
  705. return 0;
  706. }
  707. /** Program the MAC address into the station address registers **/
  708. a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
  709. outw(htons(eeprom[HWADDR_OFFSET + 0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
  710. outw(htons(eeprom[HWADDR_OFFSET + 1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
  711. outw(htons(eeprom[HWADDR_OFFSET + 2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
  712. outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
  713. outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
  714. outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
  715. /** Fill in our entry in the etherboot arp table **/
  716. for(i=0;i<ETH_ALEN;i++)
  717. nic->node_addr[i] = (eeprom[HWADDR_OFFSET + i/2] >> (8*((i&1)^1))) & 0xff;
  718. /** Read the media options register, print a message and set default
  719. ** xcvr.
  720. **
  721. ** Uses Media Option command on B revision, Reset Option on non-B
  722. ** revision cards -- same register address
  723. **/
  724. a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
  725. mopt = inw(INF_3C90X.IOAddr + regResetMediaOptions_3_w);
  726. /** mask out VCO bit that is defined as 10baseFL bit on B-rev cards **/
  727. if (! INF_3C90X.isBrev)
  728. {
  729. mopt &= 0x7F;
  730. }
  731. printf("Connectors present: ");
  732. c = 0;
  733. linktype = 0x0008;
  734. if (mopt & 0x01)
  735. {
  736. printf("%s100Base-T4",(c++)?", ":"");
  737. linktype = 0x0006;
  738. }
  739. if (mopt & 0x04)
  740. {
  741. printf("%s100Base-FX",(c++)?", ":"");
  742. linktype = 0x0005;
  743. }
  744. if (mopt & 0x10)
  745. {
  746. printf("%s10Base-2",(c++)?", ":"");
  747. linktype = 0x0003;
  748. }
  749. if (mopt & 0x20)
  750. {
  751. printf("%sAUI",(c++)?", ":"");
  752. linktype = 0x0001;
  753. }
  754. if (mopt & 0x40)
  755. {
  756. printf("%sMII",(c++)?", ":"");
  757. linktype = 0x0006;
  758. }
  759. if ((mopt & 0xA) == 0xA)
  760. {
  761. printf("%s10Base-T / 100Base-TX",(c++)?", ":"");
  762. linktype = 0x0008;
  763. }
  764. else if ((mopt & 0xA) == 0x2)
  765. {
  766. printf("%s100Base-TX",(c++)?", ":"");
  767. linktype = 0x0008;
  768. }
  769. else if ((mopt & 0xA) == 0x8)
  770. {
  771. printf("%s10Base-T",(c++)?", ":"");
  772. linktype = 0x0008;
  773. }
  774. printf(".\n");
  775. /** Determine transceiver type to use, depending on value stored in
  776. ** eeprom 0x16
  777. **/
  778. if (INF_3C90X.isBrev)
  779. {
  780. if ((eeprom[0x16] & 0xFF00) == XCVR_MAGIC)
  781. {
  782. /** User-defined **/
  783. linktype = eeprom[0x16] & 0x000F;
  784. }
  785. }
  786. else
  787. {
  788. #ifdef CFG_3C90X_XCVR
  789. if (CFG_3C90X_XCVR != 255)
  790. linktype = CFG_3C90X_XCVR;
  791. #endif /* CFG_3C90X_XCVR */
  792. /** I don't know what MII MAC only mode is!!! **/
  793. if (linktype == 0x0009)
  794. {
  795. if (INF_3C90X.isBrev)
  796. printf("WARNING: MII External MAC Mode only supported on B-revision "
  797. "cards!!!!\nFalling Back to MII Mode\n");
  798. linktype = 0x0006;
  799. }
  800. }
  801. /** enable DC converter for 10-Base-T **/
  802. if (linktype == 0x0003)
  803. {
  804. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
  805. }
  806. /** Set the link to the type we just determined. **/
  807. a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
  808. cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
  809. cfg &= ~(0xF<<20);
  810. cfg |= (linktype<<20);
  811. outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
  812. /** Now that we set the xcvr type, reset the Tx and Rx, re-enable. **/
  813. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0x00);
  814. while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
  815. ;
  816. if (!INF_3C90X.isBrev)
  817. outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
  818. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
  819. /**
  820. ** reset of the receiver on B-revision cards re-negotiates the link
  821. ** takes several seconds (a computer eternity)
  822. **/
  823. if (INF_3C90X.isBrev)
  824. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04);
  825. else
  826. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00);
  827. while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
  828. ;
  829. /** Set the RX filter = receive only individual pkts & multicast & bcast. **/
  830. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x02 + 0x04);
  831. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0);
  832. /**
  833. ** set Indication and Interrupt flags , acknowledge any IRQ's
  834. **/
  835. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
  836. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
  837. cmdSetIndicationEnable, 0x0014);
  838. a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
  839. cmdAcknowledgeInterrupt, 0x661);
  840. /** Set our exported functions **/
  841. nic->nic_op = &a3c90x_operations;
  842. return 1;
  843. }
  844. static struct nic_operations a3c90x_operations = {
  845. .connect = dummy_connect,
  846. .poll = a3c90x_poll,
  847. .transmit = a3c90x_transmit,
  848. .irq = a3c90x_irq,
  849. };
  850. static struct pci_device_id a3c90x_nics[] = {
  851. /* Original 90x revisions: */
  852. PCI_ROM(0x10b7, 0x6055, "3c556", "3C556"), /* Huricane */
  853. PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO"), /* 10 Base TPO */
  854. PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo"), /* 10/100 T4 */
  855. PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX"), /* 100 Base TX / 10/100 TPO */
  856. PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4"), /* 100 Base T4 / 10 Base Combo */
  857. /* Newer 90xB revisions: */
  858. PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO"), /* 10 Base TPO */
  859. PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo"), /* 10 Base Combo */
  860. PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T"), /* 10 Base TP and Base2 */
  861. PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL"), /* 10 Base FL */
  862. PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX"), /* 10/100 TPO */
  863. PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4"), /* 10/100 T4 */
  864. PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058"), /* Cyclone 10/100/BNC */
  865. PCI_ROM(0x10b7, 0x905a, "3c905b-fx", "3Com905B-FL"), /* 100 Base FX / 10 Base FX */
  866. /* Newer 90xC revision: */
  867. PCI_ROM(0x10b7, 0x9200, "3c905c-tpo", "3Com905C-TXM"), /* 10/100 TPO (3C905C-TXM) */
  868. PCI_ROM(0x10b7, 0x9202, "3c920b-emb-ati", "3c920B-EMB-WNM (ATI Radeon 9100 IGP)"), /* 3c920B-EMB-WNM (ATI Radeon 9100 IGP) */
  869. PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm","3Com20B-EMB WNM"),
  870. PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone"), /* Cyclone */
  871. PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805"), /* Dual Port Server Cyclone */
  872. PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX"), /* Hurricane */
  873. PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado"),
  874. PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A"),
  875. PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B"),
  876. };
  877. PCI_DRIVER ( a3c90x_driver, a3c90x_nics, PCI_NO_CLASS );
  878. DRIVER ( "3C90X", nic_driver, pci_driver, a3c90x_driver,
  879. a3c90x_probe, a3c90x_disable );