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natsemi.h 5.6KB

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  1. FILE_LICENCE ( GPL_ANY );
  2. #define NATSEMI_HW_TIMEOUT 400
  3. #define TX_RING_SIZE 4
  4. #define NUM_RX_DESC 4
  5. #define RX_BUF_SIZE 1536
  6. #define OWN 0x80000000
  7. #define DSIZE 0x00000FFF
  8. #define CRC_SIZE 4
  9. struct natsemi_tx {
  10. uint32_t link;
  11. uint32_t cmdsts;
  12. uint32_t bufptr;
  13. };
  14. struct natsemi_rx {
  15. uint32_t link;
  16. uint32_t cmdsts;
  17. uint32_t bufptr;
  18. };
  19. struct natsemi_private {
  20. unsigned short ioaddr;
  21. unsigned short tx_cur;
  22. unsigned short tx_dirty;
  23. unsigned short rx_cur;
  24. struct natsemi_tx tx[TX_RING_SIZE];
  25. struct natsemi_rx rx[NUM_RX_DESC];
  26. /* need to add iobuf as we cannot free iobuf->data in close without this
  27. * alternatively substracting sizeof(head) and sizeof(list_head) can also
  28. * give the same.
  29. */
  30. struct io_buffer *iobuf[NUM_RX_DESC];
  31. /* netdev_tx_complete needs pointer to the iobuf of the data so as to free
  32. * it from the memory.
  33. */
  34. struct io_buffer *tx_iobuf[TX_RING_SIZE];
  35. struct spi_bit_basher spibit;
  36. struct spi_device eeprom;
  37. struct nvo_block nvo;
  38. };
  39. /*
  40. * Support for fibre connections on Am79C874:
  41. * This phy needs a special setup when connected to a fibre cable.
  42. * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
  43. */
  44. #define PHYID_AM79C874 0x0022561b
  45. enum {
  46. MII_MCTRL = 0x15, /* mode control register */
  47. MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
  48. MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
  49. };
  50. /* values we might find in the silicon revision register */
  51. #define SRR_DP83815_C 0x0302
  52. #define SRR_DP83815_D 0x0403
  53. #define SRR_DP83816_A4 0x0504
  54. #define SRR_DP83816_A5 0x0505
  55. /* NATSEMI: Offsets to the device registers.
  56. * Unlike software-only systems, device drivers interact with complex hardware.
  57. * It's not useful to define symbolic names for every register bit in the
  58. * device.
  59. */
  60. enum register_offsets {
  61. ChipCmd = 0x00,
  62. ChipConfig = 0x04,
  63. EECtrl = 0x08,
  64. PCIBusCfg = 0x0C,
  65. IntrStatus = 0x10,
  66. IntrMask = 0x14,
  67. IntrEnable = 0x18,
  68. TxRingPtr = 0x20,
  69. TxConfig = 0x24,
  70. RxRingPtr = 0x30,
  71. RxConfig = 0x34,
  72. ClkRun = 0x3C,
  73. WOLCmd = 0x40,
  74. PauseCmd = 0x44,
  75. RxFilterAddr = 0x48,
  76. RxFilterData = 0x4C,
  77. BootRomAddr = 0x50,
  78. BootRomData = 0x54,
  79. SiliconRev = 0x58,
  80. StatsCtrl = 0x5C,
  81. StatsData = 0x60,
  82. RxPktErrs = 0x60,
  83. RxMissed = 0x68,
  84. RxCRCErrs = 0x64,
  85. PCIPM = 0x44,
  86. PhyStatus = 0xC0,
  87. MIntrCtrl = 0xC4,
  88. MIntrStatus = 0xC8,
  89. /* These are from the spec, around page 78... on a separate table.
  90. */
  91. PGSEL = 0xCC,
  92. PMDCSR = 0xE4,
  93. TSTDAT = 0xFC,
  94. DSPCFG = 0xF4,
  95. SDCFG = 0x8C,
  96. BasicControl = 0x80,
  97. BasicStatus = 0x84
  98. };
  99. /* the values for the 'magic' registers above (PGSEL=1) */
  100. #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
  101. #define TSTDAT_VAL 0x0
  102. #define DSPCFG_VAL 0x5040
  103. #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
  104. #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
  105. #define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
  106. #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
  107. /* Bit in ChipCmd.
  108. */
  109. enum ChipCmdBits {
  110. ChipReset = 0x100,
  111. RxReset = 0x20,
  112. TxReset = 0x10,
  113. RxOff = 0x08,
  114. RxOn = 0x04,
  115. TxOff = 0x02,
  116. TxOn = 0x01
  117. };
  118. enum ChipConfig_bits {
  119. CfgPhyDis = 0x200,
  120. CfgPhyRst = 0x400,
  121. CfgExtPhy = 0x1000,
  122. CfgAnegEnable = 0x2000,
  123. CfgAneg100 = 0x4000,
  124. CfgAnegFull = 0x8000,
  125. CfgAnegDone = 0x8000000,
  126. CfgFullDuplex = 0x20000000,
  127. CfgSpeed100 = 0x40000000,
  128. CfgLink = 0x80000000,
  129. };
  130. /* Bits in the RxMode register.
  131. */
  132. enum rx_mode_bits {
  133. AcceptErr = 0x20,
  134. AcceptRunt = 0x10,
  135. AcceptBroadcast = 0xC0000000,
  136. AcceptMulticast = 0x00200000,
  137. AcceptAllMulticast = 0x20000000,
  138. AcceptAllPhys = 0x10000000,
  139. AcceptMyPhys = 0x08000000,
  140. RxFilterEnable = 0x80000000
  141. };
  142. /* Bits in network_desc.status
  143. */
  144. enum desc_status_bits {
  145. DescOwn = 0x80000000,
  146. DescMore = 0x40000000,
  147. DescIntr = 0x20000000,
  148. DescNoCRC = 0x10000000,
  149. DescPktOK = 0x08000000,
  150. RxTooLong = 0x00400000
  151. };
  152. /*Bits in Interrupt Mask register
  153. */
  154. enum Intr_mask_register_bits {
  155. RxOk = 0x001,
  156. RxErr = 0x004,
  157. TxOk = 0x040,
  158. TxErr = 0x100
  159. };
  160. enum MIntrCtrl_bits {
  161. MICRIntEn = 0x2,
  162. };
  163. /* CFG bits [13:16] [18:23] */
  164. #define CFG_RESET_SAVE 0xfde000
  165. /* WCSR bits [0:4] [9:10] */
  166. #define WCSR_RESET_SAVE 0x61f
  167. /* RFCR bits [20] [22] [27:31] */
  168. #define RFCR_RESET_SAVE 0xf8500000;
  169. /* Delay between EEPROM clock transitions.
  170. No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
  171. a delay. */
  172. #define eeprom_delay(ee_addr) inl(ee_addr)
  173. enum EEPROM_Ctrl_Bits {
  174. EE_ShiftClk = 0x04,
  175. EE_DataIn = 0x01,
  176. EE_ChipSelect = 0x08,
  177. EE_DataOut = 0x02
  178. };
  179. #define EE_Write0 (EE_ChipSelect)
  180. #define EE_Write1 (EE_ChipSelect | EE_DataIn)
  181. /* The EEPROM commands include the alway-set leading bit. */
  182. enum EEPROM_Cmds {
  183. EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
  184. };
  185. /* EEPROM access , values are devices specific
  186. */
  187. #define EE_CS 0x08 /* EEPROM chip select */
  188. #define EE_SK 0x04 /* EEPROM shift clock */
  189. #define EE_DI 0x01 /* Data in */
  190. #define EE_DO 0x02 /* Data out */
  191. /* Offsets within EEPROM (these are word offsets)
  192. */
  193. #define EE_MAC 7
  194. #define EE_REG EECtrl
  195. static const uint8_t natsemi_ee_bits[] = {
  196. [SPI_BIT_SCLK] = EE_SK,
  197. [SPI_BIT_MOSI] = EE_DI,
  198. [SPI_BIT_MISO] = EE_DO,
  199. [SPI_BIT_SS(0)] = EE_CS,
  200. };