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hermon.c 74KB

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  1. /*
  2. * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
  3. * Copyright (C) 2008 Mellanox Technologies Ltd.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of the
  8. * License, or any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. FILE_LICENCE ( GPL2_OR_LATER );
  20. #include <stdint.h>
  21. #include <stdlib.h>
  22. #include <stdio.h>
  23. #include <string.h>
  24. #include <strings.h>
  25. #include <unistd.h>
  26. #include <errno.h>
  27. #include <byteswap.h>
  28. #include <gpxe/io.h>
  29. #include <gpxe/pci.h>
  30. #include <gpxe/malloc.h>
  31. #include <gpxe/umalloc.h>
  32. #include <gpxe/iobuf.h>
  33. #include <gpxe/netdevice.h>
  34. #include <gpxe/infiniband.h>
  35. #include <gpxe/ib_smc.h>
  36. #include "hermon.h"
  37. /**
  38. * @file
  39. *
  40. * Mellanox Hermon Infiniband HCA
  41. *
  42. */
  43. /***************************************************************************
  44. *
  45. * Queue number allocation
  46. *
  47. ***************************************************************************
  48. */
  49. /**
  50. * Allocate offsets within usage bitmask
  51. *
  52. * @v bits Usage bitmask
  53. * @v bits_len Length of usage bitmask
  54. * @v num_bits Number of contiguous bits to allocate within bitmask
  55. * @ret bit First free bit within bitmask, or negative error
  56. */
  57. static int hermon_bitmask_alloc ( hermon_bitmask_t *bits,
  58. unsigned int bits_len,
  59. unsigned int num_bits ) {
  60. unsigned int bit = 0;
  61. hermon_bitmask_t mask = 1;
  62. unsigned int found = 0;
  63. /* Search bits for num_bits contiguous free bits */
  64. while ( bit < bits_len ) {
  65. if ( ( mask & *bits ) == 0 ) {
  66. if ( ++found == num_bits )
  67. goto found;
  68. } else {
  69. found = 0;
  70. }
  71. bit++;
  72. mask = ( mask << 1 ) | ( mask >> ( 8 * sizeof ( mask ) - 1 ) );
  73. if ( mask == 1 )
  74. bits++;
  75. }
  76. return -ENFILE;
  77. found:
  78. /* Mark bits as in-use */
  79. do {
  80. *bits |= mask;
  81. if ( mask == 1 )
  82. bits--;
  83. mask = ( mask >> 1 ) | ( mask << ( 8 * sizeof ( mask ) - 1 ) );
  84. } while ( --found );
  85. return ( bit - num_bits + 1 );
  86. }
  87. /**
  88. * Free offsets within usage bitmask
  89. *
  90. * @v bits Usage bitmask
  91. * @v bit Starting bit within bitmask
  92. * @v num_bits Number of contiguous bits to free within bitmask
  93. */
  94. static void hermon_bitmask_free ( hermon_bitmask_t *bits,
  95. int bit, unsigned int num_bits ) {
  96. hermon_bitmask_t mask;
  97. for ( ; num_bits ; bit++, num_bits-- ) {
  98. mask = ( 1 << ( bit % ( 8 * sizeof ( mask ) ) ) );
  99. bits[ ( bit / ( 8 * sizeof ( mask ) ) ) ] &= ~mask;
  100. }
  101. }
  102. /***************************************************************************
  103. *
  104. * HCA commands
  105. *
  106. ***************************************************************************
  107. */
  108. /**
  109. * Wait for Hermon command completion
  110. *
  111. * @v hermon Hermon device
  112. * @v hcr HCA command registers
  113. * @ret rc Return status code
  114. */
  115. static int hermon_cmd_wait ( struct hermon *hermon,
  116. struct hermonprm_hca_command_register *hcr ) {
  117. unsigned int wait;
  118. for ( wait = HERMON_HCR_MAX_WAIT_MS ; wait ; wait-- ) {
  119. hcr->u.dwords[6] =
  120. readl ( hermon->config + HERMON_HCR_REG ( 6 ) );
  121. if ( ( MLX_GET ( hcr, go ) == 0 ) &&
  122. ( MLX_GET ( hcr, t ) == hermon->toggle ) )
  123. return 0;
  124. mdelay ( 1 );
  125. }
  126. return -EBUSY;
  127. }
  128. /**
  129. * Issue HCA command
  130. *
  131. * @v hermon Hermon device
  132. * @v command Command opcode, flags and input/output lengths
  133. * @v op_mod Opcode modifier (0 if no modifier applicable)
  134. * @v in Input parameters
  135. * @v in_mod Input modifier (0 if no modifier applicable)
  136. * @v out Output parameters
  137. * @ret rc Return status code
  138. */
  139. static int hermon_cmd ( struct hermon *hermon, unsigned long command,
  140. unsigned int op_mod, const void *in,
  141. unsigned int in_mod, void *out ) {
  142. struct hermonprm_hca_command_register hcr;
  143. unsigned int opcode = HERMON_HCR_OPCODE ( command );
  144. size_t in_len = HERMON_HCR_IN_LEN ( command );
  145. size_t out_len = HERMON_HCR_OUT_LEN ( command );
  146. void *in_buffer;
  147. void *out_buffer;
  148. unsigned int status;
  149. unsigned int i;
  150. int rc;
  151. assert ( in_len <= HERMON_MBOX_SIZE );
  152. assert ( out_len <= HERMON_MBOX_SIZE );
  153. DBGC2 ( hermon, "Hermon %p command %02x in %zx%s out %zx%s\n",
  154. hermon, opcode, in_len,
  155. ( ( command & HERMON_HCR_IN_MBOX ) ? "(mbox)" : "" ), out_len,
  156. ( ( command & HERMON_HCR_OUT_MBOX ) ? "(mbox)" : "" ) );
  157. /* Check that HCR is free */
  158. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  159. DBGC ( hermon, "Hermon %p command interface locked\n",
  160. hermon );
  161. return rc;
  162. }
  163. /* Flip HCR toggle */
  164. hermon->toggle = ( 1 - hermon->toggle );
  165. /* Prepare HCR */
  166. memset ( &hcr, 0, sizeof ( hcr ) );
  167. in_buffer = &hcr.u.dwords[0];
  168. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  169. in_buffer = hermon->mailbox_in;
  170. MLX_FILL_1 ( &hcr, 1, in_param_l, virt_to_bus ( in_buffer ) );
  171. }
  172. memcpy ( in_buffer, in, in_len );
  173. MLX_FILL_1 ( &hcr, 2, input_modifier, in_mod );
  174. out_buffer = &hcr.u.dwords[3];
  175. if ( out_len && ( command & HERMON_HCR_OUT_MBOX ) ) {
  176. out_buffer = hermon->mailbox_out;
  177. MLX_FILL_1 ( &hcr, 4, out_param_l,
  178. virt_to_bus ( out_buffer ) );
  179. }
  180. MLX_FILL_4 ( &hcr, 6,
  181. opcode, opcode,
  182. opcode_modifier, op_mod,
  183. go, 1,
  184. t, hermon->toggle );
  185. DBGC ( hermon, "Hermon %p issuing command:\n", hermon );
  186. DBGC_HDA ( hermon, virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  187. &hcr, sizeof ( hcr ) );
  188. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  189. DBGC2 ( hermon, "Input mailbox:\n" );
  190. DBGC2_HDA ( hermon, virt_to_phys ( in_buffer ), in_buffer,
  191. ( ( in_len < 512 ) ? in_len : 512 ) );
  192. }
  193. /* Issue command */
  194. for ( i = 0 ; i < ( sizeof ( hcr ) / sizeof ( hcr.u.dwords[0] ) ) ;
  195. i++ ) {
  196. writel ( hcr.u.dwords[i],
  197. hermon->config + HERMON_HCR_REG ( i ) );
  198. barrier();
  199. }
  200. /* Wait for command completion */
  201. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  202. DBGC ( hermon, "Hermon %p timed out waiting for command:\n",
  203. hermon );
  204. DBGC_HDA ( hermon,
  205. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  206. &hcr, sizeof ( hcr ) );
  207. return rc;
  208. }
  209. /* Check command status */
  210. status = MLX_GET ( &hcr, status );
  211. if ( status != 0 ) {
  212. DBGC ( hermon, "Hermon %p command failed with status %02x:\n",
  213. hermon, status );
  214. DBGC_HDA ( hermon,
  215. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  216. &hcr, sizeof ( hcr ) );
  217. return -EIO;
  218. }
  219. /* Read output parameters, if any */
  220. hcr.u.dwords[3] = readl ( hermon->config + HERMON_HCR_REG ( 3 ) );
  221. hcr.u.dwords[4] = readl ( hermon->config + HERMON_HCR_REG ( 4 ) );
  222. memcpy ( out, out_buffer, out_len );
  223. if ( out_len ) {
  224. DBGC2 ( hermon, "Output%s:\n",
  225. ( command & HERMON_HCR_OUT_MBOX ) ? " mailbox" : "" );
  226. DBGC2_HDA ( hermon, virt_to_phys ( out_buffer ), out_buffer,
  227. ( ( out_len < 512 ) ? out_len : 512 ) );
  228. }
  229. return 0;
  230. }
  231. static inline int
  232. hermon_cmd_query_dev_cap ( struct hermon *hermon,
  233. struct hermonprm_query_dev_cap *dev_cap ) {
  234. return hermon_cmd ( hermon,
  235. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_DEV_CAP,
  236. 1, sizeof ( *dev_cap ) ),
  237. 0, NULL, 0, dev_cap );
  238. }
  239. static inline int
  240. hermon_cmd_query_fw ( struct hermon *hermon, struct hermonprm_query_fw *fw ) {
  241. return hermon_cmd ( hermon,
  242. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_FW,
  243. 1, sizeof ( *fw ) ),
  244. 0, NULL, 0, fw );
  245. }
  246. static inline int
  247. hermon_cmd_init_hca ( struct hermon *hermon,
  248. const struct hermonprm_init_hca *init_hca ) {
  249. return hermon_cmd ( hermon,
  250. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_HCA,
  251. 1, sizeof ( *init_hca ) ),
  252. 0, init_hca, 0, NULL );
  253. }
  254. static inline int
  255. hermon_cmd_close_hca ( struct hermon *hermon ) {
  256. return hermon_cmd ( hermon,
  257. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_HCA ),
  258. 0, NULL, 0, NULL );
  259. }
  260. static inline int
  261. hermon_cmd_init_port ( struct hermon *hermon, unsigned int port,
  262. const struct hermonprm_init_port *init_port ) {
  263. return hermon_cmd ( hermon,
  264. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_PORT,
  265. 1, sizeof ( *init_port ) ),
  266. 0, init_port, port, NULL );
  267. }
  268. static inline int
  269. hermon_cmd_close_port ( struct hermon *hermon, unsigned int port ) {
  270. return hermon_cmd ( hermon,
  271. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_PORT ),
  272. 0, NULL, port, NULL );
  273. }
  274. static inline int
  275. hermon_cmd_sw2hw_mpt ( struct hermon *hermon, unsigned int index,
  276. const struct hermonprm_mpt *mpt ) {
  277. return hermon_cmd ( hermon,
  278. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_MPT,
  279. 1, sizeof ( *mpt ) ),
  280. 0, mpt, index, NULL );
  281. }
  282. static inline int
  283. hermon_cmd_write_mtt ( struct hermon *hermon,
  284. const struct hermonprm_write_mtt *write_mtt ) {
  285. return hermon_cmd ( hermon,
  286. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MTT,
  287. 1, sizeof ( *write_mtt ) ),
  288. 0, write_mtt, 1, NULL );
  289. }
  290. static inline int
  291. hermon_cmd_map_eq ( struct hermon *hermon, unsigned long index_map,
  292. const struct hermonprm_event_mask *mask ) {
  293. return hermon_cmd ( hermon,
  294. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_EQ,
  295. 0, sizeof ( *mask ) ),
  296. 0, mask, index_map, NULL );
  297. }
  298. static inline int
  299. hermon_cmd_sw2hw_eq ( struct hermon *hermon, unsigned int index,
  300. const struct hermonprm_eqc *eqctx ) {
  301. return hermon_cmd ( hermon,
  302. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_EQ,
  303. 1, sizeof ( *eqctx ) ),
  304. 0, eqctx, index, NULL );
  305. }
  306. static inline int
  307. hermon_cmd_hw2sw_eq ( struct hermon *hermon, unsigned int index,
  308. struct hermonprm_eqc *eqctx ) {
  309. return hermon_cmd ( hermon,
  310. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_EQ,
  311. 1, sizeof ( *eqctx ) ),
  312. 1, NULL, index, eqctx );
  313. }
  314. static inline int
  315. hermon_cmd_query_eq ( struct hermon *hermon, unsigned int index,
  316. struct hermonprm_eqc *eqctx ) {
  317. return hermon_cmd ( hermon,
  318. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_EQ,
  319. 1, sizeof ( *eqctx ) ),
  320. 0, NULL, index, eqctx );
  321. }
  322. static inline int
  323. hermon_cmd_sw2hw_cq ( struct hermon *hermon, unsigned long cqn,
  324. const struct hermonprm_completion_queue_context *cqctx ){
  325. return hermon_cmd ( hermon,
  326. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_CQ,
  327. 1, sizeof ( *cqctx ) ),
  328. 0, cqctx, cqn, NULL );
  329. }
  330. static inline int
  331. hermon_cmd_hw2sw_cq ( struct hermon *hermon, unsigned long cqn,
  332. struct hermonprm_completion_queue_context *cqctx) {
  333. return hermon_cmd ( hermon,
  334. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_CQ,
  335. 1, sizeof ( *cqctx ) ),
  336. 0, NULL, cqn, cqctx );
  337. }
  338. static inline int
  339. hermon_cmd_rst2init_qp ( struct hermon *hermon, unsigned long qpn,
  340. const struct hermonprm_qp_ee_state_transitions *ctx ){
  341. return hermon_cmd ( hermon,
  342. HERMON_HCR_IN_CMD ( HERMON_HCR_RST2INIT_QP,
  343. 1, sizeof ( *ctx ) ),
  344. 0, ctx, qpn, NULL );
  345. }
  346. static inline int
  347. hermon_cmd_init2rtr_qp ( struct hermon *hermon, unsigned long qpn,
  348. const struct hermonprm_qp_ee_state_transitions *ctx ){
  349. return hermon_cmd ( hermon,
  350. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT2RTR_QP,
  351. 1, sizeof ( *ctx ) ),
  352. 0, ctx, qpn, NULL );
  353. }
  354. static inline int
  355. hermon_cmd_rtr2rts_qp ( struct hermon *hermon, unsigned long qpn,
  356. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  357. return hermon_cmd ( hermon,
  358. HERMON_HCR_IN_CMD ( HERMON_HCR_RTR2RTS_QP,
  359. 1, sizeof ( *ctx ) ),
  360. 0, ctx, qpn, NULL );
  361. }
  362. static inline int
  363. hermon_cmd_rts2rts_qp ( struct hermon *hermon, unsigned long qpn,
  364. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  365. return hermon_cmd ( hermon,
  366. HERMON_HCR_IN_CMD ( HERMON_HCR_RTS2RTS_QP,
  367. 1, sizeof ( *ctx ) ),
  368. 0, ctx, qpn, NULL );
  369. }
  370. static inline int
  371. hermon_cmd_2rst_qp ( struct hermon *hermon, unsigned long qpn ) {
  372. return hermon_cmd ( hermon,
  373. HERMON_HCR_VOID_CMD ( HERMON_HCR_2RST_QP ),
  374. 0x03, NULL, qpn, NULL );
  375. }
  376. static inline int
  377. hermon_cmd_conf_special_qp ( struct hermon *hermon, unsigned int internal_qps,
  378. unsigned long base_qpn ) {
  379. return hermon_cmd ( hermon,
  380. HERMON_HCR_VOID_CMD ( HERMON_HCR_CONF_SPECIAL_QP ),
  381. internal_qps, NULL, base_qpn, NULL );
  382. }
  383. static inline int
  384. hermon_cmd_mad_ifc ( struct hermon *hermon, unsigned int port,
  385. union hermonprm_mad *mad ) {
  386. return hermon_cmd ( hermon,
  387. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MAD_IFC,
  388. 1, sizeof ( *mad ),
  389. 1, sizeof ( *mad ) ),
  390. 0x03, mad, port, mad );
  391. }
  392. static inline int
  393. hermon_cmd_read_mcg ( struct hermon *hermon, unsigned int index,
  394. struct hermonprm_mcg_entry *mcg ) {
  395. return hermon_cmd ( hermon,
  396. HERMON_HCR_OUT_CMD ( HERMON_HCR_READ_MCG,
  397. 1, sizeof ( *mcg ) ),
  398. 0, NULL, index, mcg );
  399. }
  400. static inline int
  401. hermon_cmd_write_mcg ( struct hermon *hermon, unsigned int index,
  402. const struct hermonprm_mcg_entry *mcg ) {
  403. return hermon_cmd ( hermon,
  404. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MCG,
  405. 1, sizeof ( *mcg ) ),
  406. 0, mcg, index, NULL );
  407. }
  408. static inline int
  409. hermon_cmd_mgid_hash ( struct hermon *hermon, const struct ib_gid *gid,
  410. struct hermonprm_mgm_hash *hash ) {
  411. return hermon_cmd ( hermon,
  412. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MGID_HASH,
  413. 1, sizeof ( *gid ),
  414. 0, sizeof ( *hash ) ),
  415. 0, gid, 0, hash );
  416. }
  417. static inline int
  418. hermon_cmd_run_fw ( struct hermon *hermon ) {
  419. return hermon_cmd ( hermon,
  420. HERMON_HCR_VOID_CMD ( HERMON_HCR_RUN_FW ),
  421. 0, NULL, 0, NULL );
  422. }
  423. static inline int
  424. hermon_cmd_unmap_icm ( struct hermon *hermon, unsigned int page_count,
  425. const struct hermonprm_scalar_parameter *offset ) {
  426. return hermon_cmd ( hermon,
  427. HERMON_HCR_IN_CMD ( HERMON_HCR_UNMAP_ICM,
  428. 0, sizeof ( *offset ) ),
  429. 0, offset, page_count, NULL );
  430. }
  431. static inline int
  432. hermon_cmd_map_icm ( struct hermon *hermon,
  433. const struct hermonprm_virtual_physical_mapping *map ) {
  434. return hermon_cmd ( hermon,
  435. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM,
  436. 1, sizeof ( *map ) ),
  437. 0, map, 1, NULL );
  438. }
  439. static inline int
  440. hermon_cmd_unmap_icm_aux ( struct hermon *hermon ) {
  441. return hermon_cmd ( hermon,
  442. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_ICM_AUX ),
  443. 0, NULL, 0, NULL );
  444. }
  445. static inline int
  446. hermon_cmd_map_icm_aux ( struct hermon *hermon,
  447. const struct hermonprm_virtual_physical_mapping *map ) {
  448. return hermon_cmd ( hermon,
  449. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM_AUX,
  450. 1, sizeof ( *map ) ),
  451. 0, map, 1, NULL );
  452. }
  453. static inline int
  454. hermon_cmd_set_icm_size ( struct hermon *hermon,
  455. const struct hermonprm_scalar_parameter *icm_size,
  456. struct hermonprm_scalar_parameter *icm_aux_size ) {
  457. return hermon_cmd ( hermon,
  458. HERMON_HCR_INOUT_CMD ( HERMON_HCR_SET_ICM_SIZE,
  459. 0, sizeof ( *icm_size ),
  460. 0, sizeof (*icm_aux_size) ),
  461. 0, icm_size, 0, icm_aux_size );
  462. }
  463. static inline int
  464. hermon_cmd_unmap_fa ( struct hermon *hermon ) {
  465. return hermon_cmd ( hermon,
  466. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_FA ),
  467. 0, NULL, 0, NULL );
  468. }
  469. static inline int
  470. hermon_cmd_map_fa ( struct hermon *hermon,
  471. const struct hermonprm_virtual_physical_mapping *map ) {
  472. return hermon_cmd ( hermon,
  473. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_FA,
  474. 1, sizeof ( *map ) ),
  475. 0, map, 1, NULL );
  476. }
  477. /***************************************************************************
  478. *
  479. * Memory translation table operations
  480. *
  481. ***************************************************************************
  482. */
  483. /**
  484. * Allocate MTT entries
  485. *
  486. * @v hermon Hermon device
  487. * @v memory Memory to map into MTT
  488. * @v len Length of memory to map
  489. * @v mtt MTT descriptor to fill in
  490. * @ret rc Return status code
  491. */
  492. static int hermon_alloc_mtt ( struct hermon *hermon,
  493. const void *memory, size_t len,
  494. struct hermon_mtt *mtt ) {
  495. struct hermonprm_write_mtt write_mtt;
  496. physaddr_t start;
  497. unsigned int page_offset;
  498. unsigned int num_pages;
  499. int mtt_offset;
  500. unsigned int mtt_base_addr;
  501. unsigned int i;
  502. int rc;
  503. /* Find available MTT entries */
  504. start = virt_to_phys ( memory );
  505. page_offset = ( start & ( HERMON_PAGE_SIZE - 1 ) );
  506. start -= page_offset;
  507. len += page_offset;
  508. num_pages = ( ( len + HERMON_PAGE_SIZE - 1 ) / HERMON_PAGE_SIZE );
  509. mtt_offset = hermon_bitmask_alloc ( hermon->mtt_inuse, HERMON_MAX_MTTS,
  510. num_pages );
  511. if ( mtt_offset < 0 ) {
  512. DBGC ( hermon, "Hermon %p could not allocate %d MTT entries\n",
  513. hermon, num_pages );
  514. rc = mtt_offset;
  515. goto err_mtt_offset;
  516. }
  517. mtt_base_addr = ( ( hermon->cap.reserved_mtts + mtt_offset ) *
  518. hermon->cap.mtt_entry_size );
  519. /* Fill in MTT structure */
  520. mtt->mtt_offset = mtt_offset;
  521. mtt->num_pages = num_pages;
  522. mtt->mtt_base_addr = mtt_base_addr;
  523. mtt->page_offset = page_offset;
  524. /* Construct and issue WRITE_MTT commands */
  525. for ( i = 0 ; i < num_pages ; i++ ) {
  526. memset ( &write_mtt, 0, sizeof ( write_mtt ) );
  527. MLX_FILL_1 ( &write_mtt.mtt_base_addr, 1,
  528. value, mtt_base_addr );
  529. MLX_FILL_2 ( &write_mtt.mtt, 1,
  530. p, 1,
  531. ptag_l, ( start >> 3 ) );
  532. if ( ( rc = hermon_cmd_write_mtt ( hermon,
  533. &write_mtt ) ) != 0 ) {
  534. DBGC ( hermon, "Hermon %p could not write MTT at %x\n",
  535. hermon, mtt_base_addr );
  536. goto err_write_mtt;
  537. }
  538. start += HERMON_PAGE_SIZE;
  539. mtt_base_addr += hermon->cap.mtt_entry_size;
  540. }
  541. return 0;
  542. err_write_mtt:
  543. hermon_bitmask_free ( hermon->mtt_inuse, mtt_offset, num_pages );
  544. err_mtt_offset:
  545. return rc;
  546. }
  547. /**
  548. * Free MTT entries
  549. *
  550. * @v hermon Hermon device
  551. * @v mtt MTT descriptor
  552. */
  553. static void hermon_free_mtt ( struct hermon *hermon,
  554. struct hermon_mtt *mtt ) {
  555. hermon_bitmask_free ( hermon->mtt_inuse, mtt->mtt_offset,
  556. mtt->num_pages );
  557. }
  558. /***************************************************************************
  559. *
  560. * MAD operations
  561. *
  562. ***************************************************************************
  563. */
  564. /**
  565. * Issue management datagram
  566. *
  567. * @v ibdev Infiniband device
  568. * @v mad Management datagram
  569. * @ret rc Return status code
  570. */
  571. static int hermon_mad ( struct ib_device *ibdev, union ib_mad *mad ) {
  572. struct hermon *hermon = ib_get_drvdata ( ibdev );
  573. union hermonprm_mad mad_ifc;
  574. int rc;
  575. linker_assert ( sizeof ( *mad ) == sizeof ( mad_ifc.mad ),
  576. mad_size_mismatch );
  577. /* Copy in request packet */
  578. memcpy ( &mad_ifc.mad, mad, sizeof ( mad_ifc.mad ) );
  579. /* Issue MAD */
  580. if ( ( rc = hermon_cmd_mad_ifc ( hermon, ibdev->port,
  581. &mad_ifc ) ) != 0 ) {
  582. DBGC ( hermon, "Hermon %p could not issue MAD IFC: %s\n",
  583. hermon, strerror ( rc ) );
  584. return rc;
  585. }
  586. /* Copy out reply packet */
  587. memcpy ( mad, &mad_ifc.mad, sizeof ( *mad ) );
  588. if ( mad->hdr.status != 0 ) {
  589. DBGC ( hermon, "Hermon %p MAD IFC status %04x\n",
  590. hermon, ntohs ( mad->hdr.status ) );
  591. return -EIO;
  592. }
  593. return 0;
  594. }
  595. /***************************************************************************
  596. *
  597. * Completion queue operations
  598. *
  599. ***************************************************************************
  600. */
  601. /**
  602. * Create completion queue
  603. *
  604. * @v ibdev Infiniband device
  605. * @v cq Completion queue
  606. * @ret rc Return status code
  607. */
  608. static int hermon_create_cq ( struct ib_device *ibdev,
  609. struct ib_completion_queue *cq ) {
  610. struct hermon *hermon = ib_get_drvdata ( ibdev );
  611. struct hermon_completion_queue *hermon_cq;
  612. struct hermonprm_completion_queue_context cqctx;
  613. int cqn_offset;
  614. unsigned int i;
  615. int rc;
  616. /* Find a free completion queue number */
  617. cqn_offset = hermon_bitmask_alloc ( hermon->cq_inuse,
  618. HERMON_MAX_CQS, 1 );
  619. if ( cqn_offset < 0 ) {
  620. DBGC ( hermon, "Hermon %p out of completion queues\n",
  621. hermon );
  622. rc = cqn_offset;
  623. goto err_cqn_offset;
  624. }
  625. cq->cqn = ( hermon->cap.reserved_cqs + cqn_offset );
  626. /* Allocate control structures */
  627. hermon_cq = zalloc ( sizeof ( *hermon_cq ) );
  628. if ( ! hermon_cq ) {
  629. rc = -ENOMEM;
  630. goto err_hermon_cq;
  631. }
  632. /* Allocate completion queue itself */
  633. hermon_cq->cqe_size = ( cq->num_cqes * sizeof ( hermon_cq->cqe[0] ) );
  634. hermon_cq->cqe = malloc_dma ( hermon_cq->cqe_size,
  635. sizeof ( hermon_cq->cqe[0] ) );
  636. if ( ! hermon_cq->cqe ) {
  637. rc = -ENOMEM;
  638. goto err_cqe;
  639. }
  640. memset ( hermon_cq->cqe, 0, hermon_cq->cqe_size );
  641. for ( i = 0 ; i < cq->num_cqes ; i++ ) {
  642. MLX_FILL_1 ( &hermon_cq->cqe[i].normal, 7, owner, 1 );
  643. }
  644. barrier();
  645. /* Allocate MTT entries */
  646. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_cq->cqe,
  647. hermon_cq->cqe_size,
  648. &hermon_cq->mtt ) ) != 0 )
  649. goto err_alloc_mtt;
  650. /* Hand queue over to hardware */
  651. memset ( &cqctx, 0, sizeof ( cqctx ) );
  652. MLX_FILL_1 ( &cqctx, 0, st, 0xa /* "Event fired" */ );
  653. MLX_FILL_1 ( &cqctx, 2,
  654. page_offset, ( hermon_cq->mtt.page_offset >> 5 ) );
  655. MLX_FILL_2 ( &cqctx, 3,
  656. usr_page, HERMON_UAR_NON_EQ_PAGE,
  657. log_cq_size, fls ( cq->num_cqes - 1 ) );
  658. MLX_FILL_1 ( &cqctx, 7, mtt_base_addr_l,
  659. ( hermon_cq->mtt.mtt_base_addr >> 3 ) );
  660. MLX_FILL_1 ( &cqctx, 15, db_record_addr_l,
  661. ( virt_to_phys ( &hermon_cq->doorbell ) >> 3 ) );
  662. if ( ( rc = hermon_cmd_sw2hw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  663. DBGC ( hermon, "Hermon %p SW2HW_CQ failed: %s\n",
  664. hermon, strerror ( rc ) );
  665. goto err_sw2hw_cq;
  666. }
  667. DBGC ( hermon, "Hermon %p CQN %#lx ring at [%p,%p)\n",
  668. hermon, cq->cqn, hermon_cq->cqe,
  669. ( ( ( void * ) hermon_cq->cqe ) + hermon_cq->cqe_size ) );
  670. ib_cq_set_drvdata ( cq, hermon_cq );
  671. return 0;
  672. err_sw2hw_cq:
  673. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  674. err_alloc_mtt:
  675. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  676. err_cqe:
  677. free ( hermon_cq );
  678. err_hermon_cq:
  679. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  680. err_cqn_offset:
  681. return rc;
  682. }
  683. /**
  684. * Destroy completion queue
  685. *
  686. * @v ibdev Infiniband device
  687. * @v cq Completion queue
  688. */
  689. static void hermon_destroy_cq ( struct ib_device *ibdev,
  690. struct ib_completion_queue *cq ) {
  691. struct hermon *hermon = ib_get_drvdata ( ibdev );
  692. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  693. struct hermonprm_completion_queue_context cqctx;
  694. int cqn_offset;
  695. int rc;
  696. /* Take ownership back from hardware */
  697. if ( ( rc = hermon_cmd_hw2sw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  698. DBGC ( hermon, "Hermon %p FATAL HW2SW_CQ failed on CQN %#lx: "
  699. "%s\n", hermon, cq->cqn, strerror ( rc ) );
  700. /* Leak memory and return; at least we avoid corruption */
  701. return;
  702. }
  703. /* Free MTT entries */
  704. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  705. /* Free memory */
  706. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  707. free ( hermon_cq );
  708. /* Mark queue number as free */
  709. cqn_offset = ( cq->cqn - hermon->cap.reserved_cqs );
  710. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  711. ib_cq_set_drvdata ( cq, NULL );
  712. }
  713. /***************************************************************************
  714. *
  715. * Queue pair operations
  716. *
  717. ***************************************************************************
  718. */
  719. /**
  720. * Assign queue pair number
  721. *
  722. * @v ibdev Infiniband device
  723. * @v qp Queue pair
  724. * @ret rc Return status code
  725. */
  726. static int hermon_alloc_qpn ( struct ib_device *ibdev,
  727. struct ib_queue_pair *qp ) {
  728. struct hermon *hermon = ib_get_drvdata ( ibdev );
  729. unsigned int port_offset;
  730. int qpn_offset;
  731. /* Calculate queue pair number */
  732. port_offset = ( ibdev->port - HERMON_PORT_BASE );
  733. switch ( qp->type ) {
  734. case IB_QPT_SMA:
  735. qp->qpn = ( hermon->special_qpn_base + port_offset );
  736. return 0;
  737. case IB_QPT_GMA:
  738. qp->qpn = ( hermon->special_qpn_base + 2 + port_offset );
  739. return 0;
  740. case IB_QPT_UD:
  741. /* Find a free queue pair number */
  742. qpn_offset = hermon_bitmask_alloc ( hermon->qp_inuse,
  743. HERMON_MAX_QPS, 1 );
  744. if ( qpn_offset < 0 ) {
  745. DBGC ( hermon, "Hermon %p out of queue pairs\n",
  746. hermon );
  747. return qpn_offset;
  748. }
  749. qp->qpn = ( hermon->qpn_base + qpn_offset );
  750. return 0;
  751. default:
  752. DBGC ( hermon, "Hermon %p unsupported QP type %d\n",
  753. hermon, qp->type );
  754. return -ENOTSUP;
  755. }
  756. }
  757. /**
  758. * Free queue pair number
  759. *
  760. * @v ibdev Infiniband device
  761. * @v qp Queue pair
  762. */
  763. static void hermon_free_qpn ( struct ib_device *ibdev,
  764. struct ib_queue_pair *qp ) {
  765. struct hermon *hermon = ib_get_drvdata ( ibdev );
  766. int qpn_offset;
  767. qpn_offset = ( qp->qpn - hermon->qpn_base );
  768. if ( qpn_offset >= 0 )
  769. hermon_bitmask_free ( hermon->qp_inuse, qpn_offset, 1 );
  770. }
  771. /**
  772. * Create queue pair
  773. *
  774. * @v ibdev Infiniband device
  775. * @v qp Queue pair
  776. * @ret rc Return status code
  777. */
  778. static int hermon_create_qp ( struct ib_device *ibdev,
  779. struct ib_queue_pair *qp ) {
  780. struct hermon *hermon = ib_get_drvdata ( ibdev );
  781. struct hermon_queue_pair *hermon_qp;
  782. struct hermonprm_qp_ee_state_transitions qpctx;
  783. int rc;
  784. /* Calculate queue pair number */
  785. if ( ( rc = hermon_alloc_qpn ( ibdev, qp ) ) != 0 )
  786. goto err_alloc_qpn;
  787. /* Allocate control structures */
  788. hermon_qp = zalloc ( sizeof ( *hermon_qp ) );
  789. if ( ! hermon_qp ) {
  790. rc = -ENOMEM;
  791. goto err_hermon_qp;
  792. }
  793. /* Calculate doorbell address */
  794. hermon_qp->send.doorbell =
  795. ( hermon->uar + HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE +
  796. HERMON_DB_POST_SND_OFFSET );
  797. /* Allocate work queue buffer */
  798. hermon_qp->send.num_wqes = ( qp->send.num_wqes /* headroom */ + 1 +
  799. ( 2048 / sizeof ( hermon_qp->send.wqe[0] ) ) );
  800. hermon_qp->send.num_wqes =
  801. ( 1 << fls ( hermon_qp->send.num_wqes - 1 ) ); /* round up */
  802. hermon_qp->send.wqe_size = ( hermon_qp->send.num_wqes *
  803. sizeof ( hermon_qp->send.wqe[0] ) );
  804. hermon_qp->recv.wqe_size = ( qp->recv.num_wqes *
  805. sizeof ( hermon_qp->recv.wqe[0] ) );
  806. hermon_qp->wqe_size = ( hermon_qp->send.wqe_size +
  807. hermon_qp->recv.wqe_size );
  808. hermon_qp->wqe = malloc_dma ( hermon_qp->wqe_size,
  809. sizeof ( hermon_qp->send.wqe[0] ) );
  810. if ( ! hermon_qp->wqe ) {
  811. rc = -ENOMEM;
  812. goto err_alloc_wqe;
  813. }
  814. hermon_qp->send.wqe = hermon_qp->wqe;
  815. memset ( hermon_qp->send.wqe, 0xff, hermon_qp->send.wqe_size );
  816. hermon_qp->recv.wqe = ( hermon_qp->wqe + hermon_qp->send.wqe_size );
  817. memset ( hermon_qp->recv.wqe, 0, hermon_qp->recv.wqe_size );
  818. /* Allocate MTT entries */
  819. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_qp->wqe,
  820. hermon_qp->wqe_size,
  821. &hermon_qp->mtt ) ) != 0 ) {
  822. goto err_alloc_mtt;
  823. }
  824. /* Transition queue to INIT state */
  825. memset ( &qpctx, 0, sizeof ( qpctx ) );
  826. MLX_FILL_2 ( &qpctx, 2,
  827. qpc_eec_data.pm_state, 0x03 /* Always 0x03 for UD */,
  828. qpc_eec_data.st,
  829. ( ( qp->type == IB_QPT_UD ) ?
  830. HERMON_ST_UD : HERMON_ST_MLX ) );
  831. MLX_FILL_1 ( &qpctx, 3, qpc_eec_data.pd, HERMON_GLOBAL_PD );
  832. MLX_FILL_4 ( &qpctx, 4,
  833. qpc_eec_data.log_rq_size, fls ( qp->recv.num_wqes - 1 ),
  834. qpc_eec_data.log_rq_stride,
  835. ( fls ( sizeof ( hermon_qp->recv.wqe[0] ) - 1 ) - 4 ),
  836. qpc_eec_data.log_sq_size,
  837. fls ( hermon_qp->send.num_wqes - 1 ),
  838. qpc_eec_data.log_sq_stride,
  839. ( fls ( sizeof ( hermon_qp->send.wqe[0] ) - 1 ) - 4 ) );
  840. MLX_FILL_1 ( &qpctx, 5,
  841. qpc_eec_data.usr_page, HERMON_UAR_NON_EQ_PAGE );
  842. MLX_FILL_1 ( &qpctx, 33, qpc_eec_data.cqn_snd, qp->send.cq->cqn );
  843. MLX_FILL_1 ( &qpctx, 38, qpc_eec_data.page_offset,
  844. ( hermon_qp->mtt.page_offset >> 6 ) );
  845. MLX_FILL_1 ( &qpctx, 41, qpc_eec_data.cqn_rcv, qp->recv.cq->cqn );
  846. MLX_FILL_1 ( &qpctx, 43, qpc_eec_data.db_record_addr_l,
  847. ( virt_to_phys ( &hermon_qp->recv.doorbell ) >> 2 ) );
  848. MLX_FILL_1 ( &qpctx, 53, qpc_eec_data.mtt_base_addr_l,
  849. ( hermon_qp->mtt.mtt_base_addr >> 3 ) );
  850. if ( ( rc = hermon_cmd_rst2init_qp ( hermon, qp->qpn,
  851. &qpctx ) ) != 0 ) {
  852. DBGC ( hermon, "Hermon %p RST2INIT_QP failed: %s\n",
  853. hermon, strerror ( rc ) );
  854. goto err_rst2init_qp;
  855. }
  856. /* Transition queue to RTR state */
  857. memset ( &qpctx, 0, sizeof ( qpctx ) );
  858. MLX_FILL_2 ( &qpctx, 4,
  859. qpc_eec_data.mtu, HERMON_MTU_2048,
  860. qpc_eec_data.msg_max, 11 /* 2^11 = 2048 */ );
  861. MLX_FILL_1 ( &qpctx, 16,
  862. qpc_eec_data.primary_address_path.sched_queue,
  863. ( ( ( qp->type == IB_QPT_SMA ) ?
  864. HERMON_SCHED_QP0 : HERMON_SCHED_DEFAULT ) |
  865. ( ( ibdev->port - 1 ) << 6 ) ) );
  866. if ( ( rc = hermon_cmd_init2rtr_qp ( hermon, qp->qpn,
  867. &qpctx ) ) != 0 ) {
  868. DBGC ( hermon, "Hermon %p INIT2RTR_QP failed: %s\n",
  869. hermon, strerror ( rc ) );
  870. goto err_init2rtr_qp;
  871. }
  872. memset ( &qpctx, 0, sizeof ( qpctx ) );
  873. if ( ( rc = hermon_cmd_rtr2rts_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ){
  874. DBGC ( hermon, "Hermon %p RTR2RTS_QP failed: %s\n",
  875. hermon, strerror ( rc ) );
  876. goto err_rtr2rts_qp;
  877. }
  878. DBGC ( hermon, "Hermon %p QPN %#lx send ring at [%p,%p)\n",
  879. hermon, qp->qpn, hermon_qp->send.wqe,
  880. ( ((void *)hermon_qp->send.wqe ) + hermon_qp->send.wqe_size ) );
  881. DBGC ( hermon, "Hermon %p QPN %#lx receive ring at [%p,%p)\n",
  882. hermon, qp->qpn, hermon_qp->recv.wqe,
  883. ( ((void *)hermon_qp->recv.wqe ) + hermon_qp->recv.wqe_size ) );
  884. ib_qp_set_drvdata ( qp, hermon_qp );
  885. return 0;
  886. err_rtr2rts_qp:
  887. err_init2rtr_qp:
  888. hermon_cmd_2rst_qp ( hermon, qp->qpn );
  889. err_rst2init_qp:
  890. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  891. err_alloc_mtt:
  892. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  893. err_alloc_wqe:
  894. free ( hermon_qp );
  895. err_hermon_qp:
  896. hermon_free_qpn ( ibdev, qp );
  897. err_alloc_qpn:
  898. return rc;
  899. }
  900. /**
  901. * Modify queue pair
  902. *
  903. * @v ibdev Infiniband device
  904. * @v qp Queue pair
  905. * @ret rc Return status code
  906. */
  907. static int hermon_modify_qp ( struct ib_device *ibdev,
  908. struct ib_queue_pair *qp ) {
  909. struct hermon *hermon = ib_get_drvdata ( ibdev );
  910. struct hermonprm_qp_ee_state_transitions qpctx;
  911. int rc;
  912. /* Issue RTS2RTS_QP */
  913. memset ( &qpctx, 0, sizeof ( qpctx ) );
  914. MLX_FILL_1 ( &qpctx, 0, opt_param_mask, HERMON_QP_OPT_PARAM_QKEY );
  915. MLX_FILL_1 ( &qpctx, 44, qpc_eec_data.q_key, qp->qkey );
  916. if ( ( rc = hermon_cmd_rts2rts_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ){
  917. DBGC ( hermon, "Hermon %p RTS2RTS_QP failed: %s\n",
  918. hermon, strerror ( rc ) );
  919. return rc;
  920. }
  921. return 0;
  922. }
  923. /**
  924. * Destroy queue pair
  925. *
  926. * @v ibdev Infiniband device
  927. * @v qp Queue pair
  928. */
  929. static void hermon_destroy_qp ( struct ib_device *ibdev,
  930. struct ib_queue_pair *qp ) {
  931. struct hermon *hermon = ib_get_drvdata ( ibdev );
  932. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  933. int rc;
  934. /* Take ownership back from hardware */
  935. if ( ( rc = hermon_cmd_2rst_qp ( hermon, qp->qpn ) ) != 0 ) {
  936. DBGC ( hermon, "Hermon %p FATAL 2RST_QP failed on QPN %#lx: "
  937. "%s\n", hermon, qp->qpn, strerror ( rc ) );
  938. /* Leak memory and return; at least we avoid corruption */
  939. return;
  940. }
  941. /* Free MTT entries */
  942. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  943. /* Free memory */
  944. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  945. free ( hermon_qp );
  946. /* Mark queue number as free */
  947. hermon_free_qpn ( ibdev, qp );
  948. ib_qp_set_drvdata ( qp, NULL );
  949. }
  950. /***************************************************************************
  951. *
  952. * Work request operations
  953. *
  954. ***************************************************************************
  955. */
  956. /**
  957. * Construct UD send work queue entry
  958. *
  959. * @v ibdev Infiniband device
  960. * @v qp Queue pair
  961. * @v av Address vector
  962. * @v iobuf I/O buffer
  963. * @v wqe Send work queue entry
  964. * @ret opcode Control opcode
  965. */
  966. static unsigned int
  967. hermon_fill_ud_send_wqe ( struct ib_device *ibdev,
  968. struct ib_queue_pair *qp __unused,
  969. struct ib_address_vector *av,
  970. struct io_buffer *iobuf,
  971. union hermon_send_wqe *wqe ) {
  972. struct hermon *hermon = ib_get_drvdata ( ibdev );
  973. MLX_FILL_1 ( &wqe->ud.ctrl, 1, ds,
  974. ( ( offsetof ( typeof ( wqe->ud ), data[1] ) / 16 ) ) );
  975. MLX_FILL_1 ( &wqe->ud.ctrl, 2, c, 0x03 /* generate completion */ );
  976. MLX_FILL_2 ( &wqe->ud.ud, 0,
  977. ud_address_vector.pd, HERMON_GLOBAL_PD,
  978. ud_address_vector.port_number, ibdev->port );
  979. MLX_FILL_2 ( &wqe->ud.ud, 1,
  980. ud_address_vector.rlid, av->lid,
  981. ud_address_vector.g, av->gid_present );
  982. MLX_FILL_1 ( &wqe->ud.ud, 2,
  983. ud_address_vector.max_stat_rate,
  984. ( ( ( av->rate < 2 ) || ( av->rate > 10 ) ) ?
  985. 8 : ( av->rate + 5 ) ) );
  986. MLX_FILL_1 ( &wqe->ud.ud, 3, ud_address_vector.sl, av->sl );
  987. memcpy ( &wqe->ud.ud.u.dwords[4], &av->gid, sizeof ( av->gid ) );
  988. MLX_FILL_1 ( &wqe->ud.ud, 8, destination_qp, av->qpn );
  989. MLX_FILL_1 ( &wqe->ud.ud, 9, q_key, av->qkey );
  990. MLX_FILL_1 ( &wqe->ud.data[0], 0, byte_count, iob_len ( iobuf ) );
  991. MLX_FILL_1 ( &wqe->ud.data[0], 1, l_key, hermon->reserved_lkey );
  992. MLX_FILL_1 ( &wqe->ud.data[0], 3,
  993. local_address_l, virt_to_bus ( iobuf->data ) );
  994. return HERMON_OPCODE_SEND;
  995. }
  996. /**
  997. * Construct MLX send work queue entry
  998. *
  999. * @v ibdev Infiniband device
  1000. * @v qp Queue pair
  1001. * @v av Address vector
  1002. * @v iobuf I/O buffer
  1003. * @v wqe Send work queue entry
  1004. * @ret opcode Control opcode
  1005. */
  1006. static unsigned int
  1007. hermon_fill_mlx_send_wqe ( struct ib_device *ibdev,
  1008. struct ib_queue_pair *qp,
  1009. struct ib_address_vector *av,
  1010. struct io_buffer *iobuf,
  1011. union hermon_send_wqe *wqe ) {
  1012. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1013. struct io_buffer headers;
  1014. /* Construct IB headers */
  1015. iob_populate ( &headers, &wqe->mlx.headers, 0,
  1016. sizeof ( wqe->mlx.headers ) );
  1017. iob_reserve ( &headers, sizeof ( wqe->mlx.headers ) );
  1018. ib_push ( ibdev, &headers, qp, iob_len ( iobuf ), av );
  1019. /* Fill work queue entry */
  1020. MLX_FILL_1 ( &wqe->mlx.ctrl, 1, ds,
  1021. ( ( offsetof ( typeof ( wqe->mlx ), data[2] ) / 16 ) ) );
  1022. MLX_FILL_5 ( &wqe->mlx.ctrl, 2,
  1023. c, 0x03 /* generate completion */,
  1024. icrc, 0 /* generate ICRC */,
  1025. max_statrate, ( ( ( av->rate < 2 ) || ( av->rate > 10 ) )
  1026. ? 8 : ( av->rate + 5 ) ),
  1027. slr, 0,
  1028. v15, ( ( qp->ext_qpn == IB_QPN_SMA ) ? 1 : 0 ) );
  1029. MLX_FILL_1 ( &wqe->mlx.ctrl, 3, rlid, av->lid );
  1030. MLX_FILL_1 ( &wqe->mlx.data[0], 0,
  1031. byte_count, iob_len ( &headers ) );
  1032. MLX_FILL_1 ( &wqe->mlx.data[0], 1, l_key, hermon->reserved_lkey );
  1033. MLX_FILL_1 ( &wqe->mlx.data[0], 3,
  1034. local_address_l, virt_to_bus ( headers.data ) );
  1035. MLX_FILL_1 ( &wqe->mlx.data[1], 0,
  1036. byte_count, ( iob_len ( iobuf ) + 4 /* ICRC */ ) );
  1037. MLX_FILL_1 ( &wqe->mlx.data[1], 1, l_key, hermon->reserved_lkey );
  1038. MLX_FILL_1 ( &wqe->mlx.data[1], 3,
  1039. local_address_l, virt_to_bus ( iobuf->data ) );
  1040. return HERMON_OPCODE_SEND;
  1041. }
  1042. /** Work queue entry constructors */
  1043. static unsigned int
  1044. ( * hermon_fill_send_wqe[] ) ( struct ib_device *ibdev,
  1045. struct ib_queue_pair *qp,
  1046. struct ib_address_vector *av,
  1047. struct io_buffer *iobuf,
  1048. union hermon_send_wqe *wqe ) = {
  1049. [IB_QPT_SMA] = hermon_fill_mlx_send_wqe,
  1050. [IB_QPT_GMA] = hermon_fill_mlx_send_wqe,
  1051. [IB_QPT_UD] = hermon_fill_ud_send_wqe,
  1052. };
  1053. /**
  1054. * Post send work queue entry
  1055. *
  1056. * @v ibdev Infiniband device
  1057. * @v qp Queue pair
  1058. * @v av Address vector
  1059. * @v iobuf I/O buffer
  1060. * @ret rc Return status code
  1061. */
  1062. static int hermon_post_send ( struct ib_device *ibdev,
  1063. struct ib_queue_pair *qp,
  1064. struct ib_address_vector *av,
  1065. struct io_buffer *iobuf ) {
  1066. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1067. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  1068. struct ib_work_queue *wq = &qp->send;
  1069. struct hermon_send_work_queue *hermon_send_wq = &hermon_qp->send;
  1070. union hermon_send_wqe *wqe;
  1071. union hermonprm_doorbell_register db_reg;
  1072. unsigned int wqe_idx_mask;
  1073. unsigned int opcode;
  1074. /* Allocate work queue entry */
  1075. wqe_idx_mask = ( wq->num_wqes - 1 );
  1076. if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) {
  1077. DBGC ( hermon, "Hermon %p send queue full", hermon );
  1078. return -ENOBUFS;
  1079. }
  1080. wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf;
  1081. wqe = &hermon_send_wq->wqe[ wq->next_idx &
  1082. ( hermon_send_wq->num_wqes - 1 ) ];
  1083. /* Construct work queue entry */
  1084. memset ( ( ( ( void * ) wqe ) + 4 /* avoid ctrl.owner */ ), 0,
  1085. ( sizeof ( *wqe ) - 4 ) );
  1086. assert ( qp->type < ( sizeof ( hermon_fill_send_wqe ) /
  1087. sizeof ( hermon_fill_send_wqe[0] ) ) );
  1088. assert ( hermon_fill_send_wqe[qp->type] != NULL );
  1089. opcode = hermon_fill_send_wqe[qp->type] ( ibdev, qp, av, iobuf, wqe );
  1090. barrier();
  1091. MLX_FILL_2 ( &wqe->ctrl, 0,
  1092. opcode, opcode,
  1093. owner,
  1094. ( ( wq->next_idx & hermon_send_wq->num_wqes ) ? 1 : 0 ) );
  1095. DBGCP ( hermon, "Hermon %p posting send WQE:\n", hermon );
  1096. DBGCP_HD ( hermon, wqe, sizeof ( *wqe ) );
  1097. barrier();
  1098. /* Ring doorbell register */
  1099. MLX_FILL_1 ( &db_reg.send, 0, qn, qp->qpn );
  1100. DBGCP ( hermon, "Ringing doorbell %08lx with %08x\n",
  1101. virt_to_phys ( hermon_send_wq->doorbell ), db_reg.dword[0] );
  1102. writel ( db_reg.dword[0], ( hermon_send_wq->doorbell ) );
  1103. /* Update work queue's index */
  1104. wq->next_idx++;
  1105. return 0;
  1106. }
  1107. /**
  1108. * Post receive work queue entry
  1109. *
  1110. * @v ibdev Infiniband device
  1111. * @v qp Queue pair
  1112. * @v iobuf I/O buffer
  1113. * @ret rc Return status code
  1114. */
  1115. static int hermon_post_recv ( struct ib_device *ibdev,
  1116. struct ib_queue_pair *qp,
  1117. struct io_buffer *iobuf ) {
  1118. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1119. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  1120. struct ib_work_queue *wq = &qp->recv;
  1121. struct hermon_recv_work_queue *hermon_recv_wq = &hermon_qp->recv;
  1122. struct hermonprm_recv_wqe *wqe;
  1123. unsigned int wqe_idx_mask;
  1124. /* Allocate work queue entry */
  1125. wqe_idx_mask = ( wq->num_wqes - 1 );
  1126. if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) {
  1127. DBGC ( hermon, "Hermon %p receive queue full", hermon );
  1128. return -ENOBUFS;
  1129. }
  1130. wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf;
  1131. wqe = &hermon_recv_wq->wqe[wq->next_idx & wqe_idx_mask].recv;
  1132. /* Construct work queue entry */
  1133. MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_tailroom ( iobuf ) );
  1134. MLX_FILL_1 ( &wqe->data[0], 1, l_key, hermon->reserved_lkey );
  1135. MLX_FILL_1 ( &wqe->data[0], 3,
  1136. local_address_l, virt_to_bus ( iobuf->data ) );
  1137. /* Update work queue's index */
  1138. wq->next_idx++;
  1139. /* Update doorbell record */
  1140. barrier();
  1141. MLX_FILL_1 ( &hermon_recv_wq->doorbell, 0, receive_wqe_counter,
  1142. ( wq->next_idx & 0xffff ) );
  1143. return 0;
  1144. }
  1145. /**
  1146. * Handle completion
  1147. *
  1148. * @v ibdev Infiniband device
  1149. * @v cq Completion queue
  1150. * @v cqe Hardware completion queue entry
  1151. * @ret rc Return status code
  1152. */
  1153. static int hermon_complete ( struct ib_device *ibdev,
  1154. struct ib_completion_queue *cq,
  1155. union hermonprm_completion_entry *cqe ) {
  1156. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1157. struct ib_work_queue *wq;
  1158. struct ib_queue_pair *qp;
  1159. struct hermon_queue_pair *hermon_qp;
  1160. struct io_buffer *iobuf;
  1161. struct ib_address_vector av;
  1162. struct ib_global_route_header *grh;
  1163. unsigned int opcode;
  1164. unsigned long qpn;
  1165. int is_send;
  1166. unsigned int wqe_idx;
  1167. size_t len;
  1168. int rc = 0;
  1169. /* Parse completion */
  1170. qpn = MLX_GET ( &cqe->normal, qpn );
  1171. is_send = MLX_GET ( &cqe->normal, s_r );
  1172. opcode = MLX_GET ( &cqe->normal, opcode );
  1173. if ( opcode >= HERMON_OPCODE_RECV_ERROR ) {
  1174. /* "s" field is not valid for error opcodes */
  1175. is_send = ( opcode == HERMON_OPCODE_SEND_ERROR );
  1176. DBGC ( hermon, "Hermon %p CQN %lx syndrome %x vendor %x\n",
  1177. hermon, cq->cqn, MLX_GET ( &cqe->error, syndrome ),
  1178. MLX_GET ( &cqe->error, vendor_error_syndrome ) );
  1179. rc = -EIO;
  1180. /* Don't return immediately; propagate error to completer */
  1181. }
  1182. /* Identify work queue */
  1183. wq = ib_find_wq ( cq, qpn, is_send );
  1184. if ( ! wq ) {
  1185. DBGC ( hermon, "Hermon %p CQN %lx unknown %s QPN %lx\n",
  1186. hermon, cq->cqn, ( is_send ? "send" : "recv" ), qpn );
  1187. return -EIO;
  1188. }
  1189. qp = wq->qp;
  1190. hermon_qp = ib_qp_get_drvdata ( qp );
  1191. /* Identify I/O buffer */
  1192. wqe_idx = ( MLX_GET ( &cqe->normal, wqe_counter ) &
  1193. ( wq->num_wqes - 1 ) );
  1194. iobuf = wq->iobufs[wqe_idx];
  1195. if ( ! iobuf ) {
  1196. DBGC ( hermon, "Hermon %p CQN %lx QPN %lx empty WQE %x\n",
  1197. hermon, cq->cqn, qp->qpn, wqe_idx );
  1198. return -EIO;
  1199. }
  1200. wq->iobufs[wqe_idx] = NULL;
  1201. if ( is_send ) {
  1202. /* Hand off to completion handler */
  1203. ib_complete_send ( ibdev, qp, iobuf, rc );
  1204. } else {
  1205. /* Set received length */
  1206. len = MLX_GET ( &cqe->normal, byte_cnt );
  1207. assert ( len <= iob_tailroom ( iobuf ) );
  1208. iob_put ( iobuf, len );
  1209. assert ( iob_len ( iobuf ) >= sizeof ( *grh ) );
  1210. grh = iobuf->data;
  1211. iob_pull ( iobuf, sizeof ( *grh ) );
  1212. /* Construct address vector */
  1213. memset ( &av, 0, sizeof ( av ) );
  1214. av.qpn = MLX_GET ( &cqe->normal, srq_rqpn );
  1215. av.lid = MLX_GET ( &cqe->normal, slid_smac47_32 );
  1216. av.sl = MLX_GET ( &cqe->normal, sl );
  1217. av.gid_present = MLX_GET ( &cqe->normal, g );
  1218. memcpy ( &av.gid, &grh->sgid, sizeof ( av.gid ) );
  1219. /* Hand off to completion handler */
  1220. ib_complete_recv ( ibdev, qp, &av, iobuf, rc );
  1221. }
  1222. return rc;
  1223. }
  1224. /**
  1225. * Poll completion queue
  1226. *
  1227. * @v ibdev Infiniband device
  1228. * @v cq Completion queue
  1229. */
  1230. static void hermon_poll_cq ( struct ib_device *ibdev,
  1231. struct ib_completion_queue *cq ) {
  1232. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1233. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  1234. union hermonprm_completion_entry *cqe;
  1235. unsigned int cqe_idx_mask;
  1236. int rc;
  1237. while ( 1 ) {
  1238. /* Look for completion entry */
  1239. cqe_idx_mask = ( cq->num_cqes - 1 );
  1240. cqe = &hermon_cq->cqe[cq->next_idx & cqe_idx_mask];
  1241. if ( MLX_GET ( &cqe->normal, owner ) ^
  1242. ( ( cq->next_idx & cq->num_cqes ) ? 1 : 0 ) ) {
  1243. /* Entry still owned by hardware; end of poll */
  1244. break;
  1245. }
  1246. DBGCP ( hermon, "Hermon %p completion:\n", hermon );
  1247. DBGCP_HD ( hermon, cqe, sizeof ( *cqe ) );
  1248. /* Handle completion */
  1249. if ( ( rc = hermon_complete ( ibdev, cq, cqe ) ) != 0 ) {
  1250. DBGC ( hermon, "Hermon %p failed to complete: %s\n",
  1251. hermon, strerror ( rc ) );
  1252. DBGC_HD ( hermon, cqe, sizeof ( *cqe ) );
  1253. }
  1254. /* Update completion queue's index */
  1255. cq->next_idx++;
  1256. /* Update doorbell record */
  1257. MLX_FILL_1 ( &hermon_cq->doorbell, 0, update_ci,
  1258. ( cq->next_idx & 0x00ffffffUL ) );
  1259. }
  1260. }
  1261. /***************************************************************************
  1262. *
  1263. * Event queues
  1264. *
  1265. ***************************************************************************
  1266. */
  1267. /**
  1268. * Create event queue
  1269. *
  1270. * @v hermon Hermon device
  1271. * @ret rc Return status code
  1272. */
  1273. static int hermon_create_eq ( struct hermon *hermon ) {
  1274. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1275. struct hermonprm_eqc eqctx;
  1276. struct hermonprm_event_mask mask;
  1277. unsigned int i;
  1278. int rc;
  1279. /* Select event queue number */
  1280. hermon_eq->eqn = ( 4 * hermon->cap.reserved_uars );
  1281. if ( hermon_eq->eqn < hermon->cap.reserved_eqs )
  1282. hermon_eq->eqn = hermon->cap.reserved_eqs;
  1283. /* Calculate doorbell address */
  1284. hermon_eq->doorbell =
  1285. ( hermon->uar + HERMON_DB_EQ_OFFSET ( hermon_eq->eqn ) );
  1286. /* Allocate event queue itself */
  1287. hermon_eq->eqe_size =
  1288. ( HERMON_NUM_EQES * sizeof ( hermon_eq->eqe[0] ) );
  1289. hermon_eq->eqe = malloc_dma ( hermon_eq->eqe_size,
  1290. sizeof ( hermon_eq->eqe[0] ) );
  1291. if ( ! hermon_eq->eqe ) {
  1292. rc = -ENOMEM;
  1293. goto err_eqe;
  1294. }
  1295. memset ( hermon_eq->eqe, 0, hermon_eq->eqe_size );
  1296. for ( i = 0 ; i < HERMON_NUM_EQES ; i++ ) {
  1297. MLX_FILL_1 ( &hermon_eq->eqe[i].generic, 7, owner, 1 );
  1298. }
  1299. barrier();
  1300. /* Allocate MTT entries */
  1301. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_eq->eqe,
  1302. hermon_eq->eqe_size,
  1303. &hermon_eq->mtt ) ) != 0 )
  1304. goto err_alloc_mtt;
  1305. /* Hand queue over to hardware */
  1306. memset ( &eqctx, 0, sizeof ( eqctx ) );
  1307. MLX_FILL_1 ( &eqctx, 0, st, 0xa /* "Fired" */ );
  1308. MLX_FILL_1 ( &eqctx, 2,
  1309. page_offset, ( hermon_eq->mtt.page_offset >> 5 ) );
  1310. MLX_FILL_1 ( &eqctx, 3, log_eq_size, fls ( HERMON_NUM_EQES - 1 ) );
  1311. MLX_FILL_1 ( &eqctx, 7, mtt_base_addr_l,
  1312. ( hermon_eq->mtt.mtt_base_addr >> 3 ) );
  1313. if ( ( rc = hermon_cmd_sw2hw_eq ( hermon, hermon_eq->eqn,
  1314. &eqctx ) ) != 0 ) {
  1315. DBGC ( hermon, "Hermon %p SW2HW_EQ failed: %s\n",
  1316. hermon, strerror ( rc ) );
  1317. goto err_sw2hw_eq;
  1318. }
  1319. /* Map events to this event queue */
  1320. memset ( &mask, 0, sizeof ( mask ) );
  1321. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1322. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1323. ( HERMON_MAP_EQ | hermon_eq->eqn ),
  1324. &mask ) ) != 0 ) {
  1325. DBGC ( hermon, "Hermon %p MAP_EQ failed: %s\n",
  1326. hermon, strerror ( rc ) );
  1327. goto err_map_eq;
  1328. }
  1329. DBGC ( hermon, "Hermon %p EQN %#lx ring at [%p,%p])\n",
  1330. hermon, hermon_eq->eqn, hermon_eq->eqe,
  1331. ( ( ( void * ) hermon_eq->eqe ) + hermon_eq->eqe_size ) );
  1332. return 0;
  1333. err_map_eq:
  1334. hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn, &eqctx );
  1335. err_sw2hw_eq:
  1336. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1337. err_alloc_mtt:
  1338. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1339. err_eqe:
  1340. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1341. return rc;
  1342. }
  1343. /**
  1344. * Destroy event queue
  1345. *
  1346. * @v hermon Hermon device
  1347. */
  1348. static void hermon_destroy_eq ( struct hermon *hermon ) {
  1349. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1350. struct hermonprm_eqc eqctx;
  1351. struct hermonprm_event_mask mask;
  1352. int rc;
  1353. /* Unmap events from event queue */
  1354. memset ( &mask, 0, sizeof ( mask ) );
  1355. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1356. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1357. ( HERMON_UNMAP_EQ | hermon_eq->eqn ),
  1358. &mask ) ) != 0 ) {
  1359. DBGC ( hermon, "Hermon %p FATAL MAP_EQ failed to unmap: %s\n",
  1360. hermon, strerror ( rc ) );
  1361. /* Continue; HCA may die but system should survive */
  1362. }
  1363. /* Take ownership back from hardware */
  1364. if ( ( rc = hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn,
  1365. &eqctx ) ) != 0 ) {
  1366. DBGC ( hermon, "Hermon %p FATAL HW2SW_EQ failed: %s\n",
  1367. hermon, strerror ( rc ) );
  1368. /* Leak memory and return; at least we avoid corruption */
  1369. return;
  1370. }
  1371. /* Free MTT entries */
  1372. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1373. /* Free memory */
  1374. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1375. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1376. }
  1377. /**
  1378. * Handle port state event
  1379. *
  1380. * @v hermon Hermon device
  1381. * @v eqe Port state change event queue entry
  1382. */
  1383. static void hermon_event_port_state_change ( struct hermon *hermon,
  1384. union hermonprm_event_entry *eqe){
  1385. unsigned int port;
  1386. int link_up;
  1387. /* Get port and link status */
  1388. port = ( MLX_GET ( &eqe->port_state_change, data.p ) - 1 );
  1389. link_up = ( MLX_GET ( &eqe->generic, event_sub_type ) & 0x04 );
  1390. DBGC ( hermon, "Hermon %p port %d link %s\n", hermon, ( port + 1 ),
  1391. ( link_up ? "up" : "down" ) );
  1392. /* Sanity check */
  1393. if ( port >= HERMON_NUM_PORTS ) {
  1394. DBGC ( hermon, "Hermon %p port %d does not exist!\n",
  1395. hermon, ( port + 1 ) );
  1396. return;
  1397. }
  1398. /* Update MAD parameters */
  1399. ib_smc_update ( hermon->ibdev[port], hermon_mad );
  1400. /* Notify Infiniband core of link state change */
  1401. ib_link_state_changed ( hermon->ibdev[port] );
  1402. }
  1403. /**
  1404. * Poll event queue
  1405. *
  1406. * @v ibdev Infiniband device
  1407. */
  1408. static void hermon_poll_eq ( struct ib_device *ibdev ) {
  1409. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1410. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1411. union hermonprm_event_entry *eqe;
  1412. union hermonprm_doorbell_register db_reg;
  1413. unsigned int eqe_idx_mask;
  1414. unsigned int event_type;
  1415. while ( 1 ) {
  1416. /* Look for event entry */
  1417. eqe_idx_mask = ( HERMON_NUM_EQES - 1 );
  1418. eqe = &hermon_eq->eqe[hermon_eq->next_idx & eqe_idx_mask];
  1419. if ( MLX_GET ( &eqe->generic, owner ) ^
  1420. ( ( hermon_eq->next_idx & HERMON_NUM_EQES ) ? 1 : 0 ) ) {
  1421. /* Entry still owned by hardware; end of poll */
  1422. break;
  1423. }
  1424. DBGCP ( hermon, "Hermon %p event:\n", hermon );
  1425. DBGCP_HD ( hermon, eqe, sizeof ( *eqe ) );
  1426. /* Handle event */
  1427. event_type = MLX_GET ( &eqe->generic, event_type );
  1428. switch ( event_type ) {
  1429. case HERMON_EV_PORT_STATE_CHANGE:
  1430. hermon_event_port_state_change ( hermon, eqe );
  1431. break;
  1432. default:
  1433. DBGC ( hermon, "Hermon %p unrecognised event type "
  1434. "%#x:\n", hermon, event_type );
  1435. DBGC_HD ( hermon, eqe, sizeof ( *eqe ) );
  1436. break;
  1437. }
  1438. /* Update event queue's index */
  1439. hermon_eq->next_idx++;
  1440. /* Ring doorbell */
  1441. MLX_FILL_1 ( &db_reg.event, 0,
  1442. ci, ( hermon_eq->next_idx & 0x00ffffffUL ) );
  1443. DBGCP ( hermon, "Ringing doorbell %08lx with %08x\n",
  1444. virt_to_phys ( hermon_eq->doorbell ),
  1445. db_reg.dword[0] );
  1446. writel ( db_reg.dword[0], hermon_eq->doorbell );
  1447. }
  1448. }
  1449. /***************************************************************************
  1450. *
  1451. * Infiniband link-layer operations
  1452. *
  1453. ***************************************************************************
  1454. */
  1455. /**
  1456. * Initialise Infiniband link
  1457. *
  1458. * @v ibdev Infiniband device
  1459. * @ret rc Return status code
  1460. */
  1461. static int hermon_open ( struct ib_device *ibdev ) {
  1462. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1463. struct hermonprm_init_port init_port;
  1464. int rc;
  1465. memset ( &init_port, 0, sizeof ( init_port ) );
  1466. MLX_FILL_2 ( &init_port, 0,
  1467. port_width_cap, 3,
  1468. vl_cap, 1 );
  1469. MLX_FILL_2 ( &init_port, 1,
  1470. mtu, HERMON_MTU_2048,
  1471. max_gid, 1 );
  1472. MLX_FILL_1 ( &init_port, 2, max_pkey, 64 );
  1473. if ( ( rc = hermon_cmd_init_port ( hermon, ibdev->port,
  1474. &init_port ) ) != 0 ) {
  1475. DBGC ( hermon, "Hermon %p could not intialise port: %s\n",
  1476. hermon, strerror ( rc ) );
  1477. return rc;
  1478. }
  1479. /* Update MAD parameters */
  1480. ib_smc_update ( ibdev, hermon_mad );
  1481. return 0;
  1482. }
  1483. /**
  1484. * Close Infiniband link
  1485. *
  1486. * @v ibdev Infiniband device
  1487. */
  1488. static void hermon_close ( struct ib_device *ibdev ) {
  1489. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1490. int rc;
  1491. if ( ( rc = hermon_cmd_close_port ( hermon, ibdev->port ) ) != 0 ) {
  1492. DBGC ( hermon, "Hermon %p could not close port: %s\n",
  1493. hermon, strerror ( rc ) );
  1494. /* Nothing we can do about this */
  1495. }
  1496. }
  1497. /**
  1498. * Set port information
  1499. *
  1500. * @v ibdev Infiniband device
  1501. * @v mad Set port information MAD
  1502. * @ret rc Return status code
  1503. */
  1504. static int hermon_set_port_info ( struct ib_device *ibdev,
  1505. union ib_mad *mad ) {
  1506. int rc;
  1507. /* Send the MAD to the embedded SMA */
  1508. if ( ( rc = hermon_mad ( ibdev, mad ) ) != 0 )
  1509. return rc;
  1510. /* Update parameters held in software */
  1511. ib_smc_update ( ibdev, hermon_mad );
  1512. return 0;
  1513. }
  1514. /***************************************************************************
  1515. *
  1516. * Multicast group operations
  1517. *
  1518. ***************************************************************************
  1519. */
  1520. /**
  1521. * Attach to multicast group
  1522. *
  1523. * @v ibdev Infiniband device
  1524. * @v qp Queue pair
  1525. * @v gid Multicast GID
  1526. * @ret rc Return status code
  1527. */
  1528. static int hermon_mcast_attach ( struct ib_device *ibdev,
  1529. struct ib_queue_pair *qp,
  1530. struct ib_gid *gid ) {
  1531. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1532. struct hermonprm_mgm_hash hash;
  1533. struct hermonprm_mcg_entry mcg;
  1534. unsigned int index;
  1535. int rc;
  1536. /* Generate hash table index */
  1537. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1538. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1539. hermon, strerror ( rc ) );
  1540. return rc;
  1541. }
  1542. index = MLX_GET ( &hash, hash );
  1543. /* Check for existing hash table entry */
  1544. if ( ( rc = hermon_cmd_read_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1545. DBGC ( hermon, "Hermon %p could not read MCG %#x: %s\n",
  1546. hermon, index, strerror ( rc ) );
  1547. return rc;
  1548. }
  1549. if ( MLX_GET ( &mcg, hdr.members_count ) != 0 ) {
  1550. /* FIXME: this implementation allows only a single QP
  1551. * per multicast group, and doesn't handle hash
  1552. * collisions. Sufficient for IPoIB but may need to
  1553. * be extended in future.
  1554. */
  1555. DBGC ( hermon, "Hermon %p MGID index %#x already in use\n",
  1556. hermon, index );
  1557. return -EBUSY;
  1558. }
  1559. /* Update hash table entry */
  1560. MLX_FILL_1 ( &mcg, 1, hdr.members_count, 1 );
  1561. MLX_FILL_1 ( &mcg, 8, qp[0].qpn, qp->qpn );
  1562. memcpy ( &mcg.u.dwords[4], gid, sizeof ( *gid ) );
  1563. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1564. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1565. hermon, index, strerror ( rc ) );
  1566. return rc;
  1567. }
  1568. return 0;
  1569. }
  1570. /**
  1571. * Detach from multicast group
  1572. *
  1573. * @v ibdev Infiniband device
  1574. * @v qp Queue pair
  1575. * @v gid Multicast GID
  1576. */
  1577. static void hermon_mcast_detach ( struct ib_device *ibdev,
  1578. struct ib_queue_pair *qp __unused,
  1579. struct ib_gid *gid ) {
  1580. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1581. struct hermonprm_mgm_hash hash;
  1582. struct hermonprm_mcg_entry mcg;
  1583. unsigned int index;
  1584. int rc;
  1585. /* Generate hash table index */
  1586. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1587. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1588. hermon, strerror ( rc ) );
  1589. return;
  1590. }
  1591. index = MLX_GET ( &hash, hash );
  1592. /* Clear hash table entry */
  1593. memset ( &mcg, 0, sizeof ( mcg ) );
  1594. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1595. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1596. hermon, index, strerror ( rc ) );
  1597. return;
  1598. }
  1599. }
  1600. /** Hermon Infiniband operations */
  1601. static struct ib_device_operations hermon_ib_operations = {
  1602. .create_cq = hermon_create_cq,
  1603. .destroy_cq = hermon_destroy_cq,
  1604. .create_qp = hermon_create_qp,
  1605. .modify_qp = hermon_modify_qp,
  1606. .destroy_qp = hermon_destroy_qp,
  1607. .post_send = hermon_post_send,
  1608. .post_recv = hermon_post_recv,
  1609. .poll_cq = hermon_poll_cq,
  1610. .poll_eq = hermon_poll_eq,
  1611. .open = hermon_open,
  1612. .close = hermon_close,
  1613. .mcast_attach = hermon_mcast_attach,
  1614. .mcast_detach = hermon_mcast_detach,
  1615. .set_port_info = hermon_set_port_info,
  1616. };
  1617. /***************************************************************************
  1618. *
  1619. * Firmware control
  1620. *
  1621. ***************************************************************************
  1622. */
  1623. /**
  1624. * Map virtual to physical address for firmware usage
  1625. *
  1626. * @v hermon Hermon device
  1627. * @v map Mapping function
  1628. * @v va Virtual address
  1629. * @v pa Physical address
  1630. * @v len Length of region
  1631. * @ret rc Return status code
  1632. */
  1633. static int hermon_map_vpm ( struct hermon *hermon,
  1634. int ( *map ) ( struct hermon *hermon,
  1635. const struct hermonprm_virtual_physical_mapping* ),
  1636. uint64_t va, physaddr_t pa, size_t len ) {
  1637. struct hermonprm_virtual_physical_mapping mapping;
  1638. int rc;
  1639. assert ( ( va & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1640. assert ( ( pa & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1641. assert ( ( len & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1642. /* These mappings tend to generate huge volumes of
  1643. * uninteresting debug data, which basically makes it
  1644. * impossible to use debugging otherwise.
  1645. */
  1646. DBG_DISABLE ( DBGLVL_LOG | DBGLVL_EXTRA );
  1647. while ( len ) {
  1648. memset ( &mapping, 0, sizeof ( mapping ) );
  1649. MLX_FILL_1 ( &mapping, 0, va_h, ( va >> 32 ) );
  1650. MLX_FILL_1 ( &mapping, 1, va_l, ( va >> 12 ) );
  1651. MLX_FILL_2 ( &mapping, 3,
  1652. log2size, 0,
  1653. pa_l, ( pa >> 12 ) );
  1654. if ( ( rc = map ( hermon, &mapping ) ) != 0 ) {
  1655. DBG_ENABLE ( DBGLVL_LOG | DBGLVL_EXTRA );
  1656. DBGC ( hermon, "Hermon %p could not map %llx => %lx: "
  1657. "%s\n", hermon, va, pa, strerror ( rc ) );
  1658. return rc;
  1659. }
  1660. pa += HERMON_PAGE_SIZE;
  1661. va += HERMON_PAGE_SIZE;
  1662. len -= HERMON_PAGE_SIZE;
  1663. }
  1664. DBG_ENABLE ( DBGLVL_LOG | DBGLVL_EXTRA );
  1665. return 0;
  1666. }
  1667. /**
  1668. * Start firmware running
  1669. *
  1670. * @v hermon Hermon device
  1671. * @ret rc Return status code
  1672. */
  1673. static int hermon_start_firmware ( struct hermon *hermon ) {
  1674. struct hermonprm_query_fw fw;
  1675. unsigned int fw_pages;
  1676. size_t fw_size;
  1677. physaddr_t fw_base;
  1678. int rc;
  1679. /* Get firmware parameters */
  1680. if ( ( rc = hermon_cmd_query_fw ( hermon, &fw ) ) != 0 ) {
  1681. DBGC ( hermon, "Hermon %p could not query firmware: %s\n",
  1682. hermon, strerror ( rc ) );
  1683. goto err_query_fw;
  1684. }
  1685. DBGC ( hermon, "Hermon %p firmware version %d.%d.%d\n", hermon,
  1686. MLX_GET ( &fw, fw_rev_major ), MLX_GET ( &fw, fw_rev_minor ),
  1687. MLX_GET ( &fw, fw_rev_subminor ) );
  1688. fw_pages = MLX_GET ( &fw, fw_pages );
  1689. DBGC ( hermon, "Hermon %p requires %d pages (%d kB) for firmware\n",
  1690. hermon, fw_pages, ( fw_pages * ( HERMON_PAGE_SIZE / 1024 ) ) );
  1691. /* Allocate firmware pages and map firmware area */
  1692. fw_size = ( fw_pages * HERMON_PAGE_SIZE );
  1693. hermon->firmware_area = umalloc ( fw_size );
  1694. if ( ! hermon->firmware_area ) {
  1695. rc = -ENOMEM;
  1696. goto err_alloc_fa;
  1697. }
  1698. fw_base = user_to_phys ( hermon->firmware_area, 0 );
  1699. DBGC ( hermon, "Hermon %p firmware area at physical [%lx,%lx)\n",
  1700. hermon, fw_base, ( fw_base + fw_size ) );
  1701. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_fa,
  1702. 0, fw_base, fw_size ) ) != 0 ) {
  1703. DBGC ( hermon, "Hermon %p could not map firmware: %s\n",
  1704. hermon, strerror ( rc ) );
  1705. goto err_map_fa;
  1706. }
  1707. /* Start firmware */
  1708. if ( ( rc = hermon_cmd_run_fw ( hermon ) ) != 0 ) {
  1709. DBGC ( hermon, "Hermon %p could not run firmware: %s\n",
  1710. hermon, strerror ( rc ) );
  1711. goto err_run_fw;
  1712. }
  1713. DBGC ( hermon, "Hermon %p firmware started\n", hermon );
  1714. return 0;
  1715. err_run_fw:
  1716. err_map_fa:
  1717. hermon_cmd_unmap_fa ( hermon );
  1718. ufree ( hermon->firmware_area );
  1719. hermon->firmware_area = UNULL;
  1720. err_alloc_fa:
  1721. err_query_fw:
  1722. return rc;
  1723. }
  1724. /**
  1725. * Stop firmware running
  1726. *
  1727. * @v hermon Hermon device
  1728. */
  1729. static void hermon_stop_firmware ( struct hermon *hermon ) {
  1730. int rc;
  1731. if ( ( rc = hermon_cmd_unmap_fa ( hermon ) ) != 0 ) {
  1732. DBGC ( hermon, "Hermon %p FATAL could not stop firmware: %s\n",
  1733. hermon, strerror ( rc ) );
  1734. /* Leak memory and return; at least we avoid corruption */
  1735. return;
  1736. }
  1737. ufree ( hermon->firmware_area );
  1738. hermon->firmware_area = UNULL;
  1739. }
  1740. /***************************************************************************
  1741. *
  1742. * Infinihost Context Memory management
  1743. *
  1744. ***************************************************************************
  1745. */
  1746. /**
  1747. * Get device limits
  1748. *
  1749. * @v hermon Hermon device
  1750. * @ret rc Return status code
  1751. */
  1752. static int hermon_get_cap ( struct hermon *hermon ) {
  1753. struct hermonprm_query_dev_cap dev_cap;
  1754. int rc;
  1755. if ( ( rc = hermon_cmd_query_dev_cap ( hermon, &dev_cap ) ) != 0 ) {
  1756. DBGC ( hermon, "Hermon %p could not get device limits: %s\n",
  1757. hermon, strerror ( rc ) );
  1758. return rc;
  1759. }
  1760. hermon->cap.cmpt_entry_size = MLX_GET ( &dev_cap, c_mpt_entry_sz );
  1761. hermon->cap.reserved_qps =
  1762. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_qps ) );
  1763. hermon->cap.qpc_entry_size = MLX_GET ( &dev_cap, qpc_entry_sz );
  1764. hermon->cap.altc_entry_size = MLX_GET ( &dev_cap, altc_entry_sz );
  1765. hermon->cap.auxc_entry_size = MLX_GET ( &dev_cap, aux_entry_sz );
  1766. hermon->cap.reserved_srqs =
  1767. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_srqs ) );
  1768. hermon->cap.srqc_entry_size = MLX_GET ( &dev_cap, srq_entry_sz );
  1769. hermon->cap.reserved_cqs =
  1770. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_cqs ) );
  1771. hermon->cap.cqc_entry_size = MLX_GET ( &dev_cap, cqc_entry_sz );
  1772. hermon->cap.reserved_eqs = MLX_GET ( &dev_cap, num_rsvd_eqs );
  1773. hermon->cap.eqc_entry_size = MLX_GET ( &dev_cap, eqc_entry_sz );
  1774. hermon->cap.reserved_mtts =
  1775. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mtts ) );
  1776. hermon->cap.mtt_entry_size = MLX_GET ( &dev_cap, mtt_entry_sz );
  1777. hermon->cap.reserved_mrws =
  1778. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mrws ) );
  1779. hermon->cap.dmpt_entry_size = MLX_GET ( &dev_cap, d_mpt_entry_sz );
  1780. hermon->cap.reserved_uars = MLX_GET ( &dev_cap, num_rsvd_uars );
  1781. return 0;
  1782. }
  1783. /**
  1784. * Get ICM usage
  1785. *
  1786. * @v log_num_entries Log2 of the number of entries
  1787. * @v entry_size Entry size
  1788. * @ret usage Usage size in ICM
  1789. */
  1790. static size_t icm_usage ( unsigned int log_num_entries, size_t entry_size ) {
  1791. size_t usage;
  1792. usage = ( ( 1 << log_num_entries ) * entry_size );
  1793. usage = ( ( usage + HERMON_PAGE_SIZE - 1 ) &
  1794. ~( HERMON_PAGE_SIZE - 1 ) );
  1795. return usage;
  1796. }
  1797. /**
  1798. * Allocate ICM
  1799. *
  1800. * @v hermon Hermon device
  1801. * @v init_hca INIT_HCA structure to fill in
  1802. * @ret rc Return status code
  1803. */
  1804. static int hermon_alloc_icm ( struct hermon *hermon,
  1805. struct hermonprm_init_hca *init_hca ) {
  1806. struct hermonprm_scalar_parameter icm_size;
  1807. struct hermonprm_scalar_parameter icm_aux_size;
  1808. uint64_t icm_offset = 0;
  1809. unsigned int log_num_qps, log_num_srqs, log_num_cqs, log_num_eqs;
  1810. unsigned int log_num_mtts, log_num_mpts;
  1811. size_t cmpt_max_len;
  1812. size_t qp_cmpt_len, srq_cmpt_len, cq_cmpt_len, eq_cmpt_len;
  1813. size_t icm_len, icm_aux_len;
  1814. physaddr_t icm_phys;
  1815. int i;
  1816. int rc;
  1817. /*
  1818. * Start by carving up the ICM virtual address space
  1819. *
  1820. */
  1821. /* Calculate number of each object type within ICM */
  1822. log_num_qps = fls ( hermon->cap.reserved_qps +
  1823. HERMON_RSVD_SPECIAL_QPS + HERMON_MAX_QPS - 1 );
  1824. log_num_srqs = fls ( hermon->cap.reserved_srqs - 1 );
  1825. log_num_cqs = fls ( hermon->cap.reserved_cqs + HERMON_MAX_CQS - 1 );
  1826. log_num_eqs = fls ( hermon->cap.reserved_eqs + HERMON_MAX_EQS - 1 );
  1827. log_num_mtts = fls ( hermon->cap.reserved_mtts + HERMON_MAX_MTTS - 1 );
  1828. /* ICM starts with the cMPT tables, which are sparse */
  1829. cmpt_max_len = ( HERMON_CMPT_MAX_ENTRIES *
  1830. ( ( uint64_t ) hermon->cap.cmpt_entry_size ) );
  1831. qp_cmpt_len = icm_usage ( log_num_qps, hermon->cap.cmpt_entry_size );
  1832. hermon->icm_map[HERMON_ICM_QP_CMPT].offset = icm_offset;
  1833. hermon->icm_map[HERMON_ICM_QP_CMPT].len = qp_cmpt_len;
  1834. icm_offset += cmpt_max_len;
  1835. srq_cmpt_len = icm_usage ( log_num_srqs, hermon->cap.cmpt_entry_size );
  1836. hermon->icm_map[HERMON_ICM_SRQ_CMPT].offset = icm_offset;
  1837. hermon->icm_map[HERMON_ICM_SRQ_CMPT].len = srq_cmpt_len;
  1838. icm_offset += cmpt_max_len;
  1839. cq_cmpt_len = icm_usage ( log_num_cqs, hermon->cap.cmpt_entry_size );
  1840. hermon->icm_map[HERMON_ICM_CQ_CMPT].offset = icm_offset;
  1841. hermon->icm_map[HERMON_ICM_CQ_CMPT].len = cq_cmpt_len;
  1842. icm_offset += cmpt_max_len;
  1843. eq_cmpt_len = icm_usage ( log_num_eqs, hermon->cap.cmpt_entry_size );
  1844. hermon->icm_map[HERMON_ICM_EQ_CMPT].offset = icm_offset;
  1845. hermon->icm_map[HERMON_ICM_EQ_CMPT].len = eq_cmpt_len;
  1846. icm_offset += cmpt_max_len;
  1847. hermon->icm_map[HERMON_ICM_OTHER].offset = icm_offset;
  1848. /* Queue pair contexts */
  1849. MLX_FILL_1 ( init_hca, 12,
  1850. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_h,
  1851. ( icm_offset >> 32 ) );
  1852. MLX_FILL_2 ( init_hca, 13,
  1853. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_l,
  1854. ( icm_offset >> 5 ),
  1855. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp,
  1856. log_num_qps );
  1857. DBGC ( hermon, "Hermon %p ICM QPC base = %llx\n", hermon, icm_offset );
  1858. icm_offset += icm_usage ( log_num_qps, hermon->cap.qpc_entry_size );
  1859. /* Extended alternate path contexts */
  1860. MLX_FILL_1 ( init_hca, 24,
  1861. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_h,
  1862. ( icm_offset >> 32 ) );
  1863. MLX_FILL_1 ( init_hca, 25,
  1864. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_l,
  1865. icm_offset );
  1866. DBGC ( hermon, "Hermon %p ICM ALTC base = %llx\n", hermon, icm_offset);
  1867. icm_offset += icm_usage ( log_num_qps,
  1868. hermon->cap.altc_entry_size );
  1869. /* Extended auxiliary contexts */
  1870. MLX_FILL_1 ( init_hca, 28,
  1871. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_h,
  1872. ( icm_offset >> 32 ) );
  1873. MLX_FILL_1 ( init_hca, 29,
  1874. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_l,
  1875. icm_offset );
  1876. DBGC ( hermon, "Hermon %p ICM AUXC base = %llx\n", hermon, icm_offset);
  1877. icm_offset += icm_usage ( log_num_qps,
  1878. hermon->cap.auxc_entry_size );
  1879. /* Shared receive queue contexts */
  1880. MLX_FILL_1 ( init_hca, 18,
  1881. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_h,
  1882. ( icm_offset >> 32 ) );
  1883. MLX_FILL_2 ( init_hca, 19,
  1884. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_l,
  1885. ( icm_offset >> 5 ),
  1886. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_srq,
  1887. log_num_srqs );
  1888. DBGC ( hermon, "Hermon %p ICM SRQC base = %llx\n", hermon, icm_offset);
  1889. icm_offset += icm_usage ( log_num_srqs,
  1890. hermon->cap.srqc_entry_size );
  1891. /* Completion queue contexts */
  1892. MLX_FILL_1 ( init_hca, 20,
  1893. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_h,
  1894. ( icm_offset >> 32 ) );
  1895. MLX_FILL_2 ( init_hca, 21,
  1896. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_l,
  1897. ( icm_offset >> 5 ),
  1898. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq,
  1899. log_num_cqs );
  1900. DBGC ( hermon, "Hermon %p ICM CQC base = %llx\n", hermon, icm_offset );
  1901. icm_offset += icm_usage ( log_num_cqs, hermon->cap.cqc_entry_size );
  1902. /* Event queue contexts */
  1903. MLX_FILL_1 ( init_hca, 32,
  1904. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_h,
  1905. ( icm_offset >> 32 ) );
  1906. MLX_FILL_2 ( init_hca, 33,
  1907. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_l,
  1908. ( icm_offset >> 5 ),
  1909. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_eq,
  1910. log_num_eqs );
  1911. DBGC ( hermon, "Hermon %p ICM EQC base = %llx\n", hermon, icm_offset );
  1912. icm_offset += icm_usage ( log_num_eqs, hermon->cap.eqc_entry_size );
  1913. /* Memory translation table */
  1914. MLX_FILL_1 ( init_hca, 64,
  1915. tpt_parameters.mtt_base_addr_h, ( icm_offset >> 32 ) );
  1916. MLX_FILL_1 ( init_hca, 65,
  1917. tpt_parameters.mtt_base_addr_l, icm_offset );
  1918. DBGC ( hermon, "Hermon %p ICM MTT base = %llx\n", hermon, icm_offset );
  1919. icm_offset += icm_usage ( log_num_mtts,
  1920. hermon->cap.mtt_entry_size );
  1921. /* Memory protection table */
  1922. log_num_mpts = fls ( hermon->cap.reserved_mrws + 1 - 1 );
  1923. MLX_FILL_1 ( init_hca, 60,
  1924. tpt_parameters.dmpt_base_adr_h, ( icm_offset >> 32 ) );
  1925. MLX_FILL_1 ( init_hca, 61,
  1926. tpt_parameters.dmpt_base_adr_l, icm_offset );
  1927. MLX_FILL_1 ( init_hca, 62,
  1928. tpt_parameters.log_dmpt_sz, log_num_mpts );
  1929. DBGC ( hermon, "Hermon %p ICM DMPT base = %llx\n", hermon, icm_offset);
  1930. icm_offset += icm_usage ( log_num_mpts,
  1931. hermon->cap.dmpt_entry_size );
  1932. /* Multicast table */
  1933. MLX_FILL_1 ( init_hca, 48,
  1934. multicast_parameters.mc_base_addr_h,
  1935. ( icm_offset >> 32 ) );
  1936. MLX_FILL_1 ( init_hca, 49,
  1937. multicast_parameters.mc_base_addr_l, icm_offset );
  1938. MLX_FILL_1 ( init_hca, 52,
  1939. multicast_parameters.log_mc_table_entry_sz,
  1940. fls ( sizeof ( struct hermonprm_mcg_entry ) - 1 ) );
  1941. MLX_FILL_1 ( init_hca, 53,
  1942. multicast_parameters.log_mc_table_hash_sz, 3 );
  1943. MLX_FILL_1 ( init_hca, 54,
  1944. multicast_parameters.log_mc_table_sz, 3 );
  1945. DBGC ( hermon, "Hermon %p ICM MC base = %llx\n", hermon, icm_offset );
  1946. icm_offset += ( ( 8 * sizeof ( struct hermonprm_mcg_entry ) +
  1947. HERMON_PAGE_SIZE - 1 ) & ~( HERMON_PAGE_SIZE - 1 ) );
  1948. hermon->icm_map[HERMON_ICM_OTHER].len =
  1949. ( icm_offset - hermon->icm_map[HERMON_ICM_OTHER].offset );
  1950. /*
  1951. * Allocate and map physical memory for (portions of) ICM
  1952. *
  1953. * Map is:
  1954. * ICM AUX area (aligned to its own size)
  1955. * cMPT areas
  1956. * Other areas
  1957. */
  1958. /* Calculate physical memory required for ICM */
  1959. icm_len = 0;
  1960. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  1961. icm_len += hermon->icm_map[i].len;
  1962. }
  1963. /* Get ICM auxiliary area size */
  1964. memset ( &icm_size, 0, sizeof ( icm_size ) );
  1965. MLX_FILL_1 ( &icm_size, 0, value_hi, ( icm_offset >> 32 ) );
  1966. MLX_FILL_1 ( &icm_size, 1, value, icm_offset );
  1967. if ( ( rc = hermon_cmd_set_icm_size ( hermon, &icm_size,
  1968. &icm_aux_size ) ) != 0 ) {
  1969. DBGC ( hermon, "Hermon %p could not set ICM size: %s\n",
  1970. hermon, strerror ( rc ) );
  1971. goto err_set_icm_size;
  1972. }
  1973. icm_aux_len = ( MLX_GET ( &icm_aux_size, value ) * HERMON_PAGE_SIZE );
  1974. /* Allocate ICM data and auxiliary area */
  1975. DBGC ( hermon, "Hermon %p requires %zd kB ICM and %zd kB AUX ICM\n",
  1976. hermon, ( icm_len / 1024 ), ( icm_aux_len / 1024 ) );
  1977. hermon->icm = umalloc ( icm_aux_len + icm_len );
  1978. if ( ! hermon->icm ) {
  1979. rc = -ENOMEM;
  1980. goto err_alloc;
  1981. }
  1982. icm_phys = user_to_phys ( hermon->icm, 0 );
  1983. /* Map ICM auxiliary area */
  1984. DBGC ( hermon, "Hermon %p mapping ICM AUX => %08lx\n",
  1985. hermon, icm_phys );
  1986. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_icm_aux,
  1987. 0, icm_phys, icm_aux_len ) ) != 0 ) {
  1988. DBGC ( hermon, "Hermon %p could not map AUX ICM: %s\n",
  1989. hermon, strerror ( rc ) );
  1990. goto err_map_icm_aux;
  1991. }
  1992. icm_phys += icm_aux_len;
  1993. /* MAP ICM area */
  1994. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  1995. DBGC ( hermon, "Hermon %p mapping ICM %llx+%zx => %08lx\n",
  1996. hermon, hermon->icm_map[i].offset,
  1997. hermon->icm_map[i].len, icm_phys );
  1998. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_icm,
  1999. hermon->icm_map[i].offset,
  2000. icm_phys,
  2001. hermon->icm_map[i].len ) ) != 0 ){
  2002. DBGC ( hermon, "Hermon %p could not map ICM: %s\n",
  2003. hermon, strerror ( rc ) );
  2004. goto err_map_icm;
  2005. }
  2006. icm_phys += hermon->icm_map[i].len;
  2007. }
  2008. return 0;
  2009. err_map_icm:
  2010. assert ( i == 0 ); /* We don't handle partial failure at present */
  2011. err_map_icm_aux:
  2012. hermon_cmd_unmap_icm_aux ( hermon );
  2013. ufree ( hermon->icm );
  2014. hermon->icm = UNULL;
  2015. err_alloc:
  2016. err_set_icm_size:
  2017. return rc;
  2018. }
  2019. /**
  2020. * Free ICM
  2021. *
  2022. * @v hermon Hermon device
  2023. */
  2024. static void hermon_free_icm ( struct hermon *hermon ) {
  2025. struct hermonprm_scalar_parameter unmap_icm;
  2026. int i;
  2027. for ( i = ( HERMON_ICM_NUM_REGIONS - 1 ) ; i >= 0 ; i-- ) {
  2028. memset ( &unmap_icm, 0, sizeof ( unmap_icm ) );
  2029. MLX_FILL_1 ( &unmap_icm, 0, value_hi,
  2030. ( hermon->icm_map[i].offset >> 32 ) );
  2031. MLX_FILL_1 ( &unmap_icm, 1, value,
  2032. hermon->icm_map[i].offset );
  2033. hermon_cmd_unmap_icm ( hermon,
  2034. ( 1 << fls ( ( hermon->icm_map[i].len /
  2035. HERMON_PAGE_SIZE ) - 1)),
  2036. &unmap_icm );
  2037. }
  2038. hermon_cmd_unmap_icm_aux ( hermon );
  2039. ufree ( hermon->icm );
  2040. hermon->icm = UNULL;
  2041. }
  2042. /***************************************************************************
  2043. *
  2044. * PCI interface
  2045. *
  2046. ***************************************************************************
  2047. */
  2048. /**
  2049. * Set up memory protection table
  2050. *
  2051. * @v hermon Hermon device
  2052. * @ret rc Return status code
  2053. */
  2054. static int hermon_setup_mpt ( struct hermon *hermon ) {
  2055. struct hermonprm_mpt mpt;
  2056. uint32_t key;
  2057. int rc;
  2058. /* Derive key */
  2059. key = ( hermon->cap.reserved_mrws | HERMON_MKEY_PREFIX );
  2060. hermon->reserved_lkey = ( ( key << 8 ) | ( key >> 24 ) );
  2061. /* Initialise memory protection table */
  2062. memset ( &mpt, 0, sizeof ( mpt ) );
  2063. MLX_FILL_4 ( &mpt, 0,
  2064. r_w, 1,
  2065. pa, 1,
  2066. lr, 1,
  2067. lw, 1 );
  2068. MLX_FILL_1 ( &mpt, 2, mem_key, key );
  2069. MLX_FILL_1 ( &mpt, 3, pd, HERMON_GLOBAL_PD );
  2070. MLX_FILL_1 ( &mpt, 10, len64, 1 );
  2071. if ( ( rc = hermon_cmd_sw2hw_mpt ( hermon,
  2072. hermon->cap.reserved_mrws,
  2073. &mpt ) ) != 0 ) {
  2074. DBGC ( hermon, "Hermon %p could not set up MPT: %s\n",
  2075. hermon, strerror ( rc ) );
  2076. return rc;
  2077. }
  2078. return 0;
  2079. }
  2080. /**
  2081. * Configure special queue pairs
  2082. *
  2083. * @v hermon Hermon device
  2084. * @ret rc Return status code
  2085. */
  2086. static int hermon_configure_special_qps ( struct hermon *hermon ) {
  2087. int rc;
  2088. /* Special QP block must be aligned on its own size */
  2089. hermon->special_qpn_base = ( ( HERMON_QPN_BASE +
  2090. hermon->cap.reserved_qps +
  2091. HERMON_NUM_SPECIAL_QPS - 1 )
  2092. & ~( HERMON_NUM_SPECIAL_QPS - 1 ) );
  2093. hermon->qpn_base = ( hermon->special_qpn_base +
  2094. HERMON_NUM_SPECIAL_QPS );
  2095. DBGC ( hermon, "Hermon %p special QPs at [%lx,%lx]\n", hermon,
  2096. hermon->special_qpn_base, ( hermon->qpn_base - 1 ) );
  2097. /* Issue command to configure special QPs */
  2098. if ( ( rc = hermon_cmd_conf_special_qp ( hermon, 0x00,
  2099. hermon->special_qpn_base ) ) != 0 ) {
  2100. DBGC ( hermon, "Hermon %p could not configure special QPs: "
  2101. "%s\n", hermon, strerror ( rc ) );
  2102. return rc;
  2103. }
  2104. return 0;
  2105. }
  2106. /**
  2107. * Probe PCI device
  2108. *
  2109. * @v pci PCI device
  2110. * @v id PCI ID
  2111. * @ret rc Return status code
  2112. */
  2113. static int hermon_probe ( struct pci_device *pci,
  2114. const struct pci_device_id *id __unused ) {
  2115. struct hermon *hermon;
  2116. struct ib_device *ibdev;
  2117. struct hermonprm_init_hca init_hca;
  2118. int i;
  2119. int rc;
  2120. /* Allocate Hermon device */
  2121. hermon = zalloc ( sizeof ( *hermon ) );
  2122. if ( ! hermon ) {
  2123. rc = -ENOMEM;
  2124. goto err_alloc_hermon;
  2125. }
  2126. pci_set_drvdata ( pci, hermon );
  2127. /* Allocate Infiniband devices */
  2128. for ( i = 0 ; i < HERMON_NUM_PORTS ; i++ ) {
  2129. ibdev = alloc_ibdev ( 0 );
  2130. if ( ! ibdev ) {
  2131. rc = -ENOMEM;
  2132. goto err_alloc_ibdev;
  2133. }
  2134. hermon->ibdev[i] = ibdev;
  2135. ibdev->op = &hermon_ib_operations;
  2136. ibdev->dev = &pci->dev;
  2137. ibdev->port = ( HERMON_PORT_BASE + i );
  2138. ib_set_drvdata ( ibdev, hermon );
  2139. }
  2140. /* Fix up PCI device */
  2141. adjust_pci_device ( pci );
  2142. /* Get PCI BARs */
  2143. hermon->config = ioremap ( pci_bar_start ( pci, HERMON_PCI_CONFIG_BAR),
  2144. HERMON_PCI_CONFIG_BAR_SIZE );
  2145. hermon->uar = ioremap ( pci_bar_start ( pci, HERMON_PCI_UAR_BAR ),
  2146. HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE );
  2147. /* Allocate space for mailboxes */
  2148. hermon->mailbox_in = malloc_dma ( HERMON_MBOX_SIZE,
  2149. HERMON_MBOX_ALIGN );
  2150. if ( ! hermon->mailbox_in ) {
  2151. rc = -ENOMEM;
  2152. goto err_mailbox_in;
  2153. }
  2154. hermon->mailbox_out = malloc_dma ( HERMON_MBOX_SIZE,
  2155. HERMON_MBOX_ALIGN );
  2156. if ( ! hermon->mailbox_out ) {
  2157. rc = -ENOMEM;
  2158. goto err_mailbox_out;
  2159. }
  2160. /* Start firmware */
  2161. if ( ( rc = hermon_start_firmware ( hermon ) ) != 0 )
  2162. goto err_start_firmware;
  2163. /* Get device limits */
  2164. if ( ( rc = hermon_get_cap ( hermon ) ) != 0 )
  2165. goto err_get_cap;
  2166. /* Allocate ICM */
  2167. memset ( &init_hca, 0, sizeof ( init_hca ) );
  2168. if ( ( rc = hermon_alloc_icm ( hermon, &init_hca ) ) != 0 )
  2169. goto err_alloc_icm;
  2170. /* Initialise HCA */
  2171. MLX_FILL_1 ( &init_hca, 0, version, 0x02 /* "Must be 0x02" */ );
  2172. MLX_FILL_1 ( &init_hca, 5, udp, 1 );
  2173. MLX_FILL_1 ( &init_hca, 74, uar_parameters.log_max_uars, 8 );
  2174. if ( ( rc = hermon_cmd_init_hca ( hermon, &init_hca ) ) != 0 ) {
  2175. DBGC ( hermon, "Hermon %p could not initialise HCA: %s\n",
  2176. hermon, strerror ( rc ) );
  2177. goto err_init_hca;
  2178. }
  2179. /* Set up memory protection */
  2180. if ( ( rc = hermon_setup_mpt ( hermon ) ) != 0 )
  2181. goto err_setup_mpt;
  2182. /* Set up event queue */
  2183. if ( ( rc = hermon_create_eq ( hermon ) ) != 0 )
  2184. goto err_create_eq;
  2185. /* Configure special QPs */
  2186. if ( ( rc = hermon_configure_special_qps ( hermon ) ) != 0 )
  2187. goto err_conf_special_qps;
  2188. /* Update MAD parameters */
  2189. for ( i = 0 ; i < HERMON_NUM_PORTS ; i++ )
  2190. ib_smc_update ( hermon->ibdev[i], hermon_mad );
  2191. /* Register Infiniband devices */
  2192. for ( i = 0 ; i < HERMON_NUM_PORTS ; i++ ) {
  2193. if ( ( rc = register_ibdev ( hermon->ibdev[i] ) ) != 0 ) {
  2194. DBGC ( hermon, "Hermon %p could not register IB "
  2195. "device: %s\n", hermon, strerror ( rc ) );
  2196. goto err_register_ibdev;
  2197. }
  2198. }
  2199. return 0;
  2200. i = HERMON_NUM_PORTS;
  2201. err_register_ibdev:
  2202. for ( i-- ; i >= 0 ; i-- )
  2203. unregister_ibdev ( hermon->ibdev[i] );
  2204. err_conf_special_qps:
  2205. hermon_destroy_eq ( hermon );
  2206. err_create_eq:
  2207. err_setup_mpt:
  2208. hermon_cmd_close_hca ( hermon );
  2209. err_init_hca:
  2210. hermon_free_icm ( hermon );
  2211. err_alloc_icm:
  2212. err_get_cap:
  2213. hermon_stop_firmware ( hermon );
  2214. err_start_firmware:
  2215. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2216. err_mailbox_out:
  2217. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2218. err_mailbox_in:
  2219. i = HERMON_NUM_PORTS;
  2220. err_alloc_ibdev:
  2221. for ( i-- ; i >= 0 ; i-- )
  2222. ibdev_put ( hermon->ibdev[i] );
  2223. free ( hermon );
  2224. err_alloc_hermon:
  2225. return rc;
  2226. }
  2227. /**
  2228. * Remove PCI device
  2229. *
  2230. * @v pci PCI device
  2231. */
  2232. static void hermon_remove ( struct pci_device *pci ) {
  2233. struct hermon *hermon = pci_get_drvdata ( pci );
  2234. int i;
  2235. for ( i = ( HERMON_NUM_PORTS - 1 ) ; i >= 0 ; i-- )
  2236. unregister_ibdev ( hermon->ibdev[i] );
  2237. hermon_destroy_eq ( hermon );
  2238. hermon_cmd_close_hca ( hermon );
  2239. hermon_free_icm ( hermon );
  2240. hermon_stop_firmware ( hermon );
  2241. hermon_stop_firmware ( hermon );
  2242. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2243. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2244. for ( i = ( HERMON_NUM_PORTS - 1 ) ; i >= 0 ; i-- )
  2245. ibdev_put ( hermon->ibdev[i] );
  2246. free ( hermon );
  2247. }
  2248. static struct pci_device_id hermon_nics[] = {
  2249. PCI_ROM ( 0x15b3, 0x6340, "mt25408", "MT25408 HCA driver", 0 ),
  2250. PCI_ROM ( 0x15b3, 0x634a, "mt25418", "MT25418 HCA driver", 0 ),
  2251. PCI_ROM ( 0x15b3, 0x6732, "mt26418", "MT26418 HCA driver", 0 ),
  2252. PCI_ROM ( 0x15b3, 0x673c, "mt26428", "MT26428 HCA driver", 0 ),
  2253. };
  2254. struct pci_driver hermon_driver __pci_driver = {
  2255. .ids = hermon_nics,
  2256. .id_count = ( sizeof ( hermon_nics ) / sizeof ( hermon_nics[0] ) ),
  2257. .probe = hermon_probe,
  2258. .remove = hermon_remove,
  2259. };