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amd8111e.c 17KB

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  1. /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
  2. * Copyright (C) 2004 Advanced Micro Devices
  3. * Copyright (C) 2005 Liu Tao <liutao1980@gmail.com> [etherboot port]
  4. *
  5. * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
  6. * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
  7. * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
  8. * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
  9. * Copyright 1993 United States Government as represented by the
  10. * Director, National Security Agency.[ pcnet32.c ]
  11. * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
  12. * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
  13. *
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  28. * USA
  29. */
  30. #include "etherboot.h"
  31. #include "nic.h"
  32. #include "mii.h"
  33. #include <gpxe/pci.h>
  34. #include <gpxe/ethernet.h>
  35. #include "string.h"
  36. #include "stdint.h"
  37. #include "amd8111e.h"
  38. /* driver definitions */
  39. #define NUM_TX_SLOTS 2
  40. #define NUM_RX_SLOTS 4
  41. #define TX_SLOTS_MASK 1
  42. #define RX_SLOTS_MASK 3
  43. #define TX_BUF_LEN 1536
  44. #define RX_BUF_LEN 1536
  45. #define TX_PKT_LEN_MAX (ETH_FRAME_LEN - ETH_HLEN)
  46. #define RX_PKT_LEN_MIN 60
  47. #define RX_PKT_LEN_MAX ETH_FRAME_LEN
  48. #define TX_TIMEOUT 3000
  49. #define TX_PROCESS_TIME 10
  50. #define TX_RETRY (TX_TIMEOUT / TX_PROCESS_TIME)
  51. #define PHY_RW_RETRY 10
  52. struct amd8111e_tx_desc {
  53. u16 buf_len;
  54. u16 tx_flags;
  55. u16 tag_ctrl_info;
  56. u16 tag_ctrl_cmd;
  57. u32 buf_phy_addr;
  58. u32 reserved;
  59. };
  60. struct amd8111e_rx_desc {
  61. u32 reserved;
  62. u16 msg_len;
  63. u16 tag_ctrl_info;
  64. u16 buf_len;
  65. u16 rx_flags;
  66. u32 buf_phy_addr;
  67. };
  68. struct eth_frame {
  69. u8 dst_addr[ETH_ALEN];
  70. u8 src_addr[ETH_ALEN];
  71. u16 type;
  72. u8 data[ETH_FRAME_LEN - ETH_HLEN];
  73. } __attribute__((packed));
  74. struct amd8111e_priv {
  75. struct amd8111e_tx_desc tx_ring[NUM_TX_SLOTS];
  76. struct amd8111e_rx_desc rx_ring[NUM_RX_SLOTS];
  77. unsigned char tx_buf[NUM_TX_SLOTS][TX_BUF_LEN];
  78. unsigned char rx_buf[NUM_RX_SLOTS][RX_BUF_LEN];
  79. unsigned long tx_idx, rx_idx;
  80. int tx_consistent;
  81. char opened;
  82. char link;
  83. char speed;
  84. char duplex;
  85. int ext_phy_addr;
  86. u32 ext_phy_id;
  87. struct pci_device *pdev;
  88. struct nic *nic;
  89. void *mmio;
  90. };
  91. static struct amd8111e_priv amd8111e;
  92. /********************************************************
  93. * locale functions *
  94. ********************************************************/
  95. static void amd8111e_init_hw_default(struct amd8111e_priv *lp);
  96. static int amd8111e_start(struct amd8111e_priv *lp);
  97. static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val);
  98. #if 0
  99. static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val);
  100. #endif
  101. static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp);
  102. static void amd8111e_disable_interrupt(struct amd8111e_priv *lp);
  103. static void amd8111e_enable_interrupt(struct amd8111e_priv *lp);
  104. static void amd8111e_force_interrupt(struct amd8111e_priv *lp);
  105. static int amd8111e_get_mac_address(struct amd8111e_priv *lp);
  106. static int amd8111e_init_rx_ring(struct amd8111e_priv *lp);
  107. static int amd8111e_init_tx_ring(struct amd8111e_priv *lp);
  108. static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index);
  109. static void amd8111e_wait_link(struct amd8111e_priv *lp);
  110. static void amd8111e_poll_link(struct amd8111e_priv *lp);
  111. static void amd8111e_restart(struct amd8111e_priv *lp);
  112. /*
  113. * This function clears necessary the device registers.
  114. */
  115. static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
  116. {
  117. unsigned int reg_val;
  118. void *mmio = lp->mmio;
  119. /* stop the chip */
  120. writel(RUN, mmio + CMD0);
  121. /* Clear RCV_RING_BASE_ADDR */
  122. writel(0, mmio + RCV_RING_BASE_ADDR0);
  123. /* Clear XMT_RING_BASE_ADDR */
  124. writel(0, mmio + XMT_RING_BASE_ADDR0);
  125. writel(0, mmio + XMT_RING_BASE_ADDR1);
  126. writel(0, mmio + XMT_RING_BASE_ADDR2);
  127. writel(0, mmio + XMT_RING_BASE_ADDR3);
  128. /* Clear CMD0 */
  129. writel(CMD0_CLEAR, mmio + CMD0);
  130. /* Clear CMD2 */
  131. writel(CMD2_CLEAR, mmio + CMD2);
  132. /* Clear CMD7 */
  133. writel(CMD7_CLEAR, mmio + CMD7);
  134. /* Clear DLY_INT_A and DLY_INT_B */
  135. writel(0x0, mmio + DLY_INT_A);
  136. writel(0x0, mmio + DLY_INT_B);
  137. /* Clear FLOW_CONTROL */
  138. writel(0x0, mmio + FLOW_CONTROL);
  139. /* Clear INT0 write 1 to clear register */
  140. reg_val = readl(mmio + INT0);
  141. writel(reg_val, mmio + INT0);
  142. /* Clear STVAL */
  143. writel(0x0, mmio + STVAL);
  144. /* Clear INTEN0 */
  145. writel(INTEN0_CLEAR, mmio + INTEN0);
  146. /* Clear LADRF */
  147. writel(0x0, mmio + LADRF);
  148. /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
  149. writel(0x80010, mmio + SRAM_SIZE);
  150. /* Clear RCV_RING0_LEN */
  151. writel(0x0, mmio + RCV_RING_LEN0);
  152. /* Clear XMT_RING0/1/2/3_LEN */
  153. writel(0x0, mmio + XMT_RING_LEN0);
  154. writel(0x0, mmio + XMT_RING_LEN1);
  155. writel(0x0, mmio + XMT_RING_LEN2);
  156. writel(0x0, mmio + XMT_RING_LEN3);
  157. /* Clear XMT_RING_LIMIT */
  158. writel(0x0, mmio + XMT_RING_LIMIT);
  159. /* Clear MIB */
  160. writew(MIB_CLEAR, mmio + MIB_ADDR);
  161. /* Clear LARF */
  162. writel( 0, mmio + LADRF);
  163. writel( 0, mmio + LADRF + 4);
  164. /* SRAM_SIZE register */
  165. reg_val = readl(mmio + SRAM_SIZE);
  166. /* Set default value to CTRL1 Register */
  167. writel(CTRL1_DEFAULT, mmio + CTRL1);
  168. /* To avoid PCI posting bug */
  169. readl(mmio + CMD2);
  170. }
  171. /*
  172. * This function initializes the device registers and starts the device.
  173. */
  174. static int amd8111e_start(struct amd8111e_priv *lp)
  175. {
  176. struct nic *nic = lp->nic;
  177. void *mmio = lp->mmio;
  178. int i, reg_val;
  179. /* stop the chip */
  180. writel(RUN, mmio + CMD0);
  181. /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
  182. writew(0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
  183. /* enable the port manager and set auto negotiation always */
  184. writel(VAL1 | EN_PMGR, mmio + CMD3 );
  185. writel(XPHYANE | XPHYRST, mmio + CTRL2);
  186. /* set control registers */
  187. reg_val = readl(mmio + CTRL1);
  188. reg_val &= ~XMTSP_MASK;
  189. writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
  190. /* initialize tx and rx ring base addresses */
  191. amd8111e_init_tx_ring(lp);
  192. amd8111e_init_rx_ring(lp);
  193. writel(virt_to_bus(lp->tx_ring), mmio + XMT_RING_BASE_ADDR0);
  194. writel(virt_to_bus(lp->rx_ring), mmio + RCV_RING_BASE_ADDR0);
  195. writew(NUM_TX_SLOTS, mmio + XMT_RING_LEN0);
  196. writew(NUM_RX_SLOTS, mmio + RCV_RING_LEN0);
  197. /* set default IPG to 96 */
  198. writew(DEFAULT_IPG, mmio + IPG);
  199. writew(DEFAULT_IPG - IFS1_DELTA, mmio + IFS1);
  200. /* AutoPAD transmit, Retransmit on Underflow */
  201. writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
  202. /* JUMBO disabled */
  203. writel(JUMBO, mmio + CMD3);
  204. /* Setting the MAC address to the device */
  205. for(i = 0; i < ETH_ALEN; i++)
  206. writeb(nic->node_addr[i], mmio + PADR + i);
  207. /* set RUN bit to start the chip, interrupt not enabled */
  208. writel(VAL2 | RDMD0 | VAL0 | RUN, mmio + CMD0);
  209. /* To avoid PCI posting bug */
  210. readl(mmio + CMD0);
  211. return 0;
  212. }
  213. /*
  214. This function will read the PHY registers.
  215. */
  216. static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val)
  217. {
  218. void *mmio = lp->mmio;
  219. unsigned int reg_val;
  220. unsigned int retry = PHY_RW_RETRY;
  221. reg_val = readl(mmio + PHY_ACCESS);
  222. while (reg_val & PHY_CMD_ACTIVE)
  223. reg_val = readl(mmio + PHY_ACCESS);
  224. writel(PHY_RD_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16),
  225. mmio + PHY_ACCESS);
  226. do {
  227. reg_val = readl(mmio + PHY_ACCESS);
  228. udelay(30); /* It takes 30 us to read/write data */
  229. } while (--retry && (reg_val & PHY_CMD_ACTIVE));
  230. if (reg_val & PHY_RD_ERR) {
  231. *val = 0;
  232. return -1;
  233. }
  234. *val = reg_val & 0xffff;
  235. return 0;
  236. }
  237. /*
  238. This function will write into PHY registers.
  239. */
  240. #if 0
  241. static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val)
  242. {
  243. void *mmio = lp->mmio;
  244. unsigned int reg_val;
  245. unsigned int retry = PHY_RW_RETRY;
  246. reg_val = readl(mmio + PHY_ACCESS);
  247. while (reg_val & PHY_CMD_ACTIVE)
  248. reg_val = readl(mmio + PHY_ACCESS);
  249. writel(PHY_WR_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16) | val,
  250. mmio + PHY_ACCESS);
  251. do {
  252. reg_val = readl(mmio + PHY_ACCESS);
  253. udelay(30); /* It takes 30 us to read/write the data */
  254. } while (--retry && (reg_val & PHY_CMD_ACTIVE));
  255. if(reg_val & PHY_RD_ERR)
  256. return -1;
  257. return 0;
  258. }
  259. #endif
  260. static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp)
  261. {
  262. int i;
  263. lp->ext_phy_id = 0;
  264. lp->ext_phy_addr = 1;
  265. for (i = 0x1e; i >= 0; i--) {
  266. u32 id1, id2;
  267. if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
  268. continue;
  269. if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
  270. continue;
  271. lp->ext_phy_id = (id1 << 16) | id2;
  272. lp->ext_phy_addr = i;
  273. break;
  274. }
  275. if (lp->ext_phy_id)
  276. printf("Found MII PHY ID 0x%08x at address 0x%02x\n",
  277. (unsigned int) lp->ext_phy_id, lp->ext_phy_addr);
  278. else
  279. printf("Couldn't detect MII PHY, assuming address 0x01\n");
  280. }
  281. static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
  282. {
  283. void *mmio = lp->mmio;
  284. unsigned int int0;
  285. writel(INTREN, mmio + CMD0);
  286. writel(INTEN0_CLEAR, mmio + INTEN0);
  287. int0 = readl(mmio + INT0);
  288. writel(int0, mmio + INT0);
  289. readl(mmio + INT0);
  290. }
  291. static void amd8111e_enable_interrupt(struct amd8111e_priv *lp)
  292. {
  293. void *mmio = lp->mmio;
  294. writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
  295. writel(VAL0 | INTREN, mmio + CMD0);
  296. readl(mmio + CMD0);
  297. }
  298. static void amd8111e_force_interrupt(struct amd8111e_priv *lp)
  299. {
  300. void *mmio = lp->mmio;
  301. writel(VAL0 | UINTCMD, mmio + CMD0);
  302. readl(mmio + CMD0);
  303. }
  304. static int amd8111e_get_mac_address(struct amd8111e_priv *lp)
  305. {
  306. struct nic *nic = lp->nic;
  307. void *mmio = lp->mmio;
  308. int i;
  309. /* BIOS should have set mac address to PADR register,
  310. * so we read PADR to get it.
  311. */
  312. for (i = 0; i < ETH_ALEN; i++)
  313. nic->node_addr[i] = readb(mmio + PADR + i);
  314. DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) );
  315. return 0;
  316. }
  317. static int amd8111e_init_rx_ring(struct amd8111e_priv *lp)
  318. {
  319. int i;
  320. lp->rx_idx = 0;
  321. /* Initilaizing receive descriptors */
  322. for (i = 0; i < NUM_RX_SLOTS; i++) {
  323. lp->rx_ring[i].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[i]));
  324. lp->rx_ring[i].buf_len = cpu_to_le16(RX_BUF_LEN);
  325. wmb();
  326. lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
  327. }
  328. return 0;
  329. }
  330. static int amd8111e_init_tx_ring(struct amd8111e_priv *lp)
  331. {
  332. int i;
  333. lp->tx_idx = 0;
  334. lp->tx_consistent = 1;
  335. /* Initializing transmit descriptors */
  336. for (i = 0; i < NUM_TX_SLOTS; i++) {
  337. lp->tx_ring[i].tx_flags = 0;
  338. lp->tx_ring[i].buf_phy_addr = 0;
  339. lp->tx_ring[i].buf_len = 0;
  340. }
  341. return 0;
  342. }
  343. static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index)
  344. {
  345. volatile u16 status;
  346. int retry = TX_RETRY;
  347. status = le16_to_cpu(lp->tx_ring[index].tx_flags);
  348. while (--retry && (status & OWN_BIT)) {
  349. mdelay(TX_PROCESS_TIME);
  350. status = le16_to_cpu(lp->tx_ring[index].tx_flags);
  351. }
  352. if (status & OWN_BIT) {
  353. printf("Error: tx slot %d timeout, stat = 0x%x\n", index, status);
  354. amd8111e_restart(lp);
  355. return -1;
  356. }
  357. return 0;
  358. }
  359. static void amd8111e_wait_link(struct amd8111e_priv *lp)
  360. {
  361. unsigned int status;
  362. u32 reg_val;
  363. do {
  364. /* read phy to update STAT0 register */
  365. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
  366. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
  367. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
  368. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
  369. status = readl(lp->mmio + STAT0);
  370. } while (!(status & AUTONEG_COMPLETE) || !(status & LINK_STATS));
  371. }
  372. static void amd8111e_poll_link(struct amd8111e_priv *lp)
  373. {
  374. unsigned int status, speed;
  375. u32 reg_val;
  376. if (!lp->link) {
  377. /* read phy to update STAT0 register */
  378. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
  379. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
  380. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
  381. amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
  382. status = readl(lp->mmio + STAT0);
  383. if (status & LINK_STATS) {
  384. lp->link = 1;
  385. speed = (status & SPEED_MASK) >> 7;
  386. if (speed == PHY_SPEED_100)
  387. lp->speed = 1;
  388. else
  389. lp->speed = 0;
  390. if (status & FULL_DPLX)
  391. lp->duplex = 1;
  392. else
  393. lp->duplex = 0;
  394. printf("Link is up: %s Mbps %s duplex\n",
  395. lp->speed ? "100" : "10", lp->duplex ? "full" : "half");
  396. }
  397. } else {
  398. status = readl(lp->mmio + STAT0);
  399. if (!(status & LINK_STATS)) {
  400. lp->link = 0;
  401. printf("Link is down\n");
  402. }
  403. }
  404. }
  405. static void amd8111e_restart(struct amd8111e_priv *lp)
  406. {
  407. printf("\nStarting nic...\n");
  408. amd8111e_disable_interrupt(lp);
  409. amd8111e_init_hw_default(lp);
  410. amd8111e_probe_ext_phy(lp);
  411. amd8111e_get_mac_address(lp);
  412. amd8111e_start(lp);
  413. printf("Waiting link up...\n");
  414. lp->link = 0;
  415. amd8111e_wait_link(lp);
  416. amd8111e_poll_link(lp);
  417. }
  418. /********************************************************
  419. * Interface Functions *
  420. ********************************************************/
  421. static void amd8111e_transmit(struct nic *nic, const char *dst_addr,
  422. unsigned int type, unsigned int size, const char *packet)
  423. {
  424. struct amd8111e_priv *lp = nic->priv_data;
  425. struct eth_frame *frame;
  426. unsigned int index;
  427. /* check packet size */
  428. if (size > TX_PKT_LEN_MAX) {
  429. printf("amd8111e_transmit(): too large packet, drop\n");
  430. return;
  431. }
  432. /* get tx slot */
  433. index = lp->tx_idx;
  434. if (amd8111e_wait_tx_ring(lp, index))
  435. return;
  436. /* fill frame */
  437. frame = (struct eth_frame *)lp->tx_buf[index];
  438. memset(frame->data, 0, TX_PKT_LEN_MAX);
  439. memcpy(frame->dst_addr, dst_addr, ETH_ALEN);
  440. memcpy(frame->src_addr, nic->node_addr, ETH_ALEN);
  441. frame->type = htons(type);
  442. memcpy(frame->data, packet, size);
  443. /* start xmit */
  444. lp->tx_ring[index].buf_len = cpu_to_le16(ETH_HLEN + size);
  445. lp->tx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(frame));
  446. wmb();
  447. lp->tx_ring[index].tx_flags =
  448. cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT | ADD_FCS_BIT | LTINT_BIT);
  449. writel(VAL1 | TDMD0, lp->mmio + CMD0);
  450. readl(lp->mmio + CMD0);
  451. /* update slot pointer */
  452. lp->tx_idx = (lp->tx_idx + 1) & TX_SLOTS_MASK;
  453. }
  454. static int amd8111e_poll(struct nic *nic, int retrieve)
  455. {
  456. /* return true if there's an ethernet packet ready to read */
  457. /* nic->packet should contain data on return */
  458. /* nic->packetlen should contain length of data */
  459. struct amd8111e_priv *lp = nic->priv_data;
  460. u16 status, pkt_len;
  461. unsigned int index, pkt_ok;
  462. amd8111e_poll_link(lp);
  463. index = lp->rx_idx;
  464. status = le16_to_cpu(lp->rx_ring[index].rx_flags);
  465. pkt_len = le16_to_cpu(lp->rx_ring[index].msg_len) - 4; /* remove 4bytes FCS */
  466. if (status & OWN_BIT)
  467. return 0;
  468. if (status & ERR_BIT)
  469. pkt_ok = 0;
  470. else if (!(status & STP_BIT))
  471. pkt_ok = 0;
  472. else if (!(status & ENP_BIT))
  473. pkt_ok = 0;
  474. else if (pkt_len < RX_PKT_LEN_MIN)
  475. pkt_ok = 0;
  476. else if (pkt_len > RX_PKT_LEN_MAX)
  477. pkt_ok = 0;
  478. else
  479. pkt_ok = 1;
  480. if (pkt_ok) {
  481. if (!retrieve)
  482. return 1;
  483. nic->packetlen = pkt_len;
  484. memcpy(nic->packet, lp->rx_buf[index], nic->packetlen);
  485. }
  486. lp->rx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[index]));
  487. lp->rx_ring[index].buf_len = cpu_to_le16(RX_BUF_LEN);
  488. wmb();
  489. lp->rx_ring[index].rx_flags = cpu_to_le16(OWN_BIT);
  490. writel(VAL2 | RDMD0, lp->mmio + CMD0);
  491. readl(lp->mmio + CMD0);
  492. lp->rx_idx = (lp->rx_idx + 1) & RX_SLOTS_MASK;
  493. return pkt_ok;
  494. }
  495. static void amd8111e_disable(struct nic *nic)
  496. {
  497. struct amd8111e_priv *lp = nic->priv_data;
  498. /* disable interrupt */
  499. amd8111e_disable_interrupt(lp);
  500. /* stop chip */
  501. amd8111e_init_hw_default(lp);
  502. /* unmap mmio */
  503. iounmap(lp->mmio);
  504. /* update status */
  505. lp->opened = 0;
  506. }
  507. static void amd8111e_irq(struct nic *nic, irq_action_t action)
  508. {
  509. struct amd8111e_priv *lp = nic->priv_data;
  510. switch (action) {
  511. case DISABLE:
  512. amd8111e_disable_interrupt(lp);
  513. break;
  514. case ENABLE:
  515. amd8111e_enable_interrupt(lp);
  516. break;
  517. case FORCE:
  518. amd8111e_force_interrupt(lp);
  519. break;
  520. }
  521. }
  522. static struct nic_operations amd8111e_operations = {
  523. .connect = dummy_connect,
  524. .poll = amd8111e_poll,
  525. .transmit = amd8111e_transmit,
  526. .irq = amd8111e_irq,
  527. };
  528. static int amd8111e_probe(struct nic *nic, struct pci_device *pdev)
  529. {
  530. struct amd8111e_priv *lp = &amd8111e;
  531. unsigned long mmio_start, mmio_len;
  532. nic->ioaddr = pdev->ioaddr;
  533. nic->irqno = pdev->irq;
  534. mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
  535. mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_0);
  536. memset(lp, 0, sizeof(*lp));
  537. lp->pdev = pdev;
  538. lp->nic = nic;
  539. lp->mmio = ioremap(mmio_start, mmio_len);
  540. lp->opened = 1;
  541. adjust_pci_device(pdev);
  542. nic->priv_data = lp;
  543. amd8111e_restart(lp);
  544. nic->nic_op = &amd8111e_operations;
  545. return 1;
  546. }
  547. static struct pci_device_id amd8111e_nics[] = {
  548. PCI_ROM(0x1022, 0x7462, "amd8111e", "AMD8111E"),
  549. };
  550. PCI_DRIVER ( amd8111e_driver, amd8111e_nics, PCI_NO_CLASS );
  551. DRIVER ( "AMD8111E", nic_driver, pci_driver, amd8111e_driver,
  552. amd8111e_probe, amd8111e_disable );
  553. /*
  554. * Local variables:
  555. * c-basic-offset: 8
  556. * c-indent-level: 8
  557. * tab-width: 8
  558. * End:
  559. */