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xhci.c 86KB

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  1. /*
  2. * Copyright (C) 2014 Michael Brown <mbrown@fensystems.co.uk>.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of the
  7. * License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12. * General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  17. * 02110-1301, USA.
  18. *
  19. * You can also choose to distribute this program under the terms of
  20. * the Unmodified Binary Distribution Licence (as given in the file
  21. * COPYING.UBDL), provided that you have satisfied its requirements.
  22. */
  23. FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
  24. #include <stdlib.h>
  25. #include <stdio.h>
  26. #include <unistd.h>
  27. #include <string.h>
  28. #include <strings.h>
  29. #include <errno.h>
  30. #include <byteswap.h>
  31. #include <ipxe/malloc.h>
  32. #include <ipxe/umalloc.h>
  33. #include <ipxe/pci.h>
  34. #include <ipxe/usb.h>
  35. #include <ipxe/init.h>
  36. #include <ipxe/profile.h>
  37. #include "xhci.h"
  38. /** @file
  39. *
  40. * USB eXtensible Host Controller Interface (xHCI) driver
  41. *
  42. */
  43. /** Message transfer profiler */
  44. static struct profiler xhci_message_profiler __profiler =
  45. { .name = "xhci.message" };
  46. /** Stream transfer profiler */
  47. static struct profiler xhci_stream_profiler __profiler =
  48. { .name = "xhci.stream" };
  49. /** Event ring profiler */
  50. static struct profiler xhci_event_profiler __profiler =
  51. { .name = "xhci.event" };
  52. /** Transfer event profiler */
  53. static struct profiler xhci_transfer_profiler __profiler =
  54. { .name = "xhci.transfer" };
  55. /* Disambiguate the various error causes */
  56. #define EIO_DATA \
  57. __einfo_error ( EINFO_EIO_DATA )
  58. #define EINFO_EIO_DATA \
  59. __einfo_uniqify ( EINFO_EIO, ( 2 - 0 ), \
  60. "Data buffer error" )
  61. #define EIO_BABBLE \
  62. __einfo_error ( EINFO_EIO_BABBLE )
  63. #define EINFO_EIO_BABBLE \
  64. __einfo_uniqify ( EINFO_EIO, ( 3 - 0 ), \
  65. "Babble detected" )
  66. #define EIO_USB \
  67. __einfo_error ( EINFO_EIO_USB )
  68. #define EINFO_EIO_USB \
  69. __einfo_uniqify ( EINFO_EIO, ( 4 - 0 ), \
  70. "USB transaction error" )
  71. #define EIO_TRB \
  72. __einfo_error ( EINFO_EIO_TRB )
  73. #define EINFO_EIO_TRB \
  74. __einfo_uniqify ( EINFO_EIO, ( 5 - 0 ), \
  75. "TRB error" )
  76. #define EIO_STALL \
  77. __einfo_error ( EINFO_EIO_STALL )
  78. #define EINFO_EIO_STALL \
  79. __einfo_uniqify ( EINFO_EIO, ( 6 - 0 ), \
  80. "Stall error" )
  81. #define EIO_RESOURCE \
  82. __einfo_error ( EINFO_EIO_RESOURCE )
  83. #define EINFO_EIO_RESOURCE \
  84. __einfo_uniqify ( EINFO_EIO, ( 7 - 0 ), \
  85. "Resource error" )
  86. #define EIO_BANDWIDTH \
  87. __einfo_error ( EINFO_EIO_BANDWIDTH )
  88. #define EINFO_EIO_BANDWIDTH \
  89. __einfo_uniqify ( EINFO_EIO, ( 8 - 0 ), \
  90. "Bandwidth error" )
  91. #define EIO_NO_SLOTS \
  92. __einfo_error ( EINFO_EIO_NO_SLOTS )
  93. #define EINFO_EIO_NO_SLOTS \
  94. __einfo_uniqify ( EINFO_EIO, ( 9 - 0 ), \
  95. "No slots available" )
  96. #define EIO_STREAM_TYPE \
  97. __einfo_error ( EINFO_EIO_STREAM_TYPE )
  98. #define EINFO_EIO_STREAM_TYPE \
  99. __einfo_uniqify ( EINFO_EIO, ( 10 - 0 ), \
  100. "Invalid stream type" )
  101. #define EIO_SLOT \
  102. __einfo_error ( EINFO_EIO_SLOT )
  103. #define EINFO_EIO_SLOT \
  104. __einfo_uniqify ( EINFO_EIO, ( 11 - 0 ), \
  105. "Slot not enabled" )
  106. #define EIO_ENDPOINT \
  107. __einfo_error ( EINFO_EIO_ENDPOINT )
  108. #define EINFO_EIO_ENDPOINT \
  109. __einfo_uniqify ( EINFO_EIO, ( 12 - 0 ), \
  110. "Endpoint not enabled" )
  111. #define EIO_SHORT \
  112. __einfo_error ( EINFO_EIO_SHORT )
  113. #define EINFO_EIO_SHORT \
  114. __einfo_uniqify ( EINFO_EIO, ( 13 - 0 ), \
  115. "Short packet" )
  116. #define EIO_UNDERRUN \
  117. __einfo_error ( EINFO_EIO_UNDERRUN )
  118. #define EINFO_EIO_UNDERRUN \
  119. __einfo_uniqify ( EINFO_EIO, ( 14 - 0 ), \
  120. "Ring underrun" )
  121. #define EIO_OVERRUN \
  122. __einfo_error ( EINFO_EIO_OVERRUN )
  123. #define EINFO_EIO_OVERRUN \
  124. __einfo_uniqify ( EINFO_EIO, ( 15 - 0 ), \
  125. "Ring overrun" )
  126. #define EIO_VF_RING_FULL \
  127. __einfo_error ( EINFO_EIO_VF_RING_FULL )
  128. #define EINFO_EIO_VF_RING_FULL \
  129. __einfo_uniqify ( EINFO_EIO, ( 16 - 0 ), \
  130. "Virtual function event ring full" )
  131. #define EIO_PARAMETER \
  132. __einfo_error ( EINFO_EIO_PARAMETER )
  133. #define EINFO_EIO_PARAMETER \
  134. __einfo_uniqify ( EINFO_EIO, ( 17 - 0 ), \
  135. "Parameter error" )
  136. #define EIO_BANDWIDTH_OVERRUN \
  137. __einfo_error ( EINFO_EIO_BANDWIDTH_OVERRUN )
  138. #define EINFO_EIO_BANDWIDTH_OVERRUN \
  139. __einfo_uniqify ( EINFO_EIO, ( 18 - 0 ), \
  140. "Bandwidth overrun" )
  141. #define EIO_CONTEXT \
  142. __einfo_error ( EINFO_EIO_CONTEXT )
  143. #define EINFO_EIO_CONTEXT \
  144. __einfo_uniqify ( EINFO_EIO, ( 19 - 0 ), \
  145. "Context state error" )
  146. #define EIO_NO_PING \
  147. __einfo_error ( EINFO_EIO_NO_PING )
  148. #define EINFO_EIO_NO_PING \
  149. __einfo_uniqify ( EINFO_EIO, ( 20 - 0 ), \
  150. "No ping response" )
  151. #define EIO_RING_FULL \
  152. __einfo_error ( EINFO_EIO_RING_FULL )
  153. #define EINFO_EIO_RING_FULL \
  154. __einfo_uniqify ( EINFO_EIO, ( 21 - 0 ), \
  155. "Event ring full" )
  156. #define EIO_INCOMPATIBLE \
  157. __einfo_error ( EINFO_EIO_INCOMPATIBLE )
  158. #define EINFO_EIO_INCOMPATIBLE \
  159. __einfo_uniqify ( EINFO_EIO, ( 22 - 0 ), \
  160. "Incompatible device" )
  161. #define EIO_MISSED \
  162. __einfo_error ( EINFO_EIO_MISSED )
  163. #define EINFO_EIO_MISSED \
  164. __einfo_uniqify ( EINFO_EIO, ( 23 - 0 ), \
  165. "Missed service error" )
  166. #define EIO_CMD_STOPPED \
  167. __einfo_error ( EINFO_EIO_CMD_STOPPED )
  168. #define EINFO_EIO_CMD_STOPPED \
  169. __einfo_uniqify ( EINFO_EIO, ( 24 - 0 ), \
  170. "Command ring stopped" )
  171. #define EIO_CMD_ABORTED \
  172. __einfo_error ( EINFO_EIO_CMD_ABORTED )
  173. #define EINFO_EIO_CMD_ABORTED \
  174. __einfo_uniqify ( EINFO_EIO, ( 25 - 0 ), \
  175. "Command aborted" )
  176. #define EIO_STOP \
  177. __einfo_error ( EINFO_EIO_STOP )
  178. #define EINFO_EIO_STOP \
  179. __einfo_uniqify ( EINFO_EIO, ( 26 - 0 ), \
  180. "Stopped" )
  181. #define EIO_STOP_LEN \
  182. __einfo_error ( EINFO_EIO_STOP_LEN )
  183. #define EINFO_EIO_STOP_LEN \
  184. __einfo_uniqify ( EINFO_EIO, ( 27 - 0 ), \
  185. "Stopped - length invalid" )
  186. #define EIO_STOP_SHORT \
  187. __einfo_error ( EINFO_EIO_STOP_SHORT )
  188. #define EINFO_EIO_STOP_SHORT \
  189. __einfo_uniqify ( EINFO_EIO, ( 28 - 0 ), \
  190. "Stopped - short packet" )
  191. #define EIO_LATENCY \
  192. __einfo_error ( EINFO_EIO_LATENCY )
  193. #define EINFO_EIO_LATENCY \
  194. __einfo_uniqify ( EINFO_EIO, ( 29 - 0 ), \
  195. "Maximum exit latency too large" )
  196. #define EIO_ISOCH \
  197. __einfo_error ( EINFO_EIO_ISOCH )
  198. #define EINFO_EIO_ISOCH \
  199. __einfo_uniqify ( EINFO_EIO, ( 31 - 0 ), \
  200. "Isochronous buffer overrun" )
  201. #define EPROTO_LOST \
  202. __einfo_error ( EINFO_EPROTO_LOST )
  203. #define EINFO_EPROTO_LOST \
  204. __einfo_uniqify ( EINFO_EPROTO, ( 32 - 32 ), \
  205. "Event lost" )
  206. #define EPROTO_UNDEFINED \
  207. __einfo_error ( EINFO_EPROTO_UNDEFINED )
  208. #define EINFO_EPROTO_UNDEFINED \
  209. __einfo_uniqify ( EINFO_EPROTO, ( 33 - 32 ), \
  210. "Undefined error" )
  211. #define EPROTO_STREAM_ID \
  212. __einfo_error ( EINFO_EPROTO_STREAM_ID )
  213. #define EINFO_EPROTO_STREAM_ID \
  214. __einfo_uniqify ( EINFO_EPROTO, ( 34 - 32 ), \
  215. "Invalid stream ID" )
  216. #define EPROTO_SECONDARY \
  217. __einfo_error ( EINFO_EPROTO_SECONDARY )
  218. #define EINFO_EPROTO_SECONDARY \
  219. __einfo_uniqify ( EINFO_EPROTO, ( 35 - 32 ), \
  220. "Secondary bandwidth error" )
  221. #define EPROTO_SPLIT \
  222. __einfo_error ( EINFO_EPROTO_SPLIT )
  223. #define EINFO_EPROTO_SPLIT \
  224. __einfo_uniqify ( EINFO_EPROTO, ( 36 - 32 ), \
  225. "Split transaction error" )
  226. #define ECODE(code) \
  227. ( ( (code) < 32 ) ? \
  228. EUNIQ ( EINFO_EIO, ( (code) & 31 ), EIO_DATA, EIO_BABBLE, \
  229. EIO_USB, EIO_TRB, EIO_STALL, EIO_RESOURCE, \
  230. EIO_BANDWIDTH, EIO_NO_SLOTS, EIO_STREAM_TYPE, \
  231. EIO_SLOT, EIO_ENDPOINT, EIO_SHORT, EIO_UNDERRUN, \
  232. EIO_OVERRUN, EIO_VF_RING_FULL, EIO_PARAMETER, \
  233. EIO_BANDWIDTH_OVERRUN, EIO_CONTEXT, EIO_NO_PING, \
  234. EIO_RING_FULL, EIO_INCOMPATIBLE, EIO_MISSED, \
  235. EIO_CMD_STOPPED, EIO_CMD_ABORTED, EIO_STOP, \
  236. EIO_STOP_LEN, EIO_STOP_SHORT, EIO_LATENCY, \
  237. EIO_ISOCH ) : \
  238. ( (code) < 64 ) ? \
  239. EUNIQ ( EINFO_EPROTO, ( (code) & 31 ), EPROTO_LOST, \
  240. EPROTO_UNDEFINED, EPROTO_STREAM_ID, \
  241. EPROTO_SECONDARY, EPROTO_SPLIT ) : \
  242. EFAULT )
  243. /******************************************************************************
  244. *
  245. * Register access
  246. *
  247. ******************************************************************************
  248. */
  249. /**
  250. * Initialise device
  251. *
  252. * @v xhci xHCI device
  253. * @v regs MMIO registers
  254. */
  255. static void xhci_init ( struct xhci_device *xhci, void *regs ) {
  256. uint32_t hcsparams1;
  257. uint32_t hcsparams2;
  258. uint32_t hccparams1;
  259. uint32_t pagesize;
  260. size_t caplength;
  261. size_t rtsoff;
  262. size_t dboff;
  263. /* Locate capability, operational, runtime, and doorbell registers */
  264. xhci->cap = regs;
  265. caplength = readb ( xhci->cap + XHCI_CAP_CAPLENGTH );
  266. rtsoff = readl ( xhci->cap + XHCI_CAP_RTSOFF );
  267. dboff = readl ( xhci->cap + XHCI_CAP_DBOFF );
  268. xhci->op = ( xhci->cap + caplength );
  269. xhci->run = ( xhci->cap + rtsoff );
  270. xhci->db = ( xhci->cap + dboff );
  271. DBGC2 ( xhci, "XHCI %s cap %08lx op %08lx run %08lx db %08lx\n",
  272. xhci->name, virt_to_phys ( xhci->cap ),
  273. virt_to_phys ( xhci->op ), virt_to_phys ( xhci->run ),
  274. virt_to_phys ( xhci->db ) );
  275. /* Read structural parameters 1 */
  276. hcsparams1 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS1 );
  277. xhci->slots = XHCI_HCSPARAMS1_SLOTS ( hcsparams1 );
  278. xhci->intrs = XHCI_HCSPARAMS1_INTRS ( hcsparams1 );
  279. xhci->ports = XHCI_HCSPARAMS1_PORTS ( hcsparams1 );
  280. DBGC ( xhci, "XHCI %s has %d slots %d intrs %d ports\n",
  281. xhci->name, xhci->slots, xhci->intrs, xhci->ports );
  282. /* Read structural parameters 2 */
  283. hcsparams2 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS2 );
  284. xhci->scratchpads = XHCI_HCSPARAMS2_SCRATCHPADS ( hcsparams2 );
  285. DBGC2 ( xhci, "XHCI %s needs %d scratchpads\n",
  286. xhci->name, xhci->scratchpads );
  287. /* Read capability parameters 1 */
  288. hccparams1 = readl ( xhci->cap + XHCI_CAP_HCCPARAMS1 );
  289. xhci->addr64 = XHCI_HCCPARAMS1_ADDR64 ( hccparams1 );
  290. xhci->csz_shift = XHCI_HCCPARAMS1_CSZ_SHIFT ( hccparams1 );
  291. xhci->xecp = XHCI_HCCPARAMS1_XECP ( hccparams1 );
  292. /* Read page size */
  293. pagesize = readl ( xhci->op + XHCI_OP_PAGESIZE );
  294. xhci->pagesize = XHCI_PAGESIZE ( pagesize );
  295. assert ( xhci->pagesize != 0 );
  296. assert ( ( ( xhci->pagesize ) & ( xhci->pagesize - 1 ) ) == 0 );
  297. DBGC2 ( xhci, "XHCI %s page size %zd bytes\n",
  298. xhci->name, xhci->pagesize );
  299. }
  300. /**
  301. * Find extended capability
  302. *
  303. * @v xhci xHCI device
  304. * @v id Capability ID
  305. * @v offset Offset to previous extended capability instance, or zero
  306. * @ret offset Offset to extended capability, or zero if not found
  307. */
  308. static unsigned int xhci_extended_capability ( struct xhci_device *xhci,
  309. unsigned int id,
  310. unsigned int offset ) {
  311. uint32_t xecp;
  312. unsigned int next;
  313. /* Locate the extended capability */
  314. while ( 1 ) {
  315. /* Locate first or next capability as applicable */
  316. if ( offset ) {
  317. xecp = readl ( xhci->cap + offset );
  318. next = XHCI_XECP_NEXT ( xecp );
  319. } else {
  320. next = xhci->xecp;
  321. }
  322. if ( ! next )
  323. return 0;
  324. offset += next;
  325. /* Check if this is the requested capability */
  326. xecp = readl ( xhci->cap + offset );
  327. if ( XHCI_XECP_ID ( xecp ) == id )
  328. return offset;
  329. }
  330. }
  331. /**
  332. * Write potentially 64-bit register
  333. *
  334. * @v xhci xHCI device
  335. * @v value Value
  336. * @v reg Register address
  337. * @ret rc Return status code
  338. */
  339. static inline __attribute__ (( always_inline )) int
  340. xhci_writeq ( struct xhci_device *xhci, physaddr_t value, void *reg ) {
  341. /* If this is a 32-bit build, then this can never fail
  342. * (allowing the compiler to optimise out the error path).
  343. */
  344. if ( sizeof ( value ) <= sizeof ( uint32_t ) ) {
  345. writel ( value, reg );
  346. writel ( 0, ( reg + sizeof ( uint32_t ) ) );
  347. return 0;
  348. }
  349. /* If the device does not support 64-bit addresses and this
  350. * address is outside the 32-bit address space, then fail.
  351. */
  352. if ( ( value & ~0xffffffffULL ) && ! xhci->addr64 ) {
  353. DBGC ( xhci, "XHCI %s cannot access address %lx\n",
  354. xhci->name, value );
  355. return -ENOTSUP;
  356. }
  357. /* If this is a 64-bit build, then writeq() is available */
  358. writeq ( value, reg );
  359. return 0;
  360. }
  361. /**
  362. * Calculate buffer alignment
  363. *
  364. * @v len Length
  365. * @ret align Buffer alignment
  366. *
  367. * Determine alignment required for a buffer which must be aligned to
  368. * at least XHCI_MIN_ALIGN and which must not cross a page boundary.
  369. */
  370. static inline size_t xhci_align ( size_t len ) {
  371. size_t align;
  372. /* Align to own length (rounded up to a power of two) */
  373. align = ( 1 << fls ( len - 1 ) );
  374. /* Round up to XHCI_MIN_ALIGN if needed */
  375. if ( align < XHCI_MIN_ALIGN )
  376. align = XHCI_MIN_ALIGN;
  377. return align;
  378. }
  379. /**
  380. * Calculate device context offset
  381. *
  382. * @v xhci xHCI device
  383. * @v ctx Context index
  384. */
  385. static inline size_t xhci_device_context_offset ( struct xhci_device *xhci,
  386. unsigned int ctx ) {
  387. return ( XHCI_DCI ( ctx ) << xhci->csz_shift );
  388. }
  389. /**
  390. * Calculate input context offset
  391. *
  392. * @v xhci xHCI device
  393. * @v ctx Context index
  394. */
  395. static inline size_t xhci_input_context_offset ( struct xhci_device *xhci,
  396. unsigned int ctx ) {
  397. return ( XHCI_ICI ( ctx ) << xhci->csz_shift );
  398. }
  399. /******************************************************************************
  400. *
  401. * Diagnostics
  402. *
  403. ******************************************************************************
  404. */
  405. /**
  406. * Dump host controller registers
  407. *
  408. * @v xhci xHCI device
  409. */
  410. static inline void xhci_dump ( struct xhci_device *xhci ) {
  411. uint32_t usbcmd;
  412. uint32_t usbsts;
  413. uint32_t pagesize;
  414. uint32_t dnctrl;
  415. uint32_t config;
  416. /* Do nothing unless debugging is enabled */
  417. if ( ! DBG_LOG )
  418. return;
  419. /* Dump USBCMD */
  420. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  421. DBGC ( xhci, "XHCI %s USBCMD %08x%s%s\n", xhci->name, usbcmd,
  422. ( ( usbcmd & XHCI_USBCMD_RUN ) ? " run" : "" ),
  423. ( ( usbcmd & XHCI_USBCMD_HCRST ) ? " hcrst" : "" ) );
  424. /* Dump USBSTS */
  425. usbsts = readl ( xhci->op + XHCI_OP_USBSTS );
  426. DBGC ( xhci, "XHCI %s USBSTS %08x%s\n", xhci->name, usbsts,
  427. ( ( usbsts & XHCI_USBSTS_HCH ) ? " hch" : "" ) );
  428. /* Dump PAGESIZE */
  429. pagesize = readl ( xhci->op + XHCI_OP_PAGESIZE );
  430. DBGC ( xhci, "XHCI %s PAGESIZE %08x\n", xhci->name, pagesize );
  431. /* Dump DNCTRL */
  432. dnctrl = readl ( xhci->op + XHCI_OP_DNCTRL );
  433. DBGC ( xhci, "XHCI %s DNCTRL %08x\n", xhci->name, dnctrl );
  434. /* Dump CONFIG */
  435. config = readl ( xhci->op + XHCI_OP_CONFIG );
  436. DBGC ( xhci, "XHCI %s CONFIG %08x\n", xhci->name, config );
  437. }
  438. /**
  439. * Dump port registers
  440. *
  441. * @v xhci xHCI device
  442. * @v port Port number
  443. */
  444. static inline void xhci_dump_port ( struct xhci_device *xhci,
  445. unsigned int port ) {
  446. uint32_t portsc;
  447. uint32_t portpmsc;
  448. uint32_t portli;
  449. uint32_t porthlpmc;
  450. /* Do nothing unless debugging is enabled */
  451. if ( ! DBG_LOG )
  452. return;
  453. /* Dump PORTSC */
  454. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) );
  455. DBGC ( xhci, "XHCI %s-%d PORTSC %08x%s%s%s%s psiv=%d\n",
  456. xhci->name, port, portsc,
  457. ( ( portsc & XHCI_PORTSC_CCS ) ? " ccs" : "" ),
  458. ( ( portsc & XHCI_PORTSC_PED ) ? " ped" : "" ),
  459. ( ( portsc & XHCI_PORTSC_PR ) ? " pr" : "" ),
  460. ( ( portsc & XHCI_PORTSC_PP ) ? " pp" : "" ),
  461. XHCI_PORTSC_PSIV ( portsc ) );
  462. /* Dump PORTPMSC */
  463. portpmsc = readl ( xhci->op + XHCI_OP_PORTPMSC ( port ) );
  464. DBGC ( xhci, "XHCI %s-%d PORTPMSC %08x\n", xhci->name, port, portpmsc );
  465. /* Dump PORTLI */
  466. portli = readl ( xhci->op + XHCI_OP_PORTLI ( port ) );
  467. DBGC ( xhci, "XHCI %s-%d PORTLI %08x\n", xhci->name, port, portli );
  468. /* Dump PORTHLPMC */
  469. porthlpmc = readl ( xhci->op + XHCI_OP_PORTHLPMC ( port ) );
  470. DBGC ( xhci, "XHCI %s-%d PORTHLPMC %08x\n",
  471. xhci->name, port, porthlpmc );
  472. }
  473. /******************************************************************************
  474. *
  475. * USB legacy support
  476. *
  477. ******************************************************************************
  478. */
  479. /** Prevent the release of ownership back to BIOS */
  480. static int xhci_legacy_prevent_release;
  481. /**
  482. * Initialise USB legacy support
  483. *
  484. * @v xhci xHCI device
  485. */
  486. static void xhci_legacy_init ( struct xhci_device *xhci ) {
  487. unsigned int legacy;
  488. uint8_t bios;
  489. /* Locate USB legacy support capability (if present) */
  490. legacy = xhci_extended_capability ( xhci, XHCI_XECP_ID_LEGACY, 0 );
  491. if ( ! legacy ) {
  492. /* Not an error; capability may not be present */
  493. DBGC ( xhci, "XHCI %s has no USB legacy support capability\n",
  494. xhci->name );
  495. return;
  496. }
  497. /* Check if legacy USB support is enabled */
  498. bios = readb ( xhci->cap + legacy + XHCI_USBLEGSUP_BIOS );
  499. if ( ! ( bios & XHCI_USBLEGSUP_BIOS_OWNED ) ) {
  500. /* Not an error; already owned by OS */
  501. DBGC ( xhci, "XHCI %s USB legacy support already disabled\n",
  502. xhci->name );
  503. return;
  504. }
  505. /* Record presence of USB legacy support capability */
  506. xhci->legacy = legacy;
  507. }
  508. /**
  509. * Claim ownership from BIOS
  510. *
  511. * @v xhci xHCI device
  512. */
  513. static void xhci_legacy_claim ( struct xhci_device *xhci ) {
  514. uint32_t ctlsts;
  515. uint8_t bios;
  516. unsigned int i;
  517. /* Do nothing unless legacy support capability is present */
  518. if ( ! xhci->legacy )
  519. return;
  520. /* Claim ownership */
  521. writeb ( XHCI_USBLEGSUP_OS_OWNED,
  522. xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS );
  523. /* Wait for BIOS to release ownership */
  524. for ( i = 0 ; i < XHCI_USBLEGSUP_MAX_WAIT_MS ; i++ ) {
  525. /* Check if BIOS has released ownership */
  526. bios = readb ( xhci->cap + xhci->legacy + XHCI_USBLEGSUP_BIOS );
  527. if ( ! ( bios & XHCI_USBLEGSUP_BIOS_OWNED ) ) {
  528. DBGC ( xhci, "XHCI %s claimed ownership from BIOS\n",
  529. xhci->name );
  530. ctlsts = readl ( xhci->cap + xhci->legacy +
  531. XHCI_USBLEGSUP_CTLSTS );
  532. if ( ctlsts ) {
  533. DBGC ( xhci, "XHCI %s warning: BIOS retained "
  534. "SMIs: %08x\n", xhci->name, ctlsts );
  535. }
  536. return;
  537. }
  538. /* Delay */
  539. mdelay ( 1 );
  540. }
  541. /* BIOS did not release ownership. Claim it forcibly by
  542. * disabling all SMIs.
  543. */
  544. DBGC ( xhci, "XHCI %s could not claim ownership from BIOS: forcibly "
  545. "disabling SMIs\n", xhci->name );
  546. writel ( 0, xhci->cap + xhci->legacy + XHCI_USBLEGSUP_CTLSTS );
  547. }
  548. /**
  549. * Release ownership back to BIOS
  550. *
  551. * @v xhci xHCI device
  552. */
  553. static void xhci_legacy_release ( struct xhci_device *xhci ) {
  554. /* Do nothing unless legacy support capability is present */
  555. if ( ! xhci->legacy )
  556. return;
  557. /* Do nothing if releasing ownership is prevented */
  558. if ( xhci_legacy_prevent_release ) {
  559. DBGC ( xhci, "XHCI %s not releasing ownership to BIOS\n",
  560. xhci->name );
  561. return;
  562. }
  563. /* Release ownership */
  564. writeb ( 0, xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS );
  565. DBGC ( xhci, "XHCI %s released ownership to BIOS\n", xhci->name );
  566. }
  567. /******************************************************************************
  568. *
  569. * Supported protocols
  570. *
  571. ******************************************************************************
  572. */
  573. /**
  574. * Transcribe port speed (for debugging)
  575. *
  576. * @v psi Protocol speed ID
  577. * @ret speed Transcribed speed
  578. */
  579. static inline const char * xhci_speed_name ( uint32_t psi ) {
  580. static const char *exponents[4] = { "", "k", "M", "G" };
  581. static char buf[ 10 /* "xxxxxXbps" + NUL */ ];
  582. unsigned int mantissa;
  583. unsigned int exponent;
  584. /* Extract mantissa and exponent */
  585. mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi );
  586. exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi );
  587. /* Transcribe speed */
  588. snprintf ( buf, sizeof ( buf ), "%d%sbps",
  589. mantissa, exponents[exponent] );
  590. return buf;
  591. }
  592. /**
  593. * Find supported protocol extended capability for a port
  594. *
  595. * @v xhci xHCI device
  596. * @v port Port number
  597. * @ret supported Offset to extended capability, or zero if not found
  598. */
  599. static unsigned int xhci_supported_protocol ( struct xhci_device *xhci,
  600. unsigned int port ) {
  601. unsigned int supported = 0;
  602. unsigned int offset;
  603. unsigned int count;
  604. uint32_t ports;
  605. /* Iterate over all supported protocol structures */
  606. while ( ( supported = xhci_extended_capability ( xhci,
  607. XHCI_XECP_ID_SUPPORTED,
  608. supported ) ) ) {
  609. /* Determine port range */
  610. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  611. offset = XHCI_SUPPORTED_PORTS_OFFSET ( ports );
  612. count = XHCI_SUPPORTED_PORTS_COUNT ( ports );
  613. /* Check if port lies within this range */
  614. if ( ( port - offset ) < count )
  615. return supported;
  616. }
  617. DBGC ( xhci, "XHCI %s-%d has no supported protocol\n",
  618. xhci->name, port );
  619. return 0;
  620. }
  621. /**
  622. * Find port protocol
  623. *
  624. * @v xhci xHCI device
  625. * @v port Port number
  626. * @ret protocol USB protocol, or zero if not found
  627. */
  628. static unsigned int xhci_port_protocol ( struct xhci_device *xhci,
  629. unsigned int port ) {
  630. unsigned int supported = xhci_supported_protocol ( xhci, port );
  631. union {
  632. uint32_t raw;
  633. char text[5];
  634. } name;
  635. unsigned int protocol;
  636. unsigned int type;
  637. unsigned int psic;
  638. unsigned int psiv;
  639. unsigned int i;
  640. uint32_t revision;
  641. uint32_t ports;
  642. uint32_t slot;
  643. uint32_t psi;
  644. /* Fail if there is no supported protocol */
  645. if ( ! supported )
  646. return 0;
  647. /* Determine protocol version */
  648. revision = readl ( xhci->cap + supported + XHCI_SUPPORTED_REVISION );
  649. protocol = XHCI_SUPPORTED_REVISION_VER ( revision );
  650. /* Describe port protocol */
  651. if ( DBG_EXTRA ) {
  652. name.raw = cpu_to_le32 ( readl ( xhci->cap + supported +
  653. XHCI_SUPPORTED_NAME ) );
  654. name.text[4] = '\0';
  655. slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT );
  656. type = XHCI_SUPPORTED_SLOT_TYPE ( slot );
  657. DBGC2 ( xhci, "XHCI %s-%d %sv%04x type %d",
  658. xhci->name, port, name.text, protocol, type );
  659. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  660. psic = XHCI_SUPPORTED_PORTS_PSIC ( ports );
  661. if ( psic ) {
  662. DBGC2 ( xhci, " speeds" );
  663. for ( i = 0 ; i < psic ; i++ ) {
  664. psi = readl ( xhci->cap + supported +
  665. XHCI_SUPPORTED_PSI ( i ) );
  666. psiv = XHCI_SUPPORTED_PSI_VALUE ( psi );
  667. DBGC2 ( xhci, " %d:%s", psiv,
  668. xhci_speed_name ( psi ) );
  669. }
  670. }
  671. if ( xhci->quirks & XHCI_BAD_PSIV )
  672. DBGC2 ( xhci, " (ignored)" );
  673. DBGC2 ( xhci, "\n" );
  674. }
  675. return protocol;
  676. }
  677. /**
  678. * Find port slot type
  679. *
  680. * @v xhci xHCI device
  681. * @v port Port number
  682. * @ret type Slot type, or negative error
  683. */
  684. static int xhci_port_slot_type ( struct xhci_device *xhci, unsigned int port ) {
  685. unsigned int supported = xhci_supported_protocol ( xhci, port );
  686. unsigned int type;
  687. uint32_t slot;
  688. /* Fail if there is no supported protocol */
  689. if ( ! supported )
  690. return -ENOTSUP;
  691. /* Get slot type */
  692. slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT );
  693. type = XHCI_SUPPORTED_SLOT_TYPE ( slot );
  694. return type;
  695. }
  696. /**
  697. * Find port speed
  698. *
  699. * @v xhci xHCI device
  700. * @v port Port number
  701. * @v psiv Protocol speed ID value
  702. * @ret speed Port speed, or negative error
  703. */
  704. static int xhci_port_speed ( struct xhci_device *xhci, unsigned int port,
  705. unsigned int psiv ) {
  706. unsigned int supported = xhci_supported_protocol ( xhci, port );
  707. unsigned int psic;
  708. unsigned int mantissa;
  709. unsigned int exponent;
  710. unsigned int speed;
  711. unsigned int i;
  712. uint32_t ports;
  713. uint32_t psi;
  714. /* Fail if there is no supported protocol */
  715. if ( ! supported )
  716. return -ENOTSUP;
  717. /* Get protocol speed ID count */
  718. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  719. psic = XHCI_SUPPORTED_PORTS_PSIC ( ports );
  720. /* Use the default mappings if applicable */
  721. if ( ( psic == 0 ) || ( xhci->quirks & XHCI_BAD_PSIV ) ) {
  722. switch ( psiv ) {
  723. case XHCI_SPEED_LOW : return USB_SPEED_LOW;
  724. case XHCI_SPEED_FULL : return USB_SPEED_FULL;
  725. case XHCI_SPEED_HIGH : return USB_SPEED_HIGH;
  726. case XHCI_SPEED_SUPER : return USB_SPEED_SUPER;
  727. default:
  728. DBGC ( xhci, "XHCI %s-%d non-standard PSI value %d\n",
  729. xhci->name, port, psiv );
  730. return -ENOTSUP;
  731. }
  732. }
  733. /* Iterate over PSI dwords looking for a match */
  734. for ( i = 0 ; i < psic ; i++ ) {
  735. psi = readl ( xhci->cap + supported + XHCI_SUPPORTED_PSI ( i ));
  736. if ( psiv == XHCI_SUPPORTED_PSI_VALUE ( psi ) ) {
  737. mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi );
  738. exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi );
  739. speed = USB_SPEED ( mantissa, exponent );
  740. return speed;
  741. }
  742. }
  743. DBGC ( xhci, "XHCI %s-%d spurious PSI value %d\n",
  744. xhci->name, port, psiv );
  745. return -ENOENT;
  746. }
  747. /**
  748. * Find protocol speed ID value
  749. *
  750. * @v xhci xHCI device
  751. * @v port Port number
  752. * @v speed USB speed
  753. * @ret psiv Protocol speed ID value, or negative error
  754. */
  755. static int xhci_port_psiv ( struct xhci_device *xhci, unsigned int port,
  756. unsigned int speed ) {
  757. unsigned int supported = xhci_supported_protocol ( xhci, port );
  758. unsigned int psic;
  759. unsigned int mantissa;
  760. unsigned int exponent;
  761. unsigned int psiv;
  762. unsigned int i;
  763. uint32_t ports;
  764. uint32_t psi;
  765. /* Fail if there is no supported protocol */
  766. if ( ! supported )
  767. return -ENOTSUP;
  768. /* Get protocol speed ID count */
  769. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  770. psic = XHCI_SUPPORTED_PORTS_PSIC ( ports );
  771. /* Use the default mappings if applicable */
  772. if ( ( psic == 0 ) || ( xhci->quirks & XHCI_BAD_PSIV ) ) {
  773. switch ( speed ) {
  774. case USB_SPEED_LOW : return XHCI_SPEED_LOW;
  775. case USB_SPEED_FULL : return XHCI_SPEED_FULL;
  776. case USB_SPEED_HIGH : return XHCI_SPEED_HIGH;
  777. case USB_SPEED_SUPER : return XHCI_SPEED_SUPER;
  778. default:
  779. DBGC ( xhci, "XHCI %s-%d non-standard speed %d\n",
  780. xhci->name, port, speed );
  781. return -ENOTSUP;
  782. }
  783. }
  784. /* Iterate over PSI dwords looking for a match */
  785. for ( i = 0 ; i < psic ; i++ ) {
  786. psi = readl ( xhci->cap + supported + XHCI_SUPPORTED_PSI ( i ));
  787. mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi );
  788. exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi );
  789. if ( speed == USB_SPEED ( mantissa, exponent ) ) {
  790. psiv = XHCI_SUPPORTED_PSI_VALUE ( psi );
  791. return psiv;
  792. }
  793. }
  794. DBGC ( xhci, "XHCI %s-%d unrepresentable speed %#x\n",
  795. xhci->name, port, speed );
  796. return -ENOENT;
  797. }
  798. /******************************************************************************
  799. *
  800. * Device context base address array
  801. *
  802. ******************************************************************************
  803. */
  804. /**
  805. * Allocate device context base address array
  806. *
  807. * @v xhci xHCI device
  808. * @ret rc Return status code
  809. */
  810. static int xhci_dcbaa_alloc ( struct xhci_device *xhci ) {
  811. size_t len;
  812. physaddr_t dcbaap;
  813. int rc;
  814. /* Allocate and initialise structure. Must be at least
  815. * 64-byte aligned and must not cross a page boundary, so
  816. * align on its own size (rounded up to a power of two and
  817. * with a minimum of 64 bytes).
  818. */
  819. len = ( ( xhci->slots + 1 ) * sizeof ( xhci->dcbaa[0] ) );
  820. xhci->dcbaa = malloc_dma ( len, xhci_align ( len ) );
  821. if ( ! xhci->dcbaa ) {
  822. DBGC ( xhci, "XHCI %s could not allocate DCBAA\n", xhci->name );
  823. rc = -ENOMEM;
  824. goto err_alloc;
  825. }
  826. memset ( xhci->dcbaa, 0, len );
  827. /* Program DCBAA pointer */
  828. dcbaap = virt_to_phys ( xhci->dcbaa );
  829. if ( ( rc = xhci_writeq ( xhci, dcbaap,
  830. xhci->op + XHCI_OP_DCBAAP ) ) != 0 )
  831. goto err_writeq;
  832. DBGC2 ( xhci, "XHCI %s DCBAA at [%08lx,%08lx)\n",
  833. xhci->name, dcbaap, ( dcbaap + len ) );
  834. return 0;
  835. err_writeq:
  836. free_dma ( xhci->dcbaa, len );
  837. err_alloc:
  838. return rc;
  839. }
  840. /**
  841. * Free device context base address array
  842. *
  843. * @v xhci xHCI device
  844. */
  845. static void xhci_dcbaa_free ( struct xhci_device *xhci ) {
  846. size_t len;
  847. unsigned int i;
  848. /* Sanity check */
  849. for ( i = 0 ; i <= xhci->slots ; i++ )
  850. assert ( xhci->dcbaa[i] == 0 );
  851. /* Clear DCBAA pointer */
  852. xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_DCBAAP );
  853. /* Free DCBAA */
  854. len = ( ( xhci->slots + 1 ) * sizeof ( xhci->dcbaa[0] ) );
  855. free_dma ( xhci->dcbaa, len );
  856. }
  857. /******************************************************************************
  858. *
  859. * Scratchpad buffers
  860. *
  861. ******************************************************************************
  862. */
  863. /**
  864. * Allocate scratchpad buffers
  865. *
  866. * @v xhci xHCI device
  867. * @ret rc Return status code
  868. */
  869. static int xhci_scratchpad_alloc ( struct xhci_device *xhci ) {
  870. size_t array_len;
  871. size_t len;
  872. physaddr_t phys;
  873. unsigned int i;
  874. int rc;
  875. /* Do nothing if no scratchpad buffers are used */
  876. if ( ! xhci->scratchpads )
  877. return 0;
  878. /* Allocate scratchpads */
  879. len = ( xhci->scratchpads * xhci->pagesize );
  880. xhci->scratchpad = umalloc ( len );
  881. if ( ! xhci->scratchpad ) {
  882. DBGC ( xhci, "XHCI %s could not allocate scratchpad buffers\n",
  883. xhci->name );
  884. rc = -ENOMEM;
  885. goto err_alloc;
  886. }
  887. memset_user ( xhci->scratchpad, 0, 0, len );
  888. /* Allocate scratchpad array */
  889. array_len = ( xhci->scratchpads * sizeof ( xhci->scratchpad_array[0] ));
  890. xhci->scratchpad_array =
  891. malloc_dma ( array_len, xhci_align ( array_len ) );
  892. if ( ! xhci->scratchpad_array ) {
  893. DBGC ( xhci, "XHCI %s could not allocate scratchpad buffer "
  894. "array\n", xhci->name );
  895. rc = -ENOMEM;
  896. goto err_alloc_array;
  897. }
  898. /* Populate scratchpad array */
  899. for ( i = 0 ; i < xhci->scratchpads ; i++ ) {
  900. phys = user_to_phys ( xhci->scratchpad, ( i * xhci->pagesize ));
  901. xhci->scratchpad_array[i] = phys;
  902. }
  903. /* Set scratchpad array pointer */
  904. assert ( xhci->dcbaa != NULL );
  905. xhci->dcbaa[0] = cpu_to_le64 ( virt_to_phys ( xhci->scratchpad_array ));
  906. DBGC2 ( xhci, "XHCI %s scratchpad [%08lx,%08lx) array [%08lx,%08lx)\n",
  907. xhci->name, user_to_phys ( xhci->scratchpad, 0 ),
  908. user_to_phys ( xhci->scratchpad, len ),
  909. virt_to_phys ( xhci->scratchpad_array ),
  910. ( virt_to_phys ( xhci->scratchpad_array ) + array_len ) );
  911. return 0;
  912. free_dma ( xhci->scratchpad_array, array_len );
  913. err_alloc_array:
  914. ufree ( xhci->scratchpad );
  915. err_alloc:
  916. return rc;
  917. }
  918. /**
  919. * Free scratchpad buffers
  920. *
  921. * @v xhci xHCI device
  922. */
  923. static void xhci_scratchpad_free ( struct xhci_device *xhci ) {
  924. size_t array_len;
  925. /* Do nothing if no scratchpad buffers are used */
  926. if ( ! xhci->scratchpads )
  927. return;
  928. /* Clear scratchpad array pointer */
  929. assert ( xhci->dcbaa != NULL );
  930. xhci->dcbaa[0] = 0;
  931. /* Free scratchpad array */
  932. array_len = ( xhci->scratchpads * sizeof ( xhci->scratchpad_array[0] ));
  933. free_dma ( xhci->scratchpad_array, array_len );
  934. /* Free scratchpads */
  935. ufree ( xhci->scratchpad );
  936. }
  937. /******************************************************************************
  938. *
  939. * Run / stop / reset
  940. *
  941. ******************************************************************************
  942. */
  943. /**
  944. * Start xHCI device
  945. *
  946. * @v xhci xHCI device
  947. */
  948. static void xhci_run ( struct xhci_device *xhci ) {
  949. uint32_t config;
  950. uint32_t usbcmd;
  951. /* Configure number of device slots */
  952. config = readl ( xhci->op + XHCI_OP_CONFIG );
  953. config &= ~XHCI_CONFIG_MAX_SLOTS_EN_MASK;
  954. config |= XHCI_CONFIG_MAX_SLOTS_EN ( xhci->slots );
  955. writel ( config, xhci->op + XHCI_OP_CONFIG );
  956. /* Set run/stop bit */
  957. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  958. usbcmd |= XHCI_USBCMD_RUN;
  959. writel ( usbcmd, xhci->op + XHCI_OP_USBCMD );
  960. }
  961. /**
  962. * Stop xHCI device
  963. *
  964. * @v xhci xHCI device
  965. * @ret rc Return status code
  966. */
  967. static int xhci_stop ( struct xhci_device *xhci ) {
  968. uint32_t usbcmd;
  969. uint32_t usbsts;
  970. unsigned int i;
  971. /* Clear run/stop bit */
  972. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  973. usbcmd &= ~XHCI_USBCMD_RUN;
  974. writel ( usbcmd, xhci->op + XHCI_OP_USBCMD );
  975. /* Wait for device to stop */
  976. for ( i = 0 ; i < XHCI_STOP_MAX_WAIT_MS ; i++ ) {
  977. /* Check if device is stopped */
  978. usbsts = readl ( xhci->op + XHCI_OP_USBSTS );
  979. if ( usbsts & XHCI_USBSTS_HCH )
  980. return 0;
  981. /* Delay */
  982. mdelay ( 1 );
  983. }
  984. DBGC ( xhci, "XHCI %s timed out waiting for stop\n", xhci->name );
  985. return -ETIMEDOUT;
  986. }
  987. /**
  988. * Reset xHCI device
  989. *
  990. * @v xhci xHCI device
  991. * @ret rc Return status code
  992. */
  993. static int xhci_reset ( struct xhci_device *xhci ) {
  994. uint32_t usbcmd;
  995. unsigned int i;
  996. int rc;
  997. /* The xHCI specification states that resetting a running
  998. * device may result in undefined behaviour, so try stopping
  999. * it first.
  1000. */
  1001. if ( ( rc = xhci_stop ( xhci ) ) != 0 ) {
  1002. /* Ignore errors and attempt to reset the device anyway */
  1003. }
  1004. /* Reset device */
  1005. writel ( XHCI_USBCMD_HCRST, xhci->op + XHCI_OP_USBCMD );
  1006. /* Wait for reset to complete */
  1007. for ( i = 0 ; i < XHCI_RESET_MAX_WAIT_MS ; i++ ) {
  1008. /* Check if reset is complete */
  1009. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  1010. if ( ! ( usbcmd & XHCI_USBCMD_HCRST ) )
  1011. return 0;
  1012. /* Delay */
  1013. mdelay ( 1 );
  1014. }
  1015. DBGC ( xhci, "XHCI %s timed out waiting for reset\n", xhci->name );
  1016. return -ETIMEDOUT;
  1017. }
  1018. /******************************************************************************
  1019. *
  1020. * Transfer request blocks
  1021. *
  1022. ******************************************************************************
  1023. */
  1024. /**
  1025. * Allocate transfer request block ring
  1026. *
  1027. * @v xhci xHCI device
  1028. * @v ring TRB ring
  1029. * @v shift Ring size (log2)
  1030. * @v slot Device slot
  1031. * @v target Doorbell target
  1032. * @v stream Doorbell stream ID
  1033. * @ret rc Return status code
  1034. */
  1035. static int xhci_ring_alloc ( struct xhci_device *xhci,
  1036. struct xhci_trb_ring *ring,
  1037. unsigned int shift, unsigned int slot,
  1038. unsigned int target, unsigned int stream ) {
  1039. struct xhci_trb_link *link;
  1040. unsigned int count;
  1041. int rc;
  1042. /* Sanity check */
  1043. assert ( shift > 0 );
  1044. /* Initialise structure */
  1045. memset ( ring, 0, sizeof ( *ring ) );
  1046. ring->shift = shift;
  1047. count = ( 1U << shift );
  1048. ring->mask = ( count - 1 );
  1049. ring->len = ( ( count + 1 /* Link TRB */ ) * sizeof ( ring->trb[0] ) );
  1050. ring->db = ( xhci->db + ( slot * sizeof ( ring->dbval ) ) );
  1051. ring->dbval = XHCI_DBVAL ( target, stream );
  1052. /* Allocate I/O buffers */
  1053. ring->iobuf = zalloc ( count * sizeof ( ring->iobuf[0] ) );
  1054. if ( ! ring->iobuf ) {
  1055. rc = -ENOMEM;
  1056. goto err_alloc_iobuf;
  1057. }
  1058. /* Allocate TRBs */
  1059. ring->trb = malloc_dma ( ring->len, xhci_align ( ring->len ) );
  1060. if ( ! ring->trb ) {
  1061. rc = -ENOMEM;
  1062. goto err_alloc_trb;
  1063. }
  1064. memset ( ring->trb, 0, ring->len );
  1065. /* Initialise Link TRB */
  1066. link = &ring->trb[count].link;
  1067. link->next = cpu_to_le64 ( virt_to_phys ( ring->trb ) );
  1068. link->flags = XHCI_TRB_TC;
  1069. link->type = XHCI_TRB_LINK;
  1070. ring->link = link;
  1071. return 0;
  1072. free_dma ( ring->trb, ring->len );
  1073. err_alloc_trb:
  1074. free ( ring->iobuf );
  1075. err_alloc_iobuf:
  1076. return rc;
  1077. }
  1078. /**
  1079. * Reset transfer request block ring
  1080. *
  1081. * @v ring TRB ring
  1082. */
  1083. static void xhci_ring_reset ( struct xhci_trb_ring *ring ) {
  1084. unsigned int count = ( 1U << ring->shift );
  1085. /* Reset producer and consumer counters */
  1086. ring->prod = 0;
  1087. ring->cons = 0;
  1088. /* Reset TRBs (except Link TRB) */
  1089. memset ( ring->trb, 0, ( count * sizeof ( ring->trb[0] ) ) );
  1090. }
  1091. /**
  1092. * Free transfer request block ring
  1093. *
  1094. * @v ring TRB ring
  1095. */
  1096. static void xhci_ring_free ( struct xhci_trb_ring *ring ) {
  1097. unsigned int count = ( 1U << ring->shift );
  1098. unsigned int i;
  1099. /* Sanity checks */
  1100. assert ( ring->cons == ring->prod );
  1101. for ( i = 0 ; i < count ; i++ )
  1102. assert ( ring->iobuf[i] == NULL );
  1103. /* Free TRBs */
  1104. free_dma ( ring->trb, ring->len );
  1105. /* Free I/O buffers */
  1106. free ( ring->iobuf );
  1107. }
  1108. /**
  1109. * Enqueue a transfer request block
  1110. *
  1111. * @v ring TRB ring
  1112. * @v iobuf I/O buffer (if any)
  1113. * @v trb Transfer request block (with empty Cycle flag)
  1114. * @ret rc Return status code
  1115. *
  1116. * This operation does not implicitly ring the doorbell register.
  1117. */
  1118. static int xhci_enqueue ( struct xhci_trb_ring *ring, struct io_buffer *iobuf,
  1119. const union xhci_trb *trb ) {
  1120. union xhci_trb *dest;
  1121. unsigned int prod;
  1122. unsigned int mask;
  1123. unsigned int index;
  1124. unsigned int cycle;
  1125. /* Sanity check */
  1126. assert ( ! ( trb->common.flags & XHCI_TRB_C ) );
  1127. /* Fail if ring is full */
  1128. if ( ! xhci_ring_remaining ( ring ) )
  1129. return -ENOBUFS;
  1130. /* Update producer counter (and link TRB, if applicable) */
  1131. prod = ring->prod++;
  1132. mask = ring->mask;
  1133. cycle = ( ( ~( prod >> ring->shift ) ) & XHCI_TRB_C );
  1134. index = ( prod & mask );
  1135. if ( index == 0 )
  1136. ring->link->flags = ( XHCI_TRB_TC | ( cycle ^ XHCI_TRB_C ) );
  1137. /* Record I/O buffer */
  1138. ring->iobuf[index] = iobuf;
  1139. /* Enqueue TRB */
  1140. dest = &ring->trb[index];
  1141. dest->template.parameter = trb->template.parameter;
  1142. dest->template.status = trb->template.status;
  1143. wmb();
  1144. dest->template.control = ( trb->template.control |
  1145. cpu_to_le32 ( cycle ) );
  1146. return 0;
  1147. }
  1148. /**
  1149. * Dequeue a transfer request block
  1150. *
  1151. * @v ring TRB ring
  1152. * @ret iobuf I/O buffer
  1153. */
  1154. static struct io_buffer * xhci_dequeue ( struct xhci_trb_ring *ring ) {
  1155. struct io_buffer *iobuf;
  1156. unsigned int cons;
  1157. unsigned int mask;
  1158. unsigned int index;
  1159. /* Sanity check */
  1160. assert ( xhci_ring_fill ( ring ) != 0 );
  1161. /* Update consumer counter */
  1162. cons = ring->cons++;
  1163. mask = ring->mask;
  1164. index = ( cons & mask );
  1165. /* Retrieve I/O buffer */
  1166. iobuf = ring->iobuf[index];
  1167. ring->iobuf[index] = NULL;
  1168. return iobuf;
  1169. }
  1170. /**
  1171. * Enqueue multiple transfer request blocks
  1172. *
  1173. * @v ring TRB ring
  1174. * @v iobuf I/O buffer
  1175. * @v trbs Transfer request blocks (with empty Cycle flag)
  1176. * @v count Number of transfer request blocks
  1177. * @ret rc Return status code
  1178. *
  1179. * This operation does not implicitly ring the doorbell register.
  1180. */
  1181. static int xhci_enqueue_multi ( struct xhci_trb_ring *ring,
  1182. struct io_buffer *iobuf,
  1183. const union xhci_trb *trbs,
  1184. unsigned int count ) {
  1185. const union xhci_trb *trb = trbs;
  1186. int rc;
  1187. /* Sanity check */
  1188. assert ( iobuf != NULL );
  1189. /* Fail if ring does not have sufficient space */
  1190. if ( xhci_ring_remaining ( ring ) < count )
  1191. return -ENOBUFS;
  1192. /* Enqueue each TRB, recording the I/O buffer with the final TRB */
  1193. while ( count-- ) {
  1194. rc = xhci_enqueue ( ring, ( count ? NULL : iobuf ), trb++ );
  1195. assert ( rc == 0 ); /* Should never be able to fail */
  1196. }
  1197. return 0;
  1198. }
  1199. /**
  1200. * Dequeue multiple transfer request blocks
  1201. *
  1202. * @v ring TRB ring
  1203. * @ret iobuf I/O buffer
  1204. */
  1205. static struct io_buffer * xhci_dequeue_multi ( struct xhci_trb_ring *ring ) {
  1206. struct io_buffer *iobuf;
  1207. /* Dequeue TRBs until we reach the final TRB for an I/O buffer */
  1208. do {
  1209. iobuf = xhci_dequeue ( ring );
  1210. } while ( iobuf == NULL );
  1211. return iobuf;
  1212. }
  1213. /**
  1214. * Ring doorbell register
  1215. *
  1216. * @v ring TRB ring
  1217. */
  1218. static inline __attribute__ (( always_inline )) void
  1219. xhci_doorbell ( struct xhci_trb_ring *ring ) {
  1220. wmb();
  1221. writel ( ring->dbval, ring->db );
  1222. }
  1223. /******************************************************************************
  1224. *
  1225. * Command and event rings
  1226. *
  1227. ******************************************************************************
  1228. */
  1229. /**
  1230. * Allocate command ring
  1231. *
  1232. * @v xhci xHCI device
  1233. * @ret rc Return status code
  1234. */
  1235. static int xhci_command_alloc ( struct xhci_device *xhci ) {
  1236. physaddr_t crp;
  1237. int rc;
  1238. /* Allocate TRB ring */
  1239. if ( ( rc = xhci_ring_alloc ( xhci, &xhci->command, XHCI_CMD_TRBS_LOG2,
  1240. 0, 0, 0 ) ) != 0 )
  1241. goto err_ring_alloc;
  1242. /* Program command ring control register */
  1243. crp = virt_to_phys ( xhci->command.trb );
  1244. if ( ( rc = xhci_writeq ( xhci, ( crp | XHCI_CRCR_RCS ),
  1245. xhci->op + XHCI_OP_CRCR ) ) != 0 )
  1246. goto err_writeq;
  1247. DBGC2 ( xhci, "XHCI %s CRCR at [%08lx,%08lx)\n",
  1248. xhci->name, crp, ( crp + xhci->command.len ) );
  1249. return 0;
  1250. err_writeq:
  1251. xhci_ring_free ( &xhci->command );
  1252. err_ring_alloc:
  1253. return rc;
  1254. }
  1255. /**
  1256. * Free command ring
  1257. *
  1258. * @v xhci xHCI device
  1259. */
  1260. static void xhci_command_free ( struct xhci_device *xhci ) {
  1261. /* Sanity check */
  1262. assert ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 );
  1263. /* Clear command ring control register */
  1264. xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_CRCR );
  1265. /* Free TRB ring */
  1266. xhci_ring_free ( &xhci->command );
  1267. }
  1268. /**
  1269. * Allocate event ring
  1270. *
  1271. * @v xhci xHCI device
  1272. * @ret rc Return status code
  1273. */
  1274. static int xhci_event_alloc ( struct xhci_device *xhci ) {
  1275. struct xhci_event_ring *event = &xhci->event;
  1276. unsigned int count;
  1277. size_t len;
  1278. int rc;
  1279. /* Allocate event ring */
  1280. count = ( 1 << XHCI_EVENT_TRBS_LOG2 );
  1281. len = ( count * sizeof ( event->trb[0] ) );
  1282. event->trb = malloc_dma ( len, xhci_align ( len ) );
  1283. if ( ! event->trb ) {
  1284. rc = -ENOMEM;
  1285. goto err_alloc_trb;
  1286. }
  1287. memset ( event->trb, 0, len );
  1288. /* Allocate event ring segment table */
  1289. event->segment = malloc_dma ( sizeof ( event->segment[0] ),
  1290. xhci_align ( sizeof (event->segment[0])));
  1291. if ( ! event->segment ) {
  1292. rc = -ENOMEM;
  1293. goto err_alloc_segment;
  1294. }
  1295. memset ( event->segment, 0, sizeof ( event->segment[0] ) );
  1296. event->segment[0].base = cpu_to_le64 ( virt_to_phys ( event->trb ) );
  1297. event->segment[0].count = cpu_to_le32 ( count );
  1298. /* Program event ring registers */
  1299. writel ( 1, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) );
  1300. if ( ( rc = xhci_writeq ( xhci, virt_to_phys ( event->trb ),
  1301. xhci->run + XHCI_RUN_ERDP ( 0 ) ) ) != 0 )
  1302. goto err_writeq_erdp;
  1303. if ( ( rc = xhci_writeq ( xhci, virt_to_phys ( event->segment ),
  1304. xhci->run + XHCI_RUN_ERSTBA ( 0 ) ) ) != 0 )
  1305. goto err_writeq_erstba;
  1306. DBGC2 ( xhci, "XHCI %s event ring [%08lx,%08lx) table [%08lx,%08lx)\n",
  1307. xhci->name, virt_to_phys ( event->trb ),
  1308. ( virt_to_phys ( event->trb ) + len ),
  1309. virt_to_phys ( event->segment ),
  1310. ( virt_to_phys ( event->segment ) +
  1311. sizeof (event->segment[0] ) ) );
  1312. return 0;
  1313. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERSTBA ( 0 ) );
  1314. err_writeq_erstba:
  1315. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERDP ( 0 ) );
  1316. err_writeq_erdp:
  1317. free_dma ( event->trb, len );
  1318. err_alloc_segment:
  1319. free_dma ( event->segment, sizeof ( event->segment[0] ) );
  1320. err_alloc_trb:
  1321. return rc;
  1322. }
  1323. /**
  1324. * Free event ring
  1325. *
  1326. * @v xhci xHCI device
  1327. */
  1328. static void xhci_event_free ( struct xhci_device *xhci ) {
  1329. struct xhci_event_ring *event = &xhci->event;
  1330. unsigned int count;
  1331. size_t len;
  1332. /* Clear event ring registers */
  1333. writel ( 0, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) );
  1334. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERSTBA ( 0 ) );
  1335. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERDP ( 0 ) );
  1336. /* Free event ring segment table */
  1337. free_dma ( event->segment, sizeof ( event->segment[0] ) );
  1338. /* Free event ring */
  1339. count = ( 1 << XHCI_EVENT_TRBS_LOG2 );
  1340. len = ( count * sizeof ( event->trb[0] ) );
  1341. free_dma ( event->trb, len );
  1342. }
  1343. /**
  1344. * Handle transfer event
  1345. *
  1346. * @v xhci xHCI device
  1347. * @v trb Transfer event TRB
  1348. */
  1349. static void xhci_transfer ( struct xhci_device *xhci,
  1350. struct xhci_trb_transfer *trb ) {
  1351. struct xhci_slot *slot;
  1352. struct xhci_endpoint *endpoint;
  1353. struct io_buffer *iobuf;
  1354. int rc;
  1355. /* Profile transfer events */
  1356. profile_start ( &xhci_transfer_profiler );
  1357. /* Identify slot */
  1358. if ( ( trb->slot > xhci->slots ) ||
  1359. ( ( slot = xhci->slot[trb->slot] ) == NULL ) ) {
  1360. DBGC ( xhci, "XHCI %s transfer event invalid slot %d:\n",
  1361. xhci->name, trb->slot );
  1362. DBGC_HDA ( xhci, 0, trb, sizeof ( *trb ) );
  1363. return;
  1364. }
  1365. /* Identify endpoint */
  1366. if ( ( trb->endpoint > XHCI_CTX_END ) ||
  1367. ( ( endpoint = slot->endpoint[trb->endpoint] ) == NULL ) ) {
  1368. DBGC ( xhci, "XHCI %s slot %d transfer event invalid epid "
  1369. "%d:\n", xhci->name, slot->id, trb->endpoint );
  1370. DBGC_HDA ( xhci, 0, trb, sizeof ( *trb ) );
  1371. return;
  1372. }
  1373. /* Dequeue TRB(s) */
  1374. iobuf = xhci_dequeue_multi ( &endpoint->ring );
  1375. assert ( iobuf != NULL );
  1376. /* Check for errors */
  1377. if ( ! ( ( trb->code == XHCI_CMPLT_SUCCESS ) ||
  1378. ( trb->code == XHCI_CMPLT_SHORT ) ) ) {
  1379. /* Construct error */
  1380. rc = -ECODE ( trb->code );
  1381. DBGC ( xhci, "XHCI %s slot %d ctx %d failed (code %d): %s\n",
  1382. xhci->name, slot->id, endpoint->ctx, trb->code,
  1383. strerror ( rc ) );
  1384. DBGC_HDA ( xhci, 0, trb, sizeof ( *trb ) );
  1385. /* Sanity check */
  1386. assert ( ( endpoint->context->state & XHCI_ENDPOINT_STATE_MASK )
  1387. != XHCI_ENDPOINT_RUNNING );
  1388. /* Report failure to USB core */
  1389. usb_complete_err ( endpoint->ep, iobuf, rc );
  1390. return;
  1391. }
  1392. /* Record actual transfer size */
  1393. iob_unput ( iobuf, le16_to_cpu ( trb->residual ) );
  1394. /* Sanity check (for successful completions only) */
  1395. assert ( xhci_ring_consumed ( &endpoint->ring ) ==
  1396. le64_to_cpu ( trb->transfer ) );
  1397. /* Report completion to USB core */
  1398. usb_complete ( endpoint->ep, iobuf );
  1399. profile_stop ( &xhci_transfer_profiler );
  1400. }
  1401. /**
  1402. * Handle command completion event
  1403. *
  1404. * @v xhci xHCI device
  1405. * @v trb Command completion event
  1406. */
  1407. static void xhci_complete ( struct xhci_device *xhci,
  1408. struct xhci_trb_complete *trb ) {
  1409. int rc;
  1410. /* Ignore "command ring stopped" notifications */
  1411. if ( trb->code == XHCI_CMPLT_CMD_STOPPED ) {
  1412. DBGC2 ( xhci, "XHCI %s command ring stopped\n", xhci->name );
  1413. return;
  1414. }
  1415. /* Ignore unexpected completions */
  1416. if ( ! xhci->pending ) {
  1417. rc = -ECODE ( trb->code );
  1418. DBGC ( xhci, "XHCI %s unexpected completion (code %d): %s\n",
  1419. xhci->name, trb->code, strerror ( rc ) );
  1420. DBGC_HDA ( xhci, 0, trb, sizeof ( *trb ) );
  1421. return;
  1422. }
  1423. /* Dequeue command TRB */
  1424. xhci_dequeue ( &xhci->command );
  1425. /* Sanity check */
  1426. assert ( xhci_ring_consumed ( &xhci->command ) ==
  1427. le64_to_cpu ( trb->command ) );
  1428. /* Record completion */
  1429. memcpy ( xhci->pending, trb, sizeof ( *xhci->pending ) );
  1430. xhci->pending = NULL;
  1431. }
  1432. /**
  1433. * Handle port status event
  1434. *
  1435. * @v xhci xHCI device
  1436. * @v trb Port status event
  1437. */
  1438. static void xhci_port_status ( struct xhci_device *xhci,
  1439. struct xhci_trb_port_status *trb ) {
  1440. struct usb_port *port = usb_port ( xhci->bus->hub, trb->port );
  1441. uint32_t portsc;
  1442. /* Sanity check */
  1443. assert ( ( trb->port > 0 ) && ( trb->port <= xhci->ports ) );
  1444. /* Record disconnections and clear changes */
  1445. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( trb->port ) );
  1446. port->disconnected |= ( portsc & XHCI_PORTSC_CSC );
  1447. portsc &= ( XHCI_PORTSC_PRESERVE | XHCI_PORTSC_CHANGE );
  1448. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( trb->port ) );
  1449. /* Report port status change */
  1450. usb_port_changed ( port );
  1451. }
  1452. /**
  1453. * Handle host controller event
  1454. *
  1455. * @v xhci xHCI device
  1456. * @v trb Host controller event
  1457. */
  1458. static void xhci_host_controller ( struct xhci_device *xhci,
  1459. struct xhci_trb_host_controller *trb ) {
  1460. int rc;
  1461. /* Construct error */
  1462. rc = -ECODE ( trb->code );
  1463. DBGC ( xhci, "XHCI %s host controller event (code %d): %s\n",
  1464. xhci->name, trb->code, strerror ( rc ) );
  1465. }
  1466. /**
  1467. * Poll event ring
  1468. *
  1469. * @v xhci xHCI device
  1470. */
  1471. static void xhci_event_poll ( struct xhci_device *xhci ) {
  1472. struct xhci_event_ring *event = &xhci->event;
  1473. union xhci_trb *trb;
  1474. unsigned int shift = XHCI_EVENT_TRBS_LOG2;
  1475. unsigned int count = ( 1 << shift );
  1476. unsigned int mask = ( count - 1 );
  1477. unsigned int consumed;
  1478. unsigned int type;
  1479. /* Poll for events */
  1480. profile_start ( &xhci_event_profiler );
  1481. for ( consumed = 0 ; ; consumed++ ) {
  1482. /* Stop if we reach an empty TRB */
  1483. rmb();
  1484. trb = &event->trb[ event->cons & mask ];
  1485. if ( ! ( ( trb->common.flags ^
  1486. ( event->cons >> shift ) ) & XHCI_TRB_C ) )
  1487. break;
  1488. /* Handle TRB */
  1489. type = ( trb->common.type & XHCI_TRB_TYPE_MASK );
  1490. switch ( type ) {
  1491. case XHCI_TRB_TRANSFER :
  1492. xhci_transfer ( xhci, &trb->transfer );
  1493. break;
  1494. case XHCI_TRB_COMPLETE :
  1495. xhci_complete ( xhci, &trb->complete );
  1496. break;
  1497. case XHCI_TRB_PORT_STATUS:
  1498. xhci_port_status ( xhci, &trb->port );
  1499. break;
  1500. case XHCI_TRB_HOST_CONTROLLER:
  1501. xhci_host_controller ( xhci, &trb->host );
  1502. break;
  1503. default:
  1504. DBGC ( xhci, "XHCI %s unrecognised event %#x\n:",
  1505. xhci->name, event->cons );
  1506. DBGC_HDA ( xhci, virt_to_phys ( trb ),
  1507. trb, sizeof ( *trb ) );
  1508. break;
  1509. }
  1510. /* Consume this TRB */
  1511. event->cons++;
  1512. }
  1513. /* Update dequeue pointer if applicable */
  1514. if ( consumed ) {
  1515. xhci_writeq ( xhci, virt_to_phys ( trb ),
  1516. xhci->run + XHCI_RUN_ERDP ( 0 ) );
  1517. profile_stop ( &xhci_event_profiler );
  1518. }
  1519. }
  1520. /**
  1521. * Abort command
  1522. *
  1523. * @v xhci xHCI device
  1524. */
  1525. static void xhci_abort ( struct xhci_device *xhci ) {
  1526. physaddr_t crp;
  1527. /* Abort the command */
  1528. DBGC2 ( xhci, "XHCI %s aborting command\n", xhci->name );
  1529. xhci_writeq ( xhci, XHCI_CRCR_CA, xhci->op + XHCI_OP_CRCR );
  1530. /* Allow time for command to abort */
  1531. mdelay ( XHCI_COMMAND_ABORT_DELAY_MS );
  1532. /* Sanity check */
  1533. assert ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 );
  1534. /* Consume (and ignore) any final command status */
  1535. xhci_event_poll ( xhci );
  1536. /* Reset the command ring control register */
  1537. xhci_ring_reset ( &xhci->command );
  1538. crp = virt_to_phys ( xhci->command.trb );
  1539. xhci_writeq ( xhci, ( crp | XHCI_CRCR_RCS ), xhci->op + XHCI_OP_CRCR );
  1540. }
  1541. /**
  1542. * Issue command and wait for completion
  1543. *
  1544. * @v xhci xHCI device
  1545. * @v trb Transfer request block (with empty Cycle flag)
  1546. * @ret rc Return status code
  1547. *
  1548. * On a successful completion, the TRB will be overwritten with the
  1549. * completion.
  1550. */
  1551. static int xhci_command ( struct xhci_device *xhci, union xhci_trb *trb ) {
  1552. struct xhci_trb_complete *complete = &trb->complete;
  1553. unsigned int i;
  1554. int rc;
  1555. /* Record the pending command */
  1556. xhci->pending = trb;
  1557. /* Enqueue the command */
  1558. if ( ( rc = xhci_enqueue ( &xhci->command, NULL, trb ) ) != 0 )
  1559. goto err_enqueue;
  1560. /* Ring the command doorbell */
  1561. xhci_doorbell ( &xhci->command );
  1562. /* Wait for the command to complete */
  1563. for ( i = 0 ; i < XHCI_COMMAND_MAX_WAIT_MS ; i++ ) {
  1564. /* Poll event ring */
  1565. xhci_event_poll ( xhci );
  1566. /* Check for completion */
  1567. if ( ! xhci->pending ) {
  1568. if ( complete->code != XHCI_CMPLT_SUCCESS ) {
  1569. rc = -ECODE ( complete->code );
  1570. DBGC ( xhci, "XHCI %s command failed (code "
  1571. "%d): %s\n", xhci->name, complete->code,
  1572. strerror ( rc ) );
  1573. DBGC_HDA ( xhci, 0, trb, sizeof ( *trb ) );
  1574. return rc;
  1575. }
  1576. return 0;
  1577. }
  1578. /* Delay */
  1579. mdelay ( 1 );
  1580. }
  1581. /* Timeout */
  1582. DBGC ( xhci, "XHCI %s timed out waiting for completion\n", xhci->name );
  1583. rc = -ETIMEDOUT;
  1584. /* Abort command */
  1585. xhci_abort ( xhci );
  1586. err_enqueue:
  1587. xhci->pending = NULL;
  1588. return rc;
  1589. }
  1590. /**
  1591. * Issue NOP and wait for completion
  1592. *
  1593. * @v xhci xHCI device
  1594. * @ret rc Return status code
  1595. */
  1596. static inline int xhci_nop ( struct xhci_device *xhci ) {
  1597. union xhci_trb trb;
  1598. struct xhci_trb_common *nop = &trb.common;
  1599. int rc;
  1600. /* Construct command */
  1601. memset ( nop, 0, sizeof ( *nop ) );
  1602. nop->flags = XHCI_TRB_IOC;
  1603. nop->type = XHCI_TRB_NOP_CMD;
  1604. /* Issue command and wait for completion */
  1605. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 )
  1606. return rc;
  1607. return 0;
  1608. }
  1609. /**
  1610. * Enable slot
  1611. *
  1612. * @v xhci xHCI device
  1613. * @v type Slot type
  1614. * @ret slot Device slot ID, or negative error
  1615. */
  1616. static inline int xhci_enable_slot ( struct xhci_device *xhci,
  1617. unsigned int type ) {
  1618. union xhci_trb trb;
  1619. struct xhci_trb_enable_slot *enable = &trb.enable;
  1620. struct xhci_trb_complete *enabled = &trb.complete;
  1621. unsigned int slot;
  1622. int rc;
  1623. /* Construct command */
  1624. memset ( enable, 0, sizeof ( *enable ) );
  1625. enable->slot = type;
  1626. enable->type = XHCI_TRB_ENABLE_SLOT;
  1627. /* Issue command and wait for completion */
  1628. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1629. DBGC ( xhci, "XHCI %s could not enable new slot: %s\n",
  1630. xhci->name, strerror ( rc ) );
  1631. return rc;
  1632. }
  1633. /* Extract slot number */
  1634. slot = enabled->slot;
  1635. DBGC2 ( xhci, "XHCI %s slot %d enabled\n", xhci->name, slot );
  1636. return slot;
  1637. }
  1638. /**
  1639. * Disable slot
  1640. *
  1641. * @v xhci xHCI device
  1642. * @v slot Device slot
  1643. * @ret rc Return status code
  1644. */
  1645. static inline int xhci_disable_slot ( struct xhci_device *xhci,
  1646. unsigned int slot ) {
  1647. union xhci_trb trb;
  1648. struct xhci_trb_disable_slot *disable = &trb.disable;
  1649. int rc;
  1650. /* Construct command */
  1651. memset ( disable, 0, sizeof ( *disable ) );
  1652. disable->type = XHCI_TRB_DISABLE_SLOT;
  1653. disable->slot = slot;
  1654. /* Issue command and wait for completion */
  1655. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1656. DBGC ( xhci, "XHCI %s could not disable slot %d: %s\n",
  1657. xhci->name, slot, strerror ( rc ) );
  1658. return rc;
  1659. }
  1660. DBGC2 ( xhci, "XHCI %s slot %d disabled\n", xhci->name, slot );
  1661. return 0;
  1662. }
  1663. /**
  1664. * Issue context-based command and wait for completion
  1665. *
  1666. * @v xhci xHCI device
  1667. * @v slot Device slot
  1668. * @v endpoint Endpoint
  1669. * @v type TRB type
  1670. * @v populate Input context populater
  1671. * @ret rc Return status code
  1672. */
  1673. static int xhci_context ( struct xhci_device *xhci, struct xhci_slot *slot,
  1674. struct xhci_endpoint *endpoint, unsigned int type,
  1675. void ( * populate ) ( struct xhci_device *xhci,
  1676. struct xhci_slot *slot,
  1677. struct xhci_endpoint *endpoint,
  1678. void *input ) ) {
  1679. union xhci_trb trb;
  1680. struct xhci_trb_context *context = &trb.context;
  1681. size_t len;
  1682. void *input;
  1683. int rc;
  1684. /* Allocate an input context */
  1685. len = xhci_input_context_offset ( xhci, XHCI_CTX_END );
  1686. input = malloc_dma ( len, xhci_align ( len ) );
  1687. if ( ! input ) {
  1688. rc = -ENOMEM;
  1689. goto err_alloc;
  1690. }
  1691. memset ( input, 0, len );
  1692. /* Populate input context */
  1693. populate ( xhci, slot, endpoint, input );
  1694. /* Construct command */
  1695. memset ( context, 0, sizeof ( *context ) );
  1696. context->type = type;
  1697. context->input = cpu_to_le64 ( virt_to_phys ( input ) );
  1698. context->slot = slot->id;
  1699. /* Issue command and wait for completion */
  1700. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 )
  1701. goto err_command;
  1702. err_command:
  1703. free_dma ( input, len );
  1704. err_alloc:
  1705. return rc;
  1706. }
  1707. /**
  1708. * Populate address device input context
  1709. *
  1710. * @v xhci xHCI device
  1711. * @v slot Device slot
  1712. * @v endpoint Endpoint
  1713. * @v input Input context
  1714. */
  1715. static void xhci_address_device_input ( struct xhci_device *xhci,
  1716. struct xhci_slot *slot,
  1717. struct xhci_endpoint *endpoint,
  1718. void *input ) {
  1719. struct xhci_control_context *control_ctx;
  1720. struct xhci_slot_context *slot_ctx;
  1721. struct xhci_endpoint_context *ep_ctx;
  1722. /* Sanity checks */
  1723. assert ( endpoint->ctx == XHCI_CTX_EP0 );
  1724. /* Populate control context */
  1725. control_ctx = input;
  1726. control_ctx->add = cpu_to_le32 ( ( 1 << XHCI_CTX_SLOT ) |
  1727. ( 1 << XHCI_CTX_EP0 ) );
  1728. /* Populate slot context */
  1729. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1730. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( 1, 0, slot->psiv,
  1731. slot->route ) );
  1732. slot_ctx->port = slot->port;
  1733. slot_ctx->tt_id = slot->tt_id;
  1734. slot_ctx->tt_port = slot->tt_port;
  1735. /* Populate control endpoint context */
  1736. ep_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_EP0 ) );
  1737. ep_ctx->type = XHCI_EP_TYPE_CONTROL;
  1738. ep_ctx->burst = endpoint->ep->burst;
  1739. ep_ctx->mtu = cpu_to_le16 ( endpoint->ep->mtu );
  1740. ep_ctx->dequeue = cpu_to_le64 ( virt_to_phys ( endpoint->ring.trb ) |
  1741. XHCI_EP_DCS );
  1742. ep_ctx->trb_len = cpu_to_le16 ( XHCI_EP0_TRB_LEN );
  1743. }
  1744. /**
  1745. * Address device
  1746. *
  1747. * @v xhci xHCI device
  1748. * @v slot Device slot
  1749. * @ret rc Return status code
  1750. */
  1751. static inline int xhci_address_device ( struct xhci_device *xhci,
  1752. struct xhci_slot *slot ) {
  1753. struct usb_device *usb = slot->usb;
  1754. struct xhci_slot_context *slot_ctx;
  1755. int rc;
  1756. /* Assign device address */
  1757. if ( ( rc = xhci_context ( xhci, slot, slot->endpoint[XHCI_CTX_EP0],
  1758. XHCI_TRB_ADDRESS_DEVICE,
  1759. xhci_address_device_input ) ) != 0 )
  1760. return rc;
  1761. /* Get assigned address */
  1762. slot_ctx = ( slot->context +
  1763. xhci_device_context_offset ( xhci, XHCI_CTX_SLOT ) );
  1764. usb->address = slot_ctx->address;
  1765. DBGC2 ( xhci, "XHCI %s assigned address %d to %s\n",
  1766. xhci->name, usb->address, usb->name );
  1767. return 0;
  1768. }
  1769. /**
  1770. * Populate configure endpoint input context
  1771. *
  1772. * @v xhci xHCI device
  1773. * @v slot Device slot
  1774. * @v endpoint Endpoint
  1775. * @v input Input context
  1776. */
  1777. static void xhci_configure_endpoint_input ( struct xhci_device *xhci,
  1778. struct xhci_slot *slot,
  1779. struct xhci_endpoint *endpoint,
  1780. void *input ) {
  1781. struct xhci_control_context *control_ctx;
  1782. struct xhci_slot_context *slot_ctx;
  1783. struct xhci_endpoint_context *ep_ctx;
  1784. /* Populate control context */
  1785. control_ctx = input;
  1786. control_ctx->add = cpu_to_le32 ( ( 1 << XHCI_CTX_SLOT ) |
  1787. ( 1 << endpoint->ctx ) );
  1788. /* Populate slot context */
  1789. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1790. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ),
  1791. ( slot->ports ? 1 : 0 ),
  1792. slot->psiv, 0 ) );
  1793. slot_ctx->ports = slot->ports;
  1794. /* Populate endpoint context */
  1795. ep_ctx = ( input + xhci_input_context_offset ( xhci, endpoint->ctx ) );
  1796. ep_ctx->interval = endpoint->interval;
  1797. ep_ctx->type = endpoint->type;
  1798. ep_ctx->burst = endpoint->ep->burst;
  1799. ep_ctx->mtu = cpu_to_le16 ( endpoint->ep->mtu );
  1800. ep_ctx->dequeue = cpu_to_le64 ( virt_to_phys ( endpoint->ring.trb ) |
  1801. XHCI_EP_DCS );
  1802. ep_ctx->trb_len = cpu_to_le16 ( endpoint->ep->mtu ); /* best guess */
  1803. }
  1804. /**
  1805. * Configure endpoint
  1806. *
  1807. * @v xhci xHCI device
  1808. * @v slot Device slot
  1809. * @v endpoint Endpoint
  1810. * @ret rc Return status code
  1811. */
  1812. static inline int xhci_configure_endpoint ( struct xhci_device *xhci,
  1813. struct xhci_slot *slot,
  1814. struct xhci_endpoint *endpoint ) {
  1815. int rc;
  1816. /* Configure endpoint */
  1817. if ( ( rc = xhci_context ( xhci, slot, endpoint,
  1818. XHCI_TRB_CONFIGURE_ENDPOINT,
  1819. xhci_configure_endpoint_input ) ) != 0 )
  1820. return rc;
  1821. DBGC2 ( xhci, "XHCI %s slot %d ctx %d configured\n",
  1822. xhci->name, slot->id, endpoint->ctx );
  1823. return 0;
  1824. }
  1825. /**
  1826. * Populate deconfigure endpoint input context
  1827. *
  1828. * @v xhci xHCI device
  1829. * @v slot Device slot
  1830. * @v endpoint Endpoint
  1831. * @v input Input context
  1832. */
  1833. static void
  1834. xhci_deconfigure_endpoint_input ( struct xhci_device *xhci __unused,
  1835. struct xhci_slot *slot __unused,
  1836. struct xhci_endpoint *endpoint,
  1837. void *input ) {
  1838. struct xhci_control_context *control_ctx;
  1839. struct xhci_slot_context *slot_ctx;
  1840. /* Populate control context */
  1841. control_ctx = input;
  1842. control_ctx->add = cpu_to_le32 ( 1 << XHCI_CTX_SLOT );
  1843. control_ctx->drop = cpu_to_le32 ( 1 << endpoint->ctx );
  1844. /* Populate slot context */
  1845. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1846. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ),
  1847. 0, 0, 0 ) );
  1848. }
  1849. /**
  1850. * Deconfigure endpoint
  1851. *
  1852. * @v xhci xHCI device
  1853. * @v slot Device slot
  1854. * @v endpoint Endpoint
  1855. * @ret rc Return status code
  1856. */
  1857. static inline int xhci_deconfigure_endpoint ( struct xhci_device *xhci,
  1858. struct xhci_slot *slot,
  1859. struct xhci_endpoint *endpoint ) {
  1860. int rc;
  1861. /* Deconfigure endpoint */
  1862. if ( ( rc = xhci_context ( xhci, slot, endpoint,
  1863. XHCI_TRB_CONFIGURE_ENDPOINT,
  1864. xhci_deconfigure_endpoint_input ) ) != 0 )
  1865. return rc;
  1866. DBGC2 ( xhci, "XHCI %s slot %d ctx %d deconfigured\n",
  1867. xhci->name, slot->id, endpoint->ctx );
  1868. return 0;
  1869. }
  1870. /**
  1871. * Populate evaluate context input context
  1872. *
  1873. * @v xhci xHCI device
  1874. * @v slot Device slot
  1875. * @v endpoint Endpoint
  1876. * @v input Input context
  1877. */
  1878. static void xhci_evaluate_context_input ( struct xhci_device *xhci,
  1879. struct xhci_slot *slot __unused,
  1880. struct xhci_endpoint *endpoint,
  1881. void *input ) {
  1882. struct xhci_control_context *control_ctx;
  1883. struct xhci_slot_context *slot_ctx;
  1884. struct xhci_endpoint_context *ep_ctx;
  1885. /* Populate control context */
  1886. control_ctx = input;
  1887. control_ctx->add = cpu_to_le32 ( ( 1 << XHCI_CTX_SLOT ) |
  1888. ( 1 << endpoint->ctx ) );
  1889. /* Populate slot context */
  1890. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1891. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ),
  1892. 0, 0, 0 ) );
  1893. /* Populate endpoint context */
  1894. ep_ctx = ( input + xhci_input_context_offset ( xhci, endpoint->ctx ) );
  1895. ep_ctx->mtu = cpu_to_le16 ( endpoint->ep->mtu );
  1896. }
  1897. /**
  1898. * Evaluate context
  1899. *
  1900. * @v xhci xHCI device
  1901. * @v slot Device slot
  1902. * @v endpoint Endpoint
  1903. * @ret rc Return status code
  1904. */
  1905. static inline int xhci_evaluate_context ( struct xhci_device *xhci,
  1906. struct xhci_slot *slot,
  1907. struct xhci_endpoint *endpoint ) {
  1908. int rc;
  1909. /* Configure endpoint */
  1910. if ( ( rc = xhci_context ( xhci, slot, endpoint,
  1911. XHCI_TRB_EVALUATE_CONTEXT,
  1912. xhci_evaluate_context_input ) ) != 0 )
  1913. return rc;
  1914. DBGC2 ( xhci, "XHCI %s slot %d ctx %d (re-)evaluated\n",
  1915. xhci->name, slot->id, endpoint->ctx );
  1916. return 0;
  1917. }
  1918. /**
  1919. * Reset endpoint
  1920. *
  1921. * @v xhci xHCI device
  1922. * @v slot Device slot
  1923. * @v endpoint Endpoint
  1924. * @ret rc Return status code
  1925. */
  1926. static inline int xhci_reset_endpoint ( struct xhci_device *xhci,
  1927. struct xhci_slot *slot,
  1928. struct xhci_endpoint *endpoint ) {
  1929. union xhci_trb trb;
  1930. struct xhci_trb_reset_endpoint *reset = &trb.reset;
  1931. int rc;
  1932. /* Construct command */
  1933. memset ( reset, 0, sizeof ( *reset ) );
  1934. reset->slot = slot->id;
  1935. reset->endpoint = endpoint->ctx;
  1936. reset->type = XHCI_TRB_RESET_ENDPOINT;
  1937. /* Issue command and wait for completion */
  1938. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1939. DBGC ( xhci, "XHCI %s slot %d ctx %d could not reset endpoint "
  1940. "in state %d: %s\n", xhci->name, slot->id, endpoint->ctx,
  1941. endpoint->context->state, strerror ( rc ) );
  1942. return rc;
  1943. }
  1944. return 0;
  1945. }
  1946. /**
  1947. * Stop endpoint
  1948. *
  1949. * @v xhci xHCI device
  1950. * @v slot Device slot
  1951. * @v endpoint Endpoint
  1952. * @ret rc Return status code
  1953. */
  1954. static inline int xhci_stop_endpoint ( struct xhci_device *xhci,
  1955. struct xhci_slot *slot,
  1956. struct xhci_endpoint *endpoint ) {
  1957. union xhci_trb trb;
  1958. struct xhci_trb_stop_endpoint *stop = &trb.stop;
  1959. int rc;
  1960. /* Construct command */
  1961. memset ( stop, 0, sizeof ( *stop ) );
  1962. stop->slot = slot->id;
  1963. stop->endpoint = endpoint->ctx;
  1964. stop->type = XHCI_TRB_STOP_ENDPOINT;
  1965. /* Issue command and wait for completion */
  1966. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1967. DBGC ( xhci, "XHCI %s slot %d ctx %d could not stop endpoint "
  1968. "in state %d: %s\n", xhci->name, slot->id, endpoint->ctx,
  1969. endpoint->context->state, strerror ( rc ) );
  1970. return rc;
  1971. }
  1972. return 0;
  1973. }
  1974. /**
  1975. * Set transfer ring dequeue pointer
  1976. *
  1977. * @v xhci xHCI device
  1978. * @v slot Device slot
  1979. * @v endpoint Endpoint
  1980. * @ret rc Return status code
  1981. */
  1982. static inline int
  1983. xhci_set_tr_dequeue_pointer ( struct xhci_device *xhci,
  1984. struct xhci_slot *slot,
  1985. struct xhci_endpoint *endpoint ) {
  1986. union xhci_trb trb;
  1987. struct xhci_trb_set_tr_dequeue_pointer *dequeue = &trb.dequeue;
  1988. struct xhci_trb_ring *ring = &endpoint->ring;
  1989. unsigned int cons;
  1990. unsigned int mask;
  1991. unsigned int index;
  1992. unsigned int dcs;
  1993. int rc;
  1994. /* Construct command */
  1995. memset ( dequeue, 0, sizeof ( *dequeue ) );
  1996. cons = ring->cons;
  1997. mask = ring->mask;
  1998. dcs = ( ( ~( cons >> ring->shift ) ) & XHCI_EP_DCS );
  1999. index = ( cons & mask );
  2000. dequeue->dequeue =
  2001. cpu_to_le64 ( virt_to_phys ( &ring->trb[index] ) | dcs );
  2002. dequeue->slot = slot->id;
  2003. dequeue->endpoint = endpoint->ctx;
  2004. dequeue->type = XHCI_TRB_SET_TR_DEQUEUE_POINTER;
  2005. /* Issue command and wait for completion */
  2006. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  2007. DBGC ( xhci, "XHCI %s slot %d ctx %d could not set TR dequeue "
  2008. "pointer in state %d: %s\n", xhci->name, slot->id,
  2009. endpoint->ctx, endpoint->context->state, strerror ( rc));
  2010. return rc;
  2011. }
  2012. return 0;
  2013. }
  2014. /******************************************************************************
  2015. *
  2016. * Endpoint operations
  2017. *
  2018. ******************************************************************************
  2019. */
  2020. /**
  2021. * Open endpoint
  2022. *
  2023. * @v ep USB endpoint
  2024. * @ret rc Return status code
  2025. */
  2026. static int xhci_endpoint_open ( struct usb_endpoint *ep ) {
  2027. struct usb_device *usb = ep->usb;
  2028. struct xhci_slot *slot = usb_get_hostdata ( usb );
  2029. struct xhci_device *xhci = slot->xhci;
  2030. struct xhci_endpoint *endpoint;
  2031. unsigned int ctx;
  2032. unsigned int type;
  2033. unsigned int interval;
  2034. int rc;
  2035. /* Calculate context index */
  2036. ctx = XHCI_CTX ( ep->address );
  2037. assert ( slot->endpoint[ctx] == NULL );
  2038. /* Calculate endpoint type */
  2039. type = XHCI_EP_TYPE ( ep->attributes & USB_ENDPOINT_ATTR_TYPE_MASK );
  2040. if ( type == XHCI_EP_TYPE ( USB_ENDPOINT_ATTR_CONTROL ) )
  2041. type = XHCI_EP_TYPE_CONTROL;
  2042. if ( ep->address & USB_DIR_IN )
  2043. type |= XHCI_EP_TYPE_IN;
  2044. /* Calculate interval */
  2045. if ( type & XHCI_EP_TYPE_PERIODIC ) {
  2046. interval = ( fls ( ep->interval ) - 1 );
  2047. } else {
  2048. interval = ep->interval;
  2049. }
  2050. /* Allocate and initialise structure */
  2051. endpoint = zalloc ( sizeof ( *endpoint ) );
  2052. if ( ! endpoint ) {
  2053. rc = -ENOMEM;
  2054. goto err_alloc;
  2055. }
  2056. usb_endpoint_set_hostdata ( ep, endpoint );
  2057. slot->endpoint[ctx] = endpoint;
  2058. endpoint->xhci = xhci;
  2059. endpoint->slot = slot;
  2060. endpoint->ep = ep;
  2061. endpoint->ctx = ctx;
  2062. endpoint->type = type;
  2063. endpoint->interval = interval;
  2064. endpoint->context = ( ( ( void * ) slot->context ) +
  2065. xhci_device_context_offset ( xhci, ctx ) );
  2066. /* Allocate transfer ring */
  2067. if ( ( rc = xhci_ring_alloc ( xhci, &endpoint->ring,
  2068. XHCI_TRANSFER_TRBS_LOG2,
  2069. slot->id, ctx, 0 ) ) != 0 )
  2070. goto err_ring_alloc;
  2071. /* Configure endpoint, if applicable */
  2072. if ( ( ctx != XHCI_CTX_EP0 ) &&
  2073. ( ( rc = xhci_configure_endpoint ( xhci, slot, endpoint ) ) != 0 ))
  2074. goto err_configure_endpoint;
  2075. DBGC2 ( xhci, "XHCI %s slot %d ctx %d ring [%08lx,%08lx)\n",
  2076. xhci->name, slot->id, ctx, virt_to_phys ( endpoint->ring.trb ),
  2077. ( virt_to_phys ( endpoint->ring.trb ) + endpoint->ring.len ) );
  2078. return 0;
  2079. xhci_deconfigure_endpoint ( xhci, slot, endpoint );
  2080. err_configure_endpoint:
  2081. xhci_ring_free ( &endpoint->ring );
  2082. err_ring_alloc:
  2083. slot->endpoint[ctx] = NULL;
  2084. free ( endpoint );
  2085. err_alloc:
  2086. return rc;
  2087. }
  2088. /**
  2089. * Close endpoint
  2090. *
  2091. * @v ep USB endpoint
  2092. */
  2093. static void xhci_endpoint_close ( struct usb_endpoint *ep ) {
  2094. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2095. struct xhci_slot *slot = endpoint->slot;
  2096. struct xhci_device *xhci = slot->xhci;
  2097. struct io_buffer *iobuf;
  2098. unsigned int ctx = endpoint->ctx;
  2099. /* Deconfigure endpoint, if applicable */
  2100. if ( ctx != XHCI_CTX_EP0 )
  2101. xhci_deconfigure_endpoint ( xhci, slot, endpoint );
  2102. /* Cancel any incomplete transfers */
  2103. while ( xhci_ring_fill ( &endpoint->ring ) ) {
  2104. iobuf = xhci_dequeue_multi ( &endpoint->ring );
  2105. usb_complete_err ( ep, iobuf, -ECANCELED );
  2106. }
  2107. /* Free endpoint */
  2108. xhci_ring_free ( &endpoint->ring );
  2109. slot->endpoint[ctx] = NULL;
  2110. free ( endpoint );
  2111. }
  2112. /**
  2113. * Reset endpoint
  2114. *
  2115. * @v ep USB endpoint
  2116. * @ret rc Return status code
  2117. */
  2118. static int xhci_endpoint_reset ( struct usb_endpoint *ep ) {
  2119. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2120. struct xhci_slot *slot = endpoint->slot;
  2121. struct xhci_device *xhci = slot->xhci;
  2122. int rc;
  2123. /* Reset endpoint context */
  2124. if ( ( rc = xhci_reset_endpoint ( xhci, slot, endpoint ) ) != 0 )
  2125. return rc;
  2126. /* Set transfer ring dequeue pointer */
  2127. if ( ( rc = xhci_set_tr_dequeue_pointer ( xhci, slot, endpoint ) ) != 0)
  2128. return rc;
  2129. /* Ring doorbell to resume processing */
  2130. xhci_doorbell ( &endpoint->ring );
  2131. DBGC ( xhci, "XHCI %s slot %d ctx %d reset\n",
  2132. xhci->name, slot->id, endpoint->ctx );
  2133. return 0;
  2134. }
  2135. /**
  2136. * Update MTU
  2137. *
  2138. * @v ep USB endpoint
  2139. * @ret rc Return status code
  2140. */
  2141. static int xhci_endpoint_mtu ( struct usb_endpoint *ep ) {
  2142. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2143. struct xhci_slot *slot = endpoint->slot;
  2144. struct xhci_device *xhci = slot->xhci;
  2145. int rc;
  2146. /* Evalulate context */
  2147. if ( ( rc = xhci_evaluate_context ( xhci, slot, endpoint ) ) != 0 )
  2148. return rc;
  2149. return 0;
  2150. }
  2151. /**
  2152. * Enqueue message transfer
  2153. *
  2154. * @v ep USB endpoint
  2155. * @v iobuf I/O buffer
  2156. * @ret rc Return status code
  2157. */
  2158. static int xhci_endpoint_message ( struct usb_endpoint *ep,
  2159. struct io_buffer *iobuf ) {
  2160. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2161. struct usb_setup_packet *packet;
  2162. unsigned int input;
  2163. size_t len;
  2164. union xhci_trb trbs[ 1 /* setup */ + 1 /* possible data */ +
  2165. 1 /* status */ ];
  2166. union xhci_trb *trb = trbs;
  2167. struct xhci_trb_setup *setup;
  2168. struct xhci_trb_data *data;
  2169. struct xhci_trb_status *status;
  2170. int rc;
  2171. /* Profile message transfers */
  2172. profile_start ( &xhci_message_profiler );
  2173. /* Construct setup stage TRB */
  2174. memset ( trbs, 0, sizeof ( trbs ) );
  2175. assert ( iob_len ( iobuf ) >= sizeof ( *packet ) );
  2176. packet = iobuf->data;
  2177. iob_pull ( iobuf, sizeof ( *packet ) );
  2178. setup = &(trb++)->setup;
  2179. memcpy ( &setup->packet, packet, sizeof ( setup->packet ) );
  2180. setup->len = cpu_to_le32 ( sizeof ( *packet ) );
  2181. setup->flags = XHCI_TRB_IDT;
  2182. setup->type = XHCI_TRB_SETUP;
  2183. len = iob_len ( iobuf );
  2184. input = ( packet->request & cpu_to_le16 ( USB_DIR_IN ) );
  2185. if ( len )
  2186. setup->direction = ( input ? XHCI_SETUP_IN : XHCI_SETUP_OUT );
  2187. /* Construct data stage TRB, if applicable */
  2188. if ( len ) {
  2189. data = &(trb++)->data;
  2190. data->data = cpu_to_le64 ( virt_to_phys ( iobuf->data ) );
  2191. data->len = cpu_to_le32 ( len );
  2192. data->type = XHCI_TRB_DATA;
  2193. data->direction = ( input ? XHCI_DATA_IN : XHCI_DATA_OUT );
  2194. }
  2195. /* Construct status stage TRB */
  2196. status = &(trb++)->status;
  2197. status->flags = XHCI_TRB_IOC;
  2198. status->type = XHCI_TRB_STATUS;
  2199. status->direction =
  2200. ( ( len && input ) ? XHCI_STATUS_OUT : XHCI_STATUS_IN );
  2201. /* Enqueue TRBs */
  2202. if ( ( rc = xhci_enqueue_multi ( &endpoint->ring, iobuf, trbs,
  2203. ( trb - trbs ) ) ) != 0 )
  2204. return rc;
  2205. /* Ring the doorbell */
  2206. xhci_doorbell ( &endpoint->ring );
  2207. profile_stop ( &xhci_message_profiler );
  2208. return 0;
  2209. }
  2210. /**
  2211. * Enqueue stream transfer
  2212. *
  2213. * @v ep USB endpoint
  2214. * @v iobuf I/O buffer
  2215. * @v terminate Terminate using a short packet
  2216. * @ret rc Return status code
  2217. */
  2218. static int xhci_endpoint_stream ( struct usb_endpoint *ep,
  2219. struct io_buffer *iobuf, int terminate ) {
  2220. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2221. union xhci_trb trbs[ 1 /* Normal */ + 1 /* Possible zero-length */ ];
  2222. union xhci_trb *trb = trbs;
  2223. struct xhci_trb_normal *normal;
  2224. size_t len = iob_len ( iobuf );
  2225. int rc;
  2226. /* Profile stream transfers */
  2227. profile_start ( &xhci_stream_profiler );
  2228. /* Construct normal TRBs */
  2229. memset ( &trbs, 0, sizeof ( trbs ) );
  2230. normal = &(trb++)->normal;
  2231. normal->data = cpu_to_le64 ( virt_to_phys ( iobuf->data ) );
  2232. normal->len = cpu_to_le32 ( len );
  2233. normal->type = XHCI_TRB_NORMAL;
  2234. if ( terminate && ( ( len & ( ep->mtu - 1 ) ) == 0 ) ) {
  2235. normal->flags = XHCI_TRB_CH;
  2236. normal = &(trb++)->normal;
  2237. normal->type = XHCI_TRB_NORMAL;
  2238. }
  2239. normal->flags = XHCI_TRB_IOC;
  2240. /* Enqueue TRBs */
  2241. if ( ( rc = xhci_enqueue_multi ( &endpoint->ring, iobuf, trbs,
  2242. ( trb - trbs ) ) ) != 0 )
  2243. return rc;
  2244. /* Ring the doorbell */
  2245. xhci_doorbell ( &endpoint->ring );
  2246. profile_stop ( &xhci_stream_profiler );
  2247. return 0;
  2248. }
  2249. /******************************************************************************
  2250. *
  2251. * Device operations
  2252. *
  2253. ******************************************************************************
  2254. */
  2255. /**
  2256. * Open device
  2257. *
  2258. * @v usb USB device
  2259. * @ret rc Return status code
  2260. */
  2261. static int xhci_device_open ( struct usb_device *usb ) {
  2262. struct xhci_device *xhci = usb_bus_get_hostdata ( usb->port->hub->bus );
  2263. struct usb_port *tt = usb_transaction_translator ( usb );
  2264. struct xhci_slot *slot;
  2265. struct xhci_slot *tt_slot;
  2266. size_t len;
  2267. int type;
  2268. int id;
  2269. int rc;
  2270. /* Determine applicable slot type */
  2271. type = xhci_port_slot_type ( xhci, usb->port->address );
  2272. if ( type < 0 ) {
  2273. rc = type;
  2274. DBGC ( xhci, "XHCI %s-%d has no slot type\n",
  2275. xhci->name, usb->port->address );
  2276. goto err_type;
  2277. }
  2278. /* Allocate a device slot number */
  2279. id = xhci_enable_slot ( xhci, type );
  2280. if ( id < 0 ) {
  2281. rc = id;
  2282. goto err_enable_slot;
  2283. }
  2284. assert ( ( id > 0 ) && ( ( unsigned int ) id <= xhci->slots ) );
  2285. assert ( xhci->slot[id] == NULL );
  2286. /* Allocate and initialise structure */
  2287. slot = zalloc ( sizeof ( *slot ) );
  2288. if ( ! slot ) {
  2289. rc = -ENOMEM;
  2290. goto err_alloc;
  2291. }
  2292. usb_set_hostdata ( usb, slot );
  2293. xhci->slot[id] = slot;
  2294. slot->xhci = xhci;
  2295. slot->usb = usb;
  2296. slot->id = id;
  2297. if ( tt ) {
  2298. tt_slot = usb_get_hostdata ( tt->hub->usb );
  2299. slot->tt_id = tt_slot->id;
  2300. slot->tt_port = tt->address;
  2301. }
  2302. /* Allocate a device context */
  2303. len = xhci_device_context_offset ( xhci, XHCI_CTX_END );
  2304. slot->context = malloc_dma ( len, xhci_align ( len ) );
  2305. if ( ! slot->context ) {
  2306. rc = -ENOMEM;
  2307. goto err_alloc_context;
  2308. }
  2309. memset ( slot->context, 0, len );
  2310. /* Set device context base address */
  2311. assert ( xhci->dcbaa[id] == 0 );
  2312. xhci->dcbaa[id] = cpu_to_le64 ( virt_to_phys ( slot->context ) );
  2313. DBGC2 ( xhci, "XHCI %s slot %d device context [%08lx,%08lx) for %s\n",
  2314. xhci->name, slot->id, virt_to_phys ( slot->context ),
  2315. ( virt_to_phys ( slot->context ) + len ), usb->name );
  2316. return 0;
  2317. xhci->dcbaa[id] = 0;
  2318. free_dma ( slot->context, len );
  2319. err_alloc_context:
  2320. xhci->slot[id] = NULL;
  2321. free ( slot );
  2322. err_alloc:
  2323. xhci_disable_slot ( xhci, id );
  2324. err_enable_slot:
  2325. err_type:
  2326. return rc;
  2327. }
  2328. /**
  2329. * Close device
  2330. *
  2331. * @v usb USB device
  2332. */
  2333. static void xhci_device_close ( struct usb_device *usb ) {
  2334. struct xhci_slot *slot = usb_get_hostdata ( usb );
  2335. struct xhci_device *xhci = slot->xhci;
  2336. size_t len = xhci_device_context_offset ( xhci, XHCI_CTX_END );
  2337. unsigned int id = slot->id;
  2338. int rc;
  2339. /* Disable slot */
  2340. if ( ( rc = xhci_disable_slot ( xhci, id ) ) != 0 ) {
  2341. /* Slot is still enabled. Leak the slot context,
  2342. * since the controller may still write to this
  2343. * memory, and leave the DCBAA entry intact.
  2344. *
  2345. * If the controller later reports that this same slot
  2346. * has been re-enabled, then some assertions will be
  2347. * triggered.
  2348. */
  2349. DBGC ( xhci, "XHCI %s slot %d leaking context memory\n",
  2350. xhci->name, slot->id );
  2351. slot->context = NULL;
  2352. }
  2353. /* Free slot */
  2354. if ( slot->context ) {
  2355. free_dma ( slot->context, len );
  2356. xhci->dcbaa[id] = 0;
  2357. }
  2358. xhci->slot[id] = NULL;
  2359. free ( slot );
  2360. }
  2361. /**
  2362. * Assign device address
  2363. *
  2364. * @v usb USB device
  2365. * @ret rc Return status code
  2366. */
  2367. static int xhci_device_address ( struct usb_device *usb ) {
  2368. struct xhci_slot *slot = usb_get_hostdata ( usb );
  2369. struct xhci_device *xhci = slot->xhci;
  2370. struct usb_port *port = usb->port;
  2371. struct usb_port *root_port;
  2372. int psiv;
  2373. int rc;
  2374. /* Calculate route string */
  2375. slot->route = usb_route_string ( usb );
  2376. /* Calculate root hub port number */
  2377. root_port = usb_root_hub_port ( usb );
  2378. slot->port = root_port->address;
  2379. /* Calculate protocol speed ID */
  2380. psiv = xhci_port_psiv ( xhci, slot->port, port->speed );
  2381. if ( psiv < 0 ) {
  2382. rc = psiv;
  2383. return rc;
  2384. }
  2385. slot->psiv = psiv;
  2386. /* Address device */
  2387. if ( ( rc = xhci_address_device ( xhci, slot ) ) != 0 )
  2388. return rc;
  2389. return 0;
  2390. }
  2391. /******************************************************************************
  2392. *
  2393. * Bus operations
  2394. *
  2395. ******************************************************************************
  2396. */
  2397. /**
  2398. * Open USB bus
  2399. *
  2400. * @v bus USB bus
  2401. * @ret rc Return status code
  2402. */
  2403. static int xhci_bus_open ( struct usb_bus *bus ) {
  2404. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2405. int rc;
  2406. /* Allocate device slot array */
  2407. xhci->slot = zalloc ( ( xhci->slots + 1 ) * sizeof ( xhci->slot[0] ) );
  2408. if ( ! xhci->slot ) {
  2409. rc = -ENOMEM;
  2410. goto err_slot_alloc;
  2411. }
  2412. /* Allocate device context base address array */
  2413. if ( ( rc = xhci_dcbaa_alloc ( xhci ) ) != 0 )
  2414. goto err_dcbaa_alloc;
  2415. /* Allocate scratchpad buffers */
  2416. if ( ( rc = xhci_scratchpad_alloc ( xhci ) ) != 0 )
  2417. goto err_scratchpad_alloc;
  2418. /* Allocate command ring */
  2419. if ( ( rc = xhci_command_alloc ( xhci ) ) != 0 )
  2420. goto err_command_alloc;
  2421. /* Allocate event ring */
  2422. if ( ( rc = xhci_event_alloc ( xhci ) ) != 0 )
  2423. goto err_event_alloc;
  2424. /* Start controller */
  2425. xhci_run ( xhci );
  2426. return 0;
  2427. xhci_stop ( xhci );
  2428. xhci_event_free ( xhci );
  2429. err_event_alloc:
  2430. xhci_command_free ( xhci );
  2431. err_command_alloc:
  2432. xhci_scratchpad_free ( xhci );
  2433. err_scratchpad_alloc:
  2434. xhci_dcbaa_free ( xhci );
  2435. err_dcbaa_alloc:
  2436. free ( xhci->slot );
  2437. err_slot_alloc:
  2438. return rc;
  2439. }
  2440. /**
  2441. * Close USB bus
  2442. *
  2443. * @v bus USB bus
  2444. */
  2445. static void xhci_bus_close ( struct usb_bus *bus ) {
  2446. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2447. unsigned int i;
  2448. /* Sanity checks */
  2449. assert ( xhci->slot != NULL );
  2450. for ( i = 0 ; i <= xhci->slots ; i++ )
  2451. assert ( xhci->slot[i] == NULL );
  2452. xhci_stop ( xhci );
  2453. xhci_event_free ( xhci );
  2454. xhci_command_free ( xhci );
  2455. xhci_scratchpad_free ( xhci );
  2456. xhci_dcbaa_free ( xhci );
  2457. free ( xhci->slot );
  2458. }
  2459. /**
  2460. * Poll USB bus
  2461. *
  2462. * @v bus USB bus
  2463. */
  2464. static void xhci_bus_poll ( struct usb_bus *bus ) {
  2465. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2466. /* Poll event ring */
  2467. xhci_event_poll ( xhci );
  2468. }
  2469. /******************************************************************************
  2470. *
  2471. * Hub operations
  2472. *
  2473. ******************************************************************************
  2474. */
  2475. /**
  2476. * Open hub
  2477. *
  2478. * @v hub USB hub
  2479. * @ret rc Return status code
  2480. */
  2481. static int xhci_hub_open ( struct usb_hub *hub ) {
  2482. struct xhci_slot *slot;
  2483. /* Do nothing if this is the root hub */
  2484. if ( ! hub->usb )
  2485. return 0;
  2486. /* Get device slot */
  2487. slot = usb_get_hostdata ( hub->usb );
  2488. /* Update device slot hub parameters. We don't inform the
  2489. * hardware of this information until the hub's interrupt
  2490. * endpoint is opened, since the only mechanism for so doing
  2491. * provided by the xHCI specification is a Configure Endpoint
  2492. * command, and we can't issue that command until we have a
  2493. * non-EP0 endpoint to configure.
  2494. */
  2495. slot->ports = hub->ports;
  2496. return 0;
  2497. }
  2498. /**
  2499. * Close hub
  2500. *
  2501. * @v hub USB hub
  2502. */
  2503. static void xhci_hub_close ( struct usb_hub *hub __unused ) {
  2504. /* Nothing to do */
  2505. }
  2506. /******************************************************************************
  2507. *
  2508. * Root hub operations
  2509. *
  2510. ******************************************************************************
  2511. */
  2512. /**
  2513. * Open root hub
  2514. *
  2515. * @v hub USB hub
  2516. * @ret rc Return status code
  2517. */
  2518. static int xhci_root_open ( struct usb_hub *hub ) {
  2519. struct usb_bus *bus = hub->bus;
  2520. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2521. struct usb_port *port;
  2522. uint32_t portsc;
  2523. unsigned int i;
  2524. /* Enable power to all ports */
  2525. for ( i = 1 ; i <= xhci->ports ; i++ ) {
  2526. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( i ) );
  2527. portsc &= XHCI_PORTSC_PRESERVE;
  2528. portsc |= XHCI_PORTSC_PP;
  2529. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( i ) );
  2530. }
  2531. /* xHCI spec requires us to potentially wait 20ms after
  2532. * enabling power to a port.
  2533. */
  2534. mdelay ( XHCI_PORT_POWER_DELAY_MS );
  2535. /* USB3 ports may power up as Disabled */
  2536. for ( i = 1 ; i <= xhci->ports ; i++ ) {
  2537. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( i ) );
  2538. port = usb_port ( hub, i );
  2539. if ( ( port->protocol >= USB_PROTO_3_0 ) &&
  2540. ( ( portsc & XHCI_PORTSC_PLS_MASK ) ==
  2541. XHCI_PORTSC_PLS_DISABLED ) ) {
  2542. /* Force link state to RxDetect */
  2543. portsc &= XHCI_PORTSC_PRESERVE;
  2544. portsc |= ( XHCI_PORTSC_PLS_RXDETECT | XHCI_PORTSC_LWS);
  2545. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( i ) );
  2546. }
  2547. }
  2548. /* Some xHCI cards seem to require an additional delay after
  2549. * setting the link state to RxDetect.
  2550. */
  2551. mdelay ( XHCI_LINK_STATE_DELAY_MS );
  2552. /* Record hub driver private data */
  2553. usb_hub_set_drvdata ( hub, xhci );
  2554. return 0;
  2555. }
  2556. /**
  2557. * Close root hub
  2558. *
  2559. * @v hub USB hub
  2560. */
  2561. static void xhci_root_close ( struct usb_hub *hub ) {
  2562. /* Clear hub driver private data */
  2563. usb_hub_set_drvdata ( hub, NULL );
  2564. }
  2565. /**
  2566. * Enable port
  2567. *
  2568. * @v hub USB hub
  2569. * @v port USB port
  2570. * @ret rc Return status code
  2571. */
  2572. static int xhci_root_enable ( struct usb_hub *hub, struct usb_port *port ) {
  2573. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2574. uint32_t portsc;
  2575. unsigned int i;
  2576. /* Reset port */
  2577. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2578. portsc &= XHCI_PORTSC_PRESERVE;
  2579. portsc |= XHCI_PORTSC_PR;
  2580. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2581. /* Wait for port to become enabled */
  2582. for ( i = 0 ; i < XHCI_PORT_RESET_MAX_WAIT_MS ; i++ ) {
  2583. /* Check port status */
  2584. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2585. if ( portsc & XHCI_PORTSC_PED )
  2586. return 0;
  2587. /* Delay */
  2588. mdelay ( 1 );
  2589. }
  2590. DBGC ( xhci, "XHCI %s-%d timed out waiting for port to enable\n",
  2591. xhci->name, port->address );
  2592. return -ETIMEDOUT;
  2593. }
  2594. /**
  2595. * Disable port
  2596. *
  2597. * @v hub USB hub
  2598. * @v port USB port
  2599. * @ret rc Return status code
  2600. */
  2601. static int xhci_root_disable ( struct usb_hub *hub, struct usb_port *port ) {
  2602. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2603. uint32_t portsc;
  2604. /* Disable port */
  2605. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2606. portsc &= XHCI_PORTSC_PRESERVE;
  2607. portsc |= XHCI_PORTSC_PED;
  2608. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2609. return 0;
  2610. }
  2611. /**
  2612. * Update root hub port speed
  2613. *
  2614. * @v hub USB hub
  2615. * @v port USB port
  2616. * @ret rc Return status code
  2617. */
  2618. static int xhci_root_speed ( struct usb_hub *hub, struct usb_port *port ) {
  2619. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2620. uint32_t portsc;
  2621. unsigned int psiv;
  2622. int ccs;
  2623. int ped;
  2624. int csc;
  2625. int speed;
  2626. int rc;
  2627. /* Read port status */
  2628. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2629. DBGC2 ( xhci, "XHCI %s-%d status is %08x\n",
  2630. xhci->name, port->address, portsc );
  2631. ccs = ( portsc & XHCI_PORTSC_CCS );
  2632. ped = ( portsc & XHCI_PORTSC_PED );
  2633. csc = ( portsc & XHCI_PORTSC_CSC );
  2634. psiv = XHCI_PORTSC_PSIV ( portsc );
  2635. /* Record disconnections and clear changes */
  2636. port->disconnected |= csc;
  2637. portsc &= ( XHCI_PORTSC_PRESERVE | XHCI_PORTSC_CHANGE );
  2638. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2639. /* Port speed is not valid unless port is connected */
  2640. if ( ! ccs ) {
  2641. port->speed = USB_SPEED_NONE;
  2642. return 0;
  2643. }
  2644. /* For USB2 ports, the PSIV field is not valid until the port
  2645. * completes reset and becomes enabled.
  2646. */
  2647. if ( ( port->protocol < USB_PROTO_3_0 ) && ! ped ) {
  2648. port->speed = USB_SPEED_FULL;
  2649. return 0;
  2650. }
  2651. /* Get port speed and map to generic USB speed */
  2652. speed = xhci_port_speed ( xhci, port->address, psiv );
  2653. if ( speed < 0 ) {
  2654. rc = speed;
  2655. return rc;
  2656. }
  2657. port->speed = speed;
  2658. return 0;
  2659. }
  2660. /**
  2661. * Clear transaction translator buffer
  2662. *
  2663. * @v hub USB hub
  2664. * @v port USB port
  2665. * @v ep USB endpoint
  2666. * @ret rc Return status code
  2667. */
  2668. static int xhci_root_clear_tt ( struct usb_hub *hub, struct usb_port *port,
  2669. struct usb_endpoint *ep ) {
  2670. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2671. /* Should never be called; this is a root hub */
  2672. DBGC ( xhci, "XHCI %s-%d nonsensical CLEAR_TT for %s %s\n", xhci->name,
  2673. port->address, ep->usb->name, usb_endpoint_name ( ep ) );
  2674. return -ENOTSUP;
  2675. }
  2676. /******************************************************************************
  2677. *
  2678. * PCI interface
  2679. *
  2680. ******************************************************************************
  2681. */
  2682. /** USB host controller operations */
  2683. static struct usb_host_operations xhci_operations = {
  2684. .endpoint = {
  2685. .open = xhci_endpoint_open,
  2686. .close = xhci_endpoint_close,
  2687. .reset = xhci_endpoint_reset,
  2688. .mtu = xhci_endpoint_mtu,
  2689. .message = xhci_endpoint_message,
  2690. .stream = xhci_endpoint_stream,
  2691. },
  2692. .device = {
  2693. .open = xhci_device_open,
  2694. .close = xhci_device_close,
  2695. .address = xhci_device_address,
  2696. },
  2697. .bus = {
  2698. .open = xhci_bus_open,
  2699. .close = xhci_bus_close,
  2700. .poll = xhci_bus_poll,
  2701. },
  2702. .hub = {
  2703. .open = xhci_hub_open,
  2704. .close = xhci_hub_close,
  2705. },
  2706. .root = {
  2707. .open = xhci_root_open,
  2708. .close = xhci_root_close,
  2709. .enable = xhci_root_enable,
  2710. .disable = xhci_root_disable,
  2711. .speed = xhci_root_speed,
  2712. .clear_tt = xhci_root_clear_tt,
  2713. },
  2714. };
  2715. /**
  2716. * Fix Intel PCH-specific quirks
  2717. *
  2718. * @v xhci xHCI device
  2719. * @v pci PCI device
  2720. */
  2721. static void xhci_pch_fix ( struct xhci_device *xhci, struct pci_device *pci ) {
  2722. struct xhci_pch *pch = &xhci->pch;
  2723. uint32_t xusb2pr;
  2724. uint32_t xusb2prm;
  2725. uint32_t usb3pssen;
  2726. uint32_t usb3prm;
  2727. /* Enable SuperSpeed capability. Do this before rerouting
  2728. * USB2 ports, so that USB3 devices connect at SuperSpeed.
  2729. */
  2730. pci_read_config_dword ( pci, XHCI_PCH_USB3PSSEN, &usb3pssen );
  2731. pci_read_config_dword ( pci, XHCI_PCH_USB3PRM, &usb3prm );
  2732. if ( usb3prm & ~usb3pssen ) {
  2733. DBGC ( xhci, "XHCI %s enabling SuperSpeed on ports %08x\n",
  2734. xhci->name, ( usb3prm & ~usb3pssen ) );
  2735. }
  2736. pch->usb3pssen = usb3pssen;
  2737. usb3pssen |= usb3prm;
  2738. pci_write_config_dword ( pci, XHCI_PCH_USB3PSSEN, usb3pssen );
  2739. /* Route USB2 ports from EHCI to xHCI */
  2740. pci_read_config_dword ( pci, XHCI_PCH_XUSB2PR, &xusb2pr );
  2741. pci_read_config_dword ( pci, XHCI_PCH_XUSB2PRM, &xusb2prm );
  2742. if ( xusb2prm & ~xusb2pr ) {
  2743. DBGC ( xhci, "XHCI %s routing ports %08x from EHCI to xHCI\n",
  2744. xhci->name, ( xusb2prm & ~xusb2pr ) );
  2745. }
  2746. pch->xusb2pr = xusb2pr;
  2747. xusb2pr |= xusb2prm;
  2748. pci_write_config_dword ( pci, XHCI_PCH_XUSB2PR, xusb2pr );
  2749. }
  2750. /**
  2751. * Undo Intel PCH-specific quirk fixes
  2752. *
  2753. * @v xhci xHCI device
  2754. * @v pci PCI device
  2755. */
  2756. static void xhci_pch_undo ( struct xhci_device *xhci, struct pci_device *pci ) {
  2757. struct xhci_pch *pch = &xhci->pch;
  2758. /* Restore USB2 port routing to original state */
  2759. pci_write_config_dword ( pci, XHCI_PCH_XUSB2PR, pch->xusb2pr );
  2760. /* Restore SuperSpeed capability to original state */
  2761. pci_write_config_dword ( pci, XHCI_PCH_USB3PSSEN, pch->usb3pssen );
  2762. }
  2763. /**
  2764. * Probe PCI device
  2765. *
  2766. * @v pci PCI device
  2767. * @ret rc Return status code
  2768. */
  2769. static int xhci_probe ( struct pci_device *pci ) {
  2770. struct xhci_device *xhci;
  2771. struct usb_port *port;
  2772. unsigned long bar_start;
  2773. size_t bar_size;
  2774. unsigned int i;
  2775. int rc;
  2776. /* Allocate and initialise structure */
  2777. xhci = zalloc ( sizeof ( *xhci ) );
  2778. if ( ! xhci ) {
  2779. rc = -ENOMEM;
  2780. goto err_alloc;
  2781. }
  2782. xhci->name = pci->dev.name;
  2783. xhci->quirks = pci->id->driver_data;
  2784. /* Fix up PCI device */
  2785. adjust_pci_device ( pci );
  2786. /* Map registers */
  2787. bar_start = pci_bar_start ( pci, XHCI_BAR );
  2788. bar_size = pci_bar_size ( pci, XHCI_BAR );
  2789. xhci->regs = ioremap ( bar_start, bar_size );
  2790. if ( ! xhci->regs ) {
  2791. rc = -ENODEV;
  2792. goto err_ioremap;
  2793. }
  2794. /* Initialise xHCI device */
  2795. xhci_init ( xhci, xhci->regs );
  2796. /* Initialise USB legacy support and claim ownership */
  2797. xhci_legacy_init ( xhci );
  2798. xhci_legacy_claim ( xhci );
  2799. /* Fix Intel PCH-specific quirks, if applicable */
  2800. if ( xhci->quirks & XHCI_PCH )
  2801. xhci_pch_fix ( xhci, pci );
  2802. /* Reset device */
  2803. if ( ( rc = xhci_reset ( xhci ) ) != 0 )
  2804. goto err_reset;
  2805. /* Allocate USB bus */
  2806. xhci->bus = alloc_usb_bus ( &pci->dev, xhci->ports, XHCI_MTU,
  2807. &xhci_operations );
  2808. if ( ! xhci->bus ) {
  2809. rc = -ENOMEM;
  2810. goto err_alloc_bus;
  2811. }
  2812. usb_bus_set_hostdata ( xhci->bus, xhci );
  2813. usb_hub_set_drvdata ( xhci->bus->hub, xhci );
  2814. /* Set port protocols */
  2815. for ( i = 1 ; i <= xhci->ports ; i++ ) {
  2816. port = usb_port ( xhci->bus->hub, i );
  2817. port->protocol = xhci_port_protocol ( xhci, i );
  2818. }
  2819. /* Register USB bus */
  2820. if ( ( rc = register_usb_bus ( xhci->bus ) ) != 0 )
  2821. goto err_register;
  2822. pci_set_drvdata ( pci, xhci );
  2823. return 0;
  2824. unregister_usb_bus ( xhci->bus );
  2825. err_register:
  2826. free_usb_bus ( xhci->bus );
  2827. err_alloc_bus:
  2828. xhci_reset ( xhci );
  2829. err_reset:
  2830. if ( xhci->quirks & XHCI_PCH )
  2831. xhci_pch_undo ( xhci, pci );
  2832. xhci_legacy_release ( xhci );
  2833. iounmap ( xhci->regs );
  2834. err_ioremap:
  2835. free ( xhci );
  2836. err_alloc:
  2837. return rc;
  2838. }
  2839. /**
  2840. * Remove PCI device
  2841. *
  2842. * @v pci PCI device
  2843. */
  2844. static void xhci_remove ( struct pci_device *pci ) {
  2845. struct xhci_device *xhci = pci_get_drvdata ( pci );
  2846. struct usb_bus *bus = xhci->bus;
  2847. unregister_usb_bus ( bus );
  2848. free_usb_bus ( bus );
  2849. xhci_reset ( xhci );
  2850. if ( xhci->quirks & XHCI_PCH )
  2851. xhci_pch_undo ( xhci, pci );
  2852. xhci_legacy_release ( xhci );
  2853. iounmap ( xhci->regs );
  2854. free ( xhci );
  2855. }
  2856. /** XHCI PCI device IDs */
  2857. static struct pci_device_id xhci_ids[] = {
  2858. PCI_ROM ( 0x8086, 0x9d2f, "xhci-skylake", "xHCI (Skylake)", ( XHCI_PCH | XHCI_BAD_PSIV ) ),
  2859. PCI_ROM ( 0x8086, 0xffff, "xhci-pch", "xHCI (Intel PCH)", XHCI_PCH ),
  2860. PCI_ROM ( 0xffff, 0xffff, "xhci", "xHCI", 0 ),
  2861. };
  2862. /** XHCI PCI driver */
  2863. struct pci_driver xhci_driver __pci_driver = {
  2864. .ids = xhci_ids,
  2865. .id_count = ( sizeof ( xhci_ids ) / sizeof ( xhci_ids[0] ) ),
  2866. .class = PCI_CLASS_ID ( PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB,
  2867. PCI_CLASS_SERIAL_USB_XHCI ),
  2868. .probe = xhci_probe,
  2869. .remove = xhci_remove,
  2870. };
  2871. /**
  2872. * Prepare for exit
  2873. *
  2874. * @v booting System is shutting down for OS boot
  2875. */
  2876. static void xhci_shutdown ( int booting ) {
  2877. /* If we are shutting down to boot an OS, then prevent the
  2878. * release of ownership back to BIOS.
  2879. */
  2880. xhci_legacy_prevent_release = booting;
  2881. }
  2882. /** Startup/shutdown function */
  2883. struct startup_fn xhci_startup __startup_fn ( STARTUP_LATE ) = {
  2884. .shutdown = xhci_shutdown,
  2885. };