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hermon.c 68KB

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  1. /*
  2. * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
  3. * Copyright (C) 2008 Mellanox Technologies Ltd.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of the
  8. * License, or any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <stdint.h>
  20. #include <stdlib.h>
  21. #include <stdio.h>
  22. #include <string.h>
  23. #include <strings.h>
  24. #include <unistd.h>
  25. #include <errno.h>
  26. #include <byteswap.h>
  27. #include <gpxe/pci.h>
  28. #include <gpxe/malloc.h>
  29. #include <gpxe/umalloc.h>
  30. #include <gpxe/iobuf.h>
  31. #include <gpxe/netdevice.h>
  32. #include <gpxe/infiniband.h>
  33. #include "hermon.h"
  34. /**
  35. * @file
  36. *
  37. * Mellanox Hermon Infiniband HCA
  38. *
  39. */
  40. /***************************************************************************
  41. *
  42. * Queue number allocation
  43. *
  44. ***************************************************************************
  45. */
  46. /**
  47. * Allocate offsets within usage bitmask
  48. *
  49. * @v bits Usage bitmask
  50. * @v bits_len Length of usage bitmask
  51. * @v num_bits Number of contiguous bits to allocate within bitmask
  52. * @ret bit First free bit within bitmask, or negative error
  53. */
  54. static int hermon_bitmask_alloc ( hermon_bitmask_t *bits,
  55. unsigned int bits_len,
  56. unsigned int num_bits ) {
  57. unsigned int bit = 0;
  58. hermon_bitmask_t mask = 1;
  59. unsigned int found = 0;
  60. /* Search bits for num_bits contiguous free bits */
  61. while ( bit < bits_len ) {
  62. if ( ( mask & *bits ) == 0 ) {
  63. if ( ++found == num_bits )
  64. goto found;
  65. } else {
  66. found = 0;
  67. }
  68. bit++;
  69. mask = ( mask << 1 ) | ( mask >> ( 8 * sizeof ( mask ) - 1 ) );
  70. if ( mask == 1 )
  71. bits++;
  72. }
  73. return -ENFILE;
  74. found:
  75. /* Mark bits as in-use */
  76. do {
  77. *bits |= mask;
  78. if ( mask == 1 )
  79. bits--;
  80. mask = ( mask >> 1 ) | ( mask << ( 8 * sizeof ( mask ) - 1 ) );
  81. } while ( --found );
  82. return ( bit - num_bits + 1 );
  83. }
  84. /**
  85. * Free offsets within usage bitmask
  86. *
  87. * @v bits Usage bitmask
  88. * @v bit Starting bit within bitmask
  89. * @v num_bits Number of contiguous bits to free within bitmask
  90. */
  91. static void hermon_bitmask_free ( hermon_bitmask_t *bits,
  92. int bit, unsigned int num_bits ) {
  93. hermon_bitmask_t mask;
  94. for ( ; num_bits ; bit++, num_bits-- ) {
  95. mask = ( 1 << ( bit % ( 8 * sizeof ( mask ) ) ) );
  96. bits[ ( bit / ( 8 * sizeof ( mask ) ) ) ] &= ~mask;
  97. }
  98. }
  99. /***************************************************************************
  100. *
  101. * HCA commands
  102. *
  103. ***************************************************************************
  104. */
  105. /**
  106. * Wait for Hermon command completion
  107. *
  108. * @v hermon Hermon device
  109. * @v hcr HCA command registers
  110. * @ret rc Return status code
  111. */
  112. static int hermon_cmd_wait ( struct hermon *hermon,
  113. struct hermonprm_hca_command_register *hcr ) {
  114. unsigned int wait;
  115. for ( wait = HERMON_HCR_MAX_WAIT_MS ; wait ; wait-- ) {
  116. hcr->u.dwords[6] =
  117. readl ( hermon->config + HERMON_HCR_REG ( 6 ) );
  118. if ( ( MLX_GET ( hcr, go ) == 0 ) &&
  119. ( MLX_GET ( hcr, t ) == hermon->toggle ) )
  120. return 0;
  121. mdelay ( 1 );
  122. }
  123. return -EBUSY;
  124. }
  125. /**
  126. * Issue HCA command
  127. *
  128. * @v hermon Hermon device
  129. * @v command Command opcode, flags and input/output lengths
  130. * @v op_mod Opcode modifier (0 if no modifier applicable)
  131. * @v in Input parameters
  132. * @v in_mod Input modifier (0 if no modifier applicable)
  133. * @v out Output parameters
  134. * @ret rc Return status code
  135. */
  136. static int hermon_cmd ( struct hermon *hermon, unsigned long command,
  137. unsigned int op_mod, const void *in,
  138. unsigned int in_mod, void *out ) {
  139. struct hermonprm_hca_command_register hcr;
  140. unsigned int opcode = HERMON_HCR_OPCODE ( command );
  141. size_t in_len = HERMON_HCR_IN_LEN ( command );
  142. size_t out_len = HERMON_HCR_OUT_LEN ( command );
  143. void *in_buffer;
  144. void *out_buffer;
  145. unsigned int status;
  146. unsigned int i;
  147. int rc;
  148. assert ( in_len <= HERMON_MBOX_SIZE );
  149. assert ( out_len <= HERMON_MBOX_SIZE );
  150. DBGC2 ( hermon, "Hermon %p command %02x in %zx%s out %zx%s\n",
  151. hermon, opcode, in_len,
  152. ( ( command & HERMON_HCR_IN_MBOX ) ? "(mbox)" : "" ), out_len,
  153. ( ( command & HERMON_HCR_OUT_MBOX ) ? "(mbox)" : "" ) );
  154. /* Check that HCR is free */
  155. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  156. DBGC ( hermon, "Hermon %p command interface locked\n",
  157. hermon );
  158. return rc;
  159. }
  160. /* Flip HCR toggle */
  161. hermon->toggle = ( 1 - hermon->toggle );
  162. /* Prepare HCR */
  163. memset ( &hcr, 0, sizeof ( hcr ) );
  164. in_buffer = &hcr.u.dwords[0];
  165. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  166. in_buffer = hermon->mailbox_in;
  167. MLX_FILL_1 ( &hcr, 1, in_param_l, virt_to_bus ( in_buffer ) );
  168. }
  169. memcpy ( in_buffer, in, in_len );
  170. MLX_FILL_1 ( &hcr, 2, input_modifier, in_mod );
  171. out_buffer = &hcr.u.dwords[3];
  172. if ( out_len && ( command & HERMON_HCR_OUT_MBOX ) ) {
  173. out_buffer = hermon->mailbox_out;
  174. MLX_FILL_1 ( &hcr, 4, out_param_l,
  175. virt_to_bus ( out_buffer ) );
  176. }
  177. MLX_FILL_4 ( &hcr, 6,
  178. opcode, opcode,
  179. opcode_modifier, op_mod,
  180. go, 1,
  181. t, hermon->toggle );
  182. DBGC ( hermon, "Hermon %p issuing command:\n", hermon );
  183. DBGC_HDA ( hermon, virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  184. &hcr, sizeof ( hcr ) );
  185. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  186. DBGC2 ( hermon, "Input mailbox:\n" );
  187. DBGC2_HDA ( hermon, virt_to_phys ( in_buffer ), in_buffer,
  188. ( ( in_len < 512 ) ? in_len : 512 ) );
  189. }
  190. /* Issue command */
  191. for ( i = 0 ; i < ( sizeof ( hcr ) / sizeof ( hcr.u.dwords[0] ) ) ;
  192. i++ ) {
  193. writel ( hcr.u.dwords[i],
  194. hermon->config + HERMON_HCR_REG ( i ) );
  195. barrier();
  196. }
  197. /* Wait for command completion */
  198. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  199. DBGC ( hermon, "Hermon %p timed out waiting for command:\n",
  200. hermon );
  201. DBGC_HDA ( hermon,
  202. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  203. &hcr, sizeof ( hcr ) );
  204. return rc;
  205. }
  206. /* Check command status */
  207. status = MLX_GET ( &hcr, status );
  208. if ( status != 0 ) {
  209. DBGC ( hermon, "Hermon %p command failed with status %02x:\n",
  210. hermon, status );
  211. DBGC_HDA ( hermon,
  212. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  213. &hcr, sizeof ( hcr ) );
  214. return -EIO;
  215. }
  216. /* Read output parameters, if any */
  217. hcr.u.dwords[3] = readl ( hermon->config + HERMON_HCR_REG ( 3 ) );
  218. hcr.u.dwords[4] = readl ( hermon->config + HERMON_HCR_REG ( 4 ) );
  219. memcpy ( out, out_buffer, out_len );
  220. if ( out_len ) {
  221. DBGC2 ( hermon, "Output%s:\n",
  222. ( command & HERMON_HCR_OUT_MBOX ) ? " mailbox" : "" );
  223. DBGC2_HDA ( hermon, virt_to_phys ( out_buffer ), out_buffer,
  224. ( ( out_len < 512 ) ? out_len : 512 ) );
  225. }
  226. return 0;
  227. }
  228. static inline int
  229. hermon_cmd_query_dev_cap ( struct hermon *hermon,
  230. struct hermonprm_query_dev_cap *dev_cap ) {
  231. return hermon_cmd ( hermon,
  232. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_DEV_CAP,
  233. 1, sizeof ( *dev_cap ) ),
  234. 0, NULL, 0, dev_cap );
  235. }
  236. static inline int
  237. hermon_cmd_query_fw ( struct hermon *hermon, struct hermonprm_query_fw *fw ) {
  238. return hermon_cmd ( hermon,
  239. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_FW,
  240. 1, sizeof ( *fw ) ),
  241. 0, NULL, 0, fw );
  242. }
  243. static inline int
  244. hermon_cmd_init_hca ( struct hermon *hermon,
  245. const struct hermonprm_init_hca *init_hca ) {
  246. return hermon_cmd ( hermon,
  247. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_HCA,
  248. 1, sizeof ( *init_hca ) ),
  249. 0, init_hca, 0, NULL );
  250. }
  251. static inline int
  252. hermon_cmd_close_hca ( struct hermon *hermon ) {
  253. return hermon_cmd ( hermon,
  254. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_HCA ),
  255. 0, NULL, 0, NULL );
  256. }
  257. static inline int
  258. hermon_cmd_init_port ( struct hermon *hermon, unsigned int port,
  259. const struct hermonprm_init_port *init_port ) {
  260. return hermon_cmd ( hermon,
  261. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_PORT,
  262. 1, sizeof ( *init_port ) ),
  263. 0, init_port, port, NULL );
  264. }
  265. static inline int
  266. hermon_cmd_close_port ( struct hermon *hermon, unsigned int port ) {
  267. return hermon_cmd ( hermon,
  268. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_PORT ),
  269. 0, NULL, port, NULL );
  270. }
  271. static inline int
  272. hermon_cmd_sw2hw_mpt ( struct hermon *hermon, unsigned int index,
  273. const struct hermonprm_mpt *mpt ) {
  274. return hermon_cmd ( hermon,
  275. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_MPT,
  276. 1, sizeof ( *mpt ) ),
  277. 0, mpt, index, NULL );
  278. }
  279. static inline int
  280. hermon_cmd_write_mtt ( struct hermon *hermon,
  281. const struct hermonprm_write_mtt *write_mtt ) {
  282. return hermon_cmd ( hermon,
  283. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MTT,
  284. 1, sizeof ( *write_mtt ) ),
  285. 0, write_mtt, 1, NULL );
  286. }
  287. static inline int
  288. hermon_cmd_map_eq ( struct hermon *hermon, unsigned long index_map,
  289. const struct hermonprm_event_mask *mask ) {
  290. return hermon_cmd ( hermon,
  291. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_EQ,
  292. 0, sizeof ( *mask ) ),
  293. 0, mask, index_map, NULL );
  294. }
  295. static inline int
  296. hermon_cmd_sw2hw_eq ( struct hermon *hermon, unsigned int index,
  297. const struct hermonprm_eqc *eqctx ) {
  298. return hermon_cmd ( hermon,
  299. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_EQ,
  300. 1, sizeof ( *eqctx ) ),
  301. 0, eqctx, index, NULL );
  302. }
  303. static inline int
  304. hermon_cmd_hw2sw_eq ( struct hermon *hermon, unsigned int index,
  305. struct hermonprm_eqc *eqctx ) {
  306. return hermon_cmd ( hermon,
  307. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_EQ,
  308. 1, sizeof ( *eqctx ) ),
  309. 1, NULL, index, eqctx );
  310. }
  311. static inline int
  312. hermon_cmd_query_eq ( struct hermon *hermon, unsigned int index,
  313. struct hermonprm_eqc *eqctx ) {
  314. return hermon_cmd ( hermon,
  315. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_EQ,
  316. 1, sizeof ( *eqctx ) ),
  317. 0, NULL, index, eqctx );
  318. }
  319. static inline int
  320. hermon_cmd_sw2hw_cq ( struct hermon *hermon, unsigned long cqn,
  321. const struct hermonprm_completion_queue_context *cqctx ){
  322. return hermon_cmd ( hermon,
  323. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_CQ,
  324. 1, sizeof ( *cqctx ) ),
  325. 0, cqctx, cqn, NULL );
  326. }
  327. static inline int
  328. hermon_cmd_hw2sw_cq ( struct hermon *hermon, unsigned long cqn,
  329. struct hermonprm_completion_queue_context *cqctx) {
  330. return hermon_cmd ( hermon,
  331. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_CQ,
  332. 1, sizeof ( *cqctx ) ),
  333. 0, NULL, cqn, cqctx );
  334. }
  335. static inline int
  336. hermon_cmd_rst2init_qp ( struct hermon *hermon, unsigned long qpn,
  337. const struct hermonprm_qp_ee_state_transitions *ctx ){
  338. return hermon_cmd ( hermon,
  339. HERMON_HCR_IN_CMD ( HERMON_HCR_RST2INIT_QP,
  340. 1, sizeof ( *ctx ) ),
  341. 0, ctx, qpn, NULL );
  342. }
  343. static inline int
  344. hermon_cmd_init2rtr_qp ( struct hermon *hermon, unsigned long qpn,
  345. const struct hermonprm_qp_ee_state_transitions *ctx ){
  346. return hermon_cmd ( hermon,
  347. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT2RTR_QP,
  348. 1, sizeof ( *ctx ) ),
  349. 0, ctx, qpn, NULL );
  350. }
  351. static inline int
  352. hermon_cmd_rtr2rts_qp ( struct hermon *hermon, unsigned long qpn,
  353. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  354. return hermon_cmd ( hermon,
  355. HERMON_HCR_IN_CMD ( HERMON_HCR_RTR2RTS_QP,
  356. 1, sizeof ( *ctx ) ),
  357. 0, ctx, qpn, NULL );
  358. }
  359. static inline int
  360. hermon_cmd_rts2rts_qp ( struct hermon *hermon, unsigned long qpn,
  361. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  362. return hermon_cmd ( hermon,
  363. HERMON_HCR_IN_CMD ( HERMON_HCR_RTS2RTS_QP,
  364. 1, sizeof ( *ctx ) ),
  365. 0, ctx, qpn, NULL );
  366. }
  367. static inline int
  368. hermon_cmd_2rst_qp ( struct hermon *hermon, unsigned long qpn ) {
  369. return hermon_cmd ( hermon,
  370. HERMON_HCR_VOID_CMD ( HERMON_HCR_2RST_QP ),
  371. 0x03, NULL, qpn, NULL );
  372. }
  373. static inline int
  374. hermon_cmd_mad_ifc ( struct hermon *hermon, unsigned int port,
  375. union hermonprm_mad *mad ) {
  376. return hermon_cmd ( hermon,
  377. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MAD_IFC,
  378. 1, sizeof ( *mad ),
  379. 1, sizeof ( *mad ) ),
  380. 0x03, mad, port, mad );
  381. }
  382. static inline int
  383. hermon_cmd_read_mcg ( struct hermon *hermon, unsigned int index,
  384. struct hermonprm_mcg_entry *mcg ) {
  385. return hermon_cmd ( hermon,
  386. HERMON_HCR_OUT_CMD ( HERMON_HCR_READ_MCG,
  387. 1, sizeof ( *mcg ) ),
  388. 0, NULL, index, mcg );
  389. }
  390. static inline int
  391. hermon_cmd_write_mcg ( struct hermon *hermon, unsigned int index,
  392. const struct hermonprm_mcg_entry *mcg ) {
  393. return hermon_cmd ( hermon,
  394. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MCG,
  395. 1, sizeof ( *mcg ) ),
  396. 0, mcg, index, NULL );
  397. }
  398. static inline int
  399. hermon_cmd_mgid_hash ( struct hermon *hermon, const struct ib_gid *gid,
  400. struct hermonprm_mgm_hash *hash ) {
  401. return hermon_cmd ( hermon,
  402. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MGID_HASH,
  403. 1, sizeof ( *gid ),
  404. 0, sizeof ( *hash ) ),
  405. 0, gid, 0, hash );
  406. }
  407. static inline int
  408. hermon_cmd_run_fw ( struct hermon *hermon ) {
  409. return hermon_cmd ( hermon,
  410. HERMON_HCR_VOID_CMD ( HERMON_HCR_RUN_FW ),
  411. 0, NULL, 0, NULL );
  412. }
  413. static inline int
  414. hermon_cmd_unmap_icm ( struct hermon *hermon, unsigned int page_count,
  415. const struct hermonprm_scalar_parameter *offset ) {
  416. return hermon_cmd ( hermon,
  417. HERMON_HCR_IN_CMD ( HERMON_HCR_UNMAP_ICM,
  418. 0, sizeof ( *offset ) ),
  419. 0, offset, page_count, NULL );
  420. }
  421. static inline int
  422. hermon_cmd_map_icm ( struct hermon *hermon,
  423. const struct hermonprm_virtual_physical_mapping *map ) {
  424. return hermon_cmd ( hermon,
  425. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM,
  426. 1, sizeof ( *map ) ),
  427. 0, map, 1, NULL );
  428. }
  429. static inline int
  430. hermon_cmd_unmap_icm_aux ( struct hermon *hermon ) {
  431. return hermon_cmd ( hermon,
  432. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_ICM_AUX ),
  433. 0, NULL, 0, NULL );
  434. }
  435. static inline int
  436. hermon_cmd_map_icm_aux ( struct hermon *hermon,
  437. const struct hermonprm_virtual_physical_mapping *map ) {
  438. return hermon_cmd ( hermon,
  439. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM_AUX,
  440. 1, sizeof ( *map ) ),
  441. 0, map, 1, NULL );
  442. }
  443. static inline int
  444. hermon_cmd_set_icm_size ( struct hermon *hermon,
  445. const struct hermonprm_scalar_parameter *icm_size,
  446. struct hermonprm_scalar_parameter *icm_aux_size ) {
  447. return hermon_cmd ( hermon,
  448. HERMON_HCR_INOUT_CMD ( HERMON_HCR_SET_ICM_SIZE,
  449. 0, sizeof ( *icm_size ),
  450. 0, sizeof (*icm_aux_size) ),
  451. 0, icm_size, 0, icm_aux_size );
  452. }
  453. static inline int
  454. hermon_cmd_unmap_fa ( struct hermon *hermon ) {
  455. return hermon_cmd ( hermon,
  456. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_FA ),
  457. 0, NULL, 0, NULL );
  458. }
  459. static inline int
  460. hermon_cmd_map_fa ( struct hermon *hermon,
  461. const struct hermonprm_virtual_physical_mapping *map ) {
  462. return hermon_cmd ( hermon,
  463. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_FA,
  464. 1, sizeof ( *map ) ),
  465. 0, map, 1, NULL );
  466. }
  467. /***************************************************************************
  468. *
  469. * Memory translation table operations
  470. *
  471. ***************************************************************************
  472. */
  473. /**
  474. * Allocate MTT entries
  475. *
  476. * @v hermon Hermon device
  477. * @v memory Memory to map into MTT
  478. * @v len Length of memory to map
  479. * @v mtt MTT descriptor to fill in
  480. * @ret rc Return status code
  481. */
  482. static int hermon_alloc_mtt ( struct hermon *hermon,
  483. const void *memory, size_t len,
  484. struct hermon_mtt *mtt ) {
  485. struct hermonprm_write_mtt write_mtt;
  486. physaddr_t start;
  487. unsigned int page_offset;
  488. unsigned int num_pages;
  489. int mtt_offset;
  490. unsigned int mtt_base_addr;
  491. unsigned int i;
  492. int rc;
  493. /* Find available MTT entries */
  494. start = virt_to_phys ( memory );
  495. page_offset = ( start & ( HERMON_PAGE_SIZE - 1 ) );
  496. start -= page_offset;
  497. len += page_offset;
  498. num_pages = ( ( len + HERMON_PAGE_SIZE - 1 ) / HERMON_PAGE_SIZE );
  499. mtt_offset = hermon_bitmask_alloc ( hermon->mtt_inuse, HERMON_MAX_MTTS,
  500. num_pages );
  501. if ( mtt_offset < 0 ) {
  502. DBGC ( hermon, "Hermon %p could not allocate %d MTT entries\n",
  503. hermon, num_pages );
  504. rc = mtt_offset;
  505. goto err_mtt_offset;
  506. }
  507. mtt_base_addr = ( ( hermon->cap.reserved_mtts + mtt_offset ) *
  508. hermon->cap.mtt_entry_size );
  509. /* Fill in MTT structure */
  510. mtt->mtt_offset = mtt_offset;
  511. mtt->num_pages = num_pages;
  512. mtt->mtt_base_addr = mtt_base_addr;
  513. mtt->page_offset = page_offset;
  514. /* Construct and issue WRITE_MTT commands */
  515. for ( i = 0 ; i < num_pages ; i++ ) {
  516. memset ( &write_mtt, 0, sizeof ( write_mtt ) );
  517. MLX_FILL_1 ( &write_mtt.mtt_base_addr, 1,
  518. value, mtt_base_addr );
  519. MLX_FILL_2 ( &write_mtt.mtt, 1,
  520. p, 1,
  521. ptag_l, ( start >> 3 ) );
  522. if ( ( rc = hermon_cmd_write_mtt ( hermon,
  523. &write_mtt ) ) != 0 ) {
  524. DBGC ( hermon, "Hermon %p could not write MTT at %x\n",
  525. hermon, mtt_base_addr );
  526. goto err_write_mtt;
  527. }
  528. start += HERMON_PAGE_SIZE;
  529. mtt_base_addr += hermon->cap.mtt_entry_size;
  530. }
  531. return 0;
  532. err_write_mtt:
  533. hermon_bitmask_free ( hermon->mtt_inuse, mtt_offset, num_pages );
  534. err_mtt_offset:
  535. return rc;
  536. }
  537. /**
  538. * Free MTT entries
  539. *
  540. * @v hermon Hermon device
  541. * @v mtt MTT descriptor
  542. */
  543. static void hermon_free_mtt ( struct hermon *hermon,
  544. struct hermon_mtt *mtt ) {
  545. hermon_bitmask_free ( hermon->mtt_inuse, mtt->mtt_offset,
  546. mtt->num_pages );
  547. }
  548. /***************************************************************************
  549. *
  550. * Completion queue operations
  551. *
  552. ***************************************************************************
  553. */
  554. /**
  555. * Create completion queue
  556. *
  557. * @v ibdev Infiniband device
  558. * @v cq Completion queue
  559. * @ret rc Return status code
  560. */
  561. static int hermon_create_cq ( struct ib_device *ibdev,
  562. struct ib_completion_queue *cq ) {
  563. struct hermon *hermon = ib_get_drvdata ( ibdev );
  564. struct hermon_completion_queue *hermon_cq;
  565. struct hermonprm_completion_queue_context cqctx;
  566. int cqn_offset;
  567. unsigned int i;
  568. int rc;
  569. /* Find a free completion queue number */
  570. cqn_offset = hermon_bitmask_alloc ( hermon->cq_inuse,
  571. HERMON_MAX_CQS, 1 );
  572. if ( cqn_offset < 0 ) {
  573. DBGC ( hermon, "Hermon %p out of completion queues\n",
  574. hermon );
  575. rc = cqn_offset;
  576. goto err_cqn_offset;
  577. }
  578. cq->cqn = ( hermon->cap.reserved_cqs + cqn_offset );
  579. /* Allocate control structures */
  580. hermon_cq = zalloc ( sizeof ( *hermon_cq ) );
  581. if ( ! hermon_cq ) {
  582. rc = -ENOMEM;
  583. goto err_hermon_cq;
  584. }
  585. /* Allocate completion queue itself */
  586. hermon_cq->cqe_size = ( cq->num_cqes * sizeof ( hermon_cq->cqe[0] ) );
  587. hermon_cq->cqe = malloc_dma ( hermon_cq->cqe_size,
  588. sizeof ( hermon_cq->cqe[0] ) );
  589. if ( ! hermon_cq->cqe ) {
  590. rc = -ENOMEM;
  591. goto err_cqe;
  592. }
  593. memset ( hermon_cq->cqe, 0, hermon_cq->cqe_size );
  594. for ( i = 0 ; i < cq->num_cqes ; i++ ) {
  595. MLX_FILL_1 ( &hermon_cq->cqe[i].normal, 7, owner, 1 );
  596. }
  597. barrier();
  598. /* Allocate MTT entries */
  599. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_cq->cqe,
  600. hermon_cq->cqe_size,
  601. &hermon_cq->mtt ) ) != 0 )
  602. goto err_alloc_mtt;
  603. /* Hand queue over to hardware */
  604. memset ( &cqctx, 0, sizeof ( cqctx ) );
  605. MLX_FILL_1 ( &cqctx, 0, st, 0xa /* "Event fired" */ );
  606. MLX_FILL_1 ( &cqctx, 2,
  607. page_offset, ( hermon_cq->mtt.page_offset >> 5 ) );
  608. MLX_FILL_2 ( &cqctx, 3,
  609. usr_page, HERMON_UAR_NON_EQ_PAGE,
  610. log_cq_size, fls ( cq->num_cqes - 1 ) );
  611. MLX_FILL_1 ( &cqctx, 7, mtt_base_addr_l,
  612. ( hermon_cq->mtt.mtt_base_addr >> 3 ) );
  613. MLX_FILL_1 ( &cqctx, 15, db_record_addr_l,
  614. ( virt_to_phys ( &hermon_cq->doorbell ) >> 3 ) );
  615. if ( ( rc = hermon_cmd_sw2hw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  616. DBGC ( hermon, "Hermon %p SW2HW_CQ failed: %s\n",
  617. hermon, strerror ( rc ) );
  618. goto err_sw2hw_cq;
  619. }
  620. DBGC ( hermon, "Hermon %p CQN %#lx ring at [%p,%p)\n",
  621. hermon, cq->cqn, hermon_cq->cqe,
  622. ( ( ( void * ) hermon_cq->cqe ) + hermon_cq->cqe_size ) );
  623. ib_cq_set_drvdata ( cq, hermon_cq );
  624. return 0;
  625. err_sw2hw_cq:
  626. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  627. err_alloc_mtt:
  628. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  629. err_cqe:
  630. free ( hermon_cq );
  631. err_hermon_cq:
  632. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  633. err_cqn_offset:
  634. return rc;
  635. }
  636. /**
  637. * Destroy completion queue
  638. *
  639. * @v ibdev Infiniband device
  640. * @v cq Completion queue
  641. */
  642. static void hermon_destroy_cq ( struct ib_device *ibdev,
  643. struct ib_completion_queue *cq ) {
  644. struct hermon *hermon = ib_get_drvdata ( ibdev );
  645. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  646. struct hermonprm_completion_queue_context cqctx;
  647. int cqn_offset;
  648. int rc;
  649. /* Take ownership back from hardware */
  650. if ( ( rc = hermon_cmd_hw2sw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  651. DBGC ( hermon, "Hermon %p FATAL HW2SW_CQ failed on CQN %#lx: "
  652. "%s\n", hermon, cq->cqn, strerror ( rc ) );
  653. /* Leak memory and return; at least we avoid corruption */
  654. return;
  655. }
  656. /* Free MTT entries */
  657. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  658. /* Free memory */
  659. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  660. free ( hermon_cq );
  661. /* Mark queue number as free */
  662. cqn_offset = ( cq->cqn - hermon->cap.reserved_cqs );
  663. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  664. ib_cq_set_drvdata ( cq, NULL );
  665. }
  666. /***************************************************************************
  667. *
  668. * Queue pair operations
  669. *
  670. ***************************************************************************
  671. */
  672. /**
  673. * Create queue pair
  674. *
  675. * @v ibdev Infiniband device
  676. * @v qp Queue pair
  677. * @ret rc Return status code
  678. */
  679. static int hermon_create_qp ( struct ib_device *ibdev,
  680. struct ib_queue_pair *qp ) {
  681. struct hermon *hermon = ib_get_drvdata ( ibdev );
  682. struct hermon_queue_pair *hermon_qp;
  683. struct hermonprm_qp_ee_state_transitions qpctx;
  684. int qpn_offset;
  685. int rc;
  686. /* Find a free queue pair number */
  687. qpn_offset = hermon_bitmask_alloc ( hermon->qp_inuse,
  688. HERMON_MAX_QPS, 1 );
  689. if ( qpn_offset < 0 ) {
  690. DBGC ( hermon, "Hermon %p out of queue pairs\n", hermon );
  691. rc = qpn_offset;
  692. goto err_qpn_offset;
  693. }
  694. qp->qpn = ( HERMON_QPN_BASE + hermon->cap.reserved_qps +
  695. qpn_offset );
  696. /* Allocate control structures */
  697. hermon_qp = zalloc ( sizeof ( *hermon_qp ) );
  698. if ( ! hermon_qp ) {
  699. rc = -ENOMEM;
  700. goto err_hermon_qp;
  701. }
  702. /* Calculate doorbell address */
  703. hermon_qp->send.doorbell =
  704. ( hermon->uar + HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE +
  705. HERMON_DB_POST_SND_OFFSET );
  706. /* Allocate work queue buffer */
  707. hermon_qp->send.num_wqes = ( qp->send.num_wqes /* headroom */ + 1 +
  708. ( 2048 / sizeof ( hermon_qp->send.wqe[0] ) ) );
  709. hermon_qp->send.num_wqes =
  710. ( 1 << fls ( hermon_qp->send.num_wqes - 1 ) ); /* round up */
  711. hermon_qp->send.wqe_size = ( hermon_qp->send.num_wqes *
  712. sizeof ( hermon_qp->send.wqe[0] ) );
  713. hermon_qp->recv.wqe_size = ( qp->recv.num_wqes *
  714. sizeof ( hermon_qp->recv.wqe[0] ) );
  715. hermon_qp->wqe_size = ( hermon_qp->send.wqe_size +
  716. hermon_qp->recv.wqe_size );
  717. hermon_qp->wqe = malloc_dma ( hermon_qp->wqe_size,
  718. sizeof ( hermon_qp->send.wqe[0] ) );
  719. if ( ! hermon_qp->wqe ) {
  720. rc = -ENOMEM;
  721. goto err_alloc_wqe;
  722. }
  723. hermon_qp->send.wqe = hermon_qp->wqe;
  724. memset ( hermon_qp->send.wqe, 0xff, hermon_qp->send.wqe_size );
  725. hermon_qp->recv.wqe = ( hermon_qp->wqe + hermon_qp->send.wqe_size );
  726. memset ( hermon_qp->recv.wqe, 0, hermon_qp->recv.wqe_size );
  727. /* Allocate MTT entries */
  728. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_qp->wqe,
  729. hermon_qp->wqe_size,
  730. &hermon_qp->mtt ) ) != 0 ) {
  731. goto err_alloc_mtt;
  732. }
  733. /* Transition queue to INIT state */
  734. memset ( &qpctx, 0, sizeof ( qpctx ) );
  735. MLX_FILL_2 ( &qpctx, 2,
  736. qpc_eec_data.pm_state, 0x03 /* Always 0x03 for UD */,
  737. qpc_eec_data.st, HERMON_ST_UD );
  738. MLX_FILL_1 ( &qpctx, 3, qpc_eec_data.pd, HERMON_GLOBAL_PD );
  739. MLX_FILL_4 ( &qpctx, 4,
  740. qpc_eec_data.log_rq_size, fls ( qp->recv.num_wqes - 1 ),
  741. qpc_eec_data.log_rq_stride,
  742. ( fls ( sizeof ( hermon_qp->recv.wqe[0] ) - 1 ) - 4 ),
  743. qpc_eec_data.log_sq_size,
  744. fls ( hermon_qp->send.num_wqes - 1 ),
  745. qpc_eec_data.log_sq_stride,
  746. ( fls ( sizeof ( hermon_qp->send.wqe[0] ) - 1 ) - 4 ) );
  747. MLX_FILL_1 ( &qpctx, 5,
  748. qpc_eec_data.usr_page, HERMON_UAR_NON_EQ_PAGE );
  749. MLX_FILL_1 ( &qpctx, 33, qpc_eec_data.cqn_snd, qp->send.cq->cqn );
  750. MLX_FILL_1 ( &qpctx, 38, qpc_eec_data.page_offset,
  751. ( hermon_qp->mtt.page_offset >> 6 ) );
  752. MLX_FILL_1 ( &qpctx, 41, qpc_eec_data.cqn_rcv, qp->recv.cq->cqn );
  753. MLX_FILL_1 ( &qpctx, 43, qpc_eec_data.db_record_addr_l,
  754. ( virt_to_phys ( &hermon_qp->recv.doorbell ) >> 2 ) );
  755. MLX_FILL_1 ( &qpctx, 44, qpc_eec_data.q_key, qp->qkey );
  756. MLX_FILL_1 ( &qpctx, 53, qpc_eec_data.mtt_base_addr_l,
  757. ( hermon_qp->mtt.mtt_base_addr >> 3 ) );
  758. if ( ( rc = hermon_cmd_rst2init_qp ( hermon, qp->qpn,
  759. &qpctx ) ) != 0 ) {
  760. DBGC ( hermon, "Hermon %p RST2INIT_QP failed: %s\n",
  761. hermon, strerror ( rc ) );
  762. goto err_rst2init_qp;
  763. }
  764. /* Transition queue to RTR state */
  765. memset ( &qpctx, 0, sizeof ( qpctx ) );
  766. MLX_FILL_2 ( &qpctx, 4,
  767. qpc_eec_data.mtu, HERMON_MTU_2048,
  768. qpc_eec_data.msg_max, 11 /* 2^11 = 2048 */ );
  769. MLX_FILL_1 ( &qpctx, 16,
  770. qpc_eec_data.primary_address_path.sched_queue,
  771. ( 0x83 /* default policy */ |
  772. ( ( ibdev->port - 1 ) << 6 ) ) );
  773. if ( ( rc = hermon_cmd_init2rtr_qp ( hermon, qp->qpn,
  774. &qpctx ) ) != 0 ) {
  775. DBGC ( hermon, "Hermon %p INIT2RTR_QP failed: %s\n",
  776. hermon, strerror ( rc ) );
  777. goto err_init2rtr_qp;
  778. }
  779. memset ( &qpctx, 0, sizeof ( qpctx ) );
  780. if ( ( rc = hermon_cmd_rtr2rts_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ){
  781. DBGC ( hermon, "Hermon %p RTR2RTS_QP failed: %s\n",
  782. hermon, strerror ( rc ) );
  783. goto err_rtr2rts_qp;
  784. }
  785. DBGC ( hermon, "Hermon %p QPN %#lx send ring at [%p,%p)\n",
  786. hermon, qp->qpn, hermon_qp->send.wqe,
  787. ( ((void *)hermon_qp->send.wqe ) + hermon_qp->send.wqe_size ) );
  788. DBGC ( hermon, "Hermon %p QPN %#lx receive ring at [%p,%p)\n",
  789. hermon, qp->qpn, hermon_qp->recv.wqe,
  790. ( ((void *)hermon_qp->recv.wqe ) + hermon_qp->recv.wqe_size ) );
  791. ib_qp_set_drvdata ( qp, hermon_qp );
  792. return 0;
  793. err_rtr2rts_qp:
  794. err_init2rtr_qp:
  795. hermon_cmd_2rst_qp ( hermon, qp->qpn );
  796. err_rst2init_qp:
  797. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  798. err_alloc_mtt:
  799. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  800. err_alloc_wqe:
  801. free ( hermon_qp );
  802. err_hermon_qp:
  803. hermon_bitmask_free ( hermon->qp_inuse, qpn_offset, 1 );
  804. err_qpn_offset:
  805. return rc;
  806. }
  807. /**
  808. * Modify queue pair
  809. *
  810. * @v ibdev Infiniband device
  811. * @v qp Queue pair
  812. * @v mod_list Modification list
  813. * @ret rc Return status code
  814. */
  815. static int hermon_modify_qp ( struct ib_device *ibdev,
  816. struct ib_queue_pair *qp,
  817. unsigned long mod_list ) {
  818. struct hermon *hermon = ib_get_drvdata ( ibdev );
  819. struct hermonprm_qp_ee_state_transitions qpctx;
  820. unsigned long optparammask = 0;
  821. int rc;
  822. /* Construct optparammask */
  823. if ( mod_list & IB_MODIFY_QKEY )
  824. optparammask |= HERMON_QP_OPT_PARAM_QKEY;
  825. /* Issue RTS2RTS_QP */
  826. memset ( &qpctx, 0, sizeof ( qpctx ) );
  827. MLX_FILL_1 ( &qpctx, 0, opt_param_mask, optparammask );
  828. MLX_FILL_1 ( &qpctx, 44, qpc_eec_data.q_key, qp->qkey );
  829. if ( ( rc = hermon_cmd_rts2rts_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ){
  830. DBGC ( hermon, "Hermon %p RTS2RTS_QP failed: %s\n",
  831. hermon, strerror ( rc ) );
  832. return rc;
  833. }
  834. return 0;
  835. }
  836. /**
  837. * Destroy queue pair
  838. *
  839. * @v ibdev Infiniband device
  840. * @v qp Queue pair
  841. */
  842. static void hermon_destroy_qp ( struct ib_device *ibdev,
  843. struct ib_queue_pair *qp ) {
  844. struct hermon *hermon = ib_get_drvdata ( ibdev );
  845. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  846. int qpn_offset;
  847. int rc;
  848. /* Take ownership back from hardware */
  849. if ( ( rc = hermon_cmd_2rst_qp ( hermon, qp->qpn ) ) != 0 ) {
  850. DBGC ( hermon, "Hermon %p FATAL 2RST_QP failed on QPN %#lx: "
  851. "%s\n", hermon, qp->qpn, strerror ( rc ) );
  852. /* Leak memory and return; at least we avoid corruption */
  853. return;
  854. }
  855. /* Free MTT entries */
  856. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  857. /* Free memory */
  858. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  859. free ( hermon_qp );
  860. /* Mark queue number as free */
  861. qpn_offset = ( qp->qpn - HERMON_QPN_BASE -
  862. hermon->cap.reserved_qps );
  863. hermon_bitmask_free ( hermon->qp_inuse, qpn_offset, 1 );
  864. ib_qp_set_drvdata ( qp, NULL );
  865. }
  866. /***************************************************************************
  867. *
  868. * Work request operations
  869. *
  870. ***************************************************************************
  871. */
  872. /** GID used for GID-less send work queue entries */
  873. static const struct ib_gid hermon_no_gid = {
  874. { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  875. };
  876. /**
  877. * Post send work queue entry
  878. *
  879. * @v ibdev Infiniband device
  880. * @v qp Queue pair
  881. * @v av Address vector
  882. * @v iobuf I/O buffer
  883. * @ret rc Return status code
  884. */
  885. static int hermon_post_send ( struct ib_device *ibdev,
  886. struct ib_queue_pair *qp,
  887. struct ib_address_vector *av,
  888. struct io_buffer *iobuf ) {
  889. struct hermon *hermon = ib_get_drvdata ( ibdev );
  890. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  891. struct ib_work_queue *wq = &qp->send;
  892. struct hermon_send_work_queue *hermon_send_wq = &hermon_qp->send;
  893. struct hermonprm_ud_send_wqe *wqe;
  894. const struct ib_gid *gid;
  895. union hermonprm_doorbell_register db_reg;
  896. unsigned int wqe_idx_mask;
  897. /* Allocate work queue entry */
  898. wqe_idx_mask = ( wq->num_wqes - 1 );
  899. if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) {
  900. DBGC ( hermon, "Hermon %p send queue full", hermon );
  901. return -ENOBUFS;
  902. }
  903. wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf;
  904. wqe = &hermon_send_wq->wqe[ wq->next_idx &
  905. ( hermon_send_wq->num_wqes - 1 ) ].ud;
  906. /* Construct work queue entry */
  907. memset ( ( ( ( void * ) wqe ) + 4 /* avoid ctrl.owner */ ), 0,
  908. ( sizeof ( *wqe ) - 4 ) );
  909. MLX_FILL_1 ( &wqe->ctrl, 1, ds, ( sizeof ( *wqe ) / 16 ) );
  910. MLX_FILL_1 ( &wqe->ctrl, 2, c, 0x03 /* generate completion */ );
  911. MLX_FILL_2 ( &wqe->ud, 0,
  912. ud_address_vector.pd, HERMON_GLOBAL_PD,
  913. ud_address_vector.port_number, ibdev->port );
  914. MLX_FILL_2 ( &wqe->ud, 1,
  915. ud_address_vector.rlid, av->dlid,
  916. ud_address_vector.g, av->gid_present );
  917. MLX_FILL_1 ( &wqe->ud, 2,
  918. ud_address_vector.max_stat_rate,
  919. ( ( ( av->rate < 2 ) || ( av->rate > 10 ) ) ?
  920. 8 : ( av->rate + 5 ) ) );
  921. MLX_FILL_1 ( &wqe->ud, 3, ud_address_vector.sl, av->sl );
  922. gid = ( av->gid_present ? &av->gid : &hermon_no_gid );
  923. memcpy ( &wqe->ud.u.dwords[4], gid, sizeof ( *gid ) );
  924. MLX_FILL_1 ( &wqe->ud, 8, destination_qp, av->dest_qp );
  925. MLX_FILL_1 ( &wqe->ud, 9, q_key, av->qkey );
  926. MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_len ( iobuf ) );
  927. MLX_FILL_1 ( &wqe->data[0], 1, l_key, hermon->reserved_lkey );
  928. MLX_FILL_1 ( &wqe->data[0], 3,
  929. local_address_l, virt_to_bus ( iobuf->data ) );
  930. barrier();
  931. MLX_FILL_2 ( &wqe->ctrl, 0,
  932. opcode, HERMON_OPCODE_SEND,
  933. owner,
  934. ( ( wq->next_idx & hermon_send_wq->num_wqes ) ? 1 : 0 ) );
  935. DBGCP ( hermon, "Hermon %p posting send WQE:\n", hermon );
  936. DBGCP_HD ( hermon, wqe, sizeof ( *wqe ) );
  937. barrier();
  938. /* Ring doorbell register */
  939. MLX_FILL_1 ( &db_reg.send, 0, qn, qp->qpn );
  940. DBGCP ( hermon, "Ringing doorbell %08lx with %08lx\n",
  941. virt_to_phys ( hermon_send_wq->doorbell ), db_reg.dword[0] );
  942. writel ( db_reg.dword[0], ( hermon_send_wq->doorbell ) );
  943. /* Update work queue's index */
  944. wq->next_idx++;
  945. return 0;
  946. }
  947. /**
  948. * Post receive work queue entry
  949. *
  950. * @v ibdev Infiniband device
  951. * @v qp Queue pair
  952. * @v iobuf I/O buffer
  953. * @ret rc Return status code
  954. */
  955. static int hermon_post_recv ( struct ib_device *ibdev,
  956. struct ib_queue_pair *qp,
  957. struct io_buffer *iobuf ) {
  958. struct hermon *hermon = ib_get_drvdata ( ibdev );
  959. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  960. struct ib_work_queue *wq = &qp->recv;
  961. struct hermon_recv_work_queue *hermon_recv_wq = &hermon_qp->recv;
  962. struct hermonprm_recv_wqe *wqe;
  963. unsigned int wqe_idx_mask;
  964. /* Allocate work queue entry */
  965. wqe_idx_mask = ( wq->num_wqes - 1 );
  966. if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) {
  967. DBGC ( hermon, "Hermon %p receive queue full", hermon );
  968. return -ENOBUFS;
  969. }
  970. wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf;
  971. wqe = &hermon_recv_wq->wqe[wq->next_idx & wqe_idx_mask].recv;
  972. /* Construct work queue entry */
  973. MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_tailroom ( iobuf ) );
  974. MLX_FILL_1 ( &wqe->data[0], 1, l_key, hermon->reserved_lkey );
  975. MLX_FILL_1 ( &wqe->data[0], 3,
  976. local_address_l, virt_to_bus ( iobuf->data ) );
  977. /* Update work queue's index */
  978. wq->next_idx++;
  979. /* Update doorbell record */
  980. barrier();
  981. MLX_FILL_1 ( &hermon_recv_wq->doorbell, 0, receive_wqe_counter,
  982. ( wq->next_idx & 0xffff ) );
  983. return 0;
  984. }
  985. /**
  986. * Handle completion
  987. *
  988. * @v ibdev Infiniband device
  989. * @v cq Completion queue
  990. * @v cqe Hardware completion queue entry
  991. * @v complete_send Send completion handler
  992. * @v complete_recv Receive completion handler
  993. * @ret rc Return status code
  994. */
  995. static int hermon_complete ( struct ib_device *ibdev,
  996. struct ib_completion_queue *cq,
  997. union hermonprm_completion_entry *cqe,
  998. ib_completer_t complete_send,
  999. ib_completer_t complete_recv ) {
  1000. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1001. struct ib_completion completion;
  1002. struct ib_work_queue *wq;
  1003. struct ib_queue_pair *qp;
  1004. struct hermon_queue_pair *hermon_qp;
  1005. struct io_buffer *iobuf;
  1006. ib_completer_t complete;
  1007. unsigned int opcode;
  1008. unsigned long qpn;
  1009. int is_send;
  1010. unsigned int wqe_idx;
  1011. int rc = 0;
  1012. /* Parse completion */
  1013. memset ( &completion, 0, sizeof ( completion ) );
  1014. qpn = MLX_GET ( &cqe->normal, qpn );
  1015. is_send = MLX_GET ( &cqe->normal, s_r );
  1016. opcode = MLX_GET ( &cqe->normal, opcode );
  1017. if ( opcode >= HERMON_OPCODE_RECV_ERROR ) {
  1018. /* "s" field is not valid for error opcodes */
  1019. is_send = ( opcode == HERMON_OPCODE_SEND_ERROR );
  1020. completion.syndrome = MLX_GET ( &cqe->error, syndrome );
  1021. DBGC ( hermon, "Hermon %p CQN %lx syndrome %x vendor %lx\n",
  1022. hermon, cq->cqn, completion.syndrome,
  1023. MLX_GET ( &cqe->error, vendor_error_syndrome ) );
  1024. rc = -EIO;
  1025. /* Don't return immediately; propagate error to completer */
  1026. }
  1027. /* Identify work queue */
  1028. wq = ib_find_wq ( cq, qpn, is_send );
  1029. if ( ! wq ) {
  1030. DBGC ( hermon, "Hermon %p CQN %lx unknown %s QPN %lx\n",
  1031. hermon, cq->cqn, ( is_send ? "send" : "recv" ), qpn );
  1032. return -EIO;
  1033. }
  1034. qp = wq->qp;
  1035. hermon_qp = ib_qp_get_drvdata ( qp );
  1036. /* Identify I/O buffer */
  1037. wqe_idx = ( MLX_GET ( &cqe->normal, wqe_counter ) &
  1038. ( wq->num_wqes - 1 ) );
  1039. iobuf = wq->iobufs[wqe_idx];
  1040. if ( ! iobuf ) {
  1041. DBGC ( hermon, "Hermon %p CQN %lx QPN %lx empty WQE %x\n",
  1042. hermon, cq->cqn, qpn, wqe_idx );
  1043. return -EIO;
  1044. }
  1045. wq->iobufs[wqe_idx] = NULL;
  1046. /* Fill in length for received packets */
  1047. if ( ! is_send ) {
  1048. completion.len = MLX_GET ( &cqe->normal, byte_cnt );
  1049. if ( completion.len > iob_tailroom ( iobuf ) ) {
  1050. DBGC ( hermon, "Hermon %p CQN %lx QPN %lx IDX %x "
  1051. "overlength received packet length %zd\n",
  1052. hermon, cq->cqn, qpn, wqe_idx, completion.len );
  1053. return -EIO;
  1054. }
  1055. }
  1056. /* Pass off to caller's completion handler */
  1057. complete = ( is_send ? complete_send : complete_recv );
  1058. complete ( ibdev, qp, &completion, iobuf );
  1059. return rc;
  1060. }
  1061. /**
  1062. * Poll completion queue
  1063. *
  1064. * @v ibdev Infiniband device
  1065. * @v cq Completion queue
  1066. * @v complete_send Send completion handler
  1067. * @v complete_recv Receive completion handler
  1068. */
  1069. static void hermon_poll_cq ( struct ib_device *ibdev,
  1070. struct ib_completion_queue *cq,
  1071. ib_completer_t complete_send,
  1072. ib_completer_t complete_recv ) {
  1073. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1074. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  1075. union hermonprm_completion_entry *cqe;
  1076. unsigned int cqe_idx_mask;
  1077. int rc;
  1078. while ( 1 ) {
  1079. /* Look for completion entry */
  1080. cqe_idx_mask = ( cq->num_cqes - 1 );
  1081. cqe = &hermon_cq->cqe[cq->next_idx & cqe_idx_mask];
  1082. if ( MLX_GET ( &cqe->normal, owner ) ^
  1083. ( ( cq->next_idx & cq->num_cqes ) ? 1 : 0 ) ) {
  1084. /* Entry still owned by hardware; end of poll */
  1085. break;
  1086. }
  1087. DBGCP ( hermon, "Hermon %p completion:\n", hermon );
  1088. DBGCP_HD ( hermon, cqe, sizeof ( *cqe ) );
  1089. /* Handle completion */
  1090. if ( ( rc = hermon_complete ( ibdev, cq, cqe, complete_send,
  1091. complete_recv ) ) != 0 ) {
  1092. DBGC ( hermon, "Hermon %p failed to complete: %s\n",
  1093. hermon, strerror ( rc ) );
  1094. DBGC_HD ( hermon, cqe, sizeof ( *cqe ) );
  1095. }
  1096. /* Update completion queue's index */
  1097. cq->next_idx++;
  1098. /* Update doorbell record */
  1099. MLX_FILL_1 ( &hermon_cq->doorbell, 0, update_ci,
  1100. ( cq->next_idx & 0x00ffffffUL ) );
  1101. }
  1102. }
  1103. /***************************************************************************
  1104. *
  1105. * Event queues
  1106. *
  1107. ***************************************************************************
  1108. */
  1109. /**
  1110. * Create event queue
  1111. *
  1112. * @v hermon Hermon device
  1113. * @ret rc Return status code
  1114. */
  1115. static int hermon_create_eq ( struct hermon *hermon ) {
  1116. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1117. struct hermonprm_eqc eqctx;
  1118. struct hermonprm_event_mask mask;
  1119. unsigned int i;
  1120. int rc;
  1121. /* Select event queue number */
  1122. hermon_eq->eqn = ( 4 * hermon->cap.reserved_uars );
  1123. if ( hermon_eq->eqn < hermon->cap.reserved_eqs )
  1124. hermon_eq->eqn = hermon->cap.reserved_eqs;
  1125. /* Calculate doorbell address */
  1126. hermon_eq->doorbell =
  1127. ( hermon->uar + HERMON_DB_EQ_OFFSET ( hermon_eq->eqn ) );
  1128. /* Allocate event queue itself */
  1129. hermon_eq->eqe_size =
  1130. ( HERMON_NUM_EQES * sizeof ( hermon_eq->eqe[0] ) );
  1131. hermon_eq->eqe = malloc_dma ( hermon_eq->eqe_size,
  1132. sizeof ( hermon_eq->eqe[0] ) );
  1133. if ( ! hermon_eq->eqe ) {
  1134. rc = -ENOMEM;
  1135. goto err_eqe;
  1136. }
  1137. memset ( hermon_eq->eqe, 0, hermon_eq->eqe_size );
  1138. for ( i = 0 ; i < HERMON_NUM_EQES ; i++ ) {
  1139. MLX_FILL_1 ( &hermon_eq->eqe[i].generic, 7, owner, 1 );
  1140. }
  1141. barrier();
  1142. /* Allocate MTT entries */
  1143. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_eq->eqe,
  1144. hermon_eq->eqe_size,
  1145. &hermon_eq->mtt ) ) != 0 )
  1146. goto err_alloc_mtt;
  1147. /* Hand queue over to hardware */
  1148. memset ( &eqctx, 0, sizeof ( eqctx ) );
  1149. MLX_FILL_1 ( &eqctx, 0, st, 0xa /* "Fired" */ );
  1150. MLX_FILL_1 ( &eqctx, 2,
  1151. page_offset, ( hermon_eq->mtt.page_offset >> 5 ) );
  1152. MLX_FILL_1 ( &eqctx, 3, log_eq_size, fls ( HERMON_NUM_EQES - 1 ) );
  1153. MLX_FILL_1 ( &eqctx, 7, mtt_base_addr_l,
  1154. ( hermon_eq->mtt.mtt_base_addr >> 3 ) );
  1155. if ( ( rc = hermon_cmd_sw2hw_eq ( hermon, hermon_eq->eqn,
  1156. &eqctx ) ) != 0 ) {
  1157. DBGC ( hermon, "Hermon %p SW2HW_EQ failed: %s\n",
  1158. hermon, strerror ( rc ) );
  1159. goto err_sw2hw_eq;
  1160. }
  1161. /* Map events to this event queue */
  1162. memset ( &mask, 0, sizeof ( mask ) );
  1163. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1164. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1165. ( HERMON_MAP_EQ | hermon_eq->eqn ),
  1166. &mask ) ) != 0 ) {
  1167. DBGC ( hermon, "Hermon %p MAP_EQ failed: %s\n",
  1168. hermon, strerror ( rc ) );
  1169. goto err_map_eq;
  1170. }
  1171. DBGC ( hermon, "Hermon %p EQN %#lx ring at [%p,%p])\n",
  1172. hermon, hermon_eq->eqn, hermon_eq->eqe,
  1173. ( ( ( void * ) hermon_eq->eqe ) + hermon_eq->eqe_size ) );
  1174. return 0;
  1175. err_map_eq:
  1176. hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn, &eqctx );
  1177. err_sw2hw_eq:
  1178. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1179. err_alloc_mtt:
  1180. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1181. err_eqe:
  1182. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1183. return rc;
  1184. }
  1185. /**
  1186. * Destroy event queue
  1187. *
  1188. * @v hermon Hermon device
  1189. */
  1190. static void hermon_destroy_eq ( struct hermon *hermon ) {
  1191. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1192. struct hermonprm_eqc eqctx;
  1193. struct hermonprm_event_mask mask;
  1194. int rc;
  1195. /* Unmap events from event queue */
  1196. memset ( &mask, 0, sizeof ( mask ) );
  1197. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1198. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1199. ( HERMON_UNMAP_EQ | hermon_eq->eqn ),
  1200. &mask ) ) != 0 ) {
  1201. DBGC ( hermon, "Hermon %p FATAL MAP_EQ failed to unmap: %s\n",
  1202. hermon, strerror ( rc ) );
  1203. /* Continue; HCA may die but system should survive */
  1204. }
  1205. /* Take ownership back from hardware */
  1206. if ( ( rc = hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn,
  1207. &eqctx ) ) != 0 ) {
  1208. DBGC ( hermon, "Hermon %p FATAL HW2SW_EQ failed: %s\n",
  1209. hermon, strerror ( rc ) );
  1210. /* Leak memory and return; at least we avoid corruption */
  1211. return;
  1212. }
  1213. /* Free MTT entries */
  1214. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1215. /* Free memory */
  1216. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1217. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1218. }
  1219. /**
  1220. * Handle port state event
  1221. *
  1222. * @v hermon Hermon device
  1223. * @v eqe Port state change event queue entry
  1224. */
  1225. static void hermon_event_port_state_change ( struct hermon *hermon,
  1226. union hermonprm_event_entry *eqe){
  1227. unsigned int port;
  1228. int link_up;
  1229. /* Get port and link status */
  1230. port = ( MLX_GET ( &eqe->port_state_change, data.p ) - 1 );
  1231. link_up = ( MLX_GET ( &eqe->generic, event_sub_type ) & 0x04 );
  1232. DBGC ( hermon, "Hermon %p port %d link %s\n", hermon, ( port + 1 ),
  1233. ( link_up ? "up" : "down" ) );
  1234. /* Sanity check */
  1235. if ( port >= HERMON_NUM_PORTS ) {
  1236. DBGC ( hermon, "Hermon %p port %d does not exist!\n",
  1237. hermon, ( port + 1 ) );
  1238. return;
  1239. }
  1240. /* Notify Infiniband core of link state change */
  1241. ib_link_state_changed ( hermon->ibdev[port] );
  1242. }
  1243. /**
  1244. * Poll event queue
  1245. *
  1246. * @v ibdev Infiniband device
  1247. */
  1248. static void hermon_poll_eq ( struct ib_device *ibdev ) {
  1249. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1250. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1251. union hermonprm_event_entry *eqe;
  1252. union hermonprm_doorbell_register db_reg;
  1253. unsigned int eqe_idx_mask;
  1254. unsigned int event_type;
  1255. while ( 1 ) {
  1256. /* Look for event entry */
  1257. eqe_idx_mask = ( HERMON_NUM_EQES - 1 );
  1258. eqe = &hermon_eq->eqe[hermon_eq->next_idx & eqe_idx_mask];
  1259. if ( MLX_GET ( &eqe->generic, owner ) ^
  1260. ( ( hermon_eq->next_idx & HERMON_NUM_EQES ) ? 1 : 0 ) ) {
  1261. /* Entry still owned by hardware; end of poll */
  1262. break;
  1263. }
  1264. DBGCP ( hermon, "Hermon %p event:\n", hermon );
  1265. DBGCP_HD ( hermon, eqe, sizeof ( *eqe ) );
  1266. /* Handle event */
  1267. event_type = MLX_GET ( &eqe->generic, event_type );
  1268. switch ( event_type ) {
  1269. case HERMON_EV_PORT_STATE_CHANGE:
  1270. hermon_event_port_state_change ( hermon, eqe );
  1271. break;
  1272. default:
  1273. DBGC ( hermon, "Hermon %p unrecognised event type "
  1274. "%#x:\n", hermon, event_type );
  1275. DBGC_HD ( hermon, eqe, sizeof ( *eqe ) );
  1276. break;
  1277. }
  1278. /* Update event queue's index */
  1279. hermon_eq->next_idx++;
  1280. /* Ring doorbell */
  1281. MLX_FILL_1 ( &db_reg.event, 0,
  1282. ci, ( hermon_eq->next_idx & 0x00ffffffUL ) );
  1283. DBGCP ( hermon, "Ringing doorbell %08lx with %08lx\n",
  1284. virt_to_phys ( hermon_eq->doorbell ),
  1285. db_reg.dword[0] );
  1286. writel ( db_reg.dword[0], hermon_eq->doorbell );
  1287. }
  1288. }
  1289. /***************************************************************************
  1290. *
  1291. * Infiniband link-layer operations
  1292. *
  1293. ***************************************************************************
  1294. */
  1295. /**
  1296. * Initialise Infiniband link
  1297. *
  1298. * @v ibdev Infiniband device
  1299. * @ret rc Return status code
  1300. */
  1301. static int hermon_open ( struct ib_device *ibdev ) {
  1302. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1303. struct hermonprm_init_port init_port;
  1304. int rc;
  1305. memset ( &init_port, 0, sizeof ( init_port ) );
  1306. MLX_FILL_2 ( &init_port, 0,
  1307. port_width_cap, 3,
  1308. vl_cap, 1 );
  1309. MLX_FILL_2 ( &init_port, 1,
  1310. mtu, HERMON_MTU_2048,
  1311. max_gid, 1 );
  1312. MLX_FILL_1 ( &init_port, 2, max_pkey, 64 );
  1313. if ( ( rc = hermon_cmd_init_port ( hermon, ibdev->port,
  1314. &init_port ) ) != 0 ) {
  1315. DBGC ( hermon, "Hermon %p could not intialise port: %s\n",
  1316. hermon, strerror ( rc ) );
  1317. return rc;
  1318. }
  1319. return 0;
  1320. }
  1321. /**
  1322. * Close Infiniband link
  1323. *
  1324. * @v ibdev Infiniband device
  1325. */
  1326. static void hermon_close ( struct ib_device *ibdev ) {
  1327. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1328. int rc;
  1329. if ( ( rc = hermon_cmd_close_port ( hermon, ibdev->port ) ) != 0 ) {
  1330. DBGC ( hermon, "Hermon %p could not close port: %s\n",
  1331. hermon, strerror ( rc ) );
  1332. /* Nothing we can do about this */
  1333. }
  1334. }
  1335. /***************************************************************************
  1336. *
  1337. * Multicast group operations
  1338. *
  1339. ***************************************************************************
  1340. */
  1341. /**
  1342. * Attach to multicast group
  1343. *
  1344. * @v ibdev Infiniband device
  1345. * @v qp Queue pair
  1346. * @v gid Multicast GID
  1347. * @ret rc Return status code
  1348. */
  1349. static int hermon_mcast_attach ( struct ib_device *ibdev,
  1350. struct ib_queue_pair *qp,
  1351. struct ib_gid *gid ) {
  1352. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1353. struct hermonprm_mgm_hash hash;
  1354. struct hermonprm_mcg_entry mcg;
  1355. unsigned int index;
  1356. int rc;
  1357. /* Generate hash table index */
  1358. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1359. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1360. hermon, strerror ( rc ) );
  1361. return rc;
  1362. }
  1363. index = MLX_GET ( &hash, hash );
  1364. /* Check for existing hash table entry */
  1365. if ( ( rc = hermon_cmd_read_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1366. DBGC ( hermon, "Hermon %p could not read MCG %#x: %s\n",
  1367. hermon, index, strerror ( rc ) );
  1368. return rc;
  1369. }
  1370. if ( MLX_GET ( &mcg, hdr.members_count ) != 0 ) {
  1371. /* FIXME: this implementation allows only a single QP
  1372. * per multicast group, and doesn't handle hash
  1373. * collisions. Sufficient for IPoIB but may need to
  1374. * be extended in future.
  1375. */
  1376. DBGC ( hermon, "Hermon %p MGID index %#x already in use\n",
  1377. hermon, index );
  1378. return -EBUSY;
  1379. }
  1380. /* Update hash table entry */
  1381. MLX_FILL_1 ( &mcg, 1, hdr.members_count, 1 );
  1382. MLX_FILL_1 ( &mcg, 8, qp[0].qpn, qp->qpn );
  1383. memcpy ( &mcg.u.dwords[4], gid, sizeof ( *gid ) );
  1384. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1385. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1386. hermon, index, strerror ( rc ) );
  1387. return rc;
  1388. }
  1389. return 0;
  1390. }
  1391. /**
  1392. * Detach from multicast group
  1393. *
  1394. * @v ibdev Infiniband device
  1395. * @v qp Queue pair
  1396. * @v gid Multicast GID
  1397. */
  1398. static void hermon_mcast_detach ( struct ib_device *ibdev,
  1399. struct ib_queue_pair *qp __unused,
  1400. struct ib_gid *gid ) {
  1401. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1402. struct hermonprm_mgm_hash hash;
  1403. struct hermonprm_mcg_entry mcg;
  1404. unsigned int index;
  1405. int rc;
  1406. /* Generate hash table index */
  1407. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1408. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1409. hermon, strerror ( rc ) );
  1410. return;
  1411. }
  1412. index = MLX_GET ( &hash, hash );
  1413. /* Clear hash table entry */
  1414. memset ( &mcg, 0, sizeof ( mcg ) );
  1415. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1416. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1417. hermon, index, strerror ( rc ) );
  1418. return;
  1419. }
  1420. }
  1421. /***************************************************************************
  1422. *
  1423. * MAD operations
  1424. *
  1425. ***************************************************************************
  1426. */
  1427. /**
  1428. * Issue management datagram
  1429. *
  1430. * @v ibdev Infiniband device
  1431. * @v mad Management datagram
  1432. * @v len Length of management datagram
  1433. * @ret rc Return status code
  1434. */
  1435. static int hermon_mad ( struct ib_device *ibdev, struct ib_mad_hdr *mad,
  1436. size_t len ) {
  1437. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1438. union hermonprm_mad mad_ifc;
  1439. int rc;
  1440. /* Copy in request packet */
  1441. memset ( &mad_ifc, 0, sizeof ( mad_ifc ) );
  1442. assert ( len <= sizeof ( mad_ifc.mad ) );
  1443. memcpy ( &mad_ifc.mad, mad, len );
  1444. /* Issue MAD */
  1445. if ( ( rc = hermon_cmd_mad_ifc ( hermon, ibdev->port,
  1446. &mad_ifc ) ) != 0 ) {
  1447. DBGC ( hermon, "Hermon %p could not issue MAD IFC: %s\n",
  1448. hermon, strerror ( rc ) );
  1449. return rc;
  1450. }
  1451. /* Copy out reply packet */
  1452. memcpy ( mad, &mad_ifc.mad, len );
  1453. if ( mad->status != 0 ) {
  1454. DBGC ( hermon, "Hermon %p MAD IFC status %04x\n",
  1455. hermon, ntohs ( mad->status ) );
  1456. return -EIO;
  1457. }
  1458. return 0;
  1459. }
  1460. /** Hermon Infiniband operations */
  1461. static struct ib_device_operations hermon_ib_operations = {
  1462. .create_cq = hermon_create_cq,
  1463. .destroy_cq = hermon_destroy_cq,
  1464. .create_qp = hermon_create_qp,
  1465. .modify_qp = hermon_modify_qp,
  1466. .destroy_qp = hermon_destroy_qp,
  1467. .post_send = hermon_post_send,
  1468. .post_recv = hermon_post_recv,
  1469. .poll_cq = hermon_poll_cq,
  1470. .poll_eq = hermon_poll_eq,
  1471. .open = hermon_open,
  1472. .close = hermon_close,
  1473. .mcast_attach = hermon_mcast_attach,
  1474. .mcast_detach = hermon_mcast_detach,
  1475. .mad = hermon_mad,
  1476. };
  1477. /***************************************************************************
  1478. *
  1479. * Firmware control
  1480. *
  1481. ***************************************************************************
  1482. */
  1483. /**
  1484. * Start firmware running
  1485. *
  1486. * @v hermon Hermon device
  1487. * @ret rc Return status code
  1488. */
  1489. static int hermon_start_firmware ( struct hermon *hermon ) {
  1490. struct hermonprm_query_fw fw;
  1491. struct hermonprm_virtual_physical_mapping map_fa;
  1492. unsigned int fw_pages;
  1493. unsigned int log2_fw_pages;
  1494. size_t fw_size;
  1495. physaddr_t fw_base;
  1496. int rc;
  1497. /* Get firmware parameters */
  1498. if ( ( rc = hermon_cmd_query_fw ( hermon, &fw ) ) != 0 ) {
  1499. DBGC ( hermon, "Hermon %p could not query firmware: %s\n",
  1500. hermon, strerror ( rc ) );
  1501. goto err_query_fw;
  1502. }
  1503. DBGC ( hermon, "Hermon %p firmware version %ld.%ld.%ld\n", hermon,
  1504. MLX_GET ( &fw, fw_rev_major ), MLX_GET ( &fw, fw_rev_minor ),
  1505. MLX_GET ( &fw, fw_rev_subminor ) );
  1506. fw_pages = MLX_GET ( &fw, fw_pages );
  1507. log2_fw_pages = fls ( fw_pages - 1 );
  1508. fw_pages = ( 1 << log2_fw_pages );
  1509. DBGC ( hermon, "Hermon %p requires %d kB for firmware\n",
  1510. hermon, ( fw_pages * 4 ) );
  1511. /* Allocate firmware pages and map firmware area */
  1512. fw_size = ( fw_pages * HERMON_PAGE_SIZE );
  1513. hermon->firmware_area = umalloc ( fw_size * 2 );
  1514. if ( ! hermon->firmware_area ) {
  1515. rc = -ENOMEM;
  1516. goto err_alloc_fa;
  1517. }
  1518. fw_base = ( user_to_phys ( hermon->firmware_area, fw_size ) &
  1519. ~( fw_size - 1 ) );
  1520. DBGC ( hermon, "Hermon %p firmware area at physical [%lx,%lx)\n",
  1521. hermon, fw_base, ( fw_base + fw_size ) );
  1522. memset ( &map_fa, 0, sizeof ( map_fa ) );
  1523. MLX_FILL_2 ( &map_fa, 3,
  1524. log2size, log2_fw_pages,
  1525. pa_l, ( fw_base >> 12 ) );
  1526. if ( ( rc = hermon_cmd_map_fa ( hermon, &map_fa ) ) != 0 ) {
  1527. DBGC ( hermon, "Hermon %p could not map firmware: %s\n",
  1528. hermon, strerror ( rc ) );
  1529. goto err_map_fa;
  1530. }
  1531. /* Start firmware */
  1532. if ( ( rc = hermon_cmd_run_fw ( hermon ) ) != 0 ) {
  1533. DBGC ( hermon, "Hermon %p could not run firmware: %s\n",
  1534. hermon, strerror ( rc ) );
  1535. goto err_run_fw;
  1536. }
  1537. DBGC ( hermon, "Hermon %p firmware started\n", hermon );
  1538. return 0;
  1539. err_run_fw:
  1540. hermon_cmd_unmap_fa ( hermon );
  1541. err_map_fa:
  1542. ufree ( hermon->firmware_area );
  1543. hermon->firmware_area = UNULL;
  1544. err_alloc_fa:
  1545. err_query_fw:
  1546. return rc;
  1547. }
  1548. /**
  1549. * Stop firmware running
  1550. *
  1551. * @v hermon Hermon device
  1552. */
  1553. static void hermon_stop_firmware ( struct hermon *hermon ) {
  1554. int rc;
  1555. if ( ( rc = hermon_cmd_unmap_fa ( hermon ) ) != 0 ) {
  1556. DBGC ( hermon, "Hermon %p FATAL could not stop firmware: %s\n",
  1557. hermon, strerror ( rc ) );
  1558. /* Leak memory and return; at least we avoid corruption */
  1559. return;
  1560. }
  1561. ufree ( hermon->firmware_area );
  1562. hermon->firmware_area = UNULL;
  1563. }
  1564. /***************************************************************************
  1565. *
  1566. * Infinihost Context Memory management
  1567. *
  1568. ***************************************************************************
  1569. */
  1570. /**
  1571. * Get device limits
  1572. *
  1573. * @v hermon Hermon device
  1574. * @ret rc Return status code
  1575. */
  1576. static int hermon_get_cap ( struct hermon *hermon ) {
  1577. struct hermonprm_query_dev_cap dev_cap;
  1578. int rc;
  1579. if ( ( rc = hermon_cmd_query_dev_cap ( hermon, &dev_cap ) ) != 0 ) {
  1580. DBGC ( hermon, "Hermon %p could not get device limits: %s\n",
  1581. hermon, strerror ( rc ) );
  1582. return rc;
  1583. }
  1584. hermon->cap.cmpt_entry_size = MLX_GET ( &dev_cap, c_mpt_entry_sz );
  1585. hermon->cap.reserved_qps =
  1586. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_qps ) );
  1587. hermon->cap.qpc_entry_size = MLX_GET ( &dev_cap, qpc_entry_sz );
  1588. hermon->cap.altc_entry_size = MLX_GET ( &dev_cap, altc_entry_sz );
  1589. hermon->cap.auxc_entry_size = MLX_GET ( &dev_cap, aux_entry_sz );
  1590. hermon->cap.reserved_srqs =
  1591. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_srqs ) );
  1592. hermon->cap.srqc_entry_size = MLX_GET ( &dev_cap, srq_entry_sz );
  1593. hermon->cap.reserved_cqs =
  1594. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_cqs ) );
  1595. hermon->cap.cqc_entry_size = MLX_GET ( &dev_cap, cqc_entry_sz );
  1596. hermon->cap.reserved_eqs = MLX_GET ( &dev_cap, num_rsvd_eqs );
  1597. hermon->cap.eqc_entry_size = MLX_GET ( &dev_cap, eqc_entry_sz );
  1598. hermon->cap.reserved_mtts =
  1599. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mtts ) );
  1600. hermon->cap.mtt_entry_size = MLX_GET ( &dev_cap, mtt_entry_sz );
  1601. hermon->cap.reserved_mrws =
  1602. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mrws ) );
  1603. hermon->cap.dmpt_entry_size = MLX_GET ( &dev_cap, d_mpt_entry_sz );
  1604. hermon->cap.reserved_uars = MLX_GET ( &dev_cap, num_rsvd_uars );
  1605. return 0;
  1606. }
  1607. /**
  1608. * Get ICM usage
  1609. *
  1610. * @v log_num_entries Log2 of the number of entries
  1611. * @v entry_size Entry size
  1612. * @ret usage Usage size in ICM
  1613. */
  1614. static size_t icm_usage ( unsigned int log_num_entries, size_t entry_size ) {
  1615. size_t usage;
  1616. usage = ( ( 1 << log_num_entries ) * entry_size );
  1617. usage = ( ( usage + HERMON_PAGE_SIZE - 1 ) &
  1618. ~( HERMON_PAGE_SIZE - 1 ) );
  1619. return usage;
  1620. }
  1621. /**
  1622. * Allocate ICM
  1623. *
  1624. * @v hermon Hermon device
  1625. * @v init_hca INIT_HCA structure to fill in
  1626. * @ret rc Return status code
  1627. */
  1628. static int hermon_alloc_icm ( struct hermon *hermon,
  1629. struct hermonprm_init_hca *init_hca ) {
  1630. struct hermonprm_scalar_parameter icm_size;
  1631. struct hermonprm_scalar_parameter icm_aux_size;
  1632. struct hermonprm_virtual_physical_mapping map_icm_aux;
  1633. struct hermonprm_virtual_physical_mapping map_icm;
  1634. uint64_t icm_offset = 0;
  1635. unsigned int log_num_qps, log_num_srqs, log_num_cqs, log_num_eqs;
  1636. unsigned int log_num_mtts, log_num_mpts;
  1637. size_t cmpt_max_len;
  1638. size_t qp_cmpt_len, srq_cmpt_len, cq_cmpt_len, eq_cmpt_len;
  1639. size_t icm_len, icm_aux_len;
  1640. physaddr_t icm_phys;
  1641. int i;
  1642. int rc;
  1643. /*
  1644. * Start by carving up the ICM virtual address space
  1645. *
  1646. */
  1647. /* Calculate number of each object type within ICM */
  1648. log_num_qps = fls ( hermon->cap.reserved_qps + HERMON_MAX_QPS - 1 );
  1649. log_num_srqs = fls ( hermon->cap.reserved_srqs - 1 );
  1650. log_num_cqs = fls ( hermon->cap.reserved_cqs + HERMON_MAX_CQS - 1 );
  1651. log_num_eqs = fls ( hermon->cap.reserved_eqs + HERMON_MAX_EQS - 1 );
  1652. log_num_mtts = fls ( hermon->cap.reserved_mtts + HERMON_MAX_MTTS - 1 );
  1653. /* ICM starts with the cMPT tables, which are sparse */
  1654. cmpt_max_len = ( HERMON_CMPT_MAX_ENTRIES *
  1655. ( ( uint64_t ) hermon->cap.cmpt_entry_size ) );
  1656. qp_cmpt_len = icm_usage ( log_num_qps, hermon->cap.cmpt_entry_size );
  1657. hermon->icm_map[HERMON_ICM_QP_CMPT].offset = icm_offset;
  1658. hermon->icm_map[HERMON_ICM_QP_CMPT].len = qp_cmpt_len;
  1659. icm_offset += cmpt_max_len;
  1660. srq_cmpt_len = icm_usage ( log_num_srqs, hermon->cap.cmpt_entry_size );
  1661. hermon->icm_map[HERMON_ICM_SRQ_CMPT].offset = icm_offset;
  1662. hermon->icm_map[HERMON_ICM_SRQ_CMPT].len = srq_cmpt_len;
  1663. icm_offset += cmpt_max_len;
  1664. cq_cmpt_len = icm_usage ( log_num_cqs, hermon->cap.cmpt_entry_size );
  1665. hermon->icm_map[HERMON_ICM_CQ_CMPT].offset = icm_offset;
  1666. hermon->icm_map[HERMON_ICM_CQ_CMPT].len = cq_cmpt_len;
  1667. icm_offset += cmpt_max_len;
  1668. eq_cmpt_len = icm_usage ( log_num_eqs, hermon->cap.cmpt_entry_size );
  1669. hermon->icm_map[HERMON_ICM_EQ_CMPT].offset = icm_offset;
  1670. hermon->icm_map[HERMON_ICM_EQ_CMPT].len = eq_cmpt_len;
  1671. icm_offset += cmpt_max_len;
  1672. hermon->icm_map[HERMON_ICM_OTHER].offset = icm_offset;
  1673. /* Queue pair contexts */
  1674. MLX_FILL_1 ( init_hca, 12,
  1675. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_h,
  1676. ( icm_offset >> 32 ) );
  1677. MLX_FILL_2 ( init_hca, 13,
  1678. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_l,
  1679. ( icm_offset >> 5 ),
  1680. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp,
  1681. log_num_qps );
  1682. DBGC ( hermon, "Hermon %p ICM QPC base = %llx\n", hermon, icm_offset );
  1683. icm_offset += icm_usage ( log_num_qps, hermon->cap.qpc_entry_size );
  1684. /* Extended alternate path contexts */
  1685. MLX_FILL_1 ( init_hca, 24,
  1686. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_h,
  1687. ( icm_offset >> 32 ) );
  1688. MLX_FILL_1 ( init_hca, 25,
  1689. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_l,
  1690. icm_offset );
  1691. DBGC ( hermon, "Hermon %p ICM ALTC base = %llx\n", hermon, icm_offset);
  1692. icm_offset += icm_usage ( log_num_qps,
  1693. hermon->cap.altc_entry_size );
  1694. /* Extended auxiliary contexts */
  1695. MLX_FILL_1 ( init_hca, 28,
  1696. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_h,
  1697. ( icm_offset >> 32 ) );
  1698. MLX_FILL_1 ( init_hca, 29,
  1699. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_l,
  1700. icm_offset );
  1701. DBGC ( hermon, "Hermon %p ICM AUXC base = %llx\n", hermon, icm_offset);
  1702. icm_offset += icm_usage ( log_num_qps,
  1703. hermon->cap.auxc_entry_size );
  1704. /* Shared receive queue contexts */
  1705. MLX_FILL_1 ( init_hca, 18,
  1706. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_h,
  1707. ( icm_offset >> 32 ) );
  1708. MLX_FILL_2 ( init_hca, 19,
  1709. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_l,
  1710. ( icm_offset >> 5 ),
  1711. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_srq,
  1712. log_num_srqs );
  1713. DBGC ( hermon, "Hermon %p ICM SRQC base = %llx\n", hermon, icm_offset);
  1714. icm_offset += icm_usage ( log_num_srqs,
  1715. hermon->cap.srqc_entry_size );
  1716. /* Completion queue contexts */
  1717. MLX_FILL_1 ( init_hca, 20,
  1718. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_h,
  1719. ( icm_offset >> 32 ) );
  1720. MLX_FILL_2 ( init_hca, 21,
  1721. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_l,
  1722. ( icm_offset >> 5 ),
  1723. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq,
  1724. log_num_cqs );
  1725. DBGC ( hermon, "Hermon %p ICM CQC base = %llx\n", hermon, icm_offset );
  1726. icm_offset += icm_usage ( log_num_cqs, hermon->cap.cqc_entry_size );
  1727. /* Event queue contexts */
  1728. MLX_FILL_1 ( init_hca, 32,
  1729. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_h,
  1730. ( icm_offset >> 32 ) );
  1731. MLX_FILL_2 ( init_hca, 33,
  1732. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_l,
  1733. ( icm_offset >> 5 ),
  1734. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_eq,
  1735. log_num_eqs );
  1736. DBGC ( hermon, "Hermon %p ICM EQC base = %llx\n", hermon, icm_offset );
  1737. icm_offset += icm_usage ( log_num_eqs, hermon->cap.eqc_entry_size );
  1738. /* Memory translation table */
  1739. MLX_FILL_1 ( init_hca, 64,
  1740. tpt_parameters.mtt_base_addr_h, ( icm_offset >> 32 ) );
  1741. MLX_FILL_1 ( init_hca, 65,
  1742. tpt_parameters.mtt_base_addr_l, icm_offset );
  1743. DBGC ( hermon, "Hermon %p ICM MTT base = %llx\n", hermon, icm_offset );
  1744. icm_offset += icm_usage ( log_num_mtts,
  1745. hermon->cap.mtt_entry_size );
  1746. /* Memory protection table */
  1747. log_num_mpts = fls ( hermon->cap.reserved_mrws + 1 - 1 );
  1748. MLX_FILL_1 ( init_hca, 60,
  1749. tpt_parameters.dmpt_base_adr_h, ( icm_offset >> 32 ) );
  1750. MLX_FILL_1 ( init_hca, 61,
  1751. tpt_parameters.dmpt_base_adr_l, icm_offset );
  1752. MLX_FILL_1 ( init_hca, 62,
  1753. tpt_parameters.log_dmpt_sz, log_num_mpts );
  1754. DBGC ( hermon, "Hermon %p ICM DMPT base = %llx\n", hermon, icm_offset);
  1755. icm_offset += icm_usage ( log_num_mpts,
  1756. hermon->cap.dmpt_entry_size );
  1757. /* Multicast table */
  1758. MLX_FILL_1 ( init_hca, 48,
  1759. multicast_parameters.mc_base_addr_h,
  1760. ( icm_offset >> 32 ) );
  1761. MLX_FILL_1 ( init_hca, 49,
  1762. multicast_parameters.mc_base_addr_l, icm_offset );
  1763. MLX_FILL_1 ( init_hca, 52,
  1764. multicast_parameters.log_mc_table_entry_sz,
  1765. fls ( sizeof ( struct hermonprm_mcg_entry ) - 1 ) );
  1766. MLX_FILL_1 ( init_hca, 53,
  1767. multicast_parameters.log_mc_table_hash_sz, 3 );
  1768. MLX_FILL_1 ( init_hca, 54,
  1769. multicast_parameters.log_mc_table_sz, 3 );
  1770. DBGC ( hermon, "Hermon %p ICM MC base = %llx\n", hermon, icm_offset );
  1771. icm_offset += ( ( 8 * sizeof ( struct hermonprm_mcg_entry ) +
  1772. HERMON_PAGE_SIZE - 1 ) & ~( HERMON_PAGE_SIZE - 1 ) );
  1773. hermon->icm_map[HERMON_ICM_OTHER].len =
  1774. ( icm_offset - hermon->icm_map[HERMON_ICM_OTHER].offset );
  1775. /*
  1776. * Allocate and map physical memory for (portions of) ICM
  1777. *
  1778. * Map is:
  1779. * ICM AUX area (aligned to its own size)
  1780. * cMPT areas
  1781. * Other areas
  1782. */
  1783. /* Calculate physical memory required for ICM */
  1784. icm_len = 0;
  1785. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  1786. icm_len += hermon->icm_map[i].len;
  1787. }
  1788. /* Get ICM auxiliary area size */
  1789. memset ( &icm_size, 0, sizeof ( icm_size ) );
  1790. MLX_FILL_1 ( &icm_size, 0, value_hi, ( icm_offset >> 32 ) );
  1791. MLX_FILL_1 ( &icm_size, 1, value, icm_offset );
  1792. if ( ( rc = hermon_cmd_set_icm_size ( hermon, &icm_size,
  1793. &icm_aux_size ) ) != 0 ) {
  1794. DBGC ( hermon, "Hermon %p could not set ICM size: %s\n",
  1795. hermon, strerror ( rc ) );
  1796. goto err_set_icm_size;
  1797. }
  1798. icm_aux_len = ( MLX_GET ( &icm_aux_size, value ) * HERMON_PAGE_SIZE );
  1799. /* Must round up to nearest power of two :( */
  1800. icm_aux_len = ( 1 << fls ( icm_aux_len - 1 ) );
  1801. /* Allocate ICM data and auxiliary area */
  1802. DBGC ( hermon, "Hermon %p requires %zd kB ICM and %zd kB AUX ICM\n",
  1803. hermon, ( icm_len / 1024 ), ( icm_aux_len / 1024 ) );
  1804. hermon->icm = umalloc ( 2 * icm_aux_len + icm_len );
  1805. if ( ! hermon->icm ) {
  1806. rc = -ENOMEM;
  1807. goto err_alloc;
  1808. }
  1809. icm_phys = user_to_phys ( hermon->icm, 0 );
  1810. /* Map ICM auxiliary area */
  1811. icm_phys = ( ( icm_phys + icm_aux_len - 1 ) & ~( icm_aux_len - 1 ) );
  1812. memset ( &map_icm_aux, 0, sizeof ( map_icm_aux ) );
  1813. MLX_FILL_2 ( &map_icm_aux, 3,
  1814. log2size, fls ( ( icm_aux_len / HERMON_PAGE_SIZE ) - 1 ),
  1815. pa_l, ( icm_phys >> 12 ) );
  1816. DBGC ( hermon, "Hermon %p mapping ICM AUX (2^%d pages) => %08lx\n",
  1817. hermon, fls ( ( icm_aux_len / HERMON_PAGE_SIZE ) - 1 ),
  1818. icm_phys );
  1819. if ( ( rc = hermon_cmd_map_icm_aux ( hermon, &map_icm_aux ) ) != 0 ) {
  1820. DBGC ( hermon, "Hermon %p could not map AUX ICM: %s\n",
  1821. hermon, strerror ( rc ) );
  1822. goto err_map_icm_aux;
  1823. }
  1824. icm_phys += icm_aux_len;
  1825. /* MAP ICM area */
  1826. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  1827. memset ( &map_icm, 0, sizeof ( map_icm ) );
  1828. MLX_FILL_1 ( &map_icm, 0,
  1829. va_h, ( hermon->icm_map[i].offset >> 32 ) );
  1830. MLX_FILL_1 ( &map_icm, 1,
  1831. va_l, ( hermon->icm_map[i].offset >> 12 ) );
  1832. MLX_FILL_2 ( &map_icm, 3,
  1833. log2size,
  1834. fls ( ( hermon->icm_map[i].len /
  1835. HERMON_PAGE_SIZE ) - 1 ),
  1836. pa_l, ( icm_phys >> 12 ) );
  1837. DBGC ( hermon, "Hermon %p mapping ICM %llx+%zx (2^%d pages) "
  1838. "=> %08lx\n", hermon, hermon->icm_map[i].offset,
  1839. hermon->icm_map[i].len,
  1840. fls ( ( hermon->icm_map[i].len /
  1841. HERMON_PAGE_SIZE ) - 1 ), icm_phys );
  1842. if ( ( rc = hermon_cmd_map_icm ( hermon, &map_icm ) ) != 0 ) {
  1843. DBGC ( hermon, "Hermon %p could not map ICM: %s\n",
  1844. hermon, strerror ( rc ) );
  1845. goto err_map_icm;
  1846. }
  1847. icm_phys += hermon->icm_map[i].len;
  1848. }
  1849. return 0;
  1850. err_map_icm:
  1851. assert ( i == 0 ); /* We don't handle partial failure at present */
  1852. hermon_cmd_unmap_icm_aux ( hermon );
  1853. err_map_icm_aux:
  1854. ufree ( hermon->icm );
  1855. hermon->icm = UNULL;
  1856. err_alloc:
  1857. err_set_icm_size:
  1858. return rc;
  1859. }
  1860. /**
  1861. * Free ICM
  1862. *
  1863. * @v hermon Hermon device
  1864. */
  1865. static void hermon_free_icm ( struct hermon *hermon ) {
  1866. struct hermonprm_scalar_parameter unmap_icm;
  1867. int i;
  1868. for ( i = ( HERMON_ICM_NUM_REGIONS - 1 ) ; i >= 0 ; i-- ) {
  1869. memset ( &unmap_icm, 0, sizeof ( unmap_icm ) );
  1870. MLX_FILL_1 ( &unmap_icm, 0, value_hi,
  1871. ( hermon->icm_map[i].offset >> 32 ) );
  1872. MLX_FILL_1 ( &unmap_icm, 1, value,
  1873. hermon->icm_map[i].offset );
  1874. hermon_cmd_unmap_icm ( hermon,
  1875. ( 1 << fls ( ( hermon->icm_map[i].len /
  1876. HERMON_PAGE_SIZE ) - 1)),
  1877. &unmap_icm );
  1878. }
  1879. hermon_cmd_unmap_icm_aux ( hermon );
  1880. ufree ( hermon->icm );
  1881. hermon->icm = UNULL;
  1882. }
  1883. /***************************************************************************
  1884. *
  1885. * PCI interface
  1886. *
  1887. ***************************************************************************
  1888. */
  1889. /**
  1890. * Set up memory protection table
  1891. *
  1892. * @v hermon Hermon device
  1893. * @ret rc Return status code
  1894. */
  1895. static int hermon_setup_mpt ( struct hermon *hermon ) {
  1896. struct hermonprm_mpt mpt;
  1897. uint32_t key;
  1898. int rc;
  1899. /* Derive key */
  1900. key = ( hermon->cap.reserved_mrws | HERMON_MKEY_PREFIX );
  1901. hermon->reserved_lkey = ( ( key << 8 ) | ( key >> 24 ) );
  1902. /* Initialise memory protection table */
  1903. memset ( &mpt, 0, sizeof ( mpt ) );
  1904. MLX_FILL_4 ( &mpt, 0,
  1905. r_w, 1,
  1906. pa, 1,
  1907. lr, 1,
  1908. lw, 1 );
  1909. MLX_FILL_1 ( &mpt, 2, mem_key, key );
  1910. MLX_FILL_1 ( &mpt, 3, pd, HERMON_GLOBAL_PD );
  1911. MLX_FILL_1 ( &mpt, 10, len64, 1 );
  1912. if ( ( rc = hermon_cmd_sw2hw_mpt ( hermon,
  1913. hermon->cap.reserved_mrws,
  1914. &mpt ) ) != 0 ) {
  1915. DBGC ( hermon, "Hermon %p could not set up MPT: %s\n",
  1916. hermon, strerror ( rc ) );
  1917. return rc;
  1918. }
  1919. return 0;
  1920. }
  1921. /**
  1922. * Probe PCI device
  1923. *
  1924. * @v pci PCI device
  1925. * @v id PCI ID
  1926. * @ret rc Return status code
  1927. */
  1928. static int hermon_probe ( struct pci_device *pci,
  1929. const struct pci_device_id *id __unused ) {
  1930. struct hermon *hermon;
  1931. struct ib_device *ibdev;
  1932. struct hermonprm_init_hca init_hca;
  1933. int i;
  1934. int rc;
  1935. /* Allocate Hermon device */
  1936. hermon = zalloc ( sizeof ( *hermon ) );
  1937. if ( ! hermon ) {
  1938. rc = -ENOMEM;
  1939. goto err_alloc_hermon;
  1940. }
  1941. pci_set_drvdata ( pci, hermon );
  1942. /* Allocate Infiniband devices */
  1943. for ( i = 0 ; i < HERMON_NUM_PORTS ; i++ ) {
  1944. ibdev = alloc_ibdev ( 0 );
  1945. if ( ! ibdev ) {
  1946. rc = -ENOMEM;
  1947. goto err_alloc_ibdev;
  1948. }
  1949. hermon->ibdev[i] = ibdev;
  1950. ibdev->op = &hermon_ib_operations;
  1951. ibdev->dev = &pci->dev;
  1952. ibdev->port = ( HERMON_PORT_BASE + i );
  1953. ib_set_drvdata ( ibdev, hermon );
  1954. }
  1955. /* Fix up PCI device */
  1956. adjust_pci_device ( pci );
  1957. /* Get PCI BARs */
  1958. hermon->config = ioremap ( pci_bar_start ( pci, HERMON_PCI_CONFIG_BAR),
  1959. HERMON_PCI_CONFIG_BAR_SIZE );
  1960. hermon->uar = ioremap ( pci_bar_start ( pci, HERMON_PCI_UAR_BAR ),
  1961. HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE );
  1962. /* Allocate space for mailboxes */
  1963. hermon->mailbox_in = malloc_dma ( HERMON_MBOX_SIZE,
  1964. HERMON_MBOX_ALIGN );
  1965. if ( ! hermon->mailbox_in ) {
  1966. rc = -ENOMEM;
  1967. goto err_mailbox_in;
  1968. }
  1969. hermon->mailbox_out = malloc_dma ( HERMON_MBOX_SIZE,
  1970. HERMON_MBOX_ALIGN );
  1971. if ( ! hermon->mailbox_out ) {
  1972. rc = -ENOMEM;
  1973. goto err_mailbox_out;
  1974. }
  1975. /* Start firmware */
  1976. if ( ( rc = hermon_start_firmware ( hermon ) ) != 0 )
  1977. goto err_start_firmware;
  1978. /* Get device limits */
  1979. if ( ( rc = hermon_get_cap ( hermon ) ) != 0 )
  1980. goto err_get_cap;
  1981. /* Allocate ICM */
  1982. memset ( &init_hca, 0, sizeof ( init_hca ) );
  1983. if ( ( rc = hermon_alloc_icm ( hermon, &init_hca ) ) != 0 )
  1984. goto err_alloc_icm;
  1985. /* Initialise HCA */
  1986. MLX_FILL_1 ( &init_hca, 0, version, 0x02 /* "Must be 0x02" */ );
  1987. MLX_FILL_1 ( &init_hca, 5, udp, 1 );
  1988. MLX_FILL_1 ( &init_hca, 74, uar_parameters.log_max_uars, 8 );
  1989. if ( ( rc = hermon_cmd_init_hca ( hermon, &init_hca ) ) != 0 ) {
  1990. DBGC ( hermon, "Hermon %p could not initialise HCA: %s\n",
  1991. hermon, strerror ( rc ) );
  1992. goto err_init_hca;
  1993. }
  1994. /* Set up memory protection */
  1995. if ( ( rc = hermon_setup_mpt ( hermon ) ) != 0 )
  1996. goto err_setup_mpt;
  1997. /* Set up event queue */
  1998. if ( ( rc = hermon_create_eq ( hermon ) ) != 0 )
  1999. goto err_create_eq;
  2000. /* Register Infiniband devices */
  2001. for ( i = 0 ; i < HERMON_NUM_PORTS ; i++ ) {
  2002. if ( ( rc = register_ibdev ( hermon->ibdev[i] ) ) != 0 ) {
  2003. DBGC ( hermon, "Hermon %p could not register IB "
  2004. "device: %s\n", hermon, strerror ( rc ) );
  2005. goto err_register_ibdev;
  2006. }
  2007. }
  2008. return 0;
  2009. i = ( HERMON_NUM_PORTS - 1 );
  2010. err_register_ibdev:
  2011. for ( ; i >= 0 ; i-- )
  2012. unregister_ibdev ( hermon->ibdev[i] );
  2013. hermon_destroy_eq ( hermon );
  2014. err_create_eq:
  2015. err_setup_mpt:
  2016. hermon_cmd_close_hca ( hermon );
  2017. err_init_hca:
  2018. hermon_free_icm ( hermon );
  2019. err_alloc_icm:
  2020. err_get_cap:
  2021. hermon_stop_firmware ( hermon );
  2022. err_start_firmware:
  2023. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2024. err_mailbox_out:
  2025. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2026. err_mailbox_in:
  2027. i = ( HERMON_NUM_PORTS - 1 );
  2028. err_alloc_ibdev:
  2029. for ( ; i >= 0 ; i-- )
  2030. ibdev_put ( hermon->ibdev[i] );
  2031. free ( hermon );
  2032. err_alloc_hermon:
  2033. return rc;
  2034. }
  2035. /**
  2036. * Remove PCI device
  2037. *
  2038. * @v pci PCI device
  2039. */
  2040. static void hermon_remove ( struct pci_device *pci ) {
  2041. struct hermon *hermon = pci_get_drvdata ( pci );
  2042. int i;
  2043. for ( i = ( HERMON_NUM_PORTS - 1 ) ; i >= 0 ; i-- )
  2044. unregister_ibdev ( hermon->ibdev[i] );
  2045. hermon_destroy_eq ( hermon );
  2046. hermon_cmd_close_hca ( hermon );
  2047. hermon_free_icm ( hermon );
  2048. hermon_stop_firmware ( hermon );
  2049. hermon_stop_firmware ( hermon );
  2050. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2051. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2052. for ( i = ( HERMON_NUM_PORTS - 1 ) ; i >= 0 ; i-- )
  2053. ibdev_put ( hermon->ibdev[i] );
  2054. free ( hermon );
  2055. }
  2056. static struct pci_device_id hermon_nics[] = {
  2057. PCI_ROM ( 0x15b3, 0x6340, "mt25408", "MT25408 HCA driver" ),
  2058. PCI_ROM ( 0x15b3, 0x634a, "mt25418", "MT25418 HCA driver" ),
  2059. PCI_ROM ( 0x15b3, 0x6732, "mt26418", "MT26418 HCA driver" ),
  2060. };
  2061. struct pci_driver hermon_driver __pci_driver = {
  2062. .ids = hermon_nics,
  2063. .id_count = ( sizeof ( hermon_nics ) / sizeof ( hermon_nics[0] ) ),
  2064. .probe = hermon_probe,
  2065. .remove = hermon_remove,
  2066. };