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  1. /*
  2. * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
  3. * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
  4. * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
  5. *
  6. * Lightly modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
  7. *
  8. * Permission to use, copy, modify, and distribute this software for any
  9. * purpose with or without fee is hereby granted, provided that the above
  10. * copyright notice and this permission notice appear in all copies.
  11. *
  12. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19. *
  20. */
  21. FILE_LICENCE ( MIT );
  22. /******************************\
  23. Hardware Descriptor Functions
  24. \******************************/
  25. #include "ath5k.h"
  26. #include "reg.h"
  27. #include "base.h"
  28. /*
  29. * TX Descriptors
  30. */
  31. #define FCS_LEN 4
  32. /*
  33. * Initialize the 2-word tx control descriptor on 5210/5211
  34. */
  35. static int
  36. ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
  37. unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
  38. unsigned int tx_power __unused, unsigned int tx_rate0, unsigned int tx_tries0,
  39. unsigned int key_index __unused, unsigned int antenna_mode, unsigned int flags,
  40. unsigned int rtscts_rate __unused, unsigned int rtscts_duration)
  41. {
  42. u32 frame_type;
  43. struct ath5k_hw_2w_tx_ctl *tx_ctl;
  44. unsigned int frame_len;
  45. tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
  46. /*
  47. * Validate input
  48. * - Zero retries don't make sense.
  49. * - A zero rate will put the HW into a mode where it continously sends
  50. * noise on the channel, so it is important to avoid this.
  51. */
  52. if (tx_tries0 == 0) {
  53. DBG("ath5k: zero retries\n");
  54. return -EINVAL;
  55. }
  56. if (tx_rate0 == 0) {
  57. DBG("ath5k: zero rate\n");
  58. return -EINVAL;
  59. }
  60. /* Clear descriptor */
  61. memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
  62. /* Setup control descriptor */
  63. /* Verify and set frame length */
  64. frame_len = pkt_len + FCS_LEN;
  65. if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
  66. return -EINVAL;
  67. tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
  68. /* Verify and set buffer length */
  69. if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
  70. return -EINVAL;
  71. tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
  72. /*
  73. * Verify and set header length
  74. * XXX: I only found that on 5210 code, does it work on 5211 ?
  75. */
  76. if (ah->ah_version == AR5K_AR5210) {
  77. if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
  78. return -EINVAL;
  79. tx_ctl->tx_control_0 |=
  80. AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
  81. }
  82. /*Diferences between 5210-5211*/
  83. if (ah->ah_version == AR5K_AR5210) {
  84. switch (type) {
  85. case AR5K_PKT_TYPE_BEACON:
  86. case AR5K_PKT_TYPE_PROBE_RESP:
  87. frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
  88. case AR5K_PKT_TYPE_PIFS:
  89. frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
  90. default:
  91. frame_type = type /*<< 2 ?*/;
  92. }
  93. tx_ctl->tx_control_0 |=
  94. AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
  95. AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
  96. } else {
  97. tx_ctl->tx_control_0 |=
  98. AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
  99. AR5K_REG_SM(antenna_mode,
  100. AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
  101. tx_ctl->tx_control_1 |=
  102. AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
  103. }
  104. #define _TX_FLAGS(_c, _flag) \
  105. if (flags & AR5K_TXDESC_##_flag) { \
  106. tx_ctl->tx_control_##_c |= \
  107. AR5K_2W_TX_DESC_CTL##_c##_##_flag; \
  108. }
  109. _TX_FLAGS(0, CLRDMASK);
  110. _TX_FLAGS(0, VEOL);
  111. _TX_FLAGS(0, INTREQ);
  112. _TX_FLAGS(0, RTSENA);
  113. _TX_FLAGS(1, NOACK);
  114. #undef _TX_FLAGS
  115. /*
  116. * RTS/CTS Duration [5210 ?]
  117. */
  118. if ((ah->ah_version == AR5K_AR5210) &&
  119. (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
  120. tx_ctl->tx_control_1 |= rtscts_duration &
  121. AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
  122. return 0;
  123. }
  124. /*
  125. * Initialize the 4-word tx control descriptor on 5212
  126. */
  127. static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
  128. struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len __unused,
  129. enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
  130. unsigned int tx_tries0, unsigned int key_index __unused,
  131. unsigned int antenna_mode, unsigned int flags,
  132. unsigned int rtscts_rate,
  133. unsigned int rtscts_duration)
  134. {
  135. struct ath5k_hw_4w_tx_ctl *tx_ctl;
  136. unsigned int frame_len;
  137. tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
  138. /*
  139. * Validate input
  140. * - Zero retries don't make sense.
  141. * - A zero rate will put the HW into a mode where it continously sends
  142. * noise on the channel, so it is important to avoid this.
  143. */
  144. if (tx_tries0 == 0) {
  145. DBG("ath5k: zero retries\n");
  146. return -EINVAL;
  147. }
  148. if (tx_rate0 == 0) {
  149. DBG("ath5k: zero rate\n");
  150. return -EINVAL;
  151. }
  152. tx_power += ah->ah_txpower.txp_offset;
  153. if (tx_power > AR5K_TUNE_MAX_TXPOWER)
  154. tx_power = AR5K_TUNE_MAX_TXPOWER;
  155. /* Clear descriptor */
  156. memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
  157. /* Setup control descriptor */
  158. /* Verify and set frame length */
  159. frame_len = pkt_len + FCS_LEN;
  160. if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
  161. return -EINVAL;
  162. tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
  163. /* Verify and set buffer length */
  164. if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
  165. return -EINVAL;
  166. tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
  167. tx_ctl->tx_control_0 |=
  168. AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
  169. AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
  170. tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
  171. AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
  172. tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
  173. AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
  174. tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
  175. #define _TX_FLAGS(_c, _flag) \
  176. if (flags & AR5K_TXDESC_##_flag) { \
  177. tx_ctl->tx_control_##_c |= \
  178. AR5K_4W_TX_DESC_CTL##_c##_##_flag; \
  179. }
  180. _TX_FLAGS(0, CLRDMASK);
  181. _TX_FLAGS(0, VEOL);
  182. _TX_FLAGS(0, INTREQ);
  183. _TX_FLAGS(0, RTSENA);
  184. _TX_FLAGS(0, CTSENA);
  185. _TX_FLAGS(1, NOACK);
  186. #undef _TX_FLAGS
  187. /*
  188. * RTS/CTS
  189. */
  190. if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
  191. if ((flags & AR5K_TXDESC_RTSENA) &&
  192. (flags & AR5K_TXDESC_CTSENA))
  193. return -EINVAL;
  194. tx_ctl->tx_control_2 |= rtscts_duration &
  195. AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
  196. tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
  197. AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
  198. }
  199. return 0;
  200. }
  201. /*
  202. * Proccess the tx status descriptor on 5210/5211
  203. */
  204. static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah __unused,
  205. struct ath5k_desc *desc, struct ath5k_tx_status *ts)
  206. {
  207. struct ath5k_hw_2w_tx_ctl *tx_ctl;
  208. struct ath5k_hw_tx_status *tx_status;
  209. tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
  210. tx_status = &desc->ud.ds_tx5210.tx_stat;
  211. /* No frame has been send or error */
  212. if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)
  213. return -EINPROGRESS;
  214. /*
  215. * Get descriptor status
  216. */
  217. ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
  218. AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
  219. ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
  220. AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
  221. ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
  222. AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
  223. /*TODO: ts->ts_virtcol + test*/
  224. ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
  225. AR5K_DESC_TX_STATUS1_SEQ_NUM);
  226. ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
  227. AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
  228. ts->ts_antenna = 1;
  229. ts->ts_status = 0;
  230. ts->ts_rate[0] = AR5K_REG_MS(tx_ctl->tx_control_0,
  231. AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
  232. ts->ts_retry[0] = ts->ts_longretry;
  233. ts->ts_final_idx = 0;
  234. if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
  235. if (tx_status->tx_status_0 &
  236. AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
  237. ts->ts_status |= AR5K_TXERR_XRETRY;
  238. if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
  239. ts->ts_status |= AR5K_TXERR_FIFO;
  240. if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
  241. ts->ts_status |= AR5K_TXERR_FILT;
  242. }
  243. return 0;
  244. }
  245. /*
  246. * Proccess a tx status descriptor on 5212
  247. */
  248. static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah __unused,
  249. struct ath5k_desc *desc, struct ath5k_tx_status *ts)
  250. {
  251. struct ath5k_hw_4w_tx_ctl *tx_ctl;
  252. struct ath5k_hw_tx_status *tx_status;
  253. tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
  254. tx_status = &desc->ud.ds_tx5212.tx_stat;
  255. /* No frame has been send or error */
  256. if (!(tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE))
  257. return -EINPROGRESS;
  258. /*
  259. * Get descriptor status
  260. */
  261. ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
  262. AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
  263. ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
  264. AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
  265. ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
  266. AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
  267. ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
  268. AR5K_DESC_TX_STATUS1_SEQ_NUM);
  269. ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
  270. AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
  271. ts->ts_antenna = (tx_status->tx_status_1 &
  272. AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
  273. ts->ts_status = 0;
  274. ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
  275. AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX);
  276. ts->ts_retry[0] = ts->ts_longretry;
  277. ts->ts_rate[0] = tx_ctl->tx_control_3 &
  278. AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
  279. /* TX error */
  280. if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
  281. if (tx_status->tx_status_0 &
  282. AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
  283. ts->ts_status |= AR5K_TXERR_XRETRY;
  284. if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
  285. ts->ts_status |= AR5K_TXERR_FIFO;
  286. if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
  287. ts->ts_status |= AR5K_TXERR_FILT;
  288. }
  289. return 0;
  290. }
  291. /*
  292. * RX Descriptors
  293. */
  294. /*
  295. * Initialize an rx control descriptor
  296. */
  297. static int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah __unused,
  298. struct ath5k_desc *desc,
  299. u32 size, unsigned int flags)
  300. {
  301. struct ath5k_hw_rx_ctl *rx_ctl;
  302. rx_ctl = &desc->ud.ds_rx.rx_ctl;
  303. /*
  304. * Clear the descriptor
  305. * If we don't clean the status descriptor,
  306. * while scanning we get too many results,
  307. * most of them virtual, after some secs
  308. * of scanning system hangs. M.F.
  309. */
  310. memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
  311. /* Setup descriptor */
  312. rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
  313. if (rx_ctl->rx_control_1 != size)
  314. return -EINVAL;
  315. if (flags & AR5K_RXDESC_INTREQ)
  316. rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
  317. return 0;
  318. }
  319. /*
  320. * Proccess the rx status descriptor on 5210/5211
  321. */
  322. static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah __unused,
  323. struct ath5k_desc *desc, struct ath5k_rx_status *rs)
  324. {
  325. struct ath5k_hw_rx_status *rx_status;
  326. rx_status = &desc->ud.ds_rx.u.rx_stat;
  327. /* No frame received / not ready */
  328. if (!(rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_DONE))
  329. return -EINPROGRESS;
  330. /*
  331. * Frame receive status
  332. */
  333. rs->rs_datalen = rx_status->rx_status_0 &
  334. AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
  335. rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
  336. AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
  337. rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
  338. AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
  339. rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
  340. AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA);
  341. rs->rs_more = !!(rx_status->rx_status_0 &
  342. AR5K_5210_RX_DESC_STATUS0_MORE);
  343. /* TODO: this timestamp is 13 bit, later on we assume 15 bit */
  344. rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
  345. AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
  346. rs->rs_status = 0;
  347. rs->rs_phyerr = 0;
  348. rs->rs_keyix = AR5K_RXKEYIX_INVALID;
  349. /*
  350. * Receive/descriptor errors
  351. */
  352. if (!(rx_status->rx_status_1 &
  353. AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
  354. if (rx_status->rx_status_1 &
  355. AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
  356. rs->rs_status |= AR5K_RXERR_CRC;
  357. if (rx_status->rx_status_1 &
  358. AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
  359. rs->rs_status |= AR5K_RXERR_FIFO;
  360. if (rx_status->rx_status_1 &
  361. AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
  362. rs->rs_status |= AR5K_RXERR_PHY;
  363. rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
  364. AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
  365. }
  366. if (rx_status->rx_status_1 &
  367. AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
  368. rs->rs_status |= AR5K_RXERR_DECRYPT;
  369. }
  370. return 0;
  371. }
  372. /*
  373. * Proccess the rx status descriptor on 5212
  374. */
  375. static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah __unused,
  376. struct ath5k_desc *desc, struct ath5k_rx_status *rs)
  377. {
  378. struct ath5k_hw_rx_status *rx_status;
  379. struct ath5k_hw_rx_error *rx_err;
  380. rx_status = &desc->ud.ds_rx.u.rx_stat;
  381. /* Overlay on error */
  382. rx_err = &desc->ud.ds_rx.u.rx_err;
  383. /* No frame received / not ready */
  384. if (!(rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_DONE))
  385. return -EINPROGRESS;
  386. /*
  387. * Frame receive status
  388. */
  389. rs->rs_datalen = rx_status->rx_status_0 &
  390. AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
  391. rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
  392. AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
  393. rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
  394. AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
  395. rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
  396. AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA);
  397. rs->rs_more = !!(rx_status->rx_status_0 &
  398. AR5K_5212_RX_DESC_STATUS0_MORE);
  399. rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
  400. AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
  401. rs->rs_status = 0;
  402. rs->rs_phyerr = 0;
  403. rs->rs_keyix = AR5K_RXKEYIX_INVALID;
  404. /*
  405. * Receive/descriptor errors
  406. */
  407. if (!(rx_status->rx_status_1 &
  408. AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
  409. if (rx_status->rx_status_1 &
  410. AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
  411. rs->rs_status |= AR5K_RXERR_CRC;
  412. if (rx_status->rx_status_1 &
  413. AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
  414. rs->rs_status |= AR5K_RXERR_PHY;
  415. rs->rs_phyerr |= AR5K_REG_MS(rx_err->rx_error_1,
  416. AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
  417. }
  418. if (rx_status->rx_status_1 &
  419. AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
  420. rs->rs_status |= AR5K_RXERR_DECRYPT;
  421. if (rx_status->rx_status_1 &
  422. AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
  423. rs->rs_status |= AR5K_RXERR_MIC;
  424. }
  425. return 0;
  426. }
  427. /*
  428. * Init function pointers inside ath5k_hw struct
  429. */
  430. int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
  431. {
  432. if (ah->ah_version != AR5K_AR5210 &&
  433. ah->ah_version != AR5K_AR5211 &&
  434. ah->ah_version != AR5K_AR5212)
  435. return -ENOTSUP;
  436. if (ah->ah_version == AR5K_AR5212) {
  437. ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
  438. ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
  439. ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
  440. } else {
  441. ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
  442. ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
  443. ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
  444. }
  445. if (ah->ah_version == AR5K_AR5212)
  446. ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
  447. else if (ah->ah_version <= AR5K_AR5211)
  448. ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
  449. return 0;
  450. }