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ath.h 6.1KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
  5. * Original from Linux kernel 3.0.1
  6. *
  7. * Permission to use, copy, modify, and/or distribute this software for any
  8. * purpose with or without fee is hereby granted, provided that the above
  9. * copyright notice and this permission notice appear in all copies.
  10. *
  11. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef ATH_H
  20. #define ATH_H
  21. #include <unistd.h>
  22. #include <ipxe/net80211.h>
  23. /* This block of functions are from kernel.h v3.0.1 */
  24. #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
  25. #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
  26. #define BITS_PER_BYTE 8
  27. #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
  28. #define BIT(nr) (1UL << (nr))
  29. #define min(x, y) ({ \
  30. typeof(x) _min1 = (x); \
  31. typeof(y) _min2 = (y); \
  32. (void) (&_min1 == &_min2); \
  33. _min1 < _min2 ? _min1 : _min2; })
  34. #define max(x, y) ({ \
  35. typeof(x) _max1 = (x); \
  36. typeof(y) _max2 = (y); \
  37. (void) (&_max1 == &_max2); \
  38. _max1 > _max2 ? _max1 : _max2; })
  39. #define abs(x) ({ \
  40. long ret; \
  41. if (sizeof(x) == sizeof(long)) { \
  42. long __x = (x); \
  43. ret = (__x < 0) ? -__x : __x; \
  44. } else { \
  45. int __x = (x); \
  46. ret = (__x < 0) ? -__x : __x; \
  47. } \
  48. ret; \
  49. })
  50. #define ___constant_swab16(x) ((uint16_t)( \
  51. (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \
  52. (((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
  53. #define ___constant_swab32(x) ((uint32_t)( \
  54. (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \
  55. (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \
  56. (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \
  57. (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
  58. #define __swab16(x) ___constant_swab16(x)
  59. #define __swab32(x) ___constant_swab32(x)
  60. #define swab16 __swab16
  61. #define swab32 __swab32
  62. static inline int32_t sign_extend32(uint32_t value, int index)
  63. {
  64. uint8_t shift = 31 - index;
  65. return (int32_t)(value << shift) >> shift;
  66. }
  67. static inline u16 __get_unaligned_le16(const u8 *p)
  68. {
  69. return p[0] | p[1] << 8;
  70. }
  71. static inline u32 __get_unaligned_le32(const u8 *p)
  72. {
  73. return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24;
  74. }
  75. static inline u16 get_unaligned_le16(const void *p)
  76. {
  77. return __get_unaligned_le16((const u8 *)p);
  78. }
  79. static inline u32 get_unaligned_le32(const void *p)
  80. {
  81. return __get_unaligned_le32((const u8 *)p);
  82. }
  83. /* End Kernel Block */
  84. /*
  85. * The key cache is used for h/w cipher state and also for
  86. * tracking station state such as the current tx antenna.
  87. * We also setup a mapping table between key cache slot indices
  88. * and station state to short-circuit node lookups on rx.
  89. * Different parts have different size key caches. We handle
  90. * up to ATH_KEYMAX entries (could dynamically allocate state).
  91. */
  92. #define ATH_KEYMAX 128 /* max key cache size we handle */
  93. static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  94. struct ath_ani {
  95. int caldone;
  96. unsigned int longcal_timer;
  97. unsigned int shortcal_timer;
  98. unsigned int resetcal_timer;
  99. unsigned int checkani_timer;
  100. int timer;
  101. };
  102. struct ath_cycle_counters {
  103. u32 cycles;
  104. u32 rx_busy;
  105. u32 rx_frame;
  106. u32 tx_frame;
  107. };
  108. enum ath_device_state {
  109. ATH_HW_UNAVAILABLE,
  110. ATH_HW_INITIALIZED,
  111. };
  112. enum ath_bus_type {
  113. ATH_PCI,
  114. ATH_AHB,
  115. ATH_USB,
  116. };
  117. struct reg_dmn_pair_mapping {
  118. u16 regDmnEnum;
  119. u16 reg_5ghz_ctl;
  120. u16 reg_2ghz_ctl;
  121. };
  122. struct ath_regulatory {
  123. char alpha2[2];
  124. u16 country_code;
  125. u16 max_power_level;
  126. u32 tp_scale;
  127. u16 current_rd;
  128. u16 current_rd_ext;
  129. int16_t power_limit;
  130. struct reg_dmn_pair_mapping *regpair;
  131. };
  132. enum ath_crypt_caps {
  133. ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
  134. ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
  135. };
  136. struct ath_keyval {
  137. u8 kv_type;
  138. u8 kv_pad;
  139. u16 kv_len;
  140. u8 kv_val[16]; /* TK */
  141. u8 kv_mic[8]; /* Michael MIC key */
  142. u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
  143. * supports both MIC keys in the same key cache entry;
  144. * in that case, kv_mic is the RX key) */
  145. };
  146. enum ath_cipher {
  147. ATH_CIPHER_WEP = 0,
  148. ATH_CIPHER_AES_OCB = 1,
  149. ATH_CIPHER_AES_CCM = 2,
  150. ATH_CIPHER_CKIP = 3,
  151. ATH_CIPHER_TKIP = 4,
  152. ATH_CIPHER_CLR = 5,
  153. ATH_CIPHER_MIC = 127
  154. };
  155. /**
  156. * struct ath_ops - Register read/write operations
  157. *
  158. * @read: Register read
  159. * @multi_read: Multiple register read
  160. * @write: Register write
  161. * @enable_write_buffer: Enable multiple register writes
  162. * @write_flush: flush buffered register writes and disable buffering
  163. */
  164. struct ath_ops {
  165. unsigned int (*read)(void *, u32 reg_offset);
  166. void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
  167. void (*write)(void *, u32 val, u32 reg_offset);
  168. void (*enable_write_buffer)(void *);
  169. void (*write_flush) (void *);
  170. u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
  171. };
  172. struct ath_common;
  173. struct ath_bus_ops;
  174. struct ath_common {
  175. void *ah;
  176. void *priv;
  177. struct net80211_device *dev;
  178. int debug_mask;
  179. enum ath_device_state state;
  180. struct ath_ani ani;
  181. u16 cachelsz;
  182. u16 curaid;
  183. u8 macaddr[ETH_ALEN];
  184. u8 curbssid[ETH_ALEN];
  185. u8 bssidmask[ETH_ALEN];
  186. u8 tx_chainmask;
  187. u8 rx_chainmask;
  188. u32 rx_bufsize;
  189. u32 keymax;
  190. enum ath_crypt_caps crypt_caps;
  191. unsigned int clockrate;
  192. struct ath_cycle_counters cc_ani;
  193. struct ath_cycle_counters cc_survey;
  194. struct ath_regulatory regulatory;
  195. const struct ath_ops *ops;
  196. const struct ath_bus_ops *bus_ops;
  197. int btcoex_enabled;
  198. };
  199. struct io_buffer *ath_rxbuf_alloc(struct ath_common *common,
  200. u32 len,
  201. u32 *iob_addr);
  202. void ath_hw_setbssidmask(struct ath_common *common);
  203. int ath_hw_keyreset(struct ath_common *common, u16 entry);
  204. void ath_hw_cycle_counters_update(struct ath_common *common);
  205. int32_t ath_hw_get_listen_time(struct ath_common *common);
  206. #endif /* ATH_H */