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3c515.c 24KB

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  1. /*
  2. * 3c515.c -- 3COM 3C515 Fast Etherlink ISA 10/100BASE-TX driver for etherboot
  3. * Copyright (C) 2002 Timothy Legge <tlegge@rogers.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. *
  19. * Portions of this code:
  20. * Copyright (C) 1997-2002 Donald Becker 3c515.c: A 3Com ISA EtherLink XL "Corkscrew" ethernet driver for linux.
  21. * Copyright (C) 2001 P.J.H.Fox (fox@roestock.demon.co.uk) ISAPNP Tools
  22. * Copyright (c) 2002 Jaroslav Kysela <perex@suse.cz> ISA Plug & Play support Linux Kernel
  23. * Copyright (C) 2000 Shusuke Nisiyama <shu@athena.qe.eng.hokudai.ac.jp> etherboot-5.0.5 3c595.c
  24. * Coptright (C) 1995 Martin Renters etherboot-5.0.5 3c509.c
  25. * Copyright (C) 1999 LightSys Technology Services, Inc. etherboot-5.0.5 3c90x.c
  26. * Portions Copyright (C) 1999 Steve Smith etherboot-5.0.5 3c90x.c
  27. *
  28. * The probe and reset functions and defines are direct copies from the
  29. * Becker code modified where necessary to make it work for etherboot
  30. *
  31. * The poll and transmit functions either contain code from or were written by referencing
  32. * the above referenced etherboot drivers. This driver would not have been
  33. * possible without this prior work
  34. *
  35. * REVISION HISTORY:
  36. * ================
  37. * v0.10 4-17-2002 TJL Initial implementation.
  38. * v0.11 4-17-2002 TJL Cleanup of the code
  39. * v0.12 4-26-2002 TJL Added ISA Plug and Play for Non-PNP Bioses
  40. * v0.13 6-10-2002 TJL Fixed ISA_PNP MAC Address problem
  41. * v0.14 9-23-2003 TJL Replaced delay with currticks
  42. *
  43. * Indent Options: indent -kr -i8
  44. * *********************************************************/
  45. /* to get some global routines like printf */
  46. #include "etherboot.h"
  47. /* to get the interface to the body of the program */
  48. #include "nic.h"
  49. #include "isapnp.h"
  50. #include "isa.h" /* for ISA_ROM */
  51. #include "timer.h"
  52. static void t3c515_wait(unsigned int nticks)
  53. {
  54. unsigned int to = currticks() + nticks;
  55. while (currticks() < to)
  56. /* wait */ ;
  57. }
  58. /* TJL definations */
  59. #define HZ 100
  60. #define u16 unsigned short
  61. #define u32 unsigned long
  62. #define s16 signed short
  63. #define s32 signed long
  64. static int if_port;
  65. struct corkscrew_private *vp;
  66. /* Brought directly from 3c515.c by Becker */
  67. #define CORKSCREW 1
  68. /* Maximum events (Rx packets, etc.) to handle at each interrupt.
  69. static int max_interrupt_work = 20;
  70. */
  71. /* Enable the automatic media selection code -- usually set. */
  72. #define AUTOMEDIA 1
  73. /* Allow the use of fragment bus master transfers instead of only
  74. programmed-I/O for Vortex cards. Full-bus-master transfers are always
  75. enabled by default on Boomerang cards. If VORTEX_BUS_MASTER is defined,
  76. the feature may be turned on using 'options'. */
  77. #define VORTEX_BUS_MASTER
  78. /* A few values that may be tweaked. */
  79. /* Keep the ring sizes a power of two for efficiency. */
  80. #define TX_RING_SIZE 16
  81. #define RX_RING_SIZE 16
  82. #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
  83. /* "Knobs" for adjusting internal parameters. */
  84. /* Put out somewhat more debugging messages. (0 - no msg, 1 minimal msgs). */
  85. #define DRIVER_DEBUG 1
  86. /* Some values here only for performance evaluation and path-coverage
  87. debugging.
  88. static int rx_nocopy, rx_copy, queued_packet;
  89. */
  90. #define CORKSCREW_ID 10
  91. #define EL3WINDOW(win_num) \
  92. outw(SelectWindow + (win_num), nic->ioaddr + EL3_CMD)
  93. #define EL3_CMD 0x0e
  94. #define EL3_STATUS 0x0e
  95. #define RX_BYTES_MASK (unsigned short) (0x07ff)
  96. enum corkscrew_cmd {
  97. TotalReset = 0 << 11, SelectWindow = 1 << 11, StartCoax = 2 << 11,
  98. RxDisable = 3 << 11, RxEnable = 4 << 11, RxReset = 5 << 11,
  99. UpStall = 6 << 11, UpUnstall = (6 << 11) + 1,
  100. DownStall = (6 << 11) + 2, DownUnstall = (6 << 11) + 3,
  101. RxDiscard = 8 << 11, TxEnable = 9 << 11, TxDisable =
  102. 10 << 11, TxReset = 11 << 11,
  103. FakeIntr = 12 << 11, AckIntr = 13 << 11, SetIntrEnb = 14 << 11,
  104. SetStatusEnb = 15 << 11, SetRxFilter = 16 << 11, SetRxThreshold =
  105. 17 << 11,
  106. SetTxThreshold = 18 << 11, SetTxStart = 19 << 11,
  107. StartDMAUp = 20 << 11, StartDMADown = (20 << 11) + 1, StatsEnable =
  108. 21 << 11,
  109. StatsDisable = 22 << 11, StopCoax = 23 << 11,
  110. };
  111. /* The SetRxFilter command accepts the following classes: */
  112. enum RxFilter {
  113. RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8
  114. };
  115. /* Bits in the general status register. */
  116. enum corkscrew_status {
  117. IntLatch = 0x0001, AdapterFailure = 0x0002, TxComplete = 0x0004,
  118. TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
  119. IntReq = 0x0040, StatsFull = 0x0080,
  120. DMADone = 1 << 8, DownComplete = 1 << 9, UpComplete = 1 << 10,
  121. DMAInProgress = 1 << 11, /* DMA controller is still busy. */
  122. CmdInProgress = 1 << 12, /* EL3_CMD is still busy. */
  123. };
  124. /* Register window 1 offsets, the window used in normal operation.
  125. On the Corkscrew this window is always mapped at offsets 0x10-0x1f. */
  126. enum Window1 {
  127. TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
  128. RxStatus = 0x18, Timer = 0x1A, TxStatus = 0x1B,
  129. TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
  130. };
  131. enum Window0 {
  132. Wn0IRQ = 0x08,
  133. #if defined(CORKSCREW)
  134. Wn0EepromCmd = 0x200A, /* Corkscrew EEPROM command register. */
  135. Wn0EepromData = 0x200C, /* Corkscrew EEPROM results register. */
  136. #else
  137. Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
  138. Wn0EepromData = 12, /* Window 0: EEPROM results register. */
  139. #endif
  140. };
  141. enum Win0_EEPROM_bits {
  142. EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
  143. EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
  144. EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
  145. };
  146. enum Window3 { /* Window 3: MAC/config bits. */
  147. Wn3_Config = 0, Wn3_MAC_Ctrl = 6, Wn3_Options = 8,
  148. };
  149. union wn3_config {
  150. int i;
  151. struct w3_config_fields {
  152. unsigned int ram_size:3, ram_width:1, ram_speed:2,
  153. rom_size:2;
  154. int pad8:8;
  155. unsigned int ram_split:2, pad18:2, xcvr:3, pad21:1,
  156. autoselect:1;
  157. int pad24:7;
  158. } u;
  159. };
  160. enum Window4 {
  161. Wn4_NetDiag = 6, Wn4_Media = 10, /* Window 4: Xcvr/media bits. */
  162. };
  163. enum Win4_Media_bits {
  164. Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
  165. Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
  166. Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
  167. Media_LnkBeat = 0x0800,
  168. };
  169. enum Window7 { /* Window 7: Bus Master control. */
  170. Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12,
  171. };
  172. /* Boomerang-style bus master control registers. Note ISA aliases! */
  173. enum MasterCtrl {
  174. PktStatus = 0x400, DownListPtr = 0x404, FragAddr = 0x408, FragLen =
  175. 0x40c,
  176. TxFreeThreshold = 0x40f, UpPktStatus = 0x410, UpListPtr = 0x418,
  177. };
  178. /* The Rx and Tx descriptor lists.
  179. Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
  180. alignment contraint on tx_ring[] and rx_ring[]. */
  181. struct boom_rx_desc {
  182. u32 next;
  183. s32 status;
  184. u32 addr;
  185. s32 length;
  186. };
  187. /* Values for the Rx status entry. */
  188. enum rx_desc_status {
  189. RxDComplete = 0x00008000, RxDError = 0x4000,
  190. /* See boomerang_rx() for actual error bits */
  191. };
  192. struct boom_tx_desc {
  193. u32 next;
  194. s32 status;
  195. u32 addr;
  196. s32 length;
  197. };
  198. struct corkscrew_private {
  199. const char *product_name;
  200. struct net_device *next_module;
  201. /* The Rx and Tx rings are here to keep them quad-word-aligned. */
  202. struct boom_rx_desc rx_ring[RX_RING_SIZE];
  203. struct boom_tx_desc tx_ring[TX_RING_SIZE];
  204. /* The addresses of transmit- and receive-in-place skbuffs. */
  205. struct sk_buff *rx_skbuff[RX_RING_SIZE];
  206. struct sk_buff *tx_skbuff[TX_RING_SIZE];
  207. unsigned int cur_rx, cur_tx; /* The next free ring entry */
  208. unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
  209. struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
  210. int capabilities; /* Adapter capabilities word. */
  211. int options; /* User-settable misc. driver options. */
  212. int last_rx_packets; /* For media autoselection. */
  213. unsigned int available_media:8, /* From Wn3_Options */
  214. media_override:3, /* Passed-in media type. */
  215. default_media:3, /* Read from the EEPROM. */
  216. full_duplex:1, autoselect:1, bus_master:1, /* Vortex can only do a fragment bus-m. */
  217. full_bus_master_tx:1, full_bus_master_rx:1, /* Boomerang */
  218. tx_full:1;
  219. };
  220. /* The action to take with a media selection timer tick.
  221. Note that we deviate from the 3Com order by checking 10base2 before AUI.
  222. */
  223. enum xcvr_types {
  224. XCVR_10baseT =
  225. 0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
  226. XCVR_100baseFx, XCVR_MII = 6, XCVR_Default = 8,
  227. };
  228. static struct media_table {
  229. char *name;
  230. unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
  231. mask:8, /* The transceiver-present bit in Wn3_Config. */
  232. next:8; /* The media type to try next. */
  233. short wait; /* Time before we check media status. */
  234. } media_tbl[] = {
  235. {
  236. "10baseT", Media_10TP, 0x08, XCVR_10base2, (14 * HZ) / 10}
  237. , {
  238. "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1 * HZ) / 10}
  239. , {
  240. "undefined", 0, 0x80, XCVR_10baseT, 10000}
  241. , {
  242. "10base2", 0, 0x10, XCVR_AUI, (1 * HZ) / 10}
  243. , {
  244. "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx,
  245. (14 * HZ) / 10}
  246. , {
  247. "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14 * HZ) / 10}
  248. , {
  249. "MII", 0, 0x40, XCVR_10baseT, 3 * HZ}
  250. , {
  251. "undefined", 0, 0x01, XCVR_10baseT, 10000}
  252. , {
  253. "Default", 0, 0xFF, XCVR_10baseT, 10000}
  254. ,};
  255. /* TILEG Modified to remove reference to dev */
  256. static int corkscrew_found_device(int ioaddr, int irq, int product_index,
  257. int options, struct nic *nic);
  258. static int corkscrew_probe1(int ioaddr, int irq, int product_index,
  259. struct nic *nic);
  260. /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
  261. /* Note: this is the only limit on the number of cards supported!! */
  262. static int options = -1;
  263. /* End Brought directly from 3c515.c by Becker */
  264. /**************************************************************************
  265. RESET - Reset adapter
  266. ***************************************************************************/
  267. static void t515_reset(struct nic *nic)
  268. {
  269. union wn3_config config;
  270. int i;
  271. /* Before initializing select the active media port. */
  272. EL3WINDOW(3);
  273. if (vp->full_duplex)
  274. outb(0x20, nic->ioaddr + Wn3_MAC_Ctrl); /* Set the full-duplex bit. */
  275. config.i = inl(nic->ioaddr + Wn3_Config);
  276. if (vp->media_override != 7) {
  277. DBG ( "Media override to transceiver %d (%s).\n",
  278. vp->media_override,
  279. media_tbl[vp->media_override].name);
  280. if_port = vp->media_override;
  281. } else if (vp->autoselect) {
  282. /* Find first available media type, starting with 100baseTx. */
  283. if_port = 4;
  284. while (!(vp->available_media & media_tbl[if_port].mask))
  285. if_port = media_tbl[if_port].next;
  286. DBG ( "Initial media type %s.\n",
  287. media_tbl[if_port].name);
  288. } else
  289. if_port = vp->default_media;
  290. config.u.xcvr = if_port;
  291. outl(config.i, nic->ioaddr + Wn3_Config);
  292. DBG ( "corkscrew_open() InternalConfig 0x%hX.\n",
  293. config.i);
  294. outw(TxReset, nic->ioaddr + EL3_CMD);
  295. for (i = 20; i >= 0; i--)
  296. if (!(inw(nic->ioaddr + EL3_STATUS) & CmdInProgress))
  297. break;
  298. outw(RxReset, nic->ioaddr + EL3_CMD);
  299. /* Wait a few ticks for the RxReset command to complete. */
  300. for (i = 20; i >= 0; i--)
  301. if (!(inw(nic->ioaddr + EL3_STATUS) & CmdInProgress))
  302. break;
  303. outw(SetStatusEnb | 0x00, nic->ioaddr + EL3_CMD);
  304. #ifdef debug_3c515
  305. EL3WINDOW(4);
  306. DBG ( "FIXME: fix print for irq, not 9" );
  307. DBG ( "corkscrew_open() irq %d media status 0x%hX.\n",
  308. 9, inw(nic->ioaddr + Wn4_Media) );
  309. #endif
  310. /* Set the station address and mask in window 2 each time opened. */
  311. EL3WINDOW(2);
  312. for (i = 0; i < 6; i++)
  313. outb(nic->node_addr[i], nic->ioaddr + i);
  314. for (; i < 12; i += 2)
  315. outw(0, nic->ioaddr + i);
  316. if (if_port == 3)
  317. /* Start the thinnet transceiver. We should really wait 50ms... */
  318. outw(StartCoax, nic->ioaddr + EL3_CMD);
  319. EL3WINDOW(4);
  320. outw((inw(nic->ioaddr + Wn4_Media) & ~(Media_10TP | Media_SQE)) |
  321. media_tbl[if_port].media_bits, nic->ioaddr + Wn4_Media);
  322. /* Switch to the stats window, and clear all stats by reading. */
  323. /* outw(StatsDisable, nic->ioaddr + EL3_CMD);*/
  324. EL3WINDOW(6);
  325. for (i = 0; i < 10; i++)
  326. inb(nic->ioaddr + i);
  327. inw(nic->ioaddr + 10);
  328. inw(nic->ioaddr + 12);
  329. /* New: On the Vortex we must also clear the BadSSD counter. */
  330. EL3WINDOW(4);
  331. inb(nic->ioaddr + 12);
  332. /* ..and on the Boomerang we enable the extra statistics bits. */
  333. outw(0x0040, nic->ioaddr + Wn4_NetDiag);
  334. /* Switch to register set 7 for normal use. */
  335. EL3WINDOW(7);
  336. /* Temporarily left in place. If these FIXMEs are printed
  337. it meand that special logic for that card may need to be added
  338. see Becker's 3c515.c driver */
  339. if (vp->full_bus_master_rx) { /* Boomerang bus master. */
  340. printf("FIXME: Is this if necessary");
  341. vp->cur_rx = vp->dirty_rx = 0;
  342. DBG ( " Filling in the Rx ring.\n" );
  343. for (i = 0; i < RX_RING_SIZE; i++) {
  344. printf("FIXME: Is this if necessary");
  345. }
  346. }
  347. if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
  348. vp->cur_tx = vp->dirty_tx = 0;
  349. outb(PKT_BUF_SZ >> 8, nic->ioaddr + TxFreeThreshold); /* Room for a packet. */
  350. /* Clear the Tx ring. */
  351. for (i = 0; i < TX_RING_SIZE; i++)
  352. vp->tx_skbuff[i] = 0;
  353. outl(0, nic->ioaddr + DownListPtr);
  354. }
  355. /* Set receiver mode: presumably accept b-case and phys addr only. */
  356. outw(SetRxFilter | RxStation | RxMulticast | RxBroadcast | RxProm,
  357. nic->ioaddr + EL3_CMD);
  358. outw(RxEnable, nic->ioaddr + EL3_CMD); /* Enable the receiver. */
  359. outw(TxEnable, nic->ioaddr + EL3_CMD); /* Enable transmitter. */
  360. /* Allow status bits to be seen. */
  361. outw(SetStatusEnb | AdapterFailure | IntReq | StatsFull |
  362. (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
  363. (vp->full_bus_master_rx ? UpComplete : RxComplete) |
  364. (vp->bus_master ? DMADone : 0), nic->ioaddr + EL3_CMD);
  365. /* Ack all pending events, and set active indicator mask. */
  366. outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
  367. nic->ioaddr + EL3_CMD);
  368. outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
  369. | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete,
  370. nic->ioaddr + EL3_CMD);
  371. }
  372. /**************************************************************************
  373. POLL - Wait for a frame
  374. ***************************************************************************/
  375. static int t515_poll(struct nic *nic, int retrieve)
  376. {
  377. short status, cst;
  378. register short rx_fifo;
  379. cst = inw(nic->ioaddr + EL3_STATUS);
  380. if ((cst & RxComplete) == 0) {
  381. /* Ack all pending events, and set active indicator mask. */
  382. outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
  383. nic->ioaddr + EL3_CMD);
  384. outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete |
  385. StatsFull | (vp->
  386. bus_master ? DMADone : 0) | UpComplete |
  387. DownComplete, nic->ioaddr + EL3_CMD);
  388. return 0;
  389. }
  390. status = inw(nic->ioaddr + RxStatus);
  391. if (status & RxDError) {
  392. printf("RxDError\n");
  393. outw(RxDiscard, nic->ioaddr + EL3_CMD);
  394. return 0;
  395. }
  396. rx_fifo = status & RX_BYTES_MASK;
  397. if (rx_fifo == 0)
  398. return 0;
  399. if ( ! retrieve ) return 1;
  400. DBG ( "[l=%d", rx_fifo );
  401. insw(nic->ioaddr + RX_FIFO, nic->packet, rx_fifo / 2);
  402. if (rx_fifo & 1)
  403. nic->packet[rx_fifo - 1] = inb(nic->ioaddr + RX_FIFO);
  404. nic->packetlen = rx_fifo;
  405. while (1) {
  406. status = inw(nic->ioaddr + RxStatus);
  407. DBG ( "0x%hX*", status );
  408. rx_fifo = status & RX_BYTES_MASK;
  409. if (rx_fifo > 0) {
  410. insw(nic->ioaddr + RX_FIFO, nic->packet + nic->packetlen,
  411. rx_fifo / 2);
  412. if (rx_fifo & 1)
  413. nic->packet[nic->packetlen + rx_fifo - 1] =
  414. inb(nic->ioaddr + RX_FIFO);
  415. nic->packetlen += rx_fifo;
  416. DBG ( "+%d", rx_fifo );
  417. }
  418. if ((status & RxComplete) == 0) {
  419. DBG ( "=%d", nic->packetlen );
  420. break;
  421. }
  422. udelay(1000);
  423. }
  424. /* acknowledge reception of packet */
  425. outw(RxDiscard, nic->ioaddr + EL3_CMD);
  426. while (inw(nic->ioaddr + EL3_STATUS) & CmdInProgress);
  427. #ifdef debug_3c515
  428. {
  429. unsigned short type = 0;
  430. type = (nic->packet[12] << 8) | nic->packet[13];
  431. if (nic->packet[0] + nic->packet[1] + nic->packet[2] +
  432. nic->packet[3] + nic->packet[4] + nic->packet[5] ==
  433. 0xFF * ETH_ALEN)
  434. DBG ( ",t=0x%hX,b]", type );
  435. else
  436. DBG ( ",t=0x%hX]", type );
  437. }
  438. #endif
  439. return 1;
  440. }
  441. /*************************************************************************
  442. 3Com 515 - specific routines
  443. **************************************************************************/
  444. static char padmap[] = {
  445. 0, 3, 2, 1
  446. };
  447. /**************************************************************************
  448. TRANSMIT - Transmit a frame
  449. ***************************************************************************/
  450. static void t515_transmit(struct nic *nic, const char *d, /* Destination */
  451. unsigned int t, /* Type */
  452. unsigned int s, /* size */
  453. const char *p)
  454. { /* Packet */
  455. register int len;
  456. int pad;
  457. int status;
  458. DBG ( "{l=%d,t=0x%hX}", s + ETH_HLEN, t );
  459. /* swap bytes of type */
  460. t = htons(t);
  461. len = s + ETH_HLEN; /* actual length of packet */
  462. pad = padmap[len & 3];
  463. /*
  464. * The 3c515 automatically pads short packets to minimum ethernet length,
  465. * but we drop packets that are too large. Perhaps we should truncate
  466. * them instead?
  467. Copied from 3c595. Is this true for the 3c515?
  468. */
  469. if (len + pad > ETH_FRAME_LEN) {
  470. return;
  471. }
  472. /* drop acknowledgements */
  473. while ((status = inb(nic->ioaddr + TxStatus)) & TxComplete) {
  474. /*if(status & (TXS_UNDERRUN|0x88|TXS_STATUS_OVERFLOW)) { */
  475. outw(TxReset, nic->ioaddr + EL3_CMD);
  476. outw(TxEnable, nic->ioaddr + EL3_CMD);
  477. /* } */
  478. outb(0x0, nic->ioaddr + TxStatus);
  479. }
  480. while (inw(nic->ioaddr + TxFree) < len + pad + 4) {
  481. /* no room in FIFO */
  482. }
  483. outw(len, nic->ioaddr + TX_FIFO);
  484. outw(0x0, nic->ioaddr + TX_FIFO); /* Second dword meaningless */
  485. /* write packet */
  486. outsw(nic->ioaddr + TX_FIFO, d, ETH_ALEN / 2);
  487. outsw(nic->ioaddr + TX_FIFO, nic->node_addr, ETH_ALEN / 2);
  488. outw(t, nic->ioaddr + TX_FIFO);
  489. outsw(nic->ioaddr + TX_FIFO, p, s / 2);
  490. if (s & 1)
  491. outb(*(p + s - 1), nic->ioaddr + TX_FIFO);
  492. while (pad--)
  493. outb(0, nic->ioaddr + TX_FIFO); /* Padding */
  494. /* wait for Tx complete */
  495. while ((inw(nic->ioaddr + EL3_STATUS) & CmdInProgress) != 0);
  496. }
  497. /**************************************************************************
  498. DISABLE - Turn off ethernet interface
  499. ***************************************************************************/
  500. static void t515_disable ( struct nic *nic ) {
  501. /* merge reset an disable */
  502. t515_reset(nic);
  503. /* This is a hack. Since ltsp worked on my
  504. system without any disable functionality I
  505. have no way to determine if this works */
  506. /* Disable the receiver and transmitter. */
  507. outw(RxDisable, nic->ioaddr + EL3_CMD);
  508. outw(TxDisable, nic->ioaddr + EL3_CMD);
  509. if (if_port == XCVR_10base2)
  510. /* Turn off thinnet power. Green! */
  511. outw(StopCoax, nic->ioaddr + EL3_CMD);
  512. outw(SetIntrEnb | 0x0000, nic->ioaddr + EL3_CMD);
  513. #ifdef ISA_PNP
  514. /*Deactivate */
  515. /* ACTIVATE;
  516. WRITE_DATA(0);
  517. */
  518. #endif
  519. return;
  520. }
  521. static void t515_irq(struct nic *nic __unused, irq_action_t action __unused)
  522. {
  523. switch ( action ) {
  524. case DISABLE :
  525. break;
  526. case ENABLE :
  527. break;
  528. case FORCE :
  529. break;
  530. }
  531. }
  532. static struct nic_operations t515_operations = {
  533. .connect = dummy_connect,
  534. .poll = t515_poll,
  535. .transmit = t515_transmit,
  536. .irq = t515_irq,
  537. .disable = t515_disable,
  538. };
  539. /**************************************************************************
  540. PROBE - Look for an adapter, this routine's visible to the outside
  541. You should omit the last argument struct pci_device * for a non-PCI NIC
  542. ***************************************************************************/
  543. static int t515_probe ( struct dev *dev, struct isapnp_device *isapnp ) {
  544. struct nic *nic = nic_device ( dev );
  545. /* Direct copy from Beckers 3c515.c removing any ISAPNP sections */
  546. nic->ioaddr = isapnp->ioaddr;
  547. nic->irqno = isapnp->irqno;
  548. activate_isapnp_device ( isapnp, 1 );
  549. /* Check the resource configuration for a matching ioaddr. */
  550. if ((unsigned)(inw(nic->ioaddr + 0x2002) & 0x1f0)
  551. != (nic->ioaddr & 0x1f0)) {
  552. DBG ( "3c515 ioaddr mismatch\n" );
  553. return 0;
  554. }
  555. /* Verify by reading the device ID from the EEPROM. */
  556. {
  557. int timer;
  558. outw(EEPROM_Read + 7, nic->ioaddr + Wn0EepromCmd);
  559. /* Pause for at least 162 us. for the read to take place. */
  560. for (timer = 4; timer >= 0; timer--) {
  561. t3c515_wait(1);
  562. if ((inw(nic->ioaddr + Wn0EepromCmd) & 0x0200) == 0)
  563. break;
  564. }
  565. if (inw(nic->ioaddr + Wn0EepromData) != 0x6d50) {
  566. DBG ( "3c515 read incorrect vendor ID from EEPROM" );
  567. return 0;
  568. }
  569. }
  570. DBG ( "3c515 Resource configuration register 0x%hX, DCR 0x%hX.\n",
  571. inl(nic->ioaddr + 0x2002), inw(nic->ioaddr + 0x2000) );
  572. corkscrew_found_device(nic->ioaddr, nic->irqno, CORKSCREW_ID,
  573. options, nic);
  574. t515_reset(nic);
  575. nic->nic_op = &t515_operations;
  576. return 1;
  577. }
  578. static int
  579. corkscrew_found_device(int ioaddr, int irq,
  580. int product_index, int options, struct nic *nic)
  581. {
  582. /* Direct copy from Becker 3c515.c with unecessary parts removed */
  583. vp->product_name = "3c515";
  584. vp->options = options;
  585. if (options >= 0) {
  586. vp->media_override =
  587. ((options & 7) == 2) ? 0 : options & 7;
  588. vp->full_duplex = (options & 8) ? 1 : 0;
  589. vp->bus_master = (options & 16) ? 1 : 0;
  590. } else {
  591. vp->media_override = 7;
  592. vp->full_duplex = 0;
  593. vp->bus_master = 0;
  594. }
  595. corkscrew_probe1(ioaddr, irq, product_index, nic);
  596. return 0;
  597. }
  598. static int
  599. corkscrew_probe1(int ioaddr, int irq, int product_index __unused,
  600. struct nic *nic)
  601. {
  602. unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
  603. int i;
  604. printf("3Com %s at 0x%hX, ", vp->product_name, ioaddr);
  605. /* Read the station address from the EEPROM. */
  606. EL3WINDOW(0);
  607. for (i = 0; i < 0x18; i++) {
  608. short *phys_addr = (short *) nic->node_addr;
  609. int timer;
  610. outw(EEPROM_Read + i, ioaddr + Wn0EepromCmd);
  611. /* Pause for at least 162 us. for the read to take place. */
  612. for (timer = 4; timer >= 0; timer--) {
  613. t3c515_wait(1);
  614. if ((inw(ioaddr + Wn0EepromCmd) & 0x0200) == 0)
  615. break;
  616. }
  617. eeprom[i] = inw(ioaddr + Wn0EepromData);
  618. DBG ( "Value %d: %hX ", i, eeprom[i] );
  619. checksum ^= eeprom[i];
  620. if (i < 3)
  621. phys_addr[i] = htons(eeprom[i]);
  622. }
  623. checksum = (checksum ^ (checksum >> 8)) & 0xff;
  624. if (checksum != 0x00)
  625. printf(" ***INVALID CHECKSUM 0x%hX*** ", checksum);
  626. printf("%!", nic->node_addr);
  627. if (eeprom[16] == 0x11c7) { /* Corkscrew */
  628. }
  629. printf(", IRQ %d\n", irq);
  630. /* Tell them about an invalid IRQ. */
  631. if ( (irq <= 0 || irq > 15) ) {
  632. DBG (" *** Warning: this IRQ is unlikely to work! ***\n" );
  633. }
  634. {
  635. char *ram_split[] = { "5:3", "3:1", "1:1", "3:5" };
  636. union wn3_config config;
  637. EL3WINDOW(3);
  638. vp->available_media = inw(ioaddr + Wn3_Options);
  639. config.i = inl(ioaddr + Wn3_Config);
  640. DBG ( " Internal config register is %4.4x, "
  641. "transceivers 0x%hX.\n",
  642. config.i, inw(ioaddr + Wn3_Options) );
  643. printf
  644. (" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
  645. 8 << config.u.ram_size,
  646. config.u.ram_width ? "word" : "byte",
  647. ram_split[config.u.ram_split],
  648. config.u.autoselect ? "autoselect/" : "",
  649. media_tbl[config.u.xcvr].name);
  650. if_port = config.u.xcvr;
  651. vp->default_media = config.u.xcvr;
  652. vp->autoselect = config.u.autoselect;
  653. }
  654. if (vp->media_override != 7) {
  655. printf(" Media override to transceiver type %d (%s).\n",
  656. vp->media_override,
  657. media_tbl[vp->media_override].name);
  658. if_port = vp->media_override;
  659. }
  660. vp->capabilities = eeprom[16];
  661. vp->full_bus_master_tx = (vp->capabilities & 0x20) ? 1 : 0;
  662. /* Rx is broken at 10mbps, so we always disable it. */
  663. /* vp->full_bus_master_rx = 0; */
  664. vp->full_bus_master_rx = (vp->capabilities & 0x20) ? 1 : 0;
  665. return 0;
  666. }
  667. static struct isapnp_id t515_adapters[] = {
  668. { "3c515 (ISAPnP)", ISAPNP_VENDOR('T','C','M'), 0x5051 },
  669. };
  670. static struct isapnp_driver t515_driver =
  671. ISAPNP_DRIVER ( "3c515", t515_adapters );
  672. BOOT_DRIVER ( "3c515", find_isapnp_boot_device, t515_driver,
  673. t515_probe );
  674. ISA_ROM ( "3c515", "3c515 Fast EtherLink ISAPnP" );