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etherfabric_nic.h 4.9KB

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  1. /**************************************************************************
  2. *
  3. * Etherboot driver for Level 5 Etherfabric network cards
  4. *
  5. * Written by Michael Brown <mbrown@fensystems.co.uk>
  6. *
  7. * Copyright Fen Systems Ltd. 2005
  8. * Copyright Level 5 Networks Inc. 2005
  9. *
  10. * This software may be used and distributed according to the terms of
  11. * the GNU General Public License (GPL), incorporated herein by
  12. * reference. Drivers based on or derived from this code fall under
  13. * the GPL and must retain the authorship, copyright and license
  14. * notice.
  15. *
  16. **************************************************************************
  17. */
  18. FILE_LICENCE ( GPL_ANY );
  19. #ifndef EFAB_NIC_H
  20. #define EFAB_NIC_H
  21. #include <ipxe/bitbash.h>
  22. #include <ipxe/i2c.h>
  23. #include <ipxe/spi.h>
  24. #include <ipxe/nvo.h>
  25. #include <ipxe/if_ether.h>
  26. /**************************************************************************
  27. *
  28. * Constants and macros
  29. *
  30. **************************************************************************
  31. */
  32. /* Board IDs. Early boards have no board_type, (e.g. EF1002 and 401/403)
  33. * But newer boards are getting bigger...
  34. */
  35. typedef enum {
  36. EFAB_BOARD_INVALID = 0, /* Early boards do not have board rev. info. */
  37. EFAB_BOARD_SFE4001 = 1,
  38. EFAB_BOARD_SFE4002 = 2,
  39. EFAB_BOARD_SFE4003 = 3,
  40. /* Insert new types before here */
  41. EFAB_BOARD_MAX
  42. } efab_board_type;
  43. /* PHY types. */
  44. typedef enum {
  45. PHY_TYPE_AUTO = 0, /* on development board detect between CX4 & alaska */
  46. PHY_TYPE_CX4_RTMR = 1,
  47. PHY_TYPE_1GIG_ALASKA = 2,
  48. PHY_TYPE_10XPRESS = 3,
  49. PHY_TYPE_XFP = 4,
  50. PHY_TYPE_CX4 = 5,
  51. PHY_TYPE_PM8358 = 6,
  52. } phy_type_t;
  53. /**************************************************************************
  54. *
  55. * Hardware data structures and sizing
  56. *
  57. **************************************************************************
  58. */
  59. #define dma_addr_t unsigned long
  60. typedef efab_qword_t falcon_rx_desc_t;
  61. typedef efab_qword_t falcon_tx_desc_t;
  62. typedef efab_qword_t falcon_event_t;
  63. #define EFAB_BUF_ALIGN 4096
  64. #define EFAB_RXD_SIZE 512
  65. #define EFAB_TXD_SIZE 512
  66. #define EFAB_EVQ_SIZE 512
  67. #define EFAB_NUM_RX_DESC 16
  68. #define EFAB_RX_BUF_SIZE 1600
  69. /**************************************************************************
  70. *
  71. * Data structures
  72. *
  73. **************************************************************************
  74. */
  75. struct efab_nic;
  76. /* A buffer table allocation backing a tx dma, rx dma or eventq */
  77. struct efab_special_buffer {
  78. dma_addr_t dma_addr;
  79. int id;
  80. };
  81. /* A TX queue */
  82. struct efab_tx_queue {
  83. /* The hardware ring */
  84. falcon_tx_desc_t *ring;
  85. /* The software ring storing io_buffers. */
  86. struct io_buffer *buf[EFAB_TXD_SIZE];
  87. /* The buffer table reservation pushed to hardware */
  88. struct efab_special_buffer entry;
  89. /* Software descriptor write ptr */
  90. unsigned int write_ptr;
  91. /* Hardware descriptor read ptr */
  92. unsigned int read_ptr;
  93. };
  94. /* An RX queue */
  95. struct efab_rx_queue {
  96. /* The hardware ring */
  97. falcon_rx_desc_t *ring;
  98. /* The software ring storing io_buffers */
  99. struct io_buffer *buf[EFAB_NUM_RX_DESC];
  100. /* The buffer table reservation pushed to hardware */
  101. struct efab_special_buffer entry;
  102. /* Descriptor write ptr, into both the hardware and software rings */
  103. unsigned int write_ptr;
  104. /* Hardware completion ptr */
  105. unsigned int read_ptr;
  106. };
  107. /* An event queue */
  108. struct efab_ev_queue {
  109. /* The hardware ring to push to hardware.
  110. * Must be the first entry in the structure */
  111. falcon_event_t *ring;
  112. /* The buffer table reservation pushed to hardware */
  113. struct efab_special_buffer entry;
  114. /* Pointers into the ring */
  115. unsigned int read_ptr;
  116. };
  117. struct efab_mac_operations {
  118. int ( * init ) ( struct efab_nic *efab );
  119. };
  120. struct efab_phy_operations {
  121. int ( * init ) ( struct efab_nic *efab );
  122. unsigned int mmds;
  123. };
  124. struct efab_board_operations {
  125. int ( * init ) ( struct efab_nic *efab );
  126. void ( * fini ) ( struct efab_nic *efab );
  127. };
  128. struct efab_nic {
  129. struct net_device *netdev;
  130. int pci_revision;
  131. int is_asic;
  132. /* I2C bit-bashed interface */
  133. struct i2c_bit_basher i2c_bb;
  134. /** SPI bus and devices, and the user visible NVO area */
  135. struct spi_bus spi_bus;
  136. struct spi_device spi_flash;
  137. struct spi_device spi_eeprom;
  138. struct spi_device *spi;
  139. struct nvo_block nvo;
  140. /** Board, MAC, and PHY operations tables */
  141. struct efab_board_operations *board_op;
  142. struct efab_mac_operations *mac_op;
  143. struct efab_phy_operations *phy_op;
  144. /* PHY and board types */
  145. int phy_addr;
  146. int phy_type;
  147. int phy_10g;
  148. int board_type;
  149. /** Memory and IO base */
  150. void *membase;
  151. unsigned int iobase;
  152. /* Buffer table allocation head */
  153. int buffer_head;
  154. /* Queues */
  155. struct efab_rx_queue rx_queue;
  156. struct efab_tx_queue tx_queue;
  157. struct efab_ev_queue ev_queue;
  158. /** MAC address */
  159. uint8_t mac_addr[ETH_ALEN];
  160. /** GMII link options */
  161. unsigned int link_options;
  162. /** Link status */
  163. int link_up;
  164. /** INT_REG_KER */
  165. efab_oword_t int_ker __attribute__ (( aligned ( 16 ) ));
  166. };
  167. #endif /* EFAB_NIC_H */