Vous ne pouvez pas sélectionner plus de 25 sujets Les noms de sujets doivent commencer par une lettre ou un nombre, peuvent contenir des tirets ('-') et peuvent comporter jusqu'à 35 caractères.

intelx.c 12KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473
  1. /*
  2. * Copyright (C) 2013 Michael Brown <mbrown@fensystems.co.uk>.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of the
  7. * License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12. * General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  17. * 02110-1301, USA.
  18. */
  19. FILE_LICENCE ( GPL2_OR_LATER );
  20. #include <stdint.h>
  21. #include <string.h>
  22. #include <unistd.h>
  23. #include <errno.h>
  24. #include <byteswap.h>
  25. #include <ipxe/netdevice.h>
  26. #include <ipxe/ethernet.h>
  27. #include <ipxe/if_ether.h>
  28. #include <ipxe/iobuf.h>
  29. #include <ipxe/malloc.h>
  30. #include <ipxe/pci.h>
  31. #include "intelx.h"
  32. /** @file
  33. *
  34. * Intel 10 Gigabit Ethernet network card driver
  35. *
  36. */
  37. /******************************************************************************
  38. *
  39. * MAC address
  40. *
  41. ******************************************************************************
  42. */
  43. /**
  44. * Try to fetch initial MAC address
  45. *
  46. * @v intel Intel device
  47. * @v ral0 RAL0 register address
  48. * @v hw_addr Hardware address to fill in
  49. * @ret rc Return status code
  50. */
  51. static int intelx_try_fetch_mac ( struct intel_nic *intel, unsigned int ral0,
  52. uint8_t *hw_addr ) {
  53. union intel_receive_address mac;
  54. /* Read current address from RAL0/RAH0 */
  55. mac.reg.low = cpu_to_le32 ( readl ( intel->regs + ral0 ) );
  56. mac.reg.high = cpu_to_le32 ( readl ( intel->regs + ral0 +
  57. ( INTELX_RAH0 - INTELX_RAL0 ) ) );
  58. /* Use current address if valid */
  59. if ( is_valid_ether_addr ( mac.raw ) ) {
  60. DBGC ( intel, "INTEL %p has autoloaded MAC address %s at "
  61. "%#05x\n", intel, eth_ntoa ( mac.raw ), ral0 );
  62. memcpy ( hw_addr, mac.raw, ETH_ALEN );
  63. return 0;
  64. }
  65. return -ENOENT;
  66. }
  67. /**
  68. * Fetch initial MAC address
  69. *
  70. * @v intel Intel device
  71. * @v hw_addr Hardware address to fill in
  72. * @ret rc Return status code
  73. */
  74. static int intelx_fetch_mac ( struct intel_nic *intel, uint8_t *hw_addr ) {
  75. int rc;
  76. /* Try to fetch address from INTELX_RAL0 */
  77. if ( ( rc = intelx_try_fetch_mac ( intel, INTELX_RAL0,
  78. hw_addr ) ) == 0 ) {
  79. return 0;
  80. }
  81. /* Try to fetch address from INTELX_RAL0_ALT */
  82. if ( ( rc = intelx_try_fetch_mac ( intel, INTELX_RAL0_ALT,
  83. hw_addr ) ) == 0 ) {
  84. return 0;
  85. }
  86. DBGC ( intel, "INTEL %p has no MAC address to use\n", intel );
  87. return -ENOENT;
  88. }
  89. /******************************************************************************
  90. *
  91. * Device reset
  92. *
  93. ******************************************************************************
  94. */
  95. /**
  96. * Reset hardware
  97. *
  98. * @v intel Intel device
  99. * @ret rc Return status code
  100. */
  101. static int intelx_reset ( struct intel_nic *intel ) {
  102. uint32_t ctrl;
  103. /* Perform a global software reset */
  104. ctrl = readl ( intel->regs + INTELX_CTRL );
  105. writel ( ( ctrl | INTELX_CTRL_RST | INTELX_CTRL_LRST ),
  106. intel->regs + INTELX_CTRL );
  107. mdelay ( INTELX_RESET_DELAY_MS );
  108. DBGC ( intel, "INTEL %p reset (ctrl %08x)\n", intel, ctrl );
  109. return 0;
  110. }
  111. /******************************************************************************
  112. *
  113. * Link state
  114. *
  115. ******************************************************************************
  116. */
  117. /**
  118. * Check link state
  119. *
  120. * @v netdev Network device
  121. */
  122. static void intelx_check_link ( struct net_device *netdev ) {
  123. struct intel_nic *intel = netdev->priv;
  124. uint32_t links;
  125. /* Read link status */
  126. links = readl ( intel->regs + INTELX_LINKS );
  127. DBGC ( intel, "INTEL %p link status is %08x\n", intel, links );
  128. /* Update network device */
  129. if ( links & INTELX_LINKS_UP ) {
  130. netdev_link_up ( netdev );
  131. } else {
  132. netdev_link_down ( netdev );
  133. }
  134. }
  135. /******************************************************************************
  136. *
  137. * Network device interface
  138. *
  139. ******************************************************************************
  140. */
  141. /**
  142. * Open network device
  143. *
  144. * @v netdev Network device
  145. * @ret rc Return status code
  146. */
  147. static int intelx_open ( struct net_device *netdev ) {
  148. struct intel_nic *intel = netdev->priv;
  149. union intel_receive_address mac;
  150. uint32_t ral0;
  151. uint32_t rah0;
  152. uint32_t dmatxctl;
  153. uint32_t fctrl;
  154. uint32_t srrctl;
  155. uint32_t hlreg0;
  156. uint32_t maxfrs;
  157. uint32_t rdrxctl;
  158. uint32_t rxctrl;
  159. uint32_t dca_rxctrl;
  160. int rc;
  161. /* Create transmit descriptor ring */
  162. if ( ( rc = intel_create_ring ( intel, &intel->tx ) ) != 0 )
  163. goto err_create_tx;
  164. /* Create receive descriptor ring */
  165. if ( ( rc = intel_create_ring ( intel, &intel->rx ) ) != 0 )
  166. goto err_create_rx;
  167. /* Program MAC address */
  168. memset ( &mac, 0, sizeof ( mac ) );
  169. memcpy ( mac.raw, netdev->ll_addr, sizeof ( mac.raw ) );
  170. ral0 = le32_to_cpu ( mac.reg.low );
  171. rah0 = ( le32_to_cpu ( mac.reg.high ) | INTELX_RAH0_AV );
  172. writel ( ral0, intel->regs + INTELX_RAL0 );
  173. writel ( rah0, intel->regs + INTELX_RAH0 );
  174. writel ( ral0, intel->regs + INTELX_RAL0_ALT );
  175. writel ( rah0, intel->regs + INTELX_RAH0_ALT );
  176. /* Allocate interrupt vectors */
  177. writel ( ( INTELX_IVAR_RX0_DEFAULT | INTELX_IVAR_RX0_VALID |
  178. INTELX_IVAR_TX0_DEFAULT | INTELX_IVAR_TX0_VALID ),
  179. intel->regs + INTELX_IVAR );
  180. /* Enable transmitter */
  181. dmatxctl = readl ( intel->regs + INTELX_DMATXCTL );
  182. dmatxctl |= INTELX_DMATXCTL_TE;
  183. writel ( dmatxctl, intel->regs + INTELX_DMATXCTL );
  184. /* Configure receive filter */
  185. fctrl = readl ( intel->regs + INTELX_FCTRL );
  186. fctrl |= ( INTELX_FCTRL_BAM | INTELX_FCTRL_UPE | INTELX_FCTRL_MPE );
  187. writel ( fctrl, intel->regs + INTELX_FCTRL );
  188. /* Configure receive buffer sizes */
  189. srrctl = readl ( intel->regs + INTELX_SRRCTL );
  190. srrctl &= ~INTELX_SRRCTL_BSIZE_MASK;
  191. srrctl |= INTELX_SRRCTL_BSIZE_DEFAULT;
  192. writel ( srrctl, intel->regs + INTELX_SRRCTL );
  193. /* Configure jumbo frames. Required to allow the extra 4-byte
  194. * headroom for VLANs, since we don't use the hardware's
  195. * native VLAN offload.
  196. */
  197. hlreg0 = readl ( intel->regs + INTELX_HLREG0 );
  198. hlreg0 |= INTELX_HLREG0_JUMBOEN;
  199. writel ( hlreg0, intel->regs + INTELX_HLREG0 );
  200. /* Configure frame size */
  201. maxfrs = readl ( intel->regs + INTELX_MAXFRS );
  202. maxfrs &= ~INTELX_MAXFRS_MFS_MASK;
  203. maxfrs |= INTELX_MAXFRS_MFS_DEFAULT;
  204. writel ( maxfrs, intel->regs + INTELX_MAXFRS );
  205. /* Configure receive DMA */
  206. rdrxctl = readl ( intel->regs + INTELX_RDRXCTL );
  207. rdrxctl |= INTELX_RDRXCTL_SECRC;
  208. writel ( rdrxctl, intel->regs + INTELX_RDRXCTL );
  209. /* Clear "must-be-zero" bit for direct cache access (DCA). We
  210. * leave DCA disabled anyway, but if we do not clear this bit
  211. * then the received packets contain garbage data.
  212. */
  213. dca_rxctrl = readl ( intel->regs + INTELX_DCA_RXCTRL );
  214. dca_rxctrl &= ~INTELX_DCA_RXCTRL_MUST_BE_ZERO;
  215. writel ( dca_rxctrl, intel->regs + INTELX_DCA_RXCTRL );
  216. /* Enable receiver */
  217. rxctrl = readl ( intel->regs + INTELX_RXCTRL );
  218. rxctrl |= INTELX_RXCTRL_RXEN;
  219. writel ( rxctrl, intel->regs + INTELX_RXCTRL );
  220. /* Fill receive ring */
  221. intel_refill_rx ( intel );
  222. /* Update link state */
  223. intelx_check_link ( netdev );
  224. return 0;
  225. intel_destroy_ring ( intel, &intel->rx );
  226. err_create_rx:
  227. intel_destroy_ring ( intel, &intel->tx );
  228. err_create_tx:
  229. return rc;
  230. }
  231. /**
  232. * Close network device
  233. *
  234. * @v netdev Network device
  235. */
  236. static void intelx_close ( struct net_device *netdev ) {
  237. struct intel_nic *intel = netdev->priv;
  238. uint32_t rxctrl;
  239. uint32_t dmatxctl;
  240. /* Disable receiver */
  241. rxctrl = readl ( intel->regs + INTELX_RXCTRL );
  242. rxctrl &= ~INTELX_RXCTRL_RXEN;
  243. writel ( rxctrl, intel->regs + INTELX_RXCTRL );
  244. /* Disable transmitter */
  245. dmatxctl = readl ( intel->regs + INTELX_DMATXCTL );
  246. dmatxctl &= ~INTELX_DMATXCTL_TE;
  247. writel ( dmatxctl, intel->regs + INTELX_DMATXCTL );
  248. /* Destroy receive descriptor ring */
  249. intel_destroy_ring ( intel, &intel->rx );
  250. /* Discard any unused receive buffers */
  251. intel_empty_rx ( intel );
  252. /* Destroy transmit descriptor ring */
  253. intel_destroy_ring ( intel, &intel->tx );
  254. /* Reset the NIC, to flush the transmit and receive FIFOs */
  255. intelx_reset ( intel );
  256. }
  257. /**
  258. * Poll for completed and received packets
  259. *
  260. * @v netdev Network device
  261. */
  262. static void intelx_poll ( struct net_device *netdev ) {
  263. struct intel_nic *intel = netdev->priv;
  264. uint32_t eicr;
  265. /* Check for and acknowledge interrupts */
  266. eicr = readl ( intel->regs + INTELX_EICR );
  267. if ( ! eicr )
  268. return;
  269. /* Poll for TX completions, if applicable */
  270. if ( eicr & INTELX_EIRQ_TX0 )
  271. intel_poll_tx ( netdev );
  272. /* Poll for RX completions, if applicable */
  273. if ( eicr & ( INTELX_EIRQ_RX0 | INTELX_EIRQ_RXO ) )
  274. intel_poll_rx ( netdev );
  275. /* Report receive overruns */
  276. if ( eicr & INTELX_EIRQ_RXO )
  277. netdev_rx_err ( netdev, NULL, -ENOBUFS );
  278. /* Check link state, if applicable */
  279. if ( eicr & INTELX_EIRQ_LSC )
  280. intelx_check_link ( netdev );
  281. /* Refill RX ring */
  282. intel_refill_rx ( intel );
  283. }
  284. /**
  285. * Enable or disable interrupts
  286. *
  287. * @v netdev Network device
  288. * @v enable Interrupts should be enabled
  289. */
  290. static void intelx_irq ( struct net_device *netdev, int enable ) {
  291. struct intel_nic *intel = netdev->priv;
  292. uint32_t mask;
  293. mask = ( INTELX_EIRQ_LSC | INTELX_EIRQ_RXO | INTELX_EIRQ_TX0 |
  294. INTELX_EIRQ_RX0 );
  295. if ( enable ) {
  296. writel ( mask, intel->regs + INTELX_EIMS );
  297. } else {
  298. writel ( mask, intel->regs + INTELX_EIMC );
  299. }
  300. }
  301. /** Network device operations */
  302. static struct net_device_operations intelx_operations = {
  303. .open = intelx_open,
  304. .close = intelx_close,
  305. .transmit = intel_transmit,
  306. .poll = intelx_poll,
  307. .irq = intelx_irq,
  308. };
  309. /******************************************************************************
  310. *
  311. * PCI interface
  312. *
  313. ******************************************************************************
  314. */
  315. /**
  316. * Probe PCI device
  317. *
  318. * @v pci PCI device
  319. * @ret rc Return status code
  320. */
  321. static int intelx_probe ( struct pci_device *pci ) {
  322. struct net_device *netdev;
  323. struct intel_nic *intel;
  324. int rc;
  325. /* Allocate and initialise net device */
  326. netdev = alloc_etherdev ( sizeof ( *intel ) );
  327. if ( ! netdev ) {
  328. rc = -ENOMEM;
  329. goto err_alloc;
  330. }
  331. netdev_init ( netdev, &intelx_operations );
  332. intel = netdev->priv;
  333. pci_set_drvdata ( pci, netdev );
  334. netdev->dev = &pci->dev;
  335. memset ( intel, 0, sizeof ( *intel ) );
  336. intel->port = PCI_FUNC ( pci->busdevfn );
  337. intel_init_ring ( &intel->tx, INTEL_NUM_TX_DESC, INTELX_TD );
  338. intel_init_ring ( &intel->rx, INTEL_NUM_RX_DESC, INTELX_RD );
  339. /* Fix up PCI device */
  340. adjust_pci_device ( pci );
  341. /* Map registers */
  342. intel->regs = ioremap ( pci->membase, INTEL_BAR_SIZE );
  343. if ( ! intel->regs ) {
  344. rc = -ENODEV;
  345. goto err_ioremap;
  346. }
  347. /* Reset the NIC */
  348. if ( ( rc = intelx_reset ( intel ) ) != 0 )
  349. goto err_reset;
  350. /* Fetch MAC address */
  351. if ( ( rc = intelx_fetch_mac ( intel, netdev->hw_addr ) ) != 0 )
  352. goto err_fetch_mac;
  353. /* Register network device */
  354. if ( ( rc = register_netdev ( netdev ) ) != 0 )
  355. goto err_register_netdev;
  356. /* Set initial link state */
  357. intelx_check_link ( netdev );
  358. return 0;
  359. unregister_netdev ( netdev );
  360. err_register_netdev:
  361. err_fetch_mac:
  362. intelx_reset ( intel );
  363. err_reset:
  364. iounmap ( intel->regs );
  365. err_ioremap:
  366. netdev_nullify ( netdev );
  367. netdev_put ( netdev );
  368. err_alloc:
  369. return rc;
  370. }
  371. /**
  372. * Remove PCI device
  373. *
  374. * @v pci PCI device
  375. */
  376. static void intelx_remove ( struct pci_device *pci ) {
  377. struct net_device *netdev = pci_get_drvdata ( pci );
  378. struct intel_nic *intel = netdev->priv;
  379. /* Unregister network device */
  380. unregister_netdev ( netdev );
  381. /* Reset the NIC */
  382. intelx_reset ( intel );
  383. /* Free network device */
  384. iounmap ( intel->regs );
  385. netdev_nullify ( netdev );
  386. netdev_put ( netdev );
  387. }
  388. /** PCI device IDs */
  389. static struct pci_device_id intelx_nics[] = {
  390. PCI_ROM ( 0x8086, 0x10fb, "82599", "82599", 0 ),
  391. PCI_ROM ( 0x8086, 0x1528, "x540at2", "X540-AT2", 0 ),
  392. PCI_ROM ( 0x8086, 0x154d, "x520", "X520", 0 ),
  393. PCI_ROM ( 0x8086, 0x1557, "82599", "82599", 0 ),
  394. };
  395. /** PCI driver */
  396. struct pci_driver intelx_driver __pci_driver = {
  397. .ids = intelx_nics,
  398. .id_count = ( sizeof ( intelx_nics ) / sizeof ( intelx_nics[0] ) ),
  399. .probe = intelx_probe,
  400. .remove = intelx_remove,
  401. };