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velocity.h 12KB

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  1. #ifndef _VELOCITY_H
  2. #define _VELOCITY_H
  3. /** @file
  4. *
  5. * VIA Velocity network driver
  6. *
  7. */
  8. FILE_LICENCE ( GPL2_OR_LATER );
  9. /** Skeleton BAR size */
  10. #define VELOCITY_BAR_SIZE 256
  11. /** Default timeout */
  12. #define VELOCITY_TIMEOUT_US 10 * 1000
  13. struct velocity_frag {
  14. uint32_t addr;
  15. uint32_t des2;
  16. } __attribute__ ((packed));
  17. /** Velocity descriptor format */
  18. struct velocity_tx_descriptor {
  19. uint32_t des0;
  20. uint32_t des1;
  21. /* We only use the first fragment, the HW requires us to have 7 */
  22. struct velocity_frag frags[7];
  23. } __attribute__ ((packed));
  24. struct velocity_rx_descriptor {
  25. uint32_t des0;
  26. uint32_t des1;
  27. uint32_t addr;
  28. uint32_t des2;
  29. } __attribute__ ((packed));
  30. #define VELOCITY_DES0_RMBC(_n) (((_n) >> 16) & 0x1fff)
  31. #define VELOCITY_DES0_OWN (1 << 31)
  32. #define VELOCITY_DES0_TERR (1 << 15)
  33. #define VELOCITY_DES0_RXOK (1 << 15)
  34. #define VELOCITY_DES0_FDX (1 << 14)
  35. #define VELOCITY_DES0_GMII (1 << 13)
  36. #define VELOCITY_DES0_LNKFL (1 << 12)
  37. #define VELOCITY_DES0_SHDN (1 << 10)
  38. #define VELOCITY_DES0_CRS (1 << 9)
  39. #define VELOCITY_DES0_CDH (1 << 8)
  40. #define VELOCITY_DES0_ABT (1 << 7)
  41. #define VELOCITY_DES0_OWT (1 << 6)
  42. #define VELOCITY_DES0_OWC (1 << 5)
  43. #define VELOCITY_DES0_COLS (1 << 4)
  44. #define VELOCITY_DES0_RXSHDN (1 << 30)
  45. #define VELOCITY_DES0_RXER (1 << 5)
  46. #define VELOCITY_DES0_RLE (1 << 4)
  47. #define VELOCITY_DES0_CE (1 << 3)
  48. #define VELOCITY_DES0_FAE (1 << 2)
  49. #define VELOCITY_DES0_CRC (1 << 1)
  50. #define VELOCITY_DES0_RX_ERR ( VELOCITY_DES0_RXER | \
  51. VELOCITY_DES0_RLE | \
  52. VELOCITY_DES0_CE | \
  53. VELOCITY_DES0_FAE | \
  54. VELOCITY_DES0_CRC )
  55. /** TX descriptor fragment number */
  56. #define VELOCITY_DES1_FRAG(_n) (((_n + 1) & 0xf) << 28)
  57. #define VELOCITY_DES1_TCPLS ((1 << 24) | (1 << 25))
  58. #define VELOCITY_DES1_INTR (1 << 23)
  59. #define VELOCITY_DES1_PIC (1 << 22)
  60. #define VELOCITY_DES1_VETAG (1 << 21)
  61. #define VELOCITY_DES1_IPCK (1 << 20)
  62. #define VELOCITY_DES1_UDPCK (1 << 19)
  63. #define VELOCITY_DES1_TCPCK (1 << 18)
  64. #define VELOCITY_DES1_JMBO (1 << 17)
  65. #define VELOCITY_DES1_CRC (1 << 16)
  66. #define VELOCITY_DES2_IC (1 << 31)
  67. #define VELOCITY_DES2_SIZE(_n) (((_n) & 0x1fff) << 16)
  68. /** Number of receive descriptors
  69. *
  70. * Must be a multiple of 4 (hardware requirement).
  71. */
  72. #define VELOCITY_RXDESC_NUM 8
  73. #define VELOCITY_RXDESC_SIZE \
  74. ( VELOCITY_RXDESC_NUM * sizeof ( struct velocity_rx_descriptor ) )
  75. /** Number of transmit descriptors */
  76. #define VELOCITY_TXDESC_NUM 8
  77. #define VELOCITY_TXDESC_SIZE \
  78. ( VELOCITY_TXDESC_NUM * sizeof ( struct velocity_tx_descriptor ) )
  79. /** Descriptor alignment */
  80. #define VELOCITY_RING_ALIGN 64
  81. /** Receive buffer length */
  82. #define VELOCITY_RX_MAX_LEN 1536
  83. /** MAC address registers */
  84. #define VELOCITY_MAC0 0x00
  85. #define VELOCITY_MAC1 0x01
  86. #define VELOCITY_MAC2 0x02
  87. #define VELOCITY_MAC3 0x03
  88. #define VELOCITY_MAC4 0x04
  89. #define VELOCITY_MAC5 0x05
  90. /** Receive control register */
  91. #define VELOCITY_RCR 0x06
  92. #define RHINE_RCR_SYMERR_ACCEPT (1 << 7) /*< Accept symbol error */
  93. #define RHINE_RCR_FILTER_ACCEPT (1 << 6) /*< Accept based on filter */
  94. #define RHINE_RCR_LONG_ACCEPT (1 << 5) /*< Accept long packets */
  95. #define RHINE_RCR_PROMISC (1 << 4) /*< Promiscuous mode */
  96. #define RHINE_RCR_BCAST_ACCEPT (1 << 3) /*< Accept broadcast */
  97. #define RHINE_RCR_MCAST_ACCEPT (1 << 2) /*< Accept multicast */
  98. #define RHINE_RCR_RUNT_ACCEPT (1 << 1) /*< Accept runt frames */
  99. #define RHINE_RCR_ERR_ACCEPT (1 << 0) /*< Accept erroneous frames */
  100. /** Transmit control register */
  101. #define VELOCITY_TCR 0x07
  102. #define VELOCITY_TCR_LB0 (1 << 0) /*< Loopback control */
  103. #define VELOCITY_TCR_LB1 (1 << 1) /*< Loopback control */
  104. #define VELOCITY_TCR_COLTMC0 (1 << 2) /*< Collision retry control */
  105. #define VELOCITY_TCR_COLTMC1 (1 << 3) /*< Collision retry control */
  106. /** Command register 0 (set) */
  107. #define VELOCITY_CRS0 0x08
  108. #define VELOCITY_CR0_TXON (1 << 3) /*< Transmit enable */
  109. #define VELOCITY_CR0_RXON (1 << 2) /*< Receive enable */
  110. #define VELOCITY_CR0_STOP (1 << 1) /*< Stop NIC */
  111. #define VELOCITY_CR0_START (1 << 0) /*< Start NIC */
  112. /** Command register 1 (set) */
  113. #define VELOCITY_CRS1 0x09
  114. #define VELOCITY_CR1_SFRST (1 << 7) /*< Software reset */
  115. #define VELOCITY_CR1_TM1EN (1 << 6) /*< Perioding software counting */
  116. #define VELOCITY_CR1_TM0EN (1 << 5) /*< Single-shot software counting */
  117. #define VELOCITY_CR1_DPOLL (1 << 3) /*< Disable auto polling */
  118. #define VELOCITY_CR1_DISAU (1 << 0) /*< Unicast reception disable */
  119. /** Command register 2 (set) */
  120. #define VELOCITY_CRS2 0x0A
  121. #define VELOCITY_CR2_XONEN (1 << 7) /*< XON/XOFF mode enable */
  122. #define VELOCITY_CR2_FDXTFCEN (1 << 6) /*< FDX flow control TX */
  123. #define VELOCITY_CR2_FDXRFCEN (1 << 5)
  124. #define VELOCITY_CR2_HDXFCEN (1 << 4)
  125. /** Command register 3 (set) */
  126. #define VELOCITY_CRS3 0x0B
  127. #define VELOCITY_CR3_FOSRST (1 << 6)
  128. #define VELOCITY_CR3_FPHYRST (1 << 5)
  129. #define VELOCITY_CR3_DIAG (1 << 4)
  130. #define VELOCITY_CR3_INTPCTL (1 << 2)
  131. #define VELOCITY_CR3_GINTMSK1 (1 << 1)
  132. #define VELOCITY_CR3_SWPEND (1 << 0)
  133. /** Command register 0 (clear) */
  134. #define VELOCITY_CRC0 0x0C
  135. /** Command register 1 (clear) */
  136. #define VELOCITY_CRC1 0x0D
  137. /** Command register 2 (clear */
  138. #define VELOCITY_CRC2 0x0E
  139. /** Command register 3 (clear */
  140. #define VELOCITY_CRC3 0x0F
  141. #define VELOCITY_CAM0 0x10
  142. #define VELOCITY_CAM1 0x11
  143. #define VELOCITY_CAM2 0x12
  144. #define VELOCITY_CAM3 0x13
  145. #define VELOCITY_CAM4 0x14
  146. #define VELOCITY_CAM5 0x15
  147. #define VELOCITY_CAM6 0x16
  148. #define VELOCITY_CAM7 0x17
  149. #define VELOCITY_TXDESC_HI 0x18 /* Hi part of 64bit txdesc base addr */
  150. #define VELOCITY_DATABUF_HI 0x1D /* Hi part of 64bit data buffer addr */
  151. #define VELOCITY_INTCTL0 0x20 /* interrupt control register */
  152. #define VELOCITY_RXSUPPTHR 0x20
  153. #define VELOCITY_TXSUPPTHR 0x20
  154. #define VELOCITY_INTHOLDOFF 0x20
  155. #define VELOCITY_INTCTL1 0x21 /* interrupt control register */
  156. #define VELOCITY_TXHOSTERR 0x22 /* TX host error status */
  157. #define VELOCITY_RXHOSTERR 0x23 /* RX host error status */
  158. /** Interrupt status register 0 */
  159. #define VELOCITY_ISR0 0x24
  160. #define VELOCITY_ISR0_PTX3 (1 << 7)
  161. #define VELOCITY_ISR0_PTX2 (1 << 6)
  162. #define VELOCITY_ISR0_PTX1 (1 << 5)
  163. #define VELOCITY_ISR0_PTX0 (1 << 4)
  164. #define VELOCITY_ISR0_PTXI (1 << 3)
  165. #define VELOCITY_ISR0_PRXI (1 << 2)
  166. #define VELOCITY_ISR0_PPTXI (1 << 1)
  167. #define VELOCITY_ISR0_PPRXI (1 << 0)
  168. /** Interrupt status register 1 */
  169. #define VELOCITY_ISR1 0x25
  170. #define VELOCITY_ISR1_SRCI (1 << 7)
  171. #define VELOCITY_ISR1_LSTPEI (1 << 6)
  172. #define VELOCITY_ISR1_LSTEI (1 << 5)
  173. #define VELOCITY_ISR1_OVFL (1 << 4)
  174. #define VELOCITY_ISR1_FLONI (1 << 3)
  175. #define VELOCITY_ISR1_RACEI (1 << 2)
  176. /** Interrupt status register 2 */
  177. #define VELOCITY_ISR2 0x26
  178. #define VELOCITY_ISR2_HFLD (1 << 7)
  179. #define VELOCITY_ISR2_UDPI (1 << 6)
  180. #define VELOCITY_ISR2_MIBFI (1 << 5)
  181. #define VELOCITY_ISR2_SHDNII (1 << 4)
  182. #define VELOCITY_ISR2_PHYI (1 << 3)
  183. #define VELOCITY_ISR2_PWEI (1 << 2)
  184. #define VELOCITY_ISR2_TMR1I (1 << 1)
  185. #define VELOCITY_ISR2_TMR0I (1 << 0)
  186. /** Interrupt status register 3 */
  187. #define VELOCITY_ISR3 0x27
  188. /** Interrupt mask register 0 */
  189. #define VELOCITY_IMR0 0x28
  190. /** Interrupt mask register 1 */
  191. #define VELOCITY_IMR1 0x29
  192. /** Interrupt mask register 2 */
  193. #define VELOCITY_IMR2 0x2a
  194. /** Interrupt mask register 3 */
  195. #define VELOCITY_IMR3 0x2b
  196. #define VELOCITY_TXSTS_PORT 0x2C /* Transmit status port (???) */
  197. #define VELOCITY_TXQCSRS 0x30 /* TX queue ctl/status set */
  198. #define VELOCITY_TXQCSRS_DEAD3 (1 << 15)
  199. #define VELOCITY_TXQCSRS_WAK3 (1 << 14)
  200. #define VELOCITY_TXQCSRS_ACT3 (1 << 13)
  201. #define VELOCITY_TXQCSRS_RUN3 (1 << 12)
  202. #define VELOCITY_TXQCSRS_DEAD2 (1 << 11)
  203. #define VELOCITY_TXQCSRS_WAK2 (1 << 10)
  204. #define VELOCITY_TXQCSRS_ACT2 (1 << 9)
  205. #define VELOCITY_TXQCSRS_RUN2 (1 << 8)
  206. #define VELOCITY_TXQCSRS_DEAD1 (1 << 7)
  207. #define VELOCITY_TXQCSRS_WAK1 (1 << 6)
  208. #define VELOCITY_TXQCSRS_ACT1 (1 << 5)
  209. #define VELOCITY_TXQCSRS_RUN1 (1 << 4)
  210. #define VELOCITY_TXQCSRS_DEAD0 (1 << 3)
  211. #define VELOCITY_TXQCSRS_WAK0 (1 << 2)
  212. #define VELOCITY_TXQCSRS_ACT0 (1 << 1)
  213. #define VELOCITY_TXQCSRS_RUN0 (1 << 0)
  214. #define VELOCITY_RXQCSRS 0x32 /* RX queue ctl/status set */
  215. #define VELOCITY_RXQCSRC 0x36
  216. #define VELOCITY_RXQCSR_DEAD (1 << 3)
  217. #define VELOCITY_RXQCSR_WAK (1 << 2)
  218. #define VELOCITY_RXQCSR_ACT (1 << 1)
  219. #define VELOCITY_RXQCSR_RUN (1 << 0)
  220. #define VELOCITY_TXQCSRC 0x34 /* TX queue ctl/status clear */
  221. #define VELOCITY_RXQCSRC 0x36 /* RX queue ctl/status clear */
  222. #define VELOCITY_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */
  223. #define VELOCITY_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */
  224. #define VELOCITY_TXQTIMER 0x3E /* TX queue timer pend register */
  225. #define VELOCITY_RXQTIMER 0x3F /* RX queue timer pend register */
  226. #define VELOCITY_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */
  227. #define VELOCITY_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */
  228. #define VELOCITY_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */
  229. #define VELOCITY_TXDESC_ADDR_LO3 0x4C /* TX desc3 base addr (lo 32 bits) */
  230. #define VELOCITY_RXDESCNUM 0x50 /* Size of RX desc ring */
  231. #define VELOCITY_TXDESCNUM 0x52 /* Size of TX desc ring */
  232. #define VELOCITY_TXDESC_CONSIDX0 0x54 /* Current TX descriptor index */
  233. #define VELOCITY_TXDESC_CONSIDX1 0x56 /* Current TX descriptor index */
  234. #define VELOCITY_TXDESC_CONSIDX2 0x58 /* Current TX descriptor index */
  235. #define VELOCITY_TXDESC_CONSIDX3 0x5A /* Current TX descriptor index */
  236. #define VELOCITY_TX_PAUSE_TIMER 0x5C /* TX pause frame timer */
  237. #define VELOCITY_RXDESC_RESIDUECNT 0x5E /* RX descriptor residue count */
  238. #define VELOCITY_FIFOTEST0 0x60 /* FIFO test register */
  239. #define VELOCITY_FIFOTEST1 0x64 /* FIFO test register */
  240. #define VELOCITY_CAMADDR 0x68 /* CAM address register */
  241. #define VELOCITY_CAMCTL 0x69 /* CAM control register */
  242. #define VELOCITY_MIICFG 0x6C /* MII port config register */
  243. #define VELOCITY_MIISR 0x6D /* MII port status register */
  244. #define VELOCITY_MIISR_IDLE (1 << 7)
  245. #define VELOCITY_PHYSTS0 0x6E /* PHY status register */
  246. #define VELOCITY_PHYSTS0_LINK (1 << 6)
  247. #define VELOCITY_PHYSTS1 0x6F /* PHY status register */
  248. #define VELOCITY_MIICR 0x70 /* MII command register */
  249. #define VELOCITY_MIICR_MAUTO (1 << 7)
  250. #define VELOCITY_MIICR_RCMD (1 << 6)
  251. #define VELOCITY_MIICR_WCMD (1 << 5)
  252. #define VELOCITY_MIICR_MDPM (1 << 4)
  253. #define VELOCITY_MIICR_MOUT (1 << 3)
  254. #define VELOCITY_MIICR_MDO (1 << 2)
  255. #define VELOCITY_MIICR_MDI (1 << 1)
  256. #define VELOCITY_MIICR_MDC (1 << 0)
  257. #define VELOCITY_MIIADDR 0x71 /* MII address register */
  258. #define VELOCITY_MIIDATA 0x72 /* MII data register */
  259. #define VELOCITY_SSTIMER 0x74 /* single-shot timer */
  260. #define VELOCITY_PTIMER 0x76 /* periodic timer */
  261. #define VELOCITY_DMACFG0 0x7C /* DMA config 0 */
  262. #define VELOCITY_DMACFG1 0x7D /* DMA config 1 */
  263. #define VELOCITY_RXCFG 0x7E /* MAC RX config */
  264. #define VELOCITY_TXCFG 0x7F /* MAC TX config */
  265. #define VELOCITY_SWEEDATA 0x85 /* EEPROM software loaded data */
  266. /** Chip Configuration Register A */
  267. #define VELOCITY_CFGA 0x78
  268. #define VELOCITY_CFGA_PACPI (1 << 0)
  269. /** Power Management Sticky Register */
  270. #define VELOCITY_STICKY 0x83
  271. #define VELOCITY_STICKY_DS0 (1 << 0)
  272. #define VELOCITY_STICKY_DS1 (1 << 1)
  273. #define VELOCITY_EEWRDAT 0x8C /* EEPROM embedded write */
  274. #define VELOCITY_EECSUM 0x92 /* EEPROM checksum */
  275. #define VELOCITY_EECSR 0x93 /* EEPROM control/status */
  276. #define VELOCITY_EECSR_RELOAD (1 << 5)
  277. #define VELOCITY_EERDDAT 0x94 /* EEPROM embedded read */
  278. #define VELOCITY_EEADDR 0x96 /* EEPROM address */
  279. #define VELOCITY_EECMD 0x97 /* EEPROM embedded command */
  280. /** A Velocity network card */
  281. struct velocity_nic {
  282. /** Registers */
  283. void *regs;
  284. /** MII interface */
  285. struct mii_interface mdio;
  286. /** MII device */
  287. struct mii_device mii;
  288. /** Netdev */
  289. struct net_device *netdev;
  290. /** Receive descriptor ring */
  291. struct velocity_rx_descriptor *rx_ring;
  292. /** Receive I/O buffers */
  293. struct io_buffer *rx_buffs[VELOCITY_RXDESC_NUM];
  294. /** Receive producer index */
  295. unsigned int rx_prod;
  296. /** Receive consumer index */
  297. unsigned int rx_cons;
  298. /** Receive commit number
  299. *
  300. * Used to fullfill the hardware requirement of returning receive buffers
  301. * to the hardware only in blocks of 4.
  302. */
  303. unsigned int rx_commit;
  304. /** Transmit descriptor ring */
  305. struct velocity_tx_descriptor *tx_ring;
  306. /** Transmit producer index */
  307. unsigned int tx_prod;
  308. /** Transmit consumer index */
  309. unsigned int tx_cons;
  310. };
  311. #endif /* _VELOCITY_H */