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e1000e_nvm.c 14KB

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  1. /*******************************************************************************
  2. Intel PRO/1000 Linux driver
  3. Copyright(c) 1999 - 2009 Intel Corporation.
  4. This program is free software; you can redistribute it and/or modify it
  5. under the terms and conditions of the GNU General Public License,
  6. version 2, as published by the Free Software Foundation.
  7. This program is distributed in the hope it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc.,
  13. 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  14. The full GNU General Public License is included in this distribution in
  15. the file called "COPYING".
  16. Contact Information:
  17. Linux NICS <linux.nics@intel.com>
  18. e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20. *******************************************************************************/
  21. FILE_LICENCE ( GPL2_OR_LATER );
  22. #include "e1000e.h"
  23. static void e1000e_stop_nvm(struct e1000_hw *hw);
  24. static void e1000e_reload_nvm(struct e1000_hw *hw);
  25. /**
  26. * e1000e_init_nvm_ops_generic - Initialize NVM function pointers
  27. * @hw: pointer to the HW structure
  28. *
  29. * Setups up the function pointers to no-op functions
  30. **/
  31. void e1000e_init_nvm_ops_generic(struct e1000_hw *hw)
  32. {
  33. struct e1000_nvm_info *nvm = &hw->nvm;
  34. /* Initialize function pointers */
  35. nvm->ops.reload = e1000e_reload_nvm;
  36. }
  37. /**
  38. * e1000e_raise_eec_clk - Raise EEPROM clock
  39. * @hw: pointer to the HW structure
  40. * @eecd: pointer to the EEPROM
  41. *
  42. * Enable/Raise the EEPROM clock bit.
  43. **/
  44. static void e1000e_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
  45. {
  46. *eecd = *eecd | E1000_EECD_SK;
  47. ew32(EECD, *eecd);
  48. e1e_flush();
  49. udelay(hw->nvm.delay_usec);
  50. }
  51. /**
  52. * e1000e_lower_eec_clk - Lower EEPROM clock
  53. * @hw: pointer to the HW structure
  54. * @eecd: pointer to the EEPROM
  55. *
  56. * Clear/Lower the EEPROM clock bit.
  57. **/
  58. static void e1000e_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
  59. {
  60. *eecd = *eecd & ~E1000_EECD_SK;
  61. ew32(EECD, *eecd);
  62. e1e_flush();
  63. udelay(hw->nvm.delay_usec);
  64. }
  65. /**
  66. * e1000e_shift_out_eec_bits - Shift data bits our to the EEPROM
  67. * @hw: pointer to the HW structure
  68. * @data: data to send to the EEPROM
  69. * @count: number of bits to shift out
  70. *
  71. * We need to shift 'count' bits out to the EEPROM. So, the value in the
  72. * "data" parameter will be shifted out to the EEPROM one bit at a time.
  73. * In order to do this, "data" must be broken down into bits.
  74. **/
  75. static void e1000e_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
  76. {
  77. struct e1000_nvm_info *nvm = &hw->nvm;
  78. u32 eecd = er32(EECD);
  79. u32 mask;
  80. mask = 0x01 << (count - 1);
  81. if (nvm->type == e1000_nvm_eeprom_spi)
  82. eecd |= E1000_EECD_DO;
  83. do {
  84. eecd &= ~E1000_EECD_DI;
  85. if (data & mask)
  86. eecd |= E1000_EECD_DI;
  87. ew32(EECD, eecd);
  88. e1e_flush();
  89. udelay(nvm->delay_usec);
  90. e1000e_raise_eec_clk(hw, &eecd);
  91. e1000e_lower_eec_clk(hw, &eecd);
  92. mask >>= 1;
  93. } while (mask);
  94. eecd &= ~E1000_EECD_DI;
  95. ew32(EECD, eecd);
  96. }
  97. /**
  98. * e1000e_shift_in_eec_bits - Shift data bits in from the EEPROM
  99. * @hw: pointer to the HW structure
  100. * @count: number of bits to shift in
  101. *
  102. * In order to read a register from the EEPROM, we need to shift 'count' bits
  103. * in from the EEPROM. Bits are "shifted in" by raising the clock input to
  104. * the EEPROM (setting the SK bit), and then reading the value of the data out
  105. * "DO" bit. During this "shifting in" process the data in "DI" bit should
  106. * always be clear.
  107. **/
  108. static u16 e1000e_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
  109. {
  110. u32 eecd;
  111. u32 i;
  112. u16 data;
  113. eecd = er32(EECD);
  114. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  115. data = 0;
  116. for (i = 0; i < count; i++) {
  117. data <<= 1;
  118. e1000e_raise_eec_clk(hw, &eecd);
  119. eecd = er32(EECD);
  120. eecd &= ~E1000_EECD_DI;
  121. if (eecd & E1000_EECD_DO)
  122. data |= 1;
  123. e1000e_lower_eec_clk(hw, &eecd);
  124. }
  125. return data;
  126. }
  127. /**
  128. * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
  129. * @hw: pointer to the HW structure
  130. * @ee_reg: EEPROM flag for polling
  131. *
  132. * Polls the EEPROM status bit for either read or write completion based
  133. * upon the value of 'ee_reg'.
  134. **/
  135. s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
  136. {
  137. u32 attempts = 100000;
  138. u32 i, reg = 0;
  139. s32 ret_val = -E1000_ERR_NVM;
  140. for (i = 0; i < attempts; i++) {
  141. if (ee_reg == E1000_NVM_POLL_READ)
  142. reg = er32(EERD);
  143. else
  144. reg = er32(EEWR);
  145. if (reg & E1000_NVM_RW_REG_DONE) {
  146. ret_val = E1000_SUCCESS;
  147. break;
  148. }
  149. udelay(5);
  150. }
  151. return ret_val;
  152. }
  153. /**
  154. * e1000e_acquire_nvm - Generic request for access to EEPROM
  155. * @hw: pointer to the HW structure
  156. *
  157. * Set the EEPROM access request bit and wait for EEPROM access grant bit.
  158. * Return successful if access grant bit set, else clear the request for
  159. * EEPROM access and return -E1000_ERR_NVM (-1).
  160. **/
  161. s32 e1000e_acquire_nvm(struct e1000_hw *hw)
  162. {
  163. u32 eecd = er32(EECD);
  164. s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
  165. s32 ret_val = E1000_SUCCESS;
  166. ew32(EECD, eecd | E1000_EECD_REQ);
  167. eecd = er32(EECD);
  168. while (timeout) {
  169. if (eecd & E1000_EECD_GNT)
  170. break;
  171. udelay(5);
  172. eecd = er32(EECD);
  173. timeout--;
  174. }
  175. if (!timeout) {
  176. eecd &= ~E1000_EECD_REQ;
  177. ew32(EECD, eecd);
  178. e_dbg("Could not acquire NVM grant\n");
  179. ret_val = -E1000_ERR_NVM;
  180. }
  181. return ret_val;
  182. }
  183. /**
  184. * e1000e_standby_nvm - Return EEPROM to standby state
  185. * @hw: pointer to the HW structure
  186. *
  187. * Return the EEPROM to a standby state.
  188. **/
  189. static void e1000e_standby_nvm(struct e1000_hw *hw)
  190. {
  191. struct e1000_nvm_info *nvm = &hw->nvm;
  192. u32 eecd = er32(EECD);
  193. if (nvm->type == e1000_nvm_eeprom_spi) {
  194. /* Toggle CS to flush commands */
  195. eecd |= E1000_EECD_CS;
  196. ew32(EECD, eecd);
  197. e1e_flush();
  198. udelay(nvm->delay_usec);
  199. eecd &= ~E1000_EECD_CS;
  200. ew32(EECD, eecd);
  201. e1e_flush();
  202. udelay(nvm->delay_usec);
  203. }
  204. }
  205. /**
  206. * e1000e_stop_nvm - Terminate EEPROM command
  207. * @hw: pointer to the HW structure
  208. *
  209. * Terminates the current command by inverting the EEPROM's chip select pin.
  210. **/
  211. static void e1000e_stop_nvm(struct e1000_hw *hw)
  212. {
  213. u32 eecd;
  214. eecd = er32(EECD);
  215. if (hw->nvm.type == e1000_nvm_eeprom_spi) {
  216. /* Pull CS high */
  217. eecd |= E1000_EECD_CS;
  218. e1000e_lower_eec_clk(hw, &eecd);
  219. }
  220. }
  221. /**
  222. * e1000e_release_nvm - Release exclusive access to EEPROM
  223. * @hw: pointer to the HW structure
  224. *
  225. * Stop any current commands to the EEPROM and clear the EEPROM request bit.
  226. **/
  227. void e1000e_release_nvm(struct e1000_hw *hw)
  228. {
  229. u32 eecd;
  230. e1000e_stop_nvm(hw);
  231. eecd = er32(EECD);
  232. eecd &= ~E1000_EECD_REQ;
  233. ew32(EECD, eecd);
  234. }
  235. /**
  236. * e1000e_ready_nvm_eeprom - Prepares EEPROM for read/write
  237. * @hw: pointer to the HW structure
  238. *
  239. * Setups the EEPROM for reading and writing.
  240. **/
  241. static s32 e1000e_ready_nvm_eeprom(struct e1000_hw *hw)
  242. {
  243. struct e1000_nvm_info *nvm = &hw->nvm;
  244. u32 eecd = er32(EECD);
  245. s32 ret_val = E1000_SUCCESS;
  246. u16 timeout = 0;
  247. u8 spi_stat_reg;
  248. if (nvm->type == e1000_nvm_eeprom_spi) {
  249. /* Clear SK and CS */
  250. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  251. ew32(EECD, eecd);
  252. udelay(1);
  253. timeout = NVM_MAX_RETRY_SPI;
  254. /*
  255. * Read "Status Register" repeatedly until the LSB is cleared.
  256. * The EEPROM will signal that the command has been completed
  257. * by clearing bit 0 of the internal status register. If it's
  258. * not cleared within 'timeout', then error out.
  259. */
  260. while (timeout) {
  261. e1000e_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
  262. hw->nvm.opcode_bits);
  263. spi_stat_reg = (u8)e1000e_shift_in_eec_bits(hw, 8);
  264. if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
  265. break;
  266. udelay(5);
  267. e1000e_standby_nvm(hw);
  268. timeout--;
  269. }
  270. if (!timeout) {
  271. e_dbg("SPI NVM Status error\n");
  272. ret_val = -E1000_ERR_NVM;
  273. goto out;
  274. }
  275. }
  276. out:
  277. return ret_val;
  278. }
  279. /**
  280. * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
  281. * @hw: pointer to the HW structure
  282. * @offset: offset of word in the EEPROM to read
  283. * @words: number of words to read
  284. * @data: word read from the EEPROM
  285. *
  286. * Reads a 16 bit word from the EEPROM using the EERD register.
  287. **/
  288. s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
  289. {
  290. struct e1000_nvm_info *nvm = &hw->nvm;
  291. u32 i, eerd = 0;
  292. s32 ret_val = E1000_SUCCESS;
  293. /*
  294. * A check for invalid values: offset too large, too many words,
  295. * too many words for the offset, and not enough words.
  296. */
  297. if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
  298. (words == 0)) {
  299. e_dbg("nvm parameter(s) out of bounds\n");
  300. ret_val = -E1000_ERR_NVM;
  301. goto out;
  302. }
  303. for (i = 0; i < words; i++) {
  304. eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
  305. E1000_NVM_RW_REG_START;
  306. ew32(EERD, eerd);
  307. ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
  308. if (ret_val)
  309. break;
  310. data[i] = (er32(EERD) >>
  311. E1000_NVM_RW_REG_DATA);
  312. }
  313. out:
  314. return ret_val;
  315. }
  316. /**
  317. * e1000e_write_nvm_spi - Write to EEPROM using SPI
  318. * @hw: pointer to the HW structure
  319. * @offset: offset within the EEPROM to be written to
  320. * @words: number of words to write
  321. * @data: 16 bit word(s) to be written to the EEPROM
  322. *
  323. * Writes data to EEPROM at offset using SPI interface.
  324. *
  325. * If e1000e_update_nvm_checksum is not called after this function , the
  326. * EEPROM will most likely contain an invalid checksum.
  327. **/
  328. s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
  329. {
  330. struct e1000_nvm_info *nvm = &hw->nvm;
  331. s32 ret_val;
  332. u16 widx = 0;
  333. /*
  334. * A check for invalid values: offset too large, too many words,
  335. * and not enough words.
  336. */
  337. if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
  338. (words == 0)) {
  339. e_dbg("nvm parameter(s) out of bounds\n");
  340. ret_val = -E1000_ERR_NVM;
  341. goto out;
  342. }
  343. ret_val = nvm->ops.acquire(hw);
  344. if (ret_val)
  345. goto out;
  346. while (widx < words) {
  347. u8 write_opcode = NVM_WRITE_OPCODE_SPI;
  348. ret_val = e1000e_ready_nvm_eeprom(hw);
  349. if (ret_val)
  350. goto release;
  351. e1000e_standby_nvm(hw);
  352. /* Send the WRITE ENABLE command (8 bit opcode) */
  353. e1000e_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
  354. nvm->opcode_bits);
  355. e1000e_standby_nvm(hw);
  356. /*
  357. * Some SPI eeproms use the 8th address bit embedded in the
  358. * opcode
  359. */
  360. if ((nvm->address_bits == 8) && (offset >= 128))
  361. write_opcode |= NVM_A8_OPCODE_SPI;
  362. /* Send the Write command (8-bit opcode + addr) */
  363. e1000e_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
  364. e1000e_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
  365. nvm->address_bits);
  366. /* Loop to allow for up to whole page write of eeprom */
  367. while (widx < words) {
  368. u16 word_out = data[widx];
  369. word_out = (word_out >> 8) | (word_out << 8);
  370. e1000e_shift_out_eec_bits(hw, word_out, 16);
  371. widx++;
  372. if ((((offset + widx) * 2) % nvm->page_size) == 0) {
  373. e1000e_standby_nvm(hw);
  374. break;
  375. }
  376. }
  377. }
  378. msleep(10);
  379. release:
  380. nvm->ops.release(hw);
  381. out:
  382. return ret_val;
  383. }
  384. /**
  385. * e1000e_read_pba_num - Read device part number
  386. * @hw: pointer to the HW structure
  387. * @pba_num: pointer to device part number
  388. *
  389. * Reads the product board assembly (PBA) number from the EEPROM and stores
  390. * the value in pba_num.
  391. **/
  392. s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
  393. {
  394. s32 ret_val;
  395. u16 nvm_data;
  396. ret_val = e1000e_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
  397. if (ret_val) {
  398. e_dbg("NVM Read Error\n");
  399. goto out;
  400. }
  401. *pba_num = (u32)(nvm_data << 16);
  402. ret_val = e1000e_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
  403. if (ret_val) {
  404. e_dbg("NVM Read Error\n");
  405. goto out;
  406. }
  407. *pba_num |= nvm_data;
  408. out:
  409. return ret_val;
  410. }
  411. /**
  412. * e1000e_read_mac_addr_generic - Read device MAC address
  413. * @hw: pointer to the HW structure
  414. *
  415. * Reads the device MAC address from the EEPROM and stores the value.
  416. * Since devices with two ports use the same EEPROM, we increment the
  417. * last bit in the MAC address for the second port.
  418. **/
  419. s32 e1000e_read_mac_addr_generic(struct e1000_hw *hw)
  420. {
  421. u32 rar_high;
  422. u32 rar_low;
  423. u16 i;
  424. rar_high = er32(RAH(0));
  425. rar_low = er32(RAL(0));
  426. for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
  427. hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
  428. for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
  429. hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
  430. for (i = 0; i < ETH_ADDR_LEN; i++)
  431. hw->mac.addr[i] = hw->mac.perm_addr[i];
  432. return E1000_SUCCESS;
  433. }
  434. /**
  435. * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
  436. * @hw: pointer to the HW structure
  437. *
  438. * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
  439. * and then verifies that the sum of the EEPROM is equal to 0xBABA.
  440. **/
  441. s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
  442. {
  443. s32 ret_val = E1000_SUCCESS;
  444. u16 checksum = 0;
  445. u16 i, nvm_data;
  446. for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
  447. ret_val = e1000e_read_nvm(hw, i, 1, &nvm_data);
  448. if (ret_val) {
  449. e_dbg("NVM Read Error\n");
  450. goto out;
  451. }
  452. checksum += nvm_data;
  453. }
  454. if (checksum != (u16) NVM_SUM) {
  455. e_dbg("NVM Checksum Invalid\n");
  456. ret_val = -E1000_ERR_NVM;
  457. goto out;
  458. }
  459. out:
  460. return ret_val;
  461. }
  462. /**
  463. * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
  464. * @hw: pointer to the HW structure
  465. *
  466. * Updates the EEPROM checksum by reading/adding each word of the EEPROM
  467. * up to the checksum. Then calculates the EEPROM checksum and writes the
  468. * value to the EEPROM.
  469. **/
  470. s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
  471. {
  472. s32 ret_val;
  473. u16 checksum = 0;
  474. u16 i, nvm_data;
  475. for (i = 0; i < NVM_CHECKSUM_REG; i++) {
  476. ret_val = e1000e_read_nvm(hw, i, 1, &nvm_data);
  477. if (ret_val) {
  478. e_dbg("NVM Read Error while updating checksum.\n");
  479. goto out;
  480. }
  481. checksum += nvm_data;
  482. }
  483. checksum = (u16) NVM_SUM - checksum;
  484. ret_val = e1000e_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
  485. if (ret_val)
  486. e_dbg("NVM Write Error while updating checksum.\n");
  487. out:
  488. return ret_val;
  489. }
  490. /**
  491. * e1000e_reload_nvm - Reloads EEPROM
  492. * @hw: pointer to the HW structure
  493. *
  494. * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
  495. * extended control register.
  496. **/
  497. static void e1000e_reload_nvm(struct e1000_hw *hw)
  498. {
  499. u32 ctrl_ext;
  500. udelay(10);
  501. ctrl_ext = er32(CTRL_EXT);
  502. ctrl_ext |= E1000_CTRL_EXT_EE_RST;
  503. ew32(CTRL_EXT, ctrl_ext);
  504. e1e_flush();
  505. }